TPS78227QDRVRQ1

TPS78225-Q1, TPS78227-Q1 TPS78228-Q1, TPS78230-Q1 www.ti.com SBVS138 – DECEMBER 2009 150-mA, ULTRA-LOW QUIESCENT CURRENT, 1-μA IQ LOW-DROPOUT LINEAR REGULATOR Check for Samples: TPS78225-Q1 TPS78227-Q1 TPS78228-Q1 TPS78230-Q1 FEATURES DESCRIPTION • • • • • • • The TPS782xx family of low-dropout regulators (LDOs) offers the benefits of ultra-low power (IQ = 1 μA), and miniaturized packaging (2-mm×2-mm SON). 1 2 • • • • Qualified for Automotive Applications Low IQ: 1 μA 150-mA Low-Dropout Regulator Low Dropout at 25°C: 130 mV at 150 mA Low Dropout at 85°C: 175 mV at 150 mA 4% Accuracy Over Load/Line/Temperature Available in Fixed Voltage Options (2.5 V, 2.7 V, 2.8 V, and 3 V) Using Innovative Factory EEPROM Programming Stable with a 1-μF Ceramic Capacitor Thermal Shutdown and Overcurrent Protection CMOS Logic Level Compatible Enable Pin Available in DDC (TSOT23-5) or DRV (2-mm x 2-mm SON-6) Packages APPLICATIONS • • TI MSP430 Attach Applications Power Rails with Programming Mode DRV PACKAGE 2mm x 2mm SON-6 (TOP VIEW) OUT 1 NC 2 Thermal Pad GND 3 6 IN 5 GND 4 EN This LDO is designed specifically for battery-powered applications where ultra-low quiescent current is a critical parameter. The TPS782, with ultra-low IQ (1 μA), is ideal for microprocessors, memory cards, and smoke detectors. The ultra-low power and miniaturized packaging allow designers to customize power consumption for specific applications. Consult with your local factory representative for exact voltage options and ordering information; minimum order quantities may apply. The TPS782xx family is designed to be compatible with the TI MSP430 and other similar products. The enable pin (EN) is compatible with standard CMOS logic. This LDO is stable with any output capacitor greater than 1.0 μF. Therefore, this device requires minimal board space because of miniaturized packaging and a potentially small output capacitor. The TPS782xx series also features thermal shutdown and current limit to protect the device during fault conditions. The devices have an operating temperature range of TJ = –40°C to 125°C. For high-performance applications that require a dual-level voltage option, consider the TPS780 series, with an IQ of 500 nA and dynamic voltage scaling. NC – No connection ORDERING INFORMATION (1) PACKAGE (2) TJ –40°C to 125°C (1) (2) SON – DRV Reel of 3000 ORDERABLE PART NUMBER TOP-SIDE MARKING TPS78225QDRVRQ1 NSY TPS78227QDRVRQ1 OFH TPS78228QDRVRQ1 OFI TPS78230QDRVRQ1 OFJ For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2009, Texas Instruments Incorporated TPS78225-Q1, TPS78227-Q1 TPS78228-Q1, TPS78230-Q1 SBVS138 – DECEMBER 2009 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ABSOLUTE MAXIMUM RATINGS (1) At TJ = –40°C to 125°C, unless otherwise noted. All voltages are with respect to GND. TPS782xx UNIT –0.3 to +6.0 V Enable –0.3 to VIN + 0.3V V Output voltage range, VOUT –0.3 to VIN + 0.3V V Input voltage range, VIN Maximum output current, IOUT Internally limited Output short-circuit duration Indefinite Total continuous power dissipation, PDISS See the Dissipation Ratings table 2 kV 500 V Operating junction temperature range, TJ –40 to 125 °C Storage temperature range, TSTG –55 to +150 °C ESD rating (1) Human body model (HBM) Charged device model (CDM) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. DISSIPATION RATINGS BOARD PACKAGE RθJC RθJA DERATING FACTOR ABOVE TA = 25°C TA < 25°C TA = 70°C TA = 85°C High-K (1) DRV 20°C/W 65°C/W 15.4 mW/°C 1540 mW 84 5mW 615 mW (1) 2 The JEDEC high-K (2s2p) board used to derive this data was a 3-inch × 3-inch, multilayer board with 1-ounce internal power and ground planes and 2-ounce copper traces on top and bottom of the board. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS78225-Q1 TPS78227-Q1 TPS78228-Q1 TPS78230-Q1 TPS78225-Q1, TPS78227-Q1 TPS78228-Q1, TPS78230-Q1 www.ti.com SBVS138 – DECEMBER 2009 ELECTRICAL CHARACTERISTICS TJ = –40°C to 125°C, VIN = VOUT(NOM) + 0.5 V or 2.2 V, whichever is greater; IOUT = 100 μA, VEN = VIN, COUT = 1.0 μF, fixed VOUT test conditions (unless otherwise noted). Typical values at TJ = 25°C. TPS782xx PARAMETER VIN VOUT ΔVOUT/ΔVIN TEST CONDITIONS Input voltage range +2 % Over VIN, IOUT, VOUT + 0.5 V ≤ VIN ≤ 5.5 V, temperature 5 mA ≤ IOUT ≤ 150 mA –4 ±2 +4 % ±1 % 0 mA ≤ IOUT ≤ 150 mA ±2 % VIN = 95% VOUT(NOM), IOUT = 150 mA 130 86 Output noise voltage ICL Output current limit VOUT = 0.90 × VOUT(NOM) IGND Ground pin current ISHDN Shutdown current (IGND) VEN ≤ 0.4 V, 2.2 V ≤ VIN < 5.5 V, TJ = 25°C EN pin current VEN = 5.5 V, TJ = 25°C tSTR tSHDN (1) (2) (3) (4) (1) VOUT(NOM) + 0.5 V ≤ VIN ≤ 5.5 V, IOUT = 5 mA VN PSRR Power-supply rejection ratio Startup time V ±1 BW = 100 Hz to 100 kHz, VIN = 2.2 V, VOUT = 1.2 V, IOUT = 1 mA IEN UNIT 5.5 –2 Line regulation Dropout voltage MAX TJ = 25°C ΔVOUT/ΔIOUT Load regulation VDO TYP 2.2 Nominal DC output accuracy MIN (2) Shutdown time (3) TSD Thermal shutdown temperature TJ Operating junction temperature mV μVRMS 230 400 mA IOUT = 0 mA 1 1.4 μA IOUT = 150 mA 8 VIN = 4.3 V, VOUT = 3.3 V, IOUT = 150 mA 150 250 18 μA 130 nA 40 nA f = 10 Hz 40 dB f = 100 Hz 20 dB f = 1 kHz 15 dB 500 μs 500 (4) μs 160 °C COUT = 1.0 μF, VOUT = 10% VOUT(NOM) to VOUT = 90% VOUT(NOM) IOUT = 150 mA, COUT = 1.0 μF, VOUT = 2.8 V, VOUT = 90% VOUT(NOM) to VOUT = 10% VOUT(NOM) Shutdown, temperature increasing Reset, temperature decreasing 140 –40 °C 125 °C VDO is not measured for devices with VOUT(NOM) ≤ 2.3 V, because minimum VIN = 2.2 V. Time from VEN = 1.2 V to VOUT = 90% (VOUT(NOM)). Time from VEN = 0.4 V to VOUT = 10% (VOUT(NOM)). See Shutdown in the Application Information section for more details. Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS78225-Q1 TPS78227-Q1 TPS78228-Q1 TPS78230-Q1 3 TPS78225-Q1, TPS78227-Q1 TPS78228-Q1, TPS78230-Q1 SBVS138 – DECEMBER 2009 www.ti.com FUNCTIONAL BLOCK DIAGRAM IN OUT Current Limit Mux Thermal Shutdown EEPROM Bandgap EN Active PullDown 10kW Logic GND PIN CONFIGURATIONS DRV PACKAGE 2mm x 2mm SON-6 (TOP VIEW) OUT 1 NC 2 GND (1) 3 Thermal Pad (2) 6 IN 5 GND 4 EN (1) All ground pins must be connected to ground for proper operation. (2) It is recommended that the thermal pad be grounded. (1) Table 1. PIN DESCRIPTIONS 4 NAME NO. DESCRIPTION OUT 1 Regulated output voltage pin. A small (1 μF) ceramic capacitor is needed from this pin to ground to assure stability. See the Input and Output Capacitor Requirements in the Application Information section for more details. NC 2 Not connected EN 4 Driving the enable pin (EN) over 1.2 V turns ON the regulator. Driving this pin below 0.4 V puts the regulator into shutdown mode, reducing operating current to 18 nA typical. GND 3, 5 IN 6 Thermal pad Thermal pad ALL ground pins must be tied to ground for proper operation. Input pin. A small capacitor is needed from this pin to ground to assure stability. Typical input capacitor = 1.0 μF. Both input and output capacitor grounds should be tied back to the IC ground with no significant impedance between them. It is recommended that the thermal pad on the SON-6 package be connected to ground. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS78225-Q1 TPS78227-Q1 TPS78228-Q1 TPS78230-Q1 TPS78225-Q1, TPS78227-Q1 TPS78228-Q1, TPS78230-Q1 www.ti.com SBVS138 – DECEMBER 2009 TYPICAL CHARACTERISTICS TJ = –40°C to 125°C, VIN = VOUT(TYP) + 0.5 V or 2.2 V, whichever is greater; IOUT = 100 μA, VEN = VIN, COUT = 1 μF, CIN = 1 μF (unless otherwise noted) LINE REGULATION IOUT = 5 mA, VOUT = 2.7 V (typ) TPS78227 LINE REGULATION IOUT = 150 mA, VOUT = 2.7 V (typ) TPS78227 1.0 3 0.8 TJ = -40°C 0.6 0.4 1 0.2 VOUT (%) VOUT (%) 2 TJ = +25°C 0 -0.2 TJ = +85°C -0.4 TJ = -40°C 0 -1 -0.6 -2 TJ = +85°C -0.8 -1.0 -3 3.8 4.0 4.2 4.4 4.6 4.8 VIN (V) 5.0 5.2 5.4 5.6 3.8 4.0 4.2 4.4 4.6 4.8 VIN (V) 5.0 5.2 5.4 Figure 1. Figure 2. LOAD REGULATION VIN = 3.8 V, VOUT = 2.7 V TPS78227 DROPOUT VOLTAGE vs OUTPUT CURRENT VOUT = 2.7 V (typ), VIN = 0.95 × VOUT (typ) TPS78227 3 5.6 250 TJ = +125°C VDO (VIN - VOUT) (mV) 2 TJ = -40°C 1 VOUT (%) TJ = +25°C 0 -1 TJ = +25°C TJ = +85°C 200 TJ = +85°C 150 100 50 -2 TJ = -40°C TJ = +25°C 0 -3 0 25 50 75 IOUT (mA) Figure 3. Copyright © 2009, Texas Instruments Incorporated 100 125 150 0 25 50 75 IOUT (mA) 100 125 150 Figure 4. Submit Documentation Feedback Product Folder Link(s): TPS78225-Q1 TPS78227-Q1 TPS78228-Q1 TPS78230-Q1 5 TPS78225-Q1, TPS78227-Q1 TPS78228-Q1, TPS78230-Q1 SBVS138 – DECEMBER 2009 www.ti.com TYPICAL CHARACTERISTICS (continued) TJ = –40°C to 125°C, VIN = VOUT(TYP) + 0.5 V or 2.2 V, whichever is greater; IOUT = 100 μA, VEN = VIN, COUT = 1 μF, CIN = 1 μF (unless otherwise noted) DROPOUT VOLTAGE vs JUNCTION TEMPERATURE VOUT = 2.7 V (typ), VIN = 0.95 × VOUT (typ) TPS78227 GROUND PIN CURRENT vs INPUT VOLTAGE IOUT = 50 mA, VOUT = 2.7 V TPS78227 6 5 200 TJ = +125°C TJ = +85°C 150mA 4 150 IGND (mA) VDO (VIN - VOUT) (mV) 250 100mA 100 3 2 50mA TJ = +25°C 50 TJ = -40°C 1 10mA 0 0 -40 -25 -10 5 20 35 50 TJ (°C) 65 80 95 110 125 3.8 4.0 4.2 4.4 4.6 4.8 VIN (V) 5.0 5.2 Figure 5. Figure 6. GROUND PIN CURRENT vs INPUT VOLTAGE IOUT = 150 mA, VOUT = 2.7 V TPS78227 CURRENT LIMIT vs INPUT VOLTAGE VOUT = 95% VOUT (typ), VOUT = 2.7 V (typ) TPS78227 3 5.4 5.6 300 290 2 VOUT (%) 1 Current Limit (mA) 280 TJ = -40°C 0 -1 TJ = -40°C 260 250 TJ = +25°C 240 TJ = +85°C 230 220 -2 TJ = +85°C TJ = +25°C TJ = +125°C 210 200 -3 3.8 4.0 4.2 4.4 4.6 4.8 VIN (V) Figure 7. 6 270 Submit Documentation Feedback 5.0 5.2 5.4 5.6 3.8 4.0 4.2 4.4 4.6 4.8 VIN (V) 5.0 5.2 5.4 5.6 Figure 8. Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS78225-Q1 TPS78227-Q1 TPS78228-Q1 TPS78230-Q1 TPS78225-Q1, TPS78227-Q1 TPS78228-Q1, TPS78230-Q1 www.ti.com SBVS138 – DECEMBER 2009 TYPICAL CHARACTERISTICS (continued) TJ = –40°C to 125°C, VIN = VOUT(TYP) + 0.5 V or 2.2 V, whichever is greater; IOUT = 100 μA, VEN = VIN, COUT = 1 μF, CIN = 1 μF (unless otherwise noted) ENABLE PIN CURRENT vs INPUT VOLTAGE IOUT = 100 μA, VOUT = 2.7 V TPS78227 ENABLE PIN HYSTERESIS vs JUNCTION TEMPERATURE IOUT = 1 mA, TPS78227 2.0 1.2 1.8 1.1 1.6 1.0 TJ = -40°C 1.2 VEN (V) IEN (nA) 1.4 TJ = +25°C 1.0 TJ = +85°C 0.8 0.8 0.7 VEN Off 0.6 0.6 0.4 0.5 0.2 0.4 0 3.8 4.0 4.2 4.4 4.6 4.8 VIN (V) 5.0 5.2 5.4 5.6 -40 -25 -10 5 20 35 50 TJ (°C) 65 80 Figure 9. Figure 10. %ΔVOUT vs JUNCTION TEMPERATURE VIN = 3.3 V, VOUT = 2.7 V (typ) TPS78227 %ΔVOUT vs JUNCTION TEMPERATURE VIN = 3.7 V, VOUT = 2.7 V (typ) TPS78227 1 95 110 125 95 110 125 3 2 0 5mA -1 %DVOUT (V) 0.1mA %DVOUT (V) VEN On 0.9 1 0.1mA 0 5mA -1 150mA 150mA -2 -2 -3 -40 -25 -10 5 20 35 50 TJ (°C) 65 Figure 11. Copyright © 2009, Texas Instruments Incorporated 80 95 110 125 -40 -25 -10 5 20 35 50 TJ (°C) 65 80 Figure 12. Submit Documentation Feedback Product Folder Link(s): TPS78225-Q1 TPS78227-Q1 TPS78228-Q1 TPS78230-Q1 7 TPS78225-Q1, TPS78227-Q1 TPS78228-Q1, TPS78230-Q1 SBVS138 – DECEMBER 2009 www.ti.com TYPICAL CHARACTERISTICS (continued) TJ = –40°C to 125°C, VIN = VOUT(TYP) + 0.5 V or 2.2 V, whichever is greater; IOUT = 100 μA, VEN = VIN, COUT = 1 μF, CIN = 1 μF (unless otherwise noted) 100 RIPPLE REJECTION vs FREQUENCY = 4.2 V, VOUT = 2.7 V, COUT = 2.2 μF TPS78227 80 1mA 70 10 60 150mA 109mVRMS 1 0.1 50mA 109mVRMS 0.01 0.001 100 1k Frequency (Hz) Figure 13. Submit Documentation Feedback 50 40 50mA 30 20 150mA 10 1mA 108mVRMS 10 8 VIN PSRR (dB) Output Spectral Noise Density (mV/ÖHz) OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY CIN = 1 μF, COUT = 2.2 μF, VIN = 3.2 V TPS78227 0 10k 100k 10 100 1k 10k 100k Frequency (Hz) 1M 10M Figure 14. Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS78225-Q1 TPS78227-Q1 TPS78228-Q1 TPS78230-Q1 TPS78225-Q1, TPS78227-Q1 TPS78228-Q1, TPS78230-Q1 www.ti.com SBVS138 – DECEMBER 2009 APPLICATION INFORMATION APPLICATION EXAMPLES The TPS782xx family of LDOs is factory-programmable to have a fixed output. Note that during startup or steady-state conditions, it is important that the EN pin voltage never exceed VIN + 0.3 V. 4.2V to 5.5V VIN 2.7V IN VOUT OUT 1 mF 1mF TPS78227 On Off EN GND Figure 15. Typical Application Circuit INPUT AND OUTPUT CAPACITOR REQUIREMENTS Although an input capacitor is not required for stability, it is good analog design practice to connect a 0.1-μF to 1.0-μF low equivalent series resistance (ESR) capacitor across the input supply near the regulator. This capacitor counteracts reactive input sources and improves transient response, noise rejection, and ripple rejection. A higher-value capacitor may be necessary if large, fast rise-time load transients are anticipated, or if the device is not located near the power source. If source impedance is not sufficiently low, a 0.1-μF input capacitor may be necessary to ensure stability. The TPS782xx series are designed to be stable with standard ceramic capacitors with values of 1.0 μF or larger at the output. X5R- and X7R-type capacitors are best because they have minimal variation in value and ESR over temperature. Maximum ESR should be less than 1.0 Ω. With tolerance and dc bias effects, the minimum capacitance to ensure stability is 1 μF. BOARD LAYOUT RECOMMENDATIONS TO IMPROVE PSRR AND NOISE PERFORMANCE To improve ac performance (such as PSRR, output noise, and transient response), it is recommended that the printed circuit board (PCB) be designed with separate ground planes for VIN and VOUT, with each ground plane connected only at the GND pin of the device. In addition, the ground connection for the output capacitor should connect directly to the GND pin of the device. High ESR capacitors may degrade PSRR. INTERNAL CURRENT LIMIT The TPS782xx is internally current-limited to protect the regulator during fault conditions. During current limit, the output sources a fixed amount of current that is largely independent of output voltage. For reliable operation, the device should not be operated in a current limit state for extended periods of time. The PMOS pass element in the TPS782xx series has a built-in body diode that conducts current when the voltage at OUT exceeds the voltage at IN. This current is not limited, so if extended reverse voltage operation is anticipated, external limiting to 5% of rated output current may be appropriate. Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS78225-Q1 TPS78227-Q1 TPS78228-Q1 TPS78230-Q1 9 TPS78225-Q1, TPS78227-Q1 TPS78228-Q1, TPS78230-Q1 SBVS138 – DECEMBER 2009 www.ti.com SHUTDOWN The enable pin (EN) is active high and is compatible with standard and low-voltage CMOS levels. When shutdown capability is not required, EN should be connected to the IN pin, as shown in Figure 16. The TPS782xx series, with internal active output pulldown circuitry, discharges the output to within 5% VOUT with a time (t) shown in Equation 1: t=3 10kW ´ RL ´ COUT 10kW + RL (1) Where: RL= output load resistance COUT = output capacitance 4.2V to 5.5V VIN 2.7V IN VOUT OUT 1 mF 1mF TPS78227 EN GND Figure 16. Circuit Showing EN Tied High when Shutdown Capability is Not Required DROPOUT VOLTAGE The TPS782xx series use a PMOS pass transistor to achieve low dropout. When (VIN – VOUT) is less than the dropout voltage (VDO), the PMOS pass device is the linear region of operation and the input-to-output resistance is the RDS(ON) of the PMOS pass element. VDO approximately scales with output current because the PMOS device behaves like a resistor in dropout. As with any linear regulator, PSRR and transient response are degraded as (VIN – VOUT) approaches dropout. This effect is shown in the Typical Characteristics section. See the application report Understanding LDO Dropout (SLVA207) available for download from www.ti.com. TRANSIENT RESPONSE As with any regulator, increasing the size of the output capacitor reduces over/undershoot magnitude but increases duration of the transient response. ACTIVE VOUT PULL-DOWN In the TPS782xx series, the active pulldown discharges VOUT when the device is off. However, the input voltage must be greater than 2.2 V for the active pulldown to work. MINIMUM LOAD The TPS782xx series are stable with no output load. Traditional PMOS LDO regulators suffer from lower loop gain at very light output loads. The TPS782xx employs an innovative, low-current circuit under very light or no-load conditions, resulting in improved output voltage regulation performance down to zero output current. 10 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS78225-Q1 TPS78227-Q1 TPS78228-Q1 TPS78230-Q1 TPS78225-Q1, TPS78227-Q1 TPS78228-Q1, TPS78230-Q1 www.ti.com SBVS138 – DECEMBER 2009 THERMAL INFORMATION THERMAL PROTECTION Thermal protection disables the device output when the junction temperature rises to approximately 160°C, allowing the device to cool. Once the junction temperature cools to approximately 140°C, the output circuitry is enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may cycle on and off again. This cycling limits the dissipation of the regulator, protecting it from damage as a result of overheating. Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate heatsink. For reliable operation, junction temperature should be limited to 125°C maximum. To estimate the margin of safety in a complete design (including heatsink), increase the ambient temperature until the thermal protection is triggered; use worst-case loads and signal conditions. For good reliability, thermal protection should trigger at least 35°C above the maximum expected ambient condition of your particular application. This configuration produces a worst-case junction temperature of 125°C at the highest expected ambient temperature and worst-case load. The internal protection circuitry of the TPS782xx series has been designed to protect against overload conditions. However, it is not intended to replace proper heatsinking. Continuously running the TPS782xx series into thermal shutdown degrades device reliability. POWER DISSIPATION The ability to remove heat from the die is different for each package type, presenting different considerations in the PCB layout. The PCB area around the device that is free of other components moves the heat from the device to the ambient air. Performance data for JEDEC low- and high-K boards are given in the Dissipation Ratings table. Using heavier copper increases the effectiveness in removing heat from the device. The addition of plated through-holes to heat-dissipating layers also improves the heatsink effectiveness. Power dissipation depends on input voltage and load conditions. Power dissipation (PD) is equal to the product of the output current times the voltage drop across the output pass element (VIN to VOUT), as shown in Equation 2: PD = (VIN - VOUT) ´ IOUT (2) PACKAGE MOUNTING Solder pad footprint recommendations for the TPS782xx series are available from the Texas Instruments web site at www.ti.com through the TPS782xx series product folders. Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS78225-Q1 TPS78227-Q1 TPS78228-Q1 TPS78230-Q1 11 PACKAGE OPTION ADDENDUM www.ti.com 24-Mar-2016 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) TPS78227QDRVRQ1 ACTIVE SON DRV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 OFH TPS78228QDRVRQ1 ACTIVE SON DRV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 OFI TPS78230QDRVRQ1 ACTIVE SON DRV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 OFJ (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 24-Mar-2016 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS78227QDRVRQ1 SON DRV 6 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2 TPS78228QDRVRQ1 SON DRV 6 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2 TPS78230QDRVRQ1 SON DRV 6 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 24-Mar-2016 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS78227QDRVRQ1 SON DRV 6 3000 203.0 203.0 35.0 TPS78228QDRVRQ1 SON DRV 6 3000 203.0 203.0 35.0 TPS78230QDRVRQ1 SON DRV 6 3000 203.0 203.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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