TPS78601DCQR

Product Folder Sample & Buy Support & Community Tools & Software Technical Documents TPS786 SLVS389M – SEPTEMBER 2002 – REVISED SEPTEMBER 2015 TPS786 Ultralow-Noise, High-PSRR, Fast, RF, 1.5-A Low-Dropout Linear Regulators 1 Features 3 Description • • The TPS786 family of low-dropout (LDO) low-power linear voltage regulators features high power-supply rejection ratio (PSRR), ultralow noise, fast start-up, and excellent line and load transient responses in small outline, SOT223-6 and DDPAK-5 packages. Each device in the family is stable, with a small 1-μF ceramic capacitor on the output. The family uses an advanced, proprietary BiCMOS fabrication process to yield extremely low dropout voltages (for example, 390 mV at 1.5 A). Each device achieves fast start-up times (approximately 50 μs with a 0.001-μF bypass capacitor) while consuming very low quiescent current (265 μA, typical). Moreover, when the device is placed in standby mode, the supply current is reduced to less than 1 μA. The TPS78630 exhibits approximately 48 μVRMS of output voltage at 3-V output noise with a 0.1-μF bypass capacitor. Applications with analog components that are noise sensitive, such as portable RF electronics, benefit from the high PSRR, low noise features, and the fast response time. 1 • • • • • • • 1.5-A Low-Dropout Regulator With Enable Available in Fixed and Adjustable (1.2 V to 5.5 V) Output Versions High PSRR (49 dB at 10 kHz) Ultralow Noise (48 μVRMS, TPS78630) Fast Start-Up Time (50 μs) Stable With a 1-μF Ceramic Capacitor Excellent Load and Line Transient Response Very Low Dropout Voltage (390 mV at Full Load, TPS78630) 3 × 3 SON PowerPAD™, 6-Pin SOT223 and 5-Pin DDPAK Package 2 Applications • • • • • RF: VCOs, Receivers, ADCs Audio Bluetooth®, Wireless LAN Cellular and Cordless Telephones Handheld Organizers, PDAs Device Information(1) PART NUMBER TPS786 PACKAGE BODY SIZE (NOM) TO-263 (5) 10.16 mm × 8.42 mm SOT-223 (6) 6.50 mm × 3.50 mm SON (8) 3.00 mm × 3.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. 80 VIN = 4 V COUT = 10 µF CNR = 0.01 µF Ripple Rejection − (dB) 70 IOUT = 1 mA 60 50 IOUT = 1.5 A 40 30 20 10 0 1 10 100 1k 10k 100k f (Hz) 1M 10M Output Spectral Noise Density vs Frequency Output Spectral Noise Density (µVÖHz) Ripple Rejection vs Frequency 0.80 VIN = 5.5 V COUT = 2.2 µF CNR = 0.1 µF 0.70 0.60 0.50 0.40 0.30 IOUT = 1 mA 0.20 0.10 0.00 100 IOUT = 1.5 A 1k 10k 100k Frequency (Hz) 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPS786 SLVS389M – SEPTEMBER 2002 – REVISED SEPTEMBER 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 4 4 4 5 6 7 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Typical Characteristics .............................................. Detailed Description ............................................ 11 7.1 7.2 7.3 7.4 Overview ................................................................. Functional Block Diagrams ..................................... Feature Description................................................. Device Functional Modes........................................ 11 11 12 12 8 Application and Implementation ........................ 13 8.1 Application Information............................................ 13 8.2 Typical Application .................................................. 14 9 Power Supply Recommendations...................... 16 10 Layout................................................................... 16 10.1 10.2 10.3 10.4 Layout Guidelines ................................................. Layout Examples................................................... Regulator Mounting............................................... Power Dissipation ................................................. 16 16 17 17 11 Device and Documentation Support ................. 21 11.1 11.2 11.3 11.4 11.5 11.6 Device Support...................................................... Documentation Support ........................................ Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 21 21 21 21 21 22 12 Mechanical, Packaging, and Orderable Information ........................................................... 22 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision L (October 2010) to Revision M Page • Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ................................................................................................. 1 • Updated Thermal Information................................................................................................................................................. 5 Changes from Revision K (August, 2010) to Revision L • Page Corrected typo in Figure 34 .................................................................................................................................................. 20 Changes from Revision J (May, 2009) to Revision K Page • Replaced the Dissipation Ratings table with the Thermal Information Table......................................................................... 5 • Revised section .................................................................................................................................................................... 17 2 Submit Documentation Feedback Copyright © 2002–2015, Texas Instruments Incorporated Product Folder Links: TPS786 TPS786 www.ti.com SLVS389M – SEPTEMBER 2002 – REVISED SEPTEMBER 2015 5 Pin Configuration and Functions DCQ Package 6-Pin SOT-223 Top View EN IN GND OUT NR/FB 1 2 3 4 5 DRB Package 8-SON Top View IN 1 6 GND IN 2 OUT 3 OUT 4 8 EN 7 NC 6 GND 5 NR/FB KTT Package 5-Pin TO-263 Top View EN IN GND OUT NR/FB 1 2 3 4 5 Pin Functions PIN NAME I/O DESCRIPTION SOT-223 TO-263 SON NR 5 5 5 — EN 1 1 8 I The EN terminal is an input that enables or shuts down the device. When EN is a logic high, the device is enabled. When the device is a logic low, the device is in shutdown mode. Feedback input voltage for the adjustable device. FB Noise-reduction pin for fixed versions only. An external bypass capacitor, connected to this terminal, in conjunction with an internal resistor, creates a low-pass filter to further reduce regulator noise. 5 5 5 I 3, 6 3, TAB 6 — IN 2 2 1, 2 I Input supply OUT 4 4 3, 4 O Regulator output GND Regulator ground Submit Documentation Feedback Copyright © 2002–2015, Texas Instruments Incorporated Product Folder Links: TPS786 3 TPS786 SLVS389M – SEPTEMBER 2002 – REVISED SEPTEMBER 2015 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT VIN –0.3 6 V VEN –0.3 VIN + 0.3 V 6 V VOUT Peak output current Internally limited Continuous total power dissipation See Thermal Information Junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) ±2000 Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2) ±500 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating junction temperature range (unless otherwise noted) MIN VIN Input supply voltage IOUT Output current TJ Operating junction temperature 4 Submit Documentation Feedback NOM MAX UNIT 2.7 5.5 V 0 1.5 A –40 125 °C Copyright © 2002–2015, Texas Instruments Incorporated Product Folder Links: TPS786 TPS786 www.ti.com SLVS389M – SEPTEMBER 2002 – REVISED SEPTEMBER 2015 6.4 Thermal Information TPS786 (3) THERMAL METRIC (1) (2) DRB (SON) DCQ (S0T-223) KTT (TO-263) 8 PINS 6 PINS 5 PINS UNIT RθJA Junction-to-ambient thermal resistance 41.1 54.2 40.7 °C/W RθJC(top) Junction-to-case (top) thermal resistance 49.1 33.3 43.1 °C/W RθJB Junction-to-board thermal resistance 16.6 8.9 21.5 °C/W ψJT Junction-to-top characterization parameter 0.7 2.6 9.4 °C/W ψJB Junction-to-board characterization parameter 16.8 8.8 20 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 5.2 N/A 2.1 °C/W (1) (2) (3) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator. Thermal data for the DRB, DCQ, and DRV packages are derived by thermal simulations based on JEDEC-standard methodology as specified in the JESD51 series. The following assumptions are used in the simulations: (a) i. DRB: The exposed pad is connected to the PCB ground layer through a 2×2 thermal via array. . ii. DCQ: The exposed pad is connected to the PCB ground layer through a 3×2 thermal via array. . iii. KTT: The exposed pad is connected to the PCB ground layer through a 5×4 thermal via array. (b) i. DRB: The top and bottom copper layers are assumed to have a 20% thermal conductivity of copper representing a 20% copper coverage. . ii. DCQ: Each of top and bottom copper layers has a dedicated pattern for 20% copper coverage. . iii. KTT: The top and bottom copper layers are assumed to have a 20% thermal conductivity of copper representing a 20% copper coverage. (c) These data were generated with only a single device at the center of a JEDEC high-K (2s2p) board with 3 inches × 3 inches copper area. To understand the effects of the copper area on thermal performance, see the Power Dissipation and Estimating Junction Temperature sections of this data sheet. Submit Documentation Feedback Copyright © 2002–2015, Texas Instruments Incorporated Product Folder Links: TPS786 5 TPS786 SLVS389M – SEPTEMBER 2002 – REVISED SEPTEMBER 2015 www.ti.com 6.5 Electrical Characteristics Over recommended operating temperature range (TJ = –40°C to 125°C), VEN = VIN, VIN = VOUT(nom) + 1 V (1), IOUT = 1 mA, COUT = 10 μF, and CNR = 0.01 μF, unless otherwise noted. Typical values are at 25°C. PARAMETER TEST CONDITIONS MIN Input voltage, VIN (1) Internal reference, VFB (TPS78601) TPS78601 (2) 0 μA ≤ IOUT ≤ 1.5 A, VOUT + 1 V ≤ VIN ≤ 5.5 V (1) Output voltage Accuracy V V 0 1.5 A 1.225 5.5 – VDO V (1.02)VOUT V VOUT 0 μA ≤ IOUT ≤ 1.5 A, VOUT + 1 V ≤ VIN ≤ 5.5 V (1) –2% 2% Fixed VOUT =5V 0 μA ≤ IOUT ≤ 1.5 A, VOUT + 1 V ≤ VIN ≤ 5.5 V (1) –3% 3% Output voltage line regulation (ΔVOUT%/VIN) Load regulation (ΔVOUT%/VOUT) Dropout voltage (3) VIN = VOUT(nom) – 0.1 V (0.98)VOUT 1.225 Fixed VOUT 50 db Noise at 1K