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TPS793-Q1
SGLS162I – APRIL 2003 – REVISED MARCH 2016
TPS793-Q1 Ultralow-Noise, High-PSRR, Fast RF 200-mA
Low-Dropout Linear Regulators
1 Features
3 Description
•
•
The TPS793xx-Q1 family of low-dropout (LDO) lowpower linear voltage regulators features high powersupply rejection ratio (PSRR), ultralow noise, fast
start-up, and excellent line and load transient
responses in a small-outline SOT-23 package. Each
TPS793-Q1 device in the family is stable, with a small
2.2-μF ceramic capacitor on the output. The
TPS793xx-Q1 family uses an advanced, proprietary,
BiCMOS fabrication process to yield extremely low
dropout voltages (for example, 112 mV at 200 mA,
TPS79330-Q1). Each device achieves fast start-up
times (approximately 50 μs with a 0.001-μF bypass
capacitor), while consuming very low quiescent
current (170 μA typical). Moreover, when the device
is placed in standby mode, the supply current is
reduced to less than 1 μA. The TPS79328-Q1
exhibits approximately 32 μVRMS of output voltage
noise with a 0.1-μF bypass capacitor. Applications
with analog components that are noise sensitive,
such as portable RF electronics, benefit from the high
PSRR and low-noise features, as well as the fast
response time.
1
•
•
•
•
•
•
•
•
•
Qualified For Automotive Applications
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 1: –40°C to
+125°C
– Device HBM ESD Classification Level 1C
– Device CDM ESD Classification Level C2
200-mA Low-Dropout Regulator With EN
Available in 1.8-V, 2.5-V, 2.8-V, 3-V, 3.3-V, 4.75V, and Adjustable Options
High PSRR (70 dB at 10 kHz)
Ultralow Noise (32 μV)
Fast Start-Up Time (50 μs)
Stable With a 2.2-μF Ceramic Capacitor
Excellent Load and Line Transient
Very Low Dropout Voltage
(112 mV at Full Load, TPS79330-Q1)
5-Pin SOT-23 (DBV) Package
2 Applications
VCOs
RF
Bluetooth™
PART NUMBER
TPS793xx-Q1
TPS79328-Q1 Ripple Rejection vs Frequency
100
SOT-23 (6)
Hz
IO = 200 mA
80
70
50
IO = 10 mA
30
VI = 3.8 V
Co = 10 mF
C(byp) = 0.01 mF
10
0
10
2.90 × 2.90 mm
0.3
VI = 3.8 V
Co = 2.2 mF
C(byp) = 0.1 mF
0.25
60
20
BODY SIZE (NOM)
TPS79328-Q1 Output Spectral Noise Density vs
Frequency
mV/
Ripple Rejection − dB
90
40
PACKAGE
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
100
1k
10 k
100 k
f − Frequency − Hz
1M
10 M
Output Spectral Noise Density −
•
•
•
Device Information(1)
0.2
0.15
IO = 1 mA
0.1
IO = 200 mA
0.05
0
100
1k
10 k
f − Frequency − Hz
100 k
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS793-Q1
SGLS162I – APRIL 2003 – REVISED MARCH 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Voltage Options .....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
7.1
7.2
7.3
7.4
7.5
7.6
4
4
4
4
5
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 11
8.1 Overview ................................................................. 11
8.2 Functional Block Diagram ....................................... 11
8.3 Feature Description................................................. 12
8.4 Device Functional Modes........................................ 13
9
Application and Implementation ........................ 14
9.1 Application Information............................................ 14
9.2 Typical Application .................................................. 14
10 Power Supply Recommendations ..................... 17
11 Layout................................................................... 17
11.1 Layout Guidelines ................................................. 17
11.2 Layout Example .................................................... 17
11.3 Power Dissipation and Junction Temperature ...... 17
12 Device and Documentation Support ................. 19
12.1
12.2
12.3
12.4
12.5
12.6
Device Support......................................................
Documentation Support ........................................
Community Resource............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
19
19
19
19
20
20
13 Mechanical, Packaging, and Orderable
Information ........................................................... 20
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision H (January 2013) to Revision I
Page
•
Changed document part numbers to the generic TPS793-Q1 .............................................................................................. 1
•
Removed the 2.85-V version from the data sheet ................................................................................................................. 1
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
2
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SGLS162I – APRIL 2003 – REVISED MARCH 2016
5 Voltage Options
(1)
OUTPUT VOLTAGE
ORDERABLE PART NUMBER
SYMBOL
1.2 V to 5.5 V
TPS79301DBVRQ1
PGV1
1.8 V
TPS79318DBVRQ1
PHH1
2.5 V
TPS79325DBVRQ1
PGW1
2.8 V
TPS79328DBVRQ1
PGX1
2.85 V
TPS793285QDBVRQ1
PHI1
3V
TPS79330QDBVRQ1
PGY1
3.3 V
TPS79333DBVRQ1
PHU1
4.75 V
TPS793475QDBVRQ1 (1)
PHJ1
Product Preview
6 Pin Configuration and Functions
Fixed Option: DBV Package
6-Pin SOT-23
Top View
IN
1
GND
2
EN
3
5
4
Adjustable Option: DBV Package
6-Pin SOT-23
Top View
OUT
IN
1
6
OUT
GND
2
5
FB
EN
3
4
BYPASS
BYPASS
Pin Functions
PIN
NAME
I/O
DESCRIPTION
ADJ
FIXED
BYPASS
4
4
—
EN
3
3
I
Enable input that enables or shuts down the device. When EN goes to a logic high, the
device is enabled. When the device goes to a logic low, the device is in shutdown mode.
FB
5
N/A
I
Feedback input voltage for the adjustable device
GND
2
2
—
Regulator ground
IN
1
1
I
Input to the device
OUT
6
5
O
Regulated output of the device
An external bypass capacitor, connected to this terminal, in conjunction with an internal
resistor, creates a low-pass filter to further reduce regulator noise.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
Input voltage (2)
–0.3
6
V
Voltage range at EN
–0.3
VI + 0.3
V
Voltage on OUT
–0.3
6
V
Peak output current
Internally limited
Continuous total power dissipation
See Thermal Information
TJ
Operating junction temperature
–40
150
°C
Tstg
Storage temperature
–65
150
°C
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal
7.2 ESD Ratings
VALUE
V(ESD)
(1)
Human-body model (HBM), per AEC Q100-002
Electrostatic discharge
(1)
UNIT
±2000
Charged-device model (CDM), per AEC Q100-011
V
±250
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VIN
Input supply voltage
2.7
5.5
VEN
Enable supply voltage
V
0
VIN
V
VOUT
Output voltage
VFB
5
IOUT
Output current
0
200
TJ
Operating junction temperature
–40
CIN
Input capacitor
0.1
1
µF
COUT
Output capacitor
2.2
10
µF
CNR
Noise reduction capacitor
0
10
nF
CFF
Feed-forward capacitor
15
pF
R2
Lower feedback resistor
30.1
kΩ
125
V
mA
°C
7.4 Thermal Information
TPS793xx-Q1
THERMAL METRIC (1)
DBV (SOT-23)
UNIT
6 PINS
RθJA
Junction-to-ambient thermal resistance
225.1
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
78.4
°C/W
RθJB
Junction-to-board thermal resistance
54.7
°C/W
ψJT
Junction-to-top characterization parameter
3.3
°C/W
ψJB
Junction-to-board characterization parameter
53.8
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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7.5 Electrical Characteristics
over recommended operating free-air temperature range, EN = VI, TJ = –40 to 125°C, VI = VO(typ) + 1 V, IO = 1 mA, Co = 10
μF, C(byp) = 0.01 μF (unless otherwise noted)
PARAMETER
VI
Input voltage (1)
IO
Continuous output current
TJ
Operating junction temperature
TPS79301-Q1
TPS79318-Q1
TPS79325-Q1
Output voltage
TPS79328-Q1
TPS79330-Q1
TPS79333-Q1
TPS793475-Q1
Quiescent current (GND current)
Output voltage line regulation (ΔVO/VO)
Time, start-up
0 μA < IO < 200 mA
TPS79328-Q1
TPS79328-Q1
MIN
TYP
0 μA < IO < 200 mA,
V
0
200
mA
–40
125
°C
5.5 –
VFB
VDROPOUT
1.8
2.8 V < VI < 5.5 V
1.764
1.836
2.5
3.5 V < VI < 5.5 V
2.45
2.55
TJ = 25°C
0 μA < IO < 200 mA,
2.8
3.8 V < VI < 5.5 V
2.744
3
4 V < VI < 5.5 V
2.94
3.06
TJ = 25°C
0 μA < IO < 200 mA,
3.3
4.3 V < VI < 5.5 V
3.234
0 μA < IO < 200 mA,
5.25 V < VI < 5.5 V
4.655
0 μA < IO < 200 mA,
TJ = 25°C
3.366
TJ = 25°C
4.75
4.845
170
0 μA < IO < 200 mA
TJ = 25°C
5
0.05
VO + 1 V < VI ≤ 5.5 V
RL = 14 Ω,
Co = 1 μF, TJ = 25°C
VO = 0 V
Standby current (2)
EN = 0 V,
High-level enable input voltage
2.7 V < VI < 5.5 V
Low-level enable input voltage
2.7 V < VI < 5.5 V
Input current (EN)
EN = 0
Input current (FB)
TPS79301-Q1
Internal reference, VFB
TPS79301-Q1
C(byp) = 0.001 μF
55
C(byp) = 0.0047 μF
36
C(byp) = 0.01 μF
33
C(byp) = 0.1 μF
32
C(byp) = 0.001 μF
50
C(byp) = 0.0047 μF
70
TPS79328-Q1
(1)
(2)
2.7 V < VI < 5.5 V
0.07
μVRMS
μs
600
mA
1
μA
2
V
–1
1.201
1.225
IO = 10 mA
70
IO = 200 mA
68
f = 10 kHz, TJ = 25°C,
f = 100 kHz, TJ =
25°C,
%/V
100
285
FB = 1.8 V
f = 100 Hz, TJ = 25°C,
Power-supply ripple
rejection
mV
0.12
C(byp) = 0.01 μF
Output current limit
μA
220
VO + 1 V < VI ≤ 5.5 V, TJ = 25°C
BW = 200 Hz to 100
kHz,
IO = 200 mA, TJ =
25°C
V
2.856
TJ = 25°C
0 μA < IO < 200 mA,
UNIT
5.5
TJ = 25°C
0 μA < IO < 200 mA,
MAX
2.7
TJ = 25°C
0 μA < IO < 200 mA,
Load regulation
Output noise voltage
TEST CONDITIONS
0.7
V
1
μA
1
μA
1.250
V
70
IO = 200 mA
dB
43
Minimum VIN is 2.7 V or VOUT + VDO, whichever is greater.
For adjustable versions, this parameter applies only after VIN is applied; then VEN transitions high to low.
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Electrical Characteristics (continued)
over recommended operating free-air temperature range, EN = VI, TJ = –40 to 125°C, VI = VO(typ) + 1 V, IO = 1 mA, Co = 10
μF, C(byp) = 0.01 μF (unless otherwise noted)
PARAMETER
TPS79328-Q1
TPS79330-Q1
Dropout voltage (3)
TPS79333-Q1
TPS793475-Q1
TEST CONDITIONS
IO = 200 mA,
IO = 200 mA,
120
TJ = 25°C
112
IO = 200 mA,
200
TJ = 25°C
102
TJ = 25°C
77
IO = 200 mA
IO = 200 mA,
TJ = 25°C
UNIT
mV
180
IO = 200 mA
VCC rising
MAX
200
IO = 200 mA
UVLO hysteresis
6
TYP
IO = 200 mA
UVLO threshold
(3)
MIN
TJ = 25°C
125
2.25
VCC rising
2.65
100
V
mV
Dropout is not measured for the TPS79318-Q1 and TPS79325-Q1 since minimum VIN = 2.7 V.
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7.6 Typical Characteristics
2.805
2.805
VI = 3.8 V
Co = 10 mF
TJ = 25° C
V O − Output Voltage − V
2.803
2.8
V O − Output Voltage − V
2.804
2.802
2.801
2.8
2.799
2.798
2.797
IO = 1 mA
2.795
2.79
IO = 200 mA
2.785
2.78
VI = 3.8 V
Co = 10 mF
2.796
2.795
2.775
0
50
100
150
−40 −25 −10 5
200
20 35 50 65 80 95 110 125
IO − Output Current − mA
TJ − Junction Temperature − °C
Figure 1. TPS79328-Q1 Output Voltage vs Output Current
Figure 2. TPS79328-Q1 Output Voltage vs
Junction Temperature
0.3
Hz
250
IO = 1 mA
Output Spectral Noise Density − mV/
Ground Current − mA
VI = 3.8 V
Co = 10 mF
200
IO = 200 mA
150
100
50
0
−40 −25 −10 5
0.2
0.15
IO = 1 mA
0.1
IO = 200 mA
0.05
20 35 50 65 80 95 110 125
0
TJ − Junction Temperature − °C
100
1k
10 k
f − Frequency − Hz
Figure 3. TPS79328-Q1 Ground Current vs
Junction Temperature
Figure 4. TPS79328-Q1 Output Spectral Noise Density vs
Frequency
Hz
Hz
Output Spectral Noise Density − mV/
VI = 3.8 V
Co = 10 mF
C(byp) = 0.1 mF
0.25
0.2
IO = 1 mA
0.15
0.1
IO = 200 mA
0.05
0
100
100 k
1.6
0.3
Output Spectral Noise Density − mV/
VI = 3.8 V
Co = 2.2 mF
C(byp) = 0.1 mF
0.25
1k
10 k
100 k
VI = 3.8 V
IO = 200 mA
Co= 10 mF
1.4
1.2
C(byp) = 0.001 mF
1
C(byp) = 0.0047 mF
0.8
C(byp) = 0.01 mF
0.6
C(byp) = 0.1 mF
0.4
0.2
0
100
1k
10 k
100 k
f − Frequency − Hz
f − Frequency − Hz
Figure 5. TPS79328-Q1 Output Spectral Noise Density vs
Frequency
Figure 6. TPS79328-Q1 Output Spectral Noise Density vs
Frequency
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2.5
VI = 3.8 V
Co = 10 mF
TJ = 25° C
60
VO = 2.8 V
IO = 200 mA
Co = 10 mF
50
Z o − Output Impedance − W
RMS − Root Mean Squared Output Noise − mV(RMS)
Typical Characteristics (continued)
40
30
20
2
1.5
IO = 1 mA
1
IO = 100 mA
0.5
10
BW = 100 Hz to 100 kHz
0
0.001
0.01
C(byp) − Bypass Capacitance − mF
0
10
100
0.1
1k
10 k 100 k
f − Frequency − Hz
1M
10 M
Figure 8. Output Impedance vs Frequency
Figure 7. Root Mean Squared Output Noise vs
Bypass Capacitance
180
100
VI = 2.7 V
Co = 10 mF
90
IO = 200 mA
80
140
120
Ripple Rejection − dB
V DO − Dropout Voltage − mV
160
IO = 200 mA
100
80
60
40
70
60
50
40
IO = 10 mA
30
20
IO = 10 mA
20
0
−40 −25 −10 5
VI = 3.8 V
Co = 10 mF
C(byp) = 0.01 mF
10
0
20 35 50 65 80 95 110 125
10
100
TJ − Junction Temperature − °C
Figure 9. TPS79328-Q1 Dropout Voltage vs Junction
Temperature
100 k
1M
10 M
100
VI = 3.8 V
Co = 2.2 mF
C(byp) = 0.01 mF
80
IO = 200 mA
70
60
50
VI = 3.8 V
Co = 2.2 mF
C(byp) = 0.1 mF
90
Ripple Rejection − dB
90
Ripple Rejection − dB
10 k
Figure 10. TPS79328-Q1 Ripple Rejection vs Frequency
100
IO = 10 mA
40
30
80
IO = 200 mA
70
60
50
IO = 10 mA
40
30
20
20
10
10
0
0
10
100
1k
10 k
100 k
1M
10 M
10
f − Frequency − Hz
100
1k
10 k
100 k
1M
10 M
f − Frequency − Hz
Figure 11. TPS79328-Q1 Ripple Rejection vs Frequency
8
1k
f − Frequency − Hz
Figure 12. TPS79328-Q1 Ripple Rejection vs Frequency
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V O − Output Voltage − mV
4
2
V − Output Voltage − V
O
0
C(byp) = 0.001 mF
VI = 3.8 V
VO = 2.8 V
IO = 200 mA
Co = 2.2 mF
TJ = 25°C
3
2
C(byp) = 0.0047 mF
1
C(byp) = 0.01 mF
0
0
20 40
60 80 100 120 140 160 180 200
t − Time − ms
DV − Change In
O
Output Voltage − mV
Figure 13. TPS79328-Q1 Output Voltage and Enable Voltage
vs Time (Start-Up)
4.8
3.8
dv
dt
0.4 V
ms
0
-20
0
10
20
30 40
50 60
70 80
90 100
t − Time − ms
Figure 14. TPS79328-Q1 Line Transient Response
VO = 3 V
RL = 15 W
VI = 3.8 V
Co = 10 mF
20
IO = 200 mA
Co = 2.2 mF
C(byp) = 0.01 mF
20
V I − Input Voltage − mV
Enable Voltage − V
Typical Characteristics (continued)
500 mV/div
0
I O − Output Current − mA
−20
−40
di
dt
300
0.02A
ms
VI
VO
200
1mA
100
0
0
1s/div
50 100 150 200 250 300 350 400 450 500
t − Time − ms
Figure 16. Power Up and Power Down
Figure 15. TPS79328-Q1 Load Transient Response
200
TJ = 125°C
200
V DO − Dropout Voltage − mV
DC Dropuoy Voltage − mV
250
TJ = 125°C
150
TJ = 25°C
100
TJ = −55°C
50
150
TJ = 25°C
100
50
TJ = −40°C
IO = 200 mA
0
0
0
20 40 60 80 100 120 140 160 180 200
2.5
3
3.5
4
4.5
5
IO − Output Current − mA
VI − Input Voltage − V
Figure 17. Dropout Voltage vs Output Current
Figure 18. TPS79301-Q1 Dropout Voltage vs Input Voltage
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Typical Characteristics (continued)
100
IO = 200 mA
ESR − Equivalent Series Resistance − W
V I − Minimum Required Input Voltage − V
4
TJ = 125°C
TJ = 25°C
TJ = −40°C
3
2.8
2
1.5
1.75
2
2.25 2.5
2.75
3
Co = 2.2 mF
VI = 5.5 V, VO ≥ 1.5 V
TJ = −40°C to 125°C
10
Region of Instability
1
0.1
Region of Stability
0.01
0
3.25 3.5
0.02
0.04
0.06
0.08
0.2
VO − Output Voltage − V
IO − Output Current − A
Figure 19. Minimum Required Input Voltage vs Output
Voltage
Figure 20. Typical Regions of Stability Equivalent Series
Resistance (ESR) vs Output Current
ESR − Equivalent Series Resistance − W
100
Co = 10 mF
VI = 5.5 V
TJ = −40°C to 125°C
10
Region of Instability
1
0.1
Region of Stability
0.01
0
0.02
0.04
0.06
0.08
0.2
IO − Output Current − A
Figure 21. Typical Regions of Stability Equivalent Series Resistance (ESR) vs Output Current
10
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8 Detailed Description
8.1 Overview
The TPS793xx-Q1 family of LDO regulators has been optimized for use in noise-sensitive battery-operated
equipment. The device features extremely low dropout voltages, high PSRR, ultralow output noise, low quiescent
current (170 μA typically), and enable-input to reduce supply currents to less than 1 μA when the regulator is
turned off.
8.2 Functional Block Diagram
VOUT
VIN
Current
Sense
UVLO
SHUTDOWN
ILIM
_
GND
R1
+
FB
EN
R2
UVLO
Thermal
Shutdown
VIN
External to
the Device
250 kW
Bandgap
Reference
Vref
Bypass
Figure 22. Functional Block Diagram – Adjustable Version
VOUT
VIN
UVLO
Current
Sense
GND
SHUTDOWN
ILIM
_
EN
R1
+
UVLO
R2
Thermal
Shutdown
VIN
Bandgap
Reference
250 kW
Vref
Bypass
Figure 23. Functional Block Diagram – Fixed Version
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8.3 Feature Description
8.3.1 Undervoltage Lockout (UVLO)
The TPS793xx-Q1 uses an undervoltage lockout (UVLO) circuit that disables the output until the input voltage is
greater than the rising UVLO voltage. This circuit ensures that the device does not exhibit any unpredictable
behavior when the supply voltage is lower than the operational range of the internal circuitry, VIN(min).
8.3.2 Shutdown
The enable pin (EN) is active high. Enable the device by forcing the EN pin to exceed VEN(high) (2 V minimum).
Turn off the device by forcing the EN pin to drop below 0.7 V. If shutdown capability is not required, connect EN
to IN.
8.3.3 Foldback Current Limit
The TPS793xx-Q1 features internal current limiting and thermal protection. During normal operation, the
TPS793xx-Q1 limits output current to approximately 400 mA. When current limiting engages, the output voltage
scales back linearly until the overcurrent condition ends. While current limiting is designed to prevent gross
device failure, care should be taken not to exceed the power dissipation ratings of the package or the absolute
maximum voltage ratings of the device.
8.3.4 Thermal Protection
Thermal protection disables the output when the junction temperature rises to approximately 165°C, allowing the
device to cool. When the junction temperature cools to approximately 140°C, the output circuitry is again
enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection
circuit may cycle on and off. This cycling limits regulator dissipation, protecting the device from damage as a
result of overheating. Any tendency to activate the thermal protection circuit indicates excessive power
dissipation or an inadequate heatsink. For reliable operation, junction temperature must be limited to 125°C
maximum. To estimate the margin of safety in a complete design (including heatsink), increase the ambient
temperature until the thermal protection is triggered; use worst-case loads and signal conditions.
The TPS793xx-Q1 internal protection circuitry is designed to protect against overload conditions. This circuitry is
not intended to replace proper heatsinking. Continuously running the TPS793xx-Q1 into thermal shutdown
degrades device reliability.
8.3.5 Reverse Current Operation
The TPS793xx-Q1 PMOS-pass transistor has a built-in back diode that conducts reverse current when the input
voltage drops below the output voltage (for example, during power down). Current is conducted from the output
to the input and is not internally limited. If extended reverse voltage operation is anticipated, external limiting to
5% of the rated output current is recommended.
8.3.6 Regulator Protection
The TPS793xx-Q1 features internal current limiting and thermal protection. During normal operation, the
TPS793xx-Q1 limits output current to approximately 400 mA. When current limiting engages, the output voltage
scales back linearly until the overcurrent condition ends. While current limiting is designed to prevent gross
device failure, care should be taken not to exceed the power dissipation ratings of the package or the absolute
maximum voltage ratings of the device. If the temperature of the device exceeds approximately 165°C, thermalprotection circuitry shuts it down. Once the device has cooled down to below approximately 140°C, regulator
operation resumes.
The TPS793xx-Q1 PMOS-pass transistor has a built-in back diode that conducts reverse current when the input
voltage drops below the output voltage (for example, during power down). Current is conducted from the output
to the input and is not internally limited. If extended reverse voltage operation is anticipated, external limiting
might be appropriate.
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8.4 Device Functional Modes
8.4.1 Normal Operation
The device regulates to the nominal output voltage under the following conditions:
• The input voltage is at least as high as VIN(min).
• The input voltage is greater than the nominal output voltage added to the dropout voltage.
• The enable voltage is greater than VEN(min).
• The output current is less than the current limit.
• The device junction temperature is less than the maximum specified junction temperature.
8.4.2 Dropout Operation
If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other
conditions are met for normal operation, the device operates in dropout mode. In this mode of operation, the
output voltage is the same as the input voltage minus the dropout voltage. The transient performance of the
device is significantly degraded because the pass device is in the linear region and no longer controls the current
through the LDO. Line or load transients in dropout can result in large output voltage deviations.
8.4.3 Disabled
The device is disabled under the following conditions:
• The enable voltage is less than the enable falling threshold voltage or has not yet exceeded the enable rising
threshold.
• The device junction temperature is greater than the thermal shutdown temperature.
• The input voltage is less than UVLOfalling.
Table 1 lists the conditions that lead to the different modes of operation.
Table 1. Device Functional Mode Comparison
OPERATING
MODE
PARAMETER
VIN
VEN
IOUT
TJ
Normal mode
VIN > VOUT(nom) + VDO and
VIN>VIN(min)
VEN > VEN(high)
IOUT < ILIM
TJ < 125°C
Dropout mode
VIN(min) < VIN< VOUT(nom) + VDO
VEN > VEN(high)
—
TJ < 125°C
Disabled mode
(any true
condition
disables the
device)
VIN < UVLOfalling
VEN < VEN(low)
—
TJ > 165°C (1)
(1)
Approximate value for thermal shutdown
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TPS793xx-Q1 family of low-dropout (LDO) regulators has been optimized for use in noise-sensitive batteryoperated equipment. The device features extremely low dropout voltages, high PSRR, ultralow output noise, low
quiescent current (170 μA typically), and enable-input to reduce supply currents to less than 1 μA when the
regulator is turned off.
9.2 Typical Application
A typical application circuit is shown in Figure 24.
1
VI
IN
BYPASS
OUT
4
5
VO
3
0.1 mF
0.01 mF
EN
+
2.2 mF
GND
2
Figure 24. Typical Application Circuit
9.2.1 Design Requirements
Table 2 lists the design requirements.
Table 2. Design Parameters
PARAMETER
DESIGN REQUIREMENTS
Input voltage
3 V – 4 V (Lithium Ion battery)
Output voltage
2.8 V
DC output current
10 mA
Peak output current
75 mA
Maximum ambient temperature
65°C
9.2.2 Detailed Design Procedure
9.2.2.1 External Capacitor Requirements
A 0.1-μF or larger ceramic input bypass capacitor, connected between IN and GND and located close to the
TPS793xx-Q1, is required for stability and improves transient response, noise rejection, and ripple rejection. A
higher-value electrolytic input capacitor may be necessary if large, fast-rise-time load transients are anticipated
and the device is located several inches from the power source.
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Like all LDOs, the TPS793xx-Q1 requires an output capacitor connected between OUT and GND to stabilize the
internal control loop. The minimum recommended capacitance is 2.2-μF. Any 2.2-μF or larger ceramic capacitor
is suitable, provided the capacitance does not vary significantly over temperature.
The internal voltage reference is a key source of noise in an LDO regulator. The TPS793xx-Q1 has a BYPASS
pin that is connected to the voltage reference through a 250-kΩ internal resistor. The 250-kΩ internal resistor, in
conjunction with an external bypass capacitor connected to the BYPASS pin, creates a low pass filter to reduce
the voltage reference noise and, therefore, the noise at the regulator output. For the regulator to operate
properly, the current flow out of the BYPASS pin must be at a minimum, because any leakage current creates an
IR drop across the internal resistor, thus, creating an output error. Therefore, the bypass capacitor must have
minimal leakage current.
For example, the TPS79328-Q1 exhibits only 32 μVRMS of output voltage noise using a 0.1-μF ceramic bypass
capacitor and a 2.2-μF ceramic output capacitor. Note that the output starts up slower as the bypass capacitance
increases due to the RC time constant at the BYPASS pin that is created by the internal 250-kΩ resistor and
external capacitor.
9.2.2.2 Programming the TPS79301-Q1 Adjustable LDO Regulator
The output voltage of the TPS79301-Q1 adjustable regulator is programmed using an external resistor divider as
shown in Figure 25. The output voltage is calculated using Equation 1.
R1 ö
æ
VO = Vref ´ ç 1 +
÷
è R2 ø
where Vref = 1.2246 V typical (the internal reference voltage)
(1)
Resistors R1 and R2 should be chosen for approximately 50-μA divider current. Lower-value resistors can be
used for improved noise performance, but the solution consumes more power. Higher resistor values should be
avoided as leakage current into/out of FB across R1/R2 creates an offset voltage that artificially
increases/decreases the feedback voltage and, thus, erroneously decreases or increases VO. The recommended
design procedure is to choose R2 = 30.1 kΩ to set the divider current at 50 μA, C1 = 15 pF for stability, and then
calculate R1 using Equation 2.
æ V
ö
R1 = ç O - 1÷ ´ R2
è Vref
ø
(2)
To improve the stability of the adjustable version, TI suggests placing a small compensation capacitor between
OUT and FB. For voltages 1.8 V, the
approximate value of this capacitor can be calculated using Equation 3.
C1 =
(3 ´ 10-7 ) ´ (R1 + R2)
(R1´ R2)
(3)
The suggested value of this capacitor for several resistor ratios is shown in the table in Table 3. If this capacitor
is not used (such as in a unity-gain configuration) or if an output voltage
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