TPS794xx
www.ti.com
SLVS349E – NOVEMBER 2001 – REVISED DECEMBER 2005
ULTRALOW-NOISE, HIGH-PSRR, FAST, RF, 250-mA
LOW-DROPOUT LINEAR REGULATORS
FEATURES
•
•
•
•
•
•
•
250-mA Low-Dropout Regulator With Enable
Available in Fixed and Adjustable (1.2 V to
5.5 V) Versions
High PSRR (60 dB at 10 kHz)
Ultralow Noise (32 µVrms, TPS79428)
Fast Start-Up Time (50 µs)
Stable With a 2.2-µF Ceramic Capacitor
Excellent Load/Line Transient Response
Very Low Dropout Voltage (155 mV at Full
Load)
Available in MSOP-8 and SOT223-6 Packages
The TPS794xx family of low-dropout (LDO) linear
voltage regulators features high power-supply
rejection ratio (PSRR), ultralow-noise, fast start-up,
and excellent line and load transient responses in
small outline, MSOP-8 PowerPAD™ and SOT223-6
packages. Each device in the family is stable with a
small 2.2-µF ceramic capacitor on the output. The
family uses an advanced, proprietary BiCMOS
fabrication process to yield extremely low dropout
voltages (for example, 155 mV at 250 mA). Each
device achieves fast start-up times (approximately
50 µs with a 0.001-µF bypass capacitor) while
consuming low quiescent current (170 µA typical).
Moreover, when the device is placed in standby
mode, the supply current is reduced to less than
1 µA. The TPS79428 exhibits approximately
32 µVRMS of output voltage noise at 2.8 V output with
a 0.1-µF bypass capacitor. Applications with analog
components that are noise-sensitive, such as
portable RF electronics, benefit from the high PSRR
and low noise features as well as the fast response
time.
APPLICATIONS
•
•
•
•
•
RF: VCOs, Receivers, ADCs
Audio
Bluetooth™, Wireless LAN
Cellular and Cordless Telephones
Handheld Organizers, PDAs
DGN PACKAGE
MSOP-8 PowerPADt
(TOP VIEW)
1
OUT
8
IN
2
7
NC
NC
3
6
FB
EN
4
5
NR
GND
DCQ PACKAGE
SOT223-6
(TOP VIEW)
EN
IN
GND
OUT
NR/FB
1
2
3
4
5
0.35
80
IOUT = 10 mA
70
IOUT = 250 mA
60
50
40
30
VIN = 4.3 V,
VOUT = 3.3 V,
CIN = 1 µF,
COUT = 10 µF,
CNR = 0.01 µF
20
6
GND
TPS79428
OUTPUT SPECTRAL NOISE DENSITY
vs
FREQUENCY
90
Ripple Rejection (dB)
NC − No internal connection
TPS79433
RIPPLE REJECTION
vs
FREQUENCY
Output Spectral Noise Density (µV/√Hz)
•
•
DESCRIPTION
10
0
10
100
1k
COUT = 2.2 µF,
CNR = 0.1 µF,
VIN = 3.8 V
0.30
0.25
IOUT = 250 mA
0.20
0.15
0.10
IOUT = 1 mA
0.05
0
10 k
100 k
Frequency (Hz)
1M
10 M
100
1000
10000
100000
Frequency (Hz)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
Bluetooth is a trademark of Bluetooth SIG, Inc.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2001–2005, Texas Instruments Incorporated
TPS794xx
www.ti.com
SLVS349E – NOVEMBER 2001 – REVISED DECEMBER 2005
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
ORDERING INFORMATION (1)
VOUT (2)
PRODUCT
TPS794xxyyyz
(1)
(2)
XX is nominal output voltage (for example, 28 = 2.8 V, 285 = 2.85 V, 01 = Adjustable).
YYY is package designator.
Z is package quantity.
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
Output voltages from 1.3 V to 5.0 V in 100 mV increments are available; minimum order quantities may apply. Contact factory for details
and availability.
ABSOLUTE MAXIMUM RATINGS
over operating temperature range unless otherwise noted (1)
VALUE
VIN range
–0.3 V to 6 V
VEN range
–0.3 V to VIN + 0.3 V
VOUT range
–0.3 V to 6 V
Peak output current
Internally limited
ESD rating, HBM
2 kV
ESD rating, CDM
500 V
Continuous total power dissipation
See Dissipation Ratings Table
Junction temperature range, TJ
–40°C to +150°C
Storage temperature range, Tstg
–65°C to +150°C
(1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
PACKAGE DISSIPATION RATINGS
PACKAGE
AIR FLOW
(CFM)
RθJC
(°C/W)
RθJA
(°C/W)
TA≤ 25°C
POWER RATING
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
0
8.47
55.09
2.27 W
1.45 W
1.18 W
DGN
150
8.21
49.97
2.50 W
1.60 W
1.30 W
250
8.20
48.10
2.60 W
1.66 W
1.35 W
6
5
PD (W)
4
Condition 1
3
Condition 2
2
CONDITIONS
PACKAGE
1
2
SOT223
SOT223
PCB AREA
4in2 Top Side Only
0.5in2 Top Side Only
1
0
0
25
50
75
100
TA (°C)
125
150
Figure 1. SOT223 Power Dissipation
2
Submit Documentation Feedback
θJA
53°C/W
110°C/W
TPS794xx
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SLVS349E – NOVEMBER 2001 – REVISED DECEMBER 2005
ELECTRICAL CHARACTERISTICS
Over recommended operating temperature range (TJ = –40°C to 125°C), VEN = VIN, VIN = VOUT(nom) + 1 V (1), IOUT = 1mA,
COUT = 10µF, CNR = 0.01 µF, unless otherwise noted. Typical values are at 25°C.
PARAMETER
TEST CONDITIONS
MIN
Input voltage, VIN (1)
Continuous output current, IOUT
Output voltage range
Output
voltage
Accuracy
TPS79401
V
250
mA
1.225
5.5 – VDO
0 µA ≤ IOUT ≤ 250 mA, VOUT + 1 V ≤ VIN ≤ 5.5
0.97(VOUT)
Fixed VOUT
0 µA ≤ IOUT ≤ 250 mA, VOUT + 1 V ≤ VIN ≤ 5.5 V (1)
–3.0
VOUT + 1 V ≤ VIN ≤ 5.5 V
0 µA ≤ IOUT ≤ 250 mA
UNIT
0
V (1)
Load regulation (∆VOUT%/∆IOUT)
MAX
5.5
TPS79401 (2)
Output voltage line regulation (∆VOUT%/∆VIN) (1)
TYP
2.7
VOUT
0.05
V
1.03(VOUT)
V
+3.0
%
0.12
%/V
10
mV
TPS79428
IOUT = 250 mA
155
210
TPS79430
IOUT = 250 mA
155
210
TPS79433
IOUT = 250 mA
145
200
Output current limit
VOUT = 0 V
925
Ground pin current
0 µA ≤ IOUT ≤ 250 mA
170
220
µA
Shutdown current (4)
VEN = 0 V, 2.7 V ≤ VIN ≤ 5.5 V
0.07
1
µA
FB pin current
VFB = 1.225 V
1
µA
Dropout voltage (3)
VIN = VOUT(nom)– 0.1 V
Power-supply ripple rejection
Output noise voltage
Time, start-up
TPS79428
TPS79428
TPS79428
f = 100 Hz, IOUT = 250 mA
65
f = 10 kHz, IOUT = 250 mA
60
f = 100 kHz, IOUT = 250 mA
40
BW = 100 Hz to 100 kHz,
IOUT = 250 mA
RL = 14 Ω, COUT = 1 µF
CNR = 0.001 µF
55
CNR = 0.0047 µF
36
CNR = 0.01 µF
33
CNR = 0.1 µF
32
CNR = 0.001 µF
50
CNR = 0.0047 µF
70
CNR = 0.01 µF
mV
mA
dB
µVRMS
µs
100
High-level enable input voltage
2.7 V ≤ VIN ≤ 5.5 V
1.7
VIN
Low-level enable input voltage
2.7 V ≤ VIN ≤ 5.5 V
0
0.7
V
EN pin current
VEN = 0
1
1
µA
UVLO threshold
VCC rising
UVLO hysteresis
(1)
(2)
(3)
(4)
2.25
2.65
100
V
V
mV
Minimum VIN is 2.7 V or VOUT + VDO, whichever is greater.
Tolerance of external resistors not included in this specification.
Dropout is not measured for the TPS79418 and TPS79425 since minimum VIN = 2.7 V.
For adjustable versions, this applies only after VIN is applied; then VEN transitions high to low.
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TPS794xx
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SLVS349E – NOVEMBER 2001 – REVISED DECEMBER 2005
FUNCTIONAL BLOCK DIAGRAM—ADJUSTABLE VERSION
OUT
IN
Current
Sense
UVLO
SHUTDOWN
ILIM
_
GND
R1
+
FB
EN
UVLO
R2
Thermal
Shutdown
Quickstart
Bandgap
Reference
1.225 V
VIN
250 kΩ
External to
the Device
Vref
NR(1)
(1) Not Available on DCQ (SOT223) options.
FUNCTIONAL BLOCK DIAGRAM—FIXED VERSION
OUT
IN
UVLO
Current
Sense
GND
SHUTDOWN
ILIM
_
EN
+
R1
UVLO
Thermal
Shutdown
R2
Quickstart
VIN
R2 = 40k
Bandgap
Reference
1.225 V
250 kΩ
Vref
NR
Terminal Functions
TERMINAL
4
DESCRIPTION
NAME
DGN
(MSOP)
DCQ
(SOT223)
NR
4
5
Connecting an external capacitor to this pin bypasses noise generated by the internal bandgap, which
improves power-supply rejection and reduces output noise.
EN
6
1
The EN terminal is an input that enables or shuts down the device. When EN is a logic high, the device
is enabled. When the device is a logic low, the device is in shutdown mode.
FB
3
5
Feedback input voltage for the adjustable device.
GND
5, PAD
3, 6
IN
8
2
NC
2, 7
OUT
1
Regulator ground
Unregulated input to the device.
No internal connection.
4
Regulator output
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SLVS349E – NOVEMBER 2001 – REVISED DECEMBER 2005
TYPICAL CHARACTERISTICS
TPS79433
OUTPUT VOLTAGE
vs OUTPUT CURRENT
TPS79428
OUTPUT VOLTAGE
vs JUNCTION TEMPERATURE
3.290
TPS79428
GROUND CURRENT
vs JUNCTION TEMPERATURE
190
2.800
3.285
IOUT = 1 mA
2.795
VIN = 3.8 V,
COUT = 10 µF
185
3.280
180
IOUT = 1 mA
3.270
3.265
3.255
2.780
2.765
50
100
IOUT (mA)
200
250
−40 −25 −10 5
155
150
−40 −25 −10 5
20 35 50 65 80 95 110 125
TJ (°C)
Figure 4.
TPS79428
OUTPUT SPECTRAL
NOISE DENSITY
vs FREQUENCY
TPS79428
OUTPUT SPECTRAL
NOISE DENSITY
vs FREQUENCY
TPS79428
OUTPUT SPECTRAL
NOISE DENSITY
vs FREQUENCY
0.35
Output Spectral Noise Density (µV/√Hz)
0.30
0.25
0.20
IOUT = 250 mA
0.15
0.10
IOUT = 1 mA
0.05
0
1.8
COUT = 10 µF,
CNR = 0.1 µF,
VIN = 3.8 V
0.30
0.25
0.20
IOUT = 1 mA
0.15
0.10
IOUT = 250 mA
0.05
1000
10000
100000
100
1000
10000
COUT = 10 µF,
IOUT = 250 mA
VIN = 3.8 V
1.6
1.4
CNR = 0.001 µF
1.2
CNR = 0.0047 µF
1.0
CNR = 0.01 µF
0.8
CNR = 0.1 µF
0.6
0.4
0.2
0
100
0
100000
1000
10000
100000
Frequency (Hz)
Frequency (Hz)
Frequency (Hz)
Figure 5.
Figure 6.
Figure 7.
TPS79428
ROOT MEAN SQUARED
OUTPUT NOISE vs CNR
TPS79433
OUTPUT IMPEDANCE
vs FREQUENCY
TPS79428
DROPOUT VOLTAGE
vs JUNCTION TEMPERATURE
10
60
250
VIN = 3.8 V,
COUT = 10 µF
VIN = 4.3 V,
COUT = 10 µF,
30
20
200
IOUT = 250 mA
IOUT = 1 mA
1
VDO (mV)
ZO, Output Impedance (Ω)
IOUT = 250 mA,
COUT = 10 µF
40
Figure 8.
0.1
100
50
IOUT = 1 mA
0.020
0.0047
0.01
CNR (µF)
150
IOUT = 250 mA
0.100
10
0
0.001
20 35 50 65 80 95 110 125
TJ (°C)
Figure 3.
COUT = 2.2 µF,
CNR = 0.1 µF,
VIN = 3.8 V
50
IOUT = 250 mA
Figure 2.
0.35
100
170
160
IOUT = 200 mA
Output Spectral Noise Density (µV/√Hz)
0
175
165
2.770
3.250
Output Spectral Noise Density (µV/√Hz)
2.785
2.775
3.260
RMS Output Noise (µVRMS)
VIN = 3.8 V
COUT = 10 µF
IGND (µA)
3.275
V OUT (V)
V OUT (V)
2.790
10
100
1k
10 k
100 k
1M
Frequency (Hz)
Figure 9.
Submit Documentation Feedback
10 M
0
−40 −25 −10 5
20 35 50 65 80 95 110 125
TJ (°C)
Figure 10.
5
TPS794xx
www.ti.com
SLVS349E – NOVEMBER 2001 – REVISED DECEMBER 2005
TYPICAL CHARACTERISTICS (continued)
TPS79433
RIPPLE REJECTION
vs FREQUENCY
TPS79433
RIPPLE REJECTION
vs FREQUENCY
80
70
Ripple Rejection (dB)
IOUT = 10 mA
IOUT = 250 mA
60
50
40
VIN = 4.3 V,
VOUT = 3.3 V,
CIN = 1 µF,
COUT = 10 µF,
CNR = 0.01 µF
10
10
100
50
40
VIN = 4.3 V,
VOUT = 3.3 V,
CIN = 1 µF,
COUT = 2.2 µF,
CNR = 0.01 µF
20
10
10 k
100 k
1M
10
10 M
10
10 k
100 k
1M
0
10 M
10
100
1k
10 k
100 k
Figure 13.
TPS79433
OUTPUT VOLTAGE,
ENABLE VOLTAGE
vs TIME (START-UP)
TPS79433
LINE TRANSIENT
RESPONSE
TPS79433
LOAD TRANSIENT
RESPONSE
VIN (V)
VIN = 4.3 V,
VOUT = 3.3 V,
IOUT = 250 mA,
COUT = 2.2 µF
IOUT = 250 mA,COUT = 10 µF,
CNR = 0.1 µF, dv/dt = 1 V/µs
5.5
10 M
Frequency (Hz)
5.0
250
50
0
4.5
10
3
CNR = 0.0047 µF
2
CNR = 0.001 µF
1
0
−10
0
−50
−20
0
0
80 160 240 320 400 480 560 640 720 800
100
200
300
400
0
500
30
60
90
120
+
0.02A
ms
150
180
Time (µs)
Time (µs)
Figure 14.
Figure 15.
Figure 16.
TPS79425
POWER-UP/
POWER-DOWN
TPS79433
DROPOUT VOLTAGE
vs OUTPUT CURRENT
TPS79401
DROPOUT VOLTAGE
vs INPUT VOLTAGE
Time (µs)
4.5
210
250
200
VOUT = 2.5 V,
RL = 10 Ω
4.0
di
dt
VIN = 4.3 V,
COUT = 10 µF
−30
0
TA = 125°C
TA = 125°C
TA = 25°C
200
3.5
150
VIN
3.0
VDO (mV)
VOUT
2.0
1.5
VDO (mV)
TA = 25°C
2.5
100
150
100
TA = −40°C
TA = −40°C
1.0
50
COUT = 10 µF,
CNR = 0.01 µF,
IOUT = 250 mA
50
0.5
0
−0.5
0
0
1.4
2.8
4.2
5.6
t (ms)
Figure 17.
6
1M
Figure 12.
∆VOUT (mV)
VOUT, VEN (V)
VIN = 4.3 V,
VOUT = 3.3 V,
CIN = 1 µF,
COUT = 2.2 µF,
CNR = 0.1 µF
Figure 11.
6.0
Power-Up (500 mV/div)
30
Frequency (Hz)
V_Enable
0
1k
40
Frequency (Hz)
4
2
100
50
20
0
1k
IOUT = 250 mA
60
IOUT (mA)
20
70
IOUT = 250 mA
60
∆VOUT (mV)
30
70
30
IOUT = 10 mA
80
IOUT = 10 mA
Ripple Rejection (dB)
80
Ripple Rejection (dB)
90
90
90
0
TPS79433
RIPPLE REJECTION
vs FREQUENCY
7.0
8.4
9.8
0
25 50 75 100 125 150 175 200 225 250
IOUT (mA)
Figure 18.
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0
2.5
3.0
3.5
4.0
VIN (V)
Figure 19.
4.5
5.0
TPS794xx
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SLVS349E – NOVEMBER 2001 – REVISED DECEMBER 2005
TYPICAL CHARACTERISTICS (continued)
TPS79428
TYPICAL REGIONS OF STABILITY
EQUIVALENT SERIES RESISTANCE
(ESR)
vs OUTPUT CURRENT
100
COUT = 2.2 µF
TA = −40 to 85°C
10
Region of Instability
1
0.1
Region of Stability
0.01
ESR, Equivalent Series Resistance (Ω)
ESR, Equivalent Series Resistance (Ω)
100
TPS79428
TYPICAL REGIONS OF STABILITY
EQUIVALENT SERIES RESISTANCE
(ESR)
vs OUTPUT CURRENT
COUT = 10 µF
TA = −40 to 85°C
10
Region of Instability
1
0.1
Region of Stability
0.01
0
25 50 75 100 125 150 175 200 225 250
IOUT (mA)
1
10
Figure 20.
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20
40
60 80
IOUT (mA)
120 200 250
Figure 21.
7
TPS794xx
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SLVS349E – NOVEMBER 2001 – REVISED DECEMBER 2005
APPLICATION INFORMATION
The TPS794xx family of low-dropout (LDO)
regulators has been optimized for use in
noise-sensitive equipment. The device features
extremely low dropout voltages, high PSRR, ultralow
output noise, low quiescent current (265 µA
typically), and an enable input to reduce supply
currents
to
less
than
1 µA when the regulator is turned off.
A typical application circuit is shown in Figure 22.
VIN
IN
VOUT
OUT
TPS794xx
1 µF
EN
GND
2.2µF
NR
0.01µF
Figure 22. Typical Application Circuit
EXTERNAL CAPACITOR REQUIREMENTS
A 1-µF or larger ceramic input bypass capacitor,
connected between IN and GND and located close
to the TPS794xx, is required for stability and
improves transient response, noise rejection, and
ripple rejection. A higher-value input capacitor may
be necessary if large, fast-rise-time load transients
are anticipated and the device is located several
inches from the power source.
order for the regulator to operate properly, the
current flow out of the NR pin must be at a minimum,
because any leakage current creates an IR drop
across the internal resistor, thus creating an output
error. Therefore, the bypass capacitor must have
minimal leakage current. The bypass capacitor
should be no more than 0.1-µF in order to ensure
that it is fully charged during the quickstart time
provided by the internal switch shown in the
Functional Block Diagram.
For example, the TPS79430 exhibits only 33 µVRMS
of output voltage noise using a 0.1-µF ceramic
bypass capacitor and a 10-µF ceramic output
capacitor. Note that the output starts up slower as
the bypass capacitance increases because of the RC
time constant at the bypass pin that is created by the
internal 250-kΩ resistor and external capacitor.
BOARD LAYOUT RECOMMENDATION TO
IMPROVE PSRR AND NOISE
PERFORMANCE
To improve ac measurements such as PSRR, output
noise, and transient response, it is recommended
that the board be designed with separate ground
planes for VIN and VOUT, with each ground plane
connected only at the ground pin of the device. In
addition, the ground connection for the bypass
capacitor should connect directly to the ground pin of
the device.
REGULATOR MOUNTING
Like most low-dropout regulators, the TPS794xx
requires an output capacitor connected between
OUT and GND to stabilize the internal control loop.
The minimum recommended capacitance is 1 µF.
Any
1 µF or larger ceramic capacitor is suitable.
The tab of the SOT223-6 package is electrically
connected to ground. For best thermal performance,
the tab of the surface-mount version should be
soldered directly to a circuit-board copper area.
Increasing the copper area improves heat
dissipation.
The internal voltage reference is a key source of
noise in an LDO regulator. The TPS794xx has an
NR pin which is connected to the voltage reference
through a 250-kΩ internal resistor. The 250-kΩ
internal resistor, in conjunction with an external
bypass capacitor connected to the NR pin, creates a
low-pass filter to reduce the voltage reference noise
and, therefore, the noise at the regulator output. In
Solder pad footprint recommendations for the
devices are presented in Application Report
SBFA015, Solder Pad Recommendations for
Surface-Mount Devices, available from the TI web
site (www.ti.com).
8
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SLVS349E – NOVEMBER 2001 – REVISED DECEMBER 2005
PROGRAMMING THE TPS79401
ADJUSTABLE LDO REGULATOR
In order to improve the stability of the adjustable
version, it is suggested that a small compensation
capacitor be placed between OUT and FB.
The output voltage of the TPS79401 adjustable
regulator is programmed using an external resistor
divider as shown in Figure 23. The output voltage is
calculated using Equation 1:
V OUT + VREF
ǒ1 ) RR Ǔ
The approximate value of this capacitor can be
calculated as Equation 3:
(3 10 *7) (R 1 ) R 2)
C1 +
(R 1 R 2)
(3)
1
2
(1)
The suggested value of this capacitor for several
resistor ratios is shown in the table within Figure 23.
If this capacitor is not used (such as in a unity-gain
configuration), then the minimum recommended
output capacitor is 2.2 µF instead of 1 µF.
where:
• VREF = 1.2246 V typ (the internal reference
voltage)
Resistors R1 and R2 should be chosen for
approximately 40-µA divider current. Lower value
resistors can be used for improved noise
performance, but the device wastes more power.
Higher values should be avoided, as leakage current
at FB increases the output voltage error.
REGULATOR PROTECTION
The TPS794xx PMOS-pass transistor has a built-in
back diode that conducts reverse current when the
input voltage drops below the output voltage (for
example, during power down). Current is conducted
from the output to the input and is not internally
limited. If extended reverse voltage operation is
anticipated, external limiting might be appropriate.
The recommended design procedure is to choose
R2 = 30.1 kΩ to set the divider current at 40 µA,
C1 = 15 pF for stability, and then calculate R1 using
Equation 2:
VOUT
R1 +
*1
R2
VREF
ǒ
Ǔ
VIN
(2)
IN
1 µF
The TPS794xx features internal current limiting and
thermal protection. During normal operation, the
TPS794xx limits output current to approximately
2.8 A. When current limiting engages, the output
voltage scales back linearly until the overcurrent
condition ends. While current limiting is designed to
prevent gross device failure, care should be taken
not to exceed the power dissipation ratings of the
package. If the temperature of the device exceeds
approximately 165°C, thermal-protection circuitry
shuts it down. Once the device has cooled down to
below approximately 140°C, regulator operation
resumes.
OUT
TPS79401
EN
GND
OUTPUT VOLTAGE
PROGRAMMING GUIDE
VOUT
R1
C1
2.2 µF
OUTPUT
VOLTAGE
R1
R2
C1
1.8 V
14.0 kΩ
30.1 kΩ
22 pF
3.6 V
61.9 kΩ
30.1 kΩ
15 pF
FB
R2
Figure 23. TPS79401 Adjustable LDO Regulator Programming
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9
TPS794xx
www.ti.com
SLVS349E – NOVEMBER 2001 – REVISED DECEMBER 2005
THERMAL INFORMATION
The amount of heat that an LDO linear regulator
generates is directly proportional to the amount of
power it dissipates during operation. All integrated
circuits have a maximum allowable junction
temperature (TJmax) above which normal operation
is not assured. A system designer must design the
operating environment so that the operating junction
temperature (TJ) does not exceed the maximum
junction temperature (TJmax). The two main
environmental variables that a designer can use to
improve thermal performance are air flow and
external heatsinks. The purpose of this information is
to aid the designer in determining the proper
operating environment for a linear regulator that is
operating at a specific power level.
In general, the maximum expected power (PDmax)
consumed by a linear regulator is computed as
shown in Equation 4:
P D max + ǒVIN(avg) * VOUT(avg)Ǔ
I OUT(avg) ) V I(avg)
IQ
(4)
where:
• VIN(avg) is the average input voltage
• VOUT(avg) is the average output voltage
• IOUT(avg) is the average output current
• IQ is the quiescent current
For most TI LDO regulators, the quiescent current is
insignificant compared to the average output current;
therefore, the term VIN(avg) x IQ can be neglected. The
operating junction temperature is computed by
adding the ambient temperature (TA) and the
increase in temperature due to the regulator's power
dissipation. The temperature rise is computed by
multiplying the maximum expected power dissipation
by the sum of the thermal resistances between the
junction and the case (RΘJC), the case to heatsink
(RΘCS), and the heatsink to ambient (RΘSA). Thermal
resistances are measures of how effectively an
object dissipates heat. Typically, the larger the
device, the more surface area available for power
dissipation and the lower the object's thermal
resistance.
Figure 24 illustrates these thermal resistances for a
SOT223 package mounted in a JEDEC low-K board.
10
A
TJ
RθJC
CIRCUIT BOARD COPPER AREA
C
B
B
TC
RθCS
A
C
RθSA
SOT223 Package
TA
Figure 24. Thermal Resistances
Equation 5 summarizes the computation:
ǒRθJC ) RθCS ) RθSAǓ
T J + T A ) PD max
(5)
The RΘJC is specific to each regulator as determined
by its package, lead frame, and die size provided in
the regulator's data sheet. The RΘSA is a function of
the type and size of heatsink. For example, black
body radiator type heatsinks can have RΘCS values
ranging from 5°C/W for very large heatsinks to
50°C/W for very small heatsinks. The RΘCS is a
function of how the package is attached to the
heatsink. For example, if a thermal compound is
used to attach a heatsink to a SOT223 package,
RΘCS of 1°C/W is reasonable.
Even if no external black body radiator type heatsink
is attached to the package, the board on which the
regulator is mounted provides some heatsinking
through the pin solder connections. Some packages,
like the DDPAK and SOT223 packages, use a
copper plane underneath the package or the circuit
board ground plane for additional heatsinking to
improve their thermal performance. Computer-aided
thermal modeling can be used to compute very
accurate approximations of an integrated circuit's
thermal
performance
in
different
operating
environments (for example, different types of circuit
boards, different types and sizes of heatsinks,
different air flows, etc.). Using these models, the
three thermal resistances can be combined into one
thermal resistance between junction and ambient
(RΘJA). This RΘJA is valid only for the specific
operating environment used in the computer model.
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TPS794xx
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SLVS349E – NOVEMBER 2001 – REVISED DECEMBER 2005
Equation 5 simplifies into Equation 6:
T J + T A ) PD max
RθJA
(6)
Rearranging Equation 6 gives Equation 7:
T * TA
R θJA + J
PD max
(7)
Using Equation 6 and the computer model generated
curves shown in Figure 25, a designer can quickly
compute
the
required
heatsink
thermal
resistance/board area for a given ambient
temperature, power dissipation, and operating
environment.
To illustrate, the TPS79425 in a SOT223 package
was chosen. For this example, the average input
voltage is 3.3 V, the output voltage is 2.5 V, the
average output current is 1 A, the ambient
temperature 55°C, no air flow is present, and the
operating environment is the same as documented
below. Neglecting the quiescent current, the
maximum average power is Equation 8:
P D max + (3.3 * 2.5)V
1A + 800mW
(8)
140
Substituting TJmax for TJ into Equation 4 gives
Equation 9:
R θJA max + (125 * 55)°Cń800mW + 87.5°CńW
120
(9)
100
From Figure 25, RθJA vs PCB Copper Area, the
ground plane needs to be 0.55 in2 for the part to
dissipate 800 mW. The operating environment used
to construct Figure 25 consisted of a board with 1 oz.
copper planes. The package is soldered to a 1 oz.
copper pad on the top of the board. The pad is tied
through thermal vias to the 1 oz. ground plane.
No Air Flow
160
80
60
40
20
0
0.1
1
10
PCB Copper Area (in2)
Figure 25. SOT223 Thermal Resistance vs PCB
Copper Area
SOT223 POWER DISSIPATION
The SOT223 package provides an effective means
of managing power dissipation in surface-mount
From the data in Figure 25 and rearranging equation
6, the maximum power dissipation for a different
ground plane area and a specific ambient
temperature can be computed, as shown in
Figure 26.
PD − Maximum Power Dissipation (W)
RθJA − Thermal Resistance (°C/W)
180
applications. The SOT223 package dimensions are
provided in the Mechanical Data section at the end
of the data sheet. The addition of a copper plane
directly underneath the SOT223 package enhances
the thermal performance of the package.
6
TA = 25°C
5
4
4 in2 PCB Area
3
0.5 in2 PCB Area
2
1
0
0
25
50
75
100
125
150
TA − Ambient Temperature (°C)
Figure 26. SOT223 Maximum Power Dissipation
vs Ambient Temperature
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11
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TPS79401DCQ
ACTIVE
SOT-223
DCQ
6
78
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
PS79401
TPS79401DCQR
LIFEBUY
SOT-223
DCQ
6
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
PS79401
TPS79401DGNR
ACTIVE
HVSSOP
DGN
8
2500
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
AXL
Samples
TPS79401DGNT
ACTIVE
HVSSOP
DGN
8
250
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
AXL
Samples
TPS79418DCQ
ACTIVE
SOT-223
DCQ
6
78
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
PS79418
Samples
TPS79418DCQR
LIFEBUY
SOT-223
DCQ
6
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
PS79418
TPS79418DGNR
ACTIVE
HVSSOP
DGN
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
AXM
Samples
TPS79418DGNT
ACTIVE
HVSSOP
DGN
8
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
AXM
Samples
TPS79425DCQ
ACTIVE
SOT-223
DCQ
6
78
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
PS79425
Samples
TPS79425DCQR
ACTIVE
SOT-223
DCQ
6
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
PS79425
Samples
TPS79425DGNR
ACTIVE
HVSSOP
DGN
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
AYB
Samples
TPS79425DGNT
ACTIVE
HVSSOP
DGN
8
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
AYB
Samples
TPS79428DCQ
ACTIVE
SOT-223
DCQ
6
78
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
PS79428
Samples
TPS79428DCQR
ACTIVE
SOT-223
DCQ
6
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
PS79428
Samples
TPS79428DGNT
LIFEBUY
HVSSOP
DGN
8
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
AYC
TPS79430DCQ
ACTIVE
SOT-223
DCQ
6
78
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
PS79430
Samples
TPS79430DCQR
ACTIVE
SOT-223
DCQ
6
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
PS79430
Samples
TPS79430DGNR
ACTIVE
HVSSOP
DGN
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
AYD
Samples
TPS79430DGNT
ACTIVE
HVSSOP
DGN
8
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
AYD
Samples
TPS79433DCQ
ACTIVE
SOT-223
DCQ
6
78
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
PS79433
Samples
TPS79433DCQR
ACTIVE
SOT-223
DCQ
6
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
PS79433
Samples
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
10-Dec-2022
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TPS79433DGNR
ACTIVE
HVSSOP
DGN
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
AYE
Samples
TPS79433DGNT
ACTIVE
HVSSOP
DGN
8
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
AYE
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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