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TPS795
SLVS350J – OCTOBER 2002 – REVISED MAY 2019
TPS795 Ultralow-Noise, High-PSRR, Fast, RF, 500-mA, Low-Dropout Linear Regulators
1 Features
3 Description
•
•
The TPS795 family of low-dropout (LDO), low-power
linear voltage regulators features high power-supply
rejection ratio (PSRR), ultralow noise, fast start-up,
and excellent line and load transient responses in
small outline, 6-pin SOT-223 and 3-mm × 3-mm
VSON packages. Each device in the family is stable
with a small 1-µF ceramic capacitor on the output.
The family uses an advanced, proprietary BiCMOS
fabrication process to yield extremely low dropout
voltages (for example, 110 mV at 500 mA). Each
device achieves fast start-up times (approximately
50 µs with a 0.001-µF bypass capacitor) while
consuming very low quiescent current (265 µA,
typical). Moreover, when the device is placed in
standby mode, the supply current is reduced to less
than 1 µA. The TPS79530 device exhibits
approximately 33 µVRMS of output voltage noise at 3V output with a 0.1-µF bypass capacitor. Applications
with analog components that are noise-sensitive,
such as portable RF electronics, benefit from the
high-PSRR and low-noise features, as well as from
the fast response time.
1
•
•
•
•
•
•
•
500-mA low-dropout regulator with enable
Available in fixed and adjustable (1.2-V to 5.5-V)
versions
High PSRR (50 dB at 10 kHz)
Ultralow noise (33 µVRMS, TPS79530)
Fast start-up time (50 µs)
Stable with a 1-µF ceramic capacitor
Excellent load and line transient response
Low dropout voltage (110 mV at full load,
TPS79530)
6-pin SOT-223 and 3-mm × 3-mm VSON
packages
2 Applications
•
•
•
•
•
RF: VCOs, receivers, ADCs
Audio
Bluetooth®, wireless LAN
Cellular and cordless telephones
Handheld organizers, PDAs
Device Information(1)
PART NUMBER
TPS795
PACKAGE
BODY SIZE (NOM)
SOT-223 (6)
6.50 mm × 3.50 mm
VSON (8)
3.00 mm × 3.00 mm
(1) For all available packages, see the package option addendum
at the end of the data sheet.
TPS79530 Ripple Rejection vs Frequency
TPS79530 vs Frequency
0.5
VIN = 4 V
COUT = 10mF
CNR = 0.01mF
Ripple Rejection − dB
70
Output Spectral Noise Density − mV/ÖHz
80
IOUT = 1 mA
60
50
40
IOUT = 500 mA
30
20
10
0
1
10
100
1 k 10 k 100 k 1 M
Frequency (Hz)
10 M
VIN = 5.5 V
COUT = 2.2mF
CNR = 0.1mF
0.4
0.3
IOUT = 1 mA
0.2
IOUT = 0.5 A
0.1
0
100
1k
10 k
Frequency (Hz)
100 k
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS795
SLVS350J – OCTOBER 2002 – REVISED MAY 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
6.1
6.2
6.3
6.4
6.5
6.6
3
3
4
4
5
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 10
7.1
7.2
7.3
7.4
Overview .................................................................
Functional Block Diagrams .....................................
Feature Description.................................................
Device Functional Modes........................................
10
10
11
12
8
Application and Implementation ........................ 13
8.1 Application Information............................................ 13
8.2 Typical Application .................................................. 13
8.3 What to Do and What Not to Do ............................. 15
9 Power Supply Recommendations...................... 16
10 Layout................................................................... 16
10.1 Layout Guidelines ................................................. 16
10.2 Layout Examples................................................... 19
11 Device and Documentation Support ................. 21
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Device Support......................................................
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
21
21
21
21
22
22
22
12 Mechanical, Packaging, and Orderable
Information ........................................................... 22
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision I (May 2015) to Revision J
Page
•
Changed DRB package name throughout data sheet from SON to VSON ........................................................................... 1
•
Changed Pin Configuration package names; switched designators to match correct package names (typo) ..................... 3
•
Added note (1) to Recommended Operating Conditions; moved from Electrical Characteristics.......................................... 4
•
Changed thermal values in Thermal Information table........................................................................................................... 4
•
Deleted Input Voltage from Electrical Characteristics; already shown in Recommended Operating Conditions................... 5
•
Deleted Junction Temperature from Electrical Characteristics; already shown in Recommended Operating Conditions..... 5
Changes from Revision H (August 2010) to Revision I
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
•
Changed front-page graphic .................................................................................................................................................. 1
•
Changed Pin Configuration and Functions section; updated table format and added pinout drawings................................. 3
•
Changed "free-air" to "junction" temperature in condition statement for Absolute Maximum Ratings .................................. 3
•
Added Added Operating junction temperature specification to Electrical Characteristics ..................................................... 5
•
Deleted Start-up time symbol ................................................................................................................................................. 5
•
Corrected min value for IEN(HI) parameter ............................................................................................................................... 5
•
Added Thermal shutdown temperature specification to Electrical Characteristics ................................................................ 5
•
Added condition statement to Typical Characteristics section .............................................................................................. 6
•
Changed title for Thermal Protection section ...................................................................................................................... 16
Changes from Revision G (July, 2006) to Revision H
Page
•
Replaced the Dissipation Ratings table with the Thermal Information table .......................................................................... 4
•
Updated the Thermal Protection section .............................................................................................................................. 16
2
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SLVS350J – OCTOBER 2002 – REVISED MAY 2019
5 Pin Configuration and Functions
DRB Package
8-Pin VSON
Top View
DCQ Package
6-Pin SOT-223
Top View
1
8
EN
IN 2
7
N/C
IN
OUT 3
6
GND
OUT 4
5
NR/FB
6
1
3
2
EN
NR/FB
GND
IN
5
4
OUT
Pin Functions
PIN
NAME
VSON
IN
SOT-223
I/O
DESCRIPTION
1, 2
2
I
GND
6
3, 6
—
Unregulated input to the device
EN
8
1
I
NR
5
5
—
FB
5
5
I
Feedback input voltage for the adjustable device.
(Not available on fixed voltage versions.)
OUT
3, 4
4
O
Regulator output
N/C
7
–
—
No internal connection
Regulator ground
Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts the
regulator into shutdown mode. EN can be connected to IN if not used.
Noise-reduction pin for fixed versions only. Connecting an external capacitor to this pin
bypasses noise generated by the internal bandgap, which improves power-supply
rejection and reduces output noise. (Not available on adjustable versions.)
6 Specifications
6.1 Absolute Maximum Ratings
over operating junction temperature range (unless otherwise noted) (1)
MIN
Voltage
MAX
IN
–0.3
6
EN
–0.3
VIN + 0.3
OUT
Peak output
Power dissipation
Continuous total
(1)
V
6
Current
Temperature
UNIT
Internally limited
A
See Thermal Information
Junction, TJ
–40
150
°C
Storage, Tstg
–65
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic
discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1)
±2000
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
over operating junction temperature range (unless otherwise noted)
MIN
(1)
VIN
Input voltage
IOUT
Output current
TJ
Operating junction temperature
(1)
NOM
MAX
UNIT
2.7
5.5
V
0
500
mA
–40
125
°C
Minimum VIN is 2.7 V or VOUT + VDO, whichever is greater.
6.4 Thermal Information
over operating free-air temperature range (unless otherwise noted)
TPS795 (3)
THERMAL METRIC
(1) (2)
DRB (VSON)
DCQ (SOT-223)
UNIT
6 PINS
8 PINS
RθJA
Junction-to-ambient thermal resistance
46.8
74.0
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
45.1
44.5
°C/W
RθJB
Junction-to-board thermal resistance
18.4
8.6
°C/W
ψJT
Junction-to-top characterization parameter
0.7
3.2
°C/W
ψJB
Junction-to-board characterization parameter
18.4
8.5
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
5.3
N/A
°C/W
(1)
(2)
(3)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator.
Thermal data for the DRB and DCQ packages are derived by thermal simulations based on JEDEC-standard methodology as specified
in the JESD51 series. The following assumptions are used in the simulations:
(a) i. DRB: The exposed pad is connected to the PCB ground layer through a 2-mm x 2-mm thermal via array.
. ii. DCQ: The exposed pad is connected to the PCB ground layer through a 3-mm x 2-mm thermal via array.
(b) i. DRB: The top and bottom copper layers are assumed to have a 20% thermal conductivity of copper representing a 20% copper
coverage.
. ii. DCQ: Each of top and bottom copper layers has a dedicated pattern for 20% copper coverage.
(c) These data were generated with only a single device at the center of a JEDEC high-K (2s2p) board with 3in × 3in copper area. To
understand the effects of the copper area on thermal performance, see Thermal Considerations and Estimating Junction Temperature
of this data sheet.
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6.5 Electrical Characteristics
over recommended operating temperature range (TJ = –40°C to 125°C), VEN = VIN, VIN = VOUT(nom) + 1 V (1), IOUT = 1 mA, COUT
= 10 µF, and CNR = 0.01 µF (unless otherwise noted); typical values are at 25°C
PARAMETER
VFB
MIN
TYP
MAX
UNIT
Internal reference (TPS79501)
TEST CONDITIONS
1.200
1.225
1.25
V
Output voltage range
1.225
5.5 – VDO
V
1.02VOUT(nom)
V
TPS79501
TPS79501
(2)
Accuracy
Fixed VOUT < 5 V
(1)
ΔVO(ΔVI)
Line regulation
ΔVO(ΔIO)
Load regulation
0 µA ≤ IOUT ≤ 500 mA,
VOUT(nom) + 1 V ≤ VIN ≤ 5.5 V (1)
0.98VOUT(nom)
0 µA ≤ IOUT ≤ 500 mA,
VOUT(nom) + 1 V ≤ VIN ≤ 5.5 V (1)
–2%
VOUT + 1 V ≤ VIN ≤ 5.5 V
2%
0.05
0 µA ≤ IOUT ≤ 500 mA
(3)
VOUT(nom)
0.12
3
%/V
mV
TPS79530
IOUT = 500 mA
110
170
mV
TPS79533
IOUT = 500 mA
105
160
mV
2.8
4.2
A
VDO
Dropout voltage
(VIN = VOUT(nom) – 0.1 V)
ICL
Output current limit
VOUT = 0 V
IGND
Ground pin current
0 µA ≤ IOUT ≤ 500 mA
265
385
µA
ISHDN
Shutdown current (4)
VEN = 0 V, 2.7 V ≤ VIN ≤ 5.5 V
0.07
1
µA
IFB
Feedback pin current
VFB = 1.225 V
1
µA
PSRR
Vn
Power-supply rejection ratio (TPS79530)
Output noise voltage (TPS79530)
Start-up time (TPS79530)
2.4
f = 100 Hz, IOUT = 10 mA
59
dB
f = 100 Hz, IOUT = 500 mA
58
dB
f = 10 kHz, IOUT = 500 mA
50
dB
f = 100 kHz, IOUT = 500 mA
BW = 100 Hz to
100 kHz,
IOUT = 500 mA
RL = 6 Ω, COUT = 1 µF
39
dB
CNR = 0.001 µF
46
µVRMS
CNR = 0.0047 µF
41
µVRMS
CNR = 0.01 µF
35
µVRMS
CNR = 0.1 µF
33
µVRMS
CNR = 0.001 µF
50
µs
CNR = 0.0047 µF
75
µs
CNR = 0.01 µF
110
VEN(HI)
Enable high (enabled)
2.7 V ≤ VIN ≤ 5.5 V
VEN(LO)
Enable low (shutdown)
2.7 V ≤ VIN ≤ 5.5 V
IEN(HI)
Enable pin current, enabled
VEN = 0 V
–1
UVLO
Undervoltage lockout
VCC rising
2.25
UVLO hysteresis
Tsd
(1)
(2)
(3)
(4)
Thermal shutdown temperature
1.7
µs
VIN
V
0.7
V
1
µA
2.65
V
100
mV
Shutdown, temperature increasing
165
°C
Reset, temperature decreasing
140
°C
Minimum VIN is 2.7 V or VOUT + VDO, whichever is greater.
Tolerance of external resistors not included in this specification.
Dropout is not measured for the TPS79501 and TPS79525 because minimum VIN = 2.7 V.
For adjustable version, this applies only after VIN is applied; then VEN transitions high to low.
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6.6 Typical Characteristics
at VEN = VIN, VIN = VOUT(nom) + 1 V, IOUT = 1 mA, COUT = 10 µF, CNR = 0.01 µF, CIN = 2.2 µF, and TJ = 25°C (unless otherwise
noted)
3.005
3.02
VIN = 4 V
COUT = 10 mF
3
3.01
IOUT = 1 mA
VOUT (V)
2.995
2.99
VOUT (V)
3
IOUT = 0.5 A
2.985
2.98
2.99
2.975
2.98
0
0.1
0.2
0.3
IOUT (mA)
0.4
2.97
0.5
−40 −25 −10 5
TJ (°C)
Figure 1. TPS79530 Output Voltage vs Output Current
Figure 2. TPS79530 Output Voltage vs Junction
Temperature
0.5
276
VIN = 4 V
COUT = 10 mF
Output Spectral Noise Density − mV/√Hz
274
272
IOUT = 1 mA
IGND (mA)
270
268
IOUT = 0.5 A
266
264
262
260
−40 −25 −10 5
20 35 50 65 80 95 110 125
VIN = 5.5 V
COUT = 2.2 mF
CNR = 0.1 mF
0.4
IOUT = 1 mA
0.3
0.2
IOUT = 0.5 A
0.1
0
100
TJ (°C)
1k
10 k
Frequency (Hz)
Figure 3. TPS79530 Ground Current vs Junction
Temperature
Figure 4. TPS79530 Output Spectral Noise Density vs
Frequency
0.5
0.4
IOUT = 1 mA
0.3
0.2
IOUT = 0.5 A
0.1
0
100
100 k
2.5
VIN = 5.5 V
COUT = 10 mF
CNR = 0.1 mF
Output Spectral Noise Density − mV/√Hz
Output Spectral Noise Density − mV/√Hz
0.6
1k
10 k
VIN = 5.5 V
IOUT = 500 mA
COUT= 10 mF
2
CNR = 0.001 mF
CNR = 0.0047 mF
1.5
CNR = 0.01 mF
1
CNR = 0.1 mF
0.5
0
100
100 k
Frequency (Hz)
1k
10 k
100 k
Frequency (Hz)
Figure 5. TPS79530 Output Spectral Noise Density vs
Frequency
6
20 35 50 65 80 95 110 125
Figure 6. TPS79530 Output Spectral Noise Density vs
Frequency
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Typical Characteristics (continued)
50
175
IOUT = 500 mA
COUT= 10 mF
40
125
30
20
75
50
25
BW = 100 Hz to 100 kHz
0
0.001
0.01
0.0047
CNR (mF)
0
−40 −25 −10 5
0.1
20 35 50 65 80 95 110 125
TJ (°C)
Figure 8. TPS79530 Dropout Voltage vs Junction
Temperature
80
80
60
IOUT = 1 mA
50
40
IOUT = 500 mA
30
VIN = 4 V
COUT = 10 mF
CNR = 0.01 mF
70
Ripple Rejection − dB
VIN = 4 V
COUT = 10 mF
CNR = 0.1 mF
70
Ripple Rejection − dB
100
10
Figure 7. TPS79530 Root Mean Squared Output Noise vs
CNR
IOUT = 1 mA
60
50
40
IOUT = 500 mA
30
20
20
10
10
0
0
1
10
100
1 k 10 k 100 k 1 M
Frequency (Hz)
10 M
Figure 9. TPS79530 Ripple Rejection vs Frequency
1
10
100
1 k 10 k 100 k 1 M
Frequency (Hz)
10 M
Figure 10. TPS79530 Ripple Rejection vs Frequency
80
80
VIN = 4 V
COUT = 2.2 mF
CNR = 0.01 mF
IOUT = 1 mA
60
VIN = 4 V
COUT = 2.2 mF
CNR = 0.1 mF
70
Ripple Rejection − dB
70
Ripple Rejection − dB
VIN = 2.9 V
COUT = 10 mF
IOUT = 500 mA
150
VDO (mV)
RMS− Root Mean Squared Output Noise −mVRMS
at VEN = VIN, VIN = VOUT(nom) + 1 V, IOUT = 1 mA, COUT = 10 µF, CNR = 0.01 µF, CIN = 2.2 µF, and TJ = 25°C (unless otherwise
noted)
50
40
30
IOUT = 500 mA
50
40
30
IOUT = 500 mA
20
20
10
10
0
IOUT = 1 mA
60
0
1
10
100
1 k 10 k 100 k 1 M
Frequency (Hz)
10 M
Figure 11. TPS79530 Ripple Rejection vs Frequency
1
10
100
1 k 10 k 100 k 1 M 10 M
Frequency (Hz)
Figure 12. TPS79530 Ripple Rejection vs Frequency
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Typical Characteristics (continued)
at VEN = VIN, VIN = VOUT(nom) + 1 V, IOUT = 1 mA, COUT = 10 µF, CNR = 0.01 µF, CIN = 2.2 µF, and TJ = 25°C (unless otherwise
noted)
20
3
2.50
VOUT (mV)
CNR = 0.001 mF
2.75
CNR = 0.0047 mF
2.25
CNR = 0.01 mF
2
Enable
VIN (V)
1.75
10
0
−10
1.50
−20
1.25
COUT = 10 mF, CNR = 0.01 mF,
IOUT = 0.5 A, dv/dt = 1 V/ms
1
4
VIN (V)
0.75
VIN = 4 V
COUT = 10 mF
IOUT = 0.5 A
0.50
0.25
0
3
2
0
100
200
300
400
0
500 600
50
Figure 13. TPS79530 Start-Up Time
150
200
Figure 14. TPS79518 Line Transient Response
60
VOUT (mV)
30
20
VOUT (mV)
100
t (ms)
t (ms)
10
40
20
0
0
−20
−10
−40
−20
IOUT (A)
5
VIN (V)
−60
COUT = 10 mF, CNR = 0.01 mF,
IOUT = 0.5 A, dv/dt = 1 V/ms
4
0
50
100
t (ms)
150
0
200
200
400
600
800
1000
t (ms)
Figure 15. TPS79530 Line Transient Response
Figure 16. TPS79530 Load Transient Response
4.5
180
VOUT = 2.5 V,
RL = 10 W
4
160
3.5
140
VIN
3
TJ = 125°C
120
TJ = 25°C
2.5
VDO (mV)
VOUT (V)
0
−0.5
3
2
1.5
100
80
60
VOUT
1
TJ = −40°C
0.5
40
0
20
−0.5
0
0
400
800
1200
1600
2000
0
Time (ms)
Figure 17. TPS79525 Power Up and Power Down
8
COUT = 10 mF, CNR = 0.01 mF,
VL = 3.8 V, dv/dt = 0.5 A/ms
0.5
100
200
300
IOUT (mA)
400
500
Figure 18. TPS79530 Dropout Voltage vs Output Current
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Typical Characteristics (continued)
at VEN = VIN, VIN = VOUT(nom) + 1 V, IOUT = 1 mA, COUT = 10 µF, CNR = 0.01 µF, CIN = 2.2 µF, and TJ = 25°C (unless otherwise
noted)
100
200
COUT = 1 mF
COUT = 10 mF,
CNR = 0.01 mF,
IOUT = 50 mA
Region of
Instability
10
150
100
ESR (Ω)
VDO (mV)
TJ = 125°C
TJ = 25°C
50
1
0.01
0
2.5
3
3.5
4
VIN (V)
4.5
0
5
Figure 19. TPS79501 Dropout Voltage vs Input Voltage
100
200
300
IOUT (mA)
400
500
Figure 20. TPS79530 Typical Regions of Stability Equivalent
Series Resistance (ESR) vs Output Current
100
100
COUT = 2.2 mF
COUT = 10 mF
Region of
Instability
10
ESR (Ω)
10
ESR (Ω)
Region of Stability
0.1
TJ = −40°C
1
Region of Stability
0.1
Region of
Instability
1
Region of Stability
0.1
0.01
0.01
1
10
100
0
1000
100
200
300
400
500
IOUT (A)
IOUT (mA)
Figure 21. TPS79530 Typical Regions of Stability Equivalent
Series Resistance (ESR) vs Output Current
Figure 22. TPS79530 Typical Regions of Stability Equivalent
Series Resistance (ESR) vs Output Current
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7 Detailed Description
7.1 Overview
The TPS795 family of LDO regulators combines the high performance required of many RF and precision analog
applications with low current consumption. High PSRR is provided by a high-gain, high-bandwidth error loop with
good supply rejection at very low headroom (VIN – VOUT). A noise-reduction pin is provided to bypass noise
generated by the band-gap reference and to improve PSRR, while a quick-start circuit quickly charges this
capacitor at start-up. All versions have thermal and overcurrent protection, and are fully specified from –40°C to
+125°C.
7.2 Functional Block Diagrams
IN
OUT
300 W
UVLO
Current
Sense
Overshoot
Detect
GND
ILIM
SHUTDOWN
R1
EN
FB
UVLO
Thermal
Shutdown
R2
Quickstart
Bandgap
Reference
1.225 V
VIN
External to
the Device
VREF
250 kW
Figure 23. Functional Block Diagram—Adjustable Version
IN
OUT
300 W
UVLO
Current
Sense
Overshoot
Detect
GND
ILIM
SHUTDOWN
R1
EN
UVLO
Thermal
Shutdown
R2
R2 = 40 kW
Quickstart
VIN
Bandgap
Reference
1.225 V
VREF
NR
250 kW
Figure 24. Functional Block Diagram—Fixed Versions
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7.3 Feature Description
7.3.1 Shutdown
The enable pin (EN) is active high and is compatible with standard and low-voltage TTL-CMOS levels. When
shutdown capability is not required, EN can be connected to IN.
7.3.2 Start-Up
The TPS795 uses a start-up circuit to quickly charge the noise reduction capacitor, CNR, if present (see
Functional Block Diagrams). This circuit allows for the combination of very low output noise and fast start-up
times. The NR pin is high impedance so a low leakage CNR capacitor must be used; most ceramic capacitors are
appropriate for this configuration.
For the fastest start-up, apply VIN first, and then drive the enable pin (EN) high. If EN is tied to IN, start-up is
somewhat slower. To ensure that CNR is fully charged during start-up, use a 0.1-µF or smaller capacitor.
7.3.3 Undervoltage Lockout (UVLO)
The TPS795 uses an undervoltage lockout circuit to keep the output shut off until internal circuitry is operating
properly. The UVLO circuit has approximately 100 mV of hysteresis to help reject input voltage drops when the
regulator first turns on.
7.3.4 Regulator Protection
The TPS795 PMOS-pass transistor has a built-in back diode that conducts reverse current when the input
voltage drops below the output voltage (for example, during power down). Current is conducted from the output
to the input and is not internally limited. If extended reverse voltage operation is anticipated, external limiting
might be appropriate.
The TPS795 features internal current limiting and thermal protection. During normal operation, the TPS795 limits
output current to approximately 2.8 A. When current limiting engages, the output voltage scales back linearly until
the overcurrent condition ends. While current limiting is designed to prevent gross device failure, care should be
taken not to exceed the power dissipation ratings of the package. If the temperature of the device exceeds
approximately 165°C (Tsd), thermal-protection circuitry shuts it down. Once the device has cooled down to less
than approximately 140°C, regulator operation resumes.
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7.4 Device Functional Modes
Table 1 provides a quick comparison between the normal, dropout, and disabled modes of operation.
Table 1. Device Functional Mode Comparison
PARAMETER
OPERATING MODE
VIN
EN
IOUT
TJ
Normal
VIN > VOUT(nom) + VDO
VEN > VEN(HI)
IOUT < ICL
TJ < Tsd
Dropout
VIN < VOUT(nom) + VDO
VEN > VEN(HI)
IOUT < ICL
TJ < Tsd
Disabled
—
VEN < VEN(LO)
—
TJ > Tsd
7.4.1 Normal Operation
The device regulates to the nominal output voltage under the following conditions:
• The input voltage is greater than the nominal output voltage plus the dropout voltage (VOUT(nom) + VDO).
• The enable voltage has previously exceeded the enable rising threshold voltage and not yet decreased below
the enable falling threshold.
• The output current is less than the current limit (IOUT < ICL).
• The device junction temperature is less than the thermal shutdown temperature (TJ < Tsd).
7.4.2 Dropout Operation
If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other
conditions are met for normal operation, the device operates in dropout mode. In this mode, the output voltage
tracks the input voltage. During this mode, the transient performance of the device becomes significantly
degraded because the pass device is in the linear region and no longer controls the current through the LDO.
Line or load transients in dropout can result in large output-voltage deviations.
7.4.3 Disabled
The device is disabled under the following conditions:
• The enable voltage is less than the enable falling threshold voltage or has not yet exceeded the enable rising
threshold.
• The device junction temperature is greater than the thermal shutdown temperature (TJ > Tsd).
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS795 family of LDO regulators has been optimized for use in noise-sensitive equipment. The device
features extremely low dropout voltages, high PSRR, ultralow output noise, low quiescent current (265 µA,
typically), and an enable input to reduce supply currents to less than 1 µA when the regulator is turned off.
8.2 Typical Application
A typical application circuit is shown in Figure 25.
VIN
IN
VOUT
OUT
TPS795xx
1mF
EN
GND
1mF
NR
0.01mF
Figure 25. Typical Application Circuit
8.2.1 Design Requirements
Table 2 lists the design requirements.
Table 2. Design Parameters
PARAMETER
DESIGN REQUIREMENT
Input voltage
3.3 V
Output voltage
2.5 V
Maximum output current
500 mA
8.2.2 Detailed Design Procedure
Select the desired device based on the output voltage.
Provide an input supply with adequate headroom to account for dropout and output current to account for the
GND terminal current, and power the load.
8.2.2.1 Input and Output Capacitor Requirements
Although not required, it is good analog design practice to place a 0.1-µF to 2.2-µF capacitor near the input of
the regulator to counteract reactive input sources. A higher-value input capacitor may be necessary if large, fastrise time load transients are anticipated and the device is located several inches from the power source.
Like most low dropout regulators, the TPS795 requires an output capacitor connected between OUT and GND to
stabilize the internal control loop. The minimum recommended capacitor is 1 µF. Any 1-µF or larger ceramic
capacitor is suitable.
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8.2.2.2 Output Noise
The internal voltage reference is a key source of noise in an LDO regulator. The TPS795 has an NR pin which is
connected to the voltage reference through a 250-kΩ internal resistor. The 250-kΩ internal resistor, in
conjunction with an external bypass capacitor connected to the NR pin, creates a low-pass filter to reduce the
voltage reference noise and, therefore, the noise at the regulator output. For the regulator to operate properly,
the current flow out of the NR pin must be at a minimum, because any leakage current creates an IR drop across
the internal resistor, thus creating an output error. Therefore, the bypass capacitor must have minimal leakage
current. The bypass capacitor should be no more than 0.1 µF to ensure that it is fully charged during the
quickstart time provided by the internal switch shown in Functional Block Diagrams.
For example, the TPS79530 exhibits 40 µVRMS of output voltage noise using a 0.1-µF ceramic bypass capacitor
and a 10-µF ceramic output capacitor. The output starts up slower as the bypass capacitance increases due to
the RC time constant at the bypass pin that is created by the internal 250-kΩ resistor and external capacitor.
8.2.2.3 Dropout Voltage
The TPS795 uses a PMOS pass transistor to achieve a low dropout voltage. When (VIN – VOUT) is less than the
dropout voltage (VDO), the PMOS pass device is in its linear region of operation and rDS(on) of the PMOS pass
element is the input-to-output resistance. Because the PMOS device behaves like a resistor in dropout, VDO
approximately scales with the output current.
As with any linear regulator, PSRR degrades as (VIN – VOUT) approaches dropout. This effect is illustrated in
Figure 9 through Figure 12.
8.2.2.4 Programming the TPS79501 Adjustable LDO Regulator
The output voltage of the TPS79501 adjustable regulator is programmed using an external resistor divider as
shown in Figure 26.
VIN
IN
1μF
OUT
TPS79501
EN
GND
OUTPUT VOLTAGE
PROGRAMMING GUIDE
VOUT
R1
C1
1μF
FB
R2
OUTPUT
VOLTAGE
R1
R2
C1
1.8 V
14.0 kΩ
30.1 kΩ
33 pF
3.6 V
57.9 kΩ
30.1 kΩ
15 pF
Figure 26. Typical Application, Adjustable Output
The output voltage is calculated using Equation 1.
VOUT
§
R1 ·
VREF u ¨ 1
¸
© R2 ¹
where
•
VREF = 1.2246 V typical (the internal reference voltage)
(1)
Resistors R1 and R2 should be chosen for approximately 40-µA divider current. Lower value resistors can be
used for improved noise performance, but the device wastes more power. Higher values should be avoided, as
leakage current at FB increases the output voltage error.
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The recommended design procedure is to choose R2 = 30.1 kΩ to set the divider current at 40 µA, C1 = 15 pF for
stability, and then calculate R1 using Equation 2.
R1
§ VOUT
¨
© VREF
·
1¸ u R2
¹
(2)
To improve the stability of the adjustable version, TI suggests placing a small compensation capacitor between
OUT and FB.
The approximate value of this capacitor can be calculated using Equation 3.
3 u 10
C1
7
u R1 R2
R1 u R2
(3)
The suggested value of this capacitor for several resistor ratios is shown in the table within Figure 26. If this
capacitor is not used (such as in a unity-gain configuration), then the minimum recommended output capacitor is
2.2 µF instead of 1 µF.
8.2.3 Application Curves
80
VIN = 5.5 V
COUT = 10 mF
CNR = 0.1 mF
0.5
0.4
VIN = 4 V
COUT = 10 mF
CNR = 0.1 mF
70
Ripple Rejection − dB
Output Spectral Noise Density − mV/√Hz
0.6
IOUT = 1 mA
0.3
0.2
IOUT = 0.5 A
60
IOUT = 1 mA
50
40
IOUT = 500 mA
30
20
0.1
10
0
100
0
1k
10 k
100 k
1
10
Frequency (Hz)
Figure 27. TPS79530 Output Spectral Noise Density vs
Frequency
100
1 k 10 k 100 k 1 M
Frequency (Hz)
10 M
Figure 28. TPS79530 Ripple Rejection vs Frequency
8.3 What to Do and What Not to Do
Place at least one 1-µF ceramic capacitor as close as possible to the OUT pin of the regulator.
Do not place the output capacitor more than 10 mm away from the regulator.
Connect a 0.1-µF or larger, low equivalent series resistance (ESR) capacitor across the IN pin and GND input of
the regulator.
Do not exceed the absolute maximum ratings.
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9 Power Supply Recommendations
These devices are designed to operate from an input voltage supply range from 2.7 V to 5.5 V. The input voltage
range provides adequate headroom for the device to have a regulated output. This input supply is well-regulated
and stable. If the input supply is noisy, additional input capacitors with low ESR can help improve the output
noise performance.
10 Layout
10.1 Layout Guidelines
10.1.1 Board Layout Recommendation to Improve PSRR and Noise Performance
To improve ac measurements like PSRR, output noise, and transient response, TI recommends designing the
board with separate ground planes for VIN and VOUT, with each ground plane connected only at the ground pin of
the device. In addition, the ground connection for the bypass capacitor should connect directly to the ground pin
of the device.
10.1.2 Regulator Mounting
The tab of the 6-pin SOT-223 package is electrically connected to ground. For best thermal performance, solder
the tab of the surface-mount version directly to a circuit-board copper area. Increasing the copper area improves
heat dissipation.
Solder pad footprint recommendations for the devices are presented in application report SBFA015, Solder Pad
Recommendations for Surface-Mount Devices, available from the TI website (www.ti.com).
10.1.3 Thermal Considerations
Knowing the device power dissipation and proper sizing of the thermal plane that is connected to the tab or pad
is critical to avoiding thermal shutdown and ensuring reliable operation.
Power dissipation of the device depends on input voltage and load conditions and can be calculated using
Equation 4:
PD
VIN VOUT u IOUT
(4)
Power dissipation can be minimized and greater efficiency can be achieved by using the lowest possible input
voltage necessary to achieve the required output voltage regulation.
On the VSON (DRB) package, the primary conduction path for heat is through the exposed pad to the printedcircuit-board (PCB). The pad can be connected to ground or be left floating; however, it should be attached to an
appropriate amount of copper PCB area to ensure the device does not overheat. On the SOT-223 (DCQ)
package, the primary conduction path for heat is through the tab to the PCB. The tab should be connected to
ground. The maximum junction-to-ambient thermal resistance depends on the maximum ambient temperature,
maximum device junction temperature, and power dissipation of the device and can be calculated using
Equation 5:
125qC TA
RTJA
PD
(5)
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Layout Guidelines (continued)
Knowing the maximum RθJA, the minimum amount of PCB copper area needed for appropriate heatsinking can
be estimated using Figure 29.
160
140
qJA (°C/W)
120
100
80
DCQ
60
DRB
40
20
0
0
Note:
2
4
6
2
Board Copper Area (in )
8
10
θJA value at board size of 9 in.2 (that is, 3 in. × 3 in.) is a JEDEC standard.
Figure 29. ΘJA vs Board Size
Figure 29 shows the variation of θJA as a function of ground plane copper area in the board. It is intended only as
a guideline to demonstrate the effect of heat spreading in the ground plane and should not be used to estimate
the thermal performance in real application environments.
NOTE
When the device is mounted on an application PCB, it is strongly recommended to use
ΨJT and ΨJB, as explained in Estimating Junction Temperature.
10.1.4 Estimating Junction Temperature
Using the thermal metrics ΨJT and ΨJB, as shown in Thermal Information, the junction temperature can be
estimated with corresponding formulas (given in Equation 6). For backwards compatibility, an older θJC,Top
parameter is also listed.
YJT: TJ = TT + YJT · PD
YJB: TJ = TB + YJB · PD
where
•
•
•
PD is the power dissipation shown by Equation 5
TT is the temperature at the center-top of the IC package
TB is the PCB temperature measured 1 mm away from the IC package on the PCB surface (see Figure 31) (6)
NOTE
Both TT and TB can be measured on actual application boards using a thermo-gun (an
infrared thermometer).
For more information about measuring TT and TB, see the application note SBVA025, Using New Thermal
Metrics, available for download at www.ti.com.
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Layout Guidelines (continued)
As shown in Figure 30, the new thermal metrics (ΨJT and ΨJB) have little dependency on board size. That is,
using ΨJT or ΨJB with Equation 6 is a good way to estimate TJ by simply measuring TT or TB, regardless of the
application board size.
35
DRB YJT
YJT and YJB (°C/W)
30
25
DRB YJB
20
15
DCQ YJT
DCQ YTB
10
5
0
0
1
2
3
4
5
6
7
8
9
10
2
Board Copper Area (in )
Figure 30. ΨJT and ΨJB vs Board Size
For a more detailed discussion of why TI does not recommend using θJC(top) to determine thermal characteristics,
see the application report SBVA025, Using New Thermal Metrics, available at www.ti.com.
For further information, see the application report SPRA953, IC Package Thermal Metrics, also available on the
TI website.
1mm
TT on Top of IC Surface
X
X
TB
TT
TB on PCB
1mm
(a) Example DRB (SON) Package Measurement
(b) Example DCQ (SOT-223) Package Measurement
Figure 31. Measuring Point for TT and TB
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10.2 Layout Examples
GND PLANE
CIN
TPS79501DRB
VIN
VOUT
IN
1
8
EN
IN
2
7
N/C
OUT
3
6
GND
OUT
4
5
NR/FB
R2
COUT
GND PLANE
R1
Figure 32. TPS79501 (Adjustable Voltage Version)—Layout Example
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Layout Examples (continued)
GND PLANE
CIN
TPS795xxDRB
VIN
VOUT
IN
1
8
EN
IN
2
7
N/C
OUT
3
6
GND
OUT
4
5
NR/FB
CNR
COUT
GND PLANE
Figure 33. TPS795 (Fixed Voltage Versions)—Layout Example
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 Evaluation Modules
An evaluation module (EVM) is available to assist in the initial circuit performance evaluation using the TPS795.
The TPS79501DRBEVM evaluation module related (and user's guide) can be requested at the TI website
through the product folders or purchased directly from the TI eStore.
11.1.1.2 Spice Models
Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of
analog circuits and systems. A SPICE model for the TPS795 is available through the product folders under Tools
& Software.
11.1.2 Device Nomenclature
Table 3. Device Nomenclature (1)
PRODUCT
TPS795xx(x) yyy z
(1)
VOUT
xx(x) is nominal output voltage (for example, 28 = 2.8 V, 285 = 2.85 V, 01 = adjustable).
yyy is package designator.
z is package quantity.
For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
11.2 Documentation Support
11.2.1 Related Documentation
• Texas Instruments, Using New Thermal Metrics application report
• Texas Instruments, IC Package Thermal Metrics application report
• Texas Instruments, TPS78601/TPS79501/TPS79601DRB Evaluation Module user's guide
• Texas Instruments, Using New Thermal Metrics application report
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
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11.5 Trademarks
E2E is a trademark of Texas Instruments.
Bluetooth is a registered trademark of Bluetooth SIG, Inc.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TPS79501DCQ
ACTIVE
SOT-223
DCQ
6
78
RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 125
PS79501
Samples
TPS79501DCQG4
ACTIVE
SOT-223
DCQ
6
78
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
PS79501
Samples
TPS79501DCQR
ACTIVE
SOT-223
DCQ
6
2500
RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 125
PS79501
Samples
TPS79501DRBR
ACTIVE
SON
DRB
8
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
BUH
Samples
TPS79501DRBT
ACTIVE
SON
DRB
8
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
BUH
Samples
TPS79501DRBTG4
ACTIVE
SON
DRB
8
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
BUH
Samples
TPS79516DCQ
ACTIVE
SOT-223
DCQ
6
78
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
PS79516
Samples
TPS79516DCQR
ACTIVE
SOT-223
DCQ
6
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
PS79516
Samples
TPS79518DCQ
ACTIVE
SOT-223
DCQ
6
78
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
PS79518
Samples
TPS79518DCQG4
ACTIVE
SOT-223
DCQ
6
78
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
PS79518
Samples
TPS79518DCQR
ACTIVE
SOT-223
DCQ
6
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
PS79518
Samples
TPS79525DCQ
ACTIVE
SOT-223
DCQ
6
78
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
PS79525
Samples
TPS79525DCQG4
ACTIVE
SOT-223
DCQ
6
78
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
PS79525
Samples
TPS79525DCQR
ACTIVE
SOT-223
DCQ
6
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
PS79525
Samples
TPS79525DCQRG4
ACTIVE
SOT-223
DCQ
6
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
PS79525
Samples
TPS79530DCQ
ACTIVE
SOT-223
DCQ
6
78
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
PS79530
Samples
TPS79530DCQR
ACTIVE
SOT-223
DCQ
6
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
PS79530
Samples
TPS79533DCQ
ACTIVE
SOT-223
DCQ
6
78
RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 125
PS79533
Samples
TPS79533DCQG4
ACTIVE
SOT-223
DCQ
6
78
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
PS79533
Samples
TPS79533DCQR
ACTIVE
SOT-223
DCQ
6
2500
RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 125
PS79533
Samples
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
14-Oct-2022
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
RoHS & Green
NIPDAU
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TPS79533DCQRG4
ACTIVE
SOT-223
DCQ
6
2500
Level-2-260C-1 YEAR
-40 to 125
PS79533
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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