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TPS799-Q1
SBVS097F – MARCH 2008 – REVISED JUNE 2015
TPS799-Q1 200 mA, Low Quiescent Current, Ultralow Noise,
High PSRR, Low Dropout, Linear Regulators
1 Features
3 Description
•
•
The TPS799xx-Q1 family of low-dropout (LDO) lowpower linear regulators offers excellent AC
performance with very low ground current. High
power-supply rejection ratio (PSRR), low noise, fast
start-up, and excellent line and load transient
response are provided while consuming a very low
40-μA (typical) ground current. The TPS799xx-Q1 is
stable with ceramic capacitors and uses an advanced
BiCMOS fabrication process to yield a dropout
voltage of 100 mV (typical) at 200-mA output. The
TPS799xx-Q1 uses a precision voltage reference and
feedback loop to achieve overall accuracy of 2% over
all load, line, process, and temperature variations. It
is fully specified from TJ = –40°C to 125°C and is
offered in low profile thin SOT-23 and 2-mm × 2-mm
SON packages, ideal for wireless handsets and
WLAN cards.
1
•
•
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
200-mA Low-Dropout (LDO) Regulator
With Enable (EN)
Low IQ: 40 μA
Multiple Output Voltage Versions Available:
– Fixed Outputs of 1.2 V to 4.5 V
– Adjustable Outputs from 1.2 V to 6.5 V
High PSRR: 66 dB at 1 kHz, 51 db at 10 kHz
Ultralow Noise: 29.5 μVRMS
Fast Start-Up Time: 45 μs
Stable With a Low ESR, 2-μF (Typical) Output
Capacitance
Excellent Load and Line Transient Response
2% Overall Accuracy (Load, Line, and
Temperature)
Very Low Dropout: 100 mV
Thin SOT-23 and 2-mm × 2-mm SON-6 Packages
2 Applications
•
•
•
VOUT
OUT
GND
NR
TPS799-Q1
SOT (5)
2.90 mm × 1.60 mm
IN
2.2mF
Ceramic
Optional bypass capacitor
to reduce output noise
and increase PSRR.
VOUT =
(R1 + R2)
R2
TPS79901-Q1
GND
´ 1.193
VOUT
OUT
EN
VEN
BODY SIZE (NOM)
2.00 mm × 2.00 mm
Optional input capacitor.
May improve source
impedance, noise, or PSRR.
VIN
TPS799xx-Q1
EN
PACKAGE
SON (6)
Typical Application Circuit
Adjustable Voltage Version
Optional input capacitor.
May improve source
impedance, noise, or PSRR.
IN
PART NUMBER
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Infotainment
Cluster
Advanced Driver Assistance Systems
SPACE
Typical Application Circuit
Fixed Voltage Versions
VIN
Device Information(1)
R1
FB
CFB
2.2mF
Ceramic
R2
VEN
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS799-Q1
SBVS097F – MARCH 2008 – REVISED JUNE 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
4
5
6
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 8
7.1
7.2
7.3
7.4
Overview ................................................................... 8
Functional Block Diagrams ....................................... 8
Feature Description................................................... 9
Device Functional Modes........................................ 10
8
Application and Implementation ........................ 11
8.1 Application Information............................................ 11
8.2 Typical Application .................................................. 11
9 Power Supply Recommendations...................... 13
10 Layout................................................................... 13
10.1
10.2
10.3
10.4
10.5
Layout Guidelines .................................................
Layout Example ....................................................
Thermal Consideration..........................................
Power Dissipation .................................................
Package Mounting ................................................
13
14
14
14
14
11 Device and Documentation Support ................. 15
11.1
11.2
11.3
11.4
11.5
Documentation Support ........................................
Related Links ........................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
15
15
15
15
15
12 Mechanical, Packaging, and Orderable
Information ........................................................... 15
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (January 2012) to Revision F
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
•
Added High PSRR: 51 db at 10 kHz ..................................................................................................................................... 1
Changes from Revision D (June 2011) to Revision E
•
2
Page
Changed CDM ESD rating from 500 V to 1000 V. ................................................................................................................ 4
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SBVS097F – MARCH 2008 – REVISED JUNE 2015
5 Pin Configuration and Functions
DDC Package
5-Pin SOT-23
Top View
IN
1
GND
2
EN
3
5
OUT
4
NR
Pin Functions
PIN
NAME
DESCRIPTION
NO. (SOT) NO. (SON)
IN
1
6
GND
2
3, Pad
Input supply
EN
3
4
Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts the regulator into
shutdown mode. EN can be connected to IN if not used.
NR
4
2
Fixed-voltage versions only; connecting an external capacitor to this pin bypasses noise generated by
the internal bandgap. This capacitor allows output noise to be reduced to very low levels.
FB
4
2
Adjustable version only; this pin is the input to the control loop error amplifier, and is used to set the
output voltage of the device.
OUT
5
1
Output of the regulator. A small capacitor (total typical capacitance ≥ 2 μF ceramic) is needed from
this pin to ground to ensure stability.
N/C
—
5
Not internally connected. This pin must either be left open or tied to GND.
Ground. The pad must be tied to GND.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
VIN
–0.3
7
V
VEN
–0.3
VIN + 0.3
V
VOUT
–0.3
VIN + 0.3
V
Peak output current
Internally limited
Continuous total power dissipation
See Thermal Information
Junction temperature, TJ
–55
150
°C
Storage junction temperature, Tstg
–55
150
°C
(1)
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human body model (HBM), per AEC Q100-002 (1)
±2000
Charged device model (CDM), per AEC Q100-011
±1000
UNIT
V
AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VIN
Input voltage
2.7
6.5
V
IOUT
Output current
0.5
200
mA
TJ
Operating junction temperature
–40
125
°C
6.4 Thermal Information
TPS799xx-Q1
THERMAL METRIC
(1) (2)
DRV (SON)
DDC (SOT-23)
6 PINS
5 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
74.2
178.1
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
58.8
70.7
°C/W
RθJB
Junction-to-board thermal resistance
145.9
73.4
°C/W
ψJT
Junction-to-top characterization parameter
0.2
2.5
°C/W
ψJB
Junction-to-board characterization parameter
54.4
74.1
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
7.2
n/a
°C/W
(1)
(2)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator.
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6.5 Electrical Characteristics
over operating temperature range (TJ = –40°C to 125°C), VIN = VOUT(TYP) + 0.3 V or 2.7 V, whichever is greater; IOUT = 1 mA,
VEN = VIN, COUT = 2.2 μF, CNR = 0.01 μF (unless otherwise noted) For TPS79901, VOUT = 3 V. Typical values are at TJ = 25°C.
PARAMETER
VIN
Input voltage range (1)
VFB
Internal reference (TPS79901)
VOUT
Output voltage range
(TPS79901)
VOUT
Output accuracy
VOUT
TEST CONDITIONS
MIN
TYP
MAX
UNIT
6.5
V
1.217
V
VFB
6.5 – VDO
V
Nominal, TJ = 25°C
–1%
1%
Output accuracy (1)
Over VIN, IOUT, temperature,
VOUT + 0.3 V ≤ VIN ≤ 6.5 V,
500 μA ≤ IOUT ≤ 200 mA
–2%
ΔVOUT%/ ΔVIN
Line regulation (1)
VOUT(NOM) + 0.3 V ≤ VIN ≤ 6.5 V
ΔVOUT%/ ΔIOUT
Load regulation
500 μA ≤ IOUT ≤ 200 mA
VDO
Dropout voltage (2)
(VIN = VOUT(NOM) – 0.1 V)
VOUT < 3.3 V
ICL
Output current limit
VOUT = 0.9 × VOUT(NOM)
IGND
Ground pin current
500 μA ≤ IOUT ≤ 200 mA
ISHDN
Shutdown current (IGND)
VEN ≤ 0.4 V, 2.7 V ≤ VIN ≤ 6.5 V
IFB
Feedback pin current
(TPS79901)
PSRR
Power-supply rejection ratio
VN
Output noise voltage
BW = 10 Hz to 100 kHz, VOUT =
2.8 V
2.7
1.169
VOUT ≥ 3.3 V
IOUT = 200 mA
200
±1%
VIN = 3.85 V,
VOUT = 2.85 V,
CNR = 0.01 μF,
IOUT = 100 mA
0.02
%/V
%/mA
100
175
90
160
400
600
mA
40
60
μA
0.15
1
μA
0.5
μA
f = 100 Hz
70
f = 1 kHz
66
f = 10 kHz
51
f = 100 kHz
VEN(HI)
Enable high (enabled)
VEN(LO)
Enable low (shutdown)
IEN(HI)
Enable pin current, enabled
TSD
Thermal shutdown temperature
TJ
Operating junction temperature
VUVLO
Undervoltage lock-out
VIN rising
VUVLO,hys
Hysteresis
VIN falling
dB
10.5 VOUT
CNR = none
Start-up time
mV
38
CNR = 0.01 μF
VOUT = 2.85 V,
RL = 14 Ω,
COUT = 2.2 μF
2%
0.002
–0.5
TSTR
μVRMS
94 VOUT
CNR = 0.001 μF
45
CNR = 0.047 μF
45
CNR = 0.01 μF
50
CNR = none
(1)
(2)
1.193
μs
50
1.2
VIN
0
VEN = VIN = 6.5 V
0.03
Shutdown, temperature increasing
165
Reset, temperature decreasing
0.4
V
1
μA
°C
145
–40
1.9
°C
125
2.2
V
2.65
70
°C
V
mV
Minimum VIN = VOUT + VDO or 2.7 V, whichever is greater.
VDO is not measured for devices with VOUT(NOM) < 2.8 V because minimum VIN = 2.7 V.
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6.6 Typical Characteristics
28.50
1.0
21.38
0.8
IOUT = 100mA
0.6
14.25
Change in VOUT (%)
Change in VOUT (mV)
Over operating temperature range (TJ = –40°C to 125°C), VIN = VOUT(TYP) + 0.3 V or 2.7 V, whichever is greater; IOUT = 1 mA, VEN = VIN,
COUT = 2.2 μF, CNR = 0.01 μF (unless otherwise noted). For TPS79901, VOUT = 3 V. Typical values are at TJ = 25°C.
TJ = +25°C
7.13
TJ = −40°C
0
-7.13
-14.25
TJ = +125°C
TJ = +25°C
0.2
0
-0.2
TJ = +125°C
-0.4
TJ = +85°C
-0.6
TJ = +85°C
-21.38
TJ = −40°C
0.4
-0.8
-1.0
-28.50
0
50
100
150
2.5
200
3.5
4.5
5.5
6.5
7.5
VIN (V)
IOUT (mA)
Figure 2. Line Regulation
Figure 1. Load Regulation
2.0
110
I OUT = 200mA
100
1.5
IOUT = 1mA
0.5
80
IOUT = 100mA
0
-0.5
VDO (mV)
Change in VOUT (%)
90
1.0
60
50
40
IOUT = 200mA
-1.0
70
30
20
-1.5
10
-2.0
0
-40 -25 -15
5
20
35
50
65
80
95
2.5
110 125
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
VIN (V)
TJ (°C)
Figure 3. Output Voltage vs
Junction Temperature
Figure 4. TPS79901 Dropout vs
Input Voltage
600
60
VEN = 0.4V
500
50
IOUT = 200mA
400
IOUT = 500mA
IGND (nA)
IGND (mA)
40
30
300
20
200
10
100
VIN = 6.5V
VOUT = 2.85V
VIN = 3.2V
0
0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
-40 -25 -15
20
35
50
65
80
95
110 125
TJ (°C)
VIN (V)
Figure 5. Ground Pin Current vs
Input Voltage
6
5
Figure 6. Ground Pin Current (Disabled) vs
Junction Temperature
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Typical Characteristics (continued)
Over operating temperature range (TJ = –40°C to 125°C), VIN = VOUT(TYP) + 0.3 V or 2.7 V, whichever is greater; IOUT = 1 mA,
VEN = VIN, COUT = 2.2 μF, CNR = 0.01 μF (unless otherwise noted). For TPS79901, VOUT = 3 V. Typical values are at
TJ = 25°C.
90
0.1kHz
1kHz
70
70
60
60
50
40
100kHz
10kHz
0.1kHz
80
PSRR (dB)
PSRR (dB)
80
90
1MHz
30
1kHz
10kHz
50
40
30
100kHz
20
10
0
0.0
1MHz
20
CNR = 0.01mF
COUT = 2.2mF
0.5
1.0
CNR = 0.01mF
COUT = 2.2mF
10
1.5
2.0
3.0
2.5
3.5
0
0.0
4.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
VIN - VOUT (V)
VIN - VOUT (V)
Figure 7. Power-Supply Ripple Rejection vs
VIN – VOUT, IOUT = 1 mA
Figure 8. Power-Supply Ripple Rejection vs
VIN – VOUT, IOUT = 100 mA
4.0
90
80
0.1kHz
1kHz
70
PSRR (dB)
60
10kHz
50
40
30
CNR = 0.01mF
COUT = 2.2mF
10
0
0.0
100kHz
1MHz
20
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
VIN - VOUT (V)
Figure 9. Power-Supply Ripple Rejection vs
VIN – VOUT, IOUT = 200 mA
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7 Detailed Description
7.1 Overview
The TPS799xx-Q1 family of low-dropout (LDO) regulators combines the high performance required of many RF
and precision analog applications with ultralow current consumption. High PSRR is provided by a high-gain, highbandwidth error loop with good supply rejection at very low headroom (VIN – VOUT). A noise-reduction pin is
provided to bypass noise generated by the band-gap reference and to improve PSRR, while a quick-start circuit
quickly charges this capacitor at start-up. The combination of high performance and low ground current also
make these devices an excellent choice for portable applications. All versions have thermal and overcurrent
protection, and are fully specified from –40°C to 125°C.
The TPS799xx-Q1 family also features inrush current protection with an EN toggle start-up, and overshoot
detection at the output. When the EN toggle is used to start the device, current limit protection is immediately
activated, restricting the inrush current to the device. If voltage at the output overshoots 5% from the nominal
value, a pulldown resistor reduces the voltage to normal operating conditions, as shown in Functional Block
Diagrams.
7.2 Functional Block Diagrams
IN
OUT
400W
2mA
Current
Limit
Overshoot
Detect
Thermal
Shutdown
EN
UVLO
Quickstart
1.193V
Bandgap
NR
500k
GND
Figure 10. Fixed-Voltage Version
8
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Functional Block Diagrams (continued)
IN
OUT
400W
3.3MW
Current
Limit
Thermal
Shutdown
EN
Overshoot
Detect
UVLO
1.193V
Bandgap
FB
500k
GND
Figure 11. Adjustable-Voltage Version
7.3 Feature Description
7.3.1 Internal Current Limit
The TPS799xx-Q1 internal current limit helps protect the regulator during fault conditions. During current limit,
the output sources a fixed amount of current that is largely independent of output voltage. For reliable operation,
the device should not be operated in current limit for extended periods of time.
The PMOS pass element in the TPS799xx-Q1 has a built-in body diode that conducts current when the voltage
at OUT exceeds the voltage at IN. This current is not limited, so if extended reverse voltage operation is
anticipated, external limiting may be appropriate.
7.3.2 Shutdown
The enable pin (EN) is active high and is compatible with standard and low voltage TTL-CMOS levels. When
shutdown capability is not required, EN can be connected to IN.
7.3.3 Dropout Voltage
The TPS799xx-Q1 uses a PMOS pass transistor to achieve low dropout. When (VIN – VOUT) is less than the
dropout voltage (VDO), the PMOS pass device is in its linear region of operation and the input-to-output
resistance is the RDS, ON of the PMOS pass element. Because the PMOS device behaves like a resistor in
dropout, VDO scales approximately with output current.
As with any linear regulator, PSRR and transient response are degraded as (VIN – VOUT) approaches dropout.
This effect is shown in Figure 7 through Figure 9 in the Typical Characteristics section.
7.3.4 Start-Up
Fixed voltage versions of the TPS799xx-Q1 use a quick-start circuit to fast-charge the noise reduction capacitor,
CNR, if present (see Figure 10). This allows the combination of very low output noise and fast start-up times. The
NR pin is high impedance so a low leakage CNR capacitor must be used; most ceramic capacitors are
appropriate in this configuration.
For the fastest start-up, VIN should be applied first, then the enable pin (EN) driven high. If EN is tied to IN,
startup is somewhat slower. The quick-start switch is closed for approximately 135 μs. To ensure that CNR is fully
charged during the quick-start time, a 0.01 μF or smaller capacitor should be used.
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Feature Description (continued)
7.3.5 Undervoltage Lockout (UVLO)
The TPS799xx-Q1 utilizes a UVLO circuit to keep the output shut off until internal circuitry is operating properly.
The UVLO circuit has a deglitch feature so that it typically ignores undershoot transients on the input if they are
less than 50-μs duration.
7.4 Device Functional Modes
Driving EN over 1.2 V turns on the regulator. Driving EN below 0.4 V puts the regulator into shutdown mode,
thus reducing the operating current to 150 nA, nominal.
10
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS799xx-Q1 family of LDO regulators combines the high performance required of many RF and precision
analog applications with ultralow current consumption. High PSRR is provided by a high gain, high bandwidth
error loop with good supply rejection at very low headroom (VIN – VOUT). Fixed-voltage versions provide a noise
reduction pin to bypass noise generated by the bandgap reference and to improve PSRR while a quick-start
circuit fast-charges this capacitor at start-up. The combination of high performance and low ground current also
make the TPS799xx-Q1 an excellent choice for portable applications. All versions have thermal and overcurrent
protection and are fully specified from –40°C to 125°C.
Figure 12 shows the basic circuit connections for fixed-voltage model. Figure 13 gives the connections for the
adjustable output version (TPS79901). R1 and R2 can be calculated for any output voltage using the formula in
Figure 13. Sample resistor values for common output voltages are shown in Figure 13.
8.2 Typical Application
Optional input capacitor.
May improve source
impedance, noise, or PSRR.
VIN
IN
VOUT
OUT
TPS799xx
EN
VEN
GND
2.2µF
Ceramic
NR
Optional bypass capacitor
to reduce output noise
and increase PSRR.
Figure 12. Typical Application Circuit for
Fixed-Voltage Version
Optional input capacitor.
May improve source
impedance, noise, or PSRR.
VIN
IN
EN
VOUT =
OUT
TPS79901
GND
(R1 + R2)
R2
´ 1.193
VOUT
R1
CFB
FB
2.2mF
Ceramic
R2
VEN
Figure 13. Typical Application Circuit for
Adjustable-Voltage Version
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Typical Application (continued)
8.2.1 Design Requirements
Select the desired device based on the output voltage. Provide an input supply with adequate headroom to
account for dropout and output current to account for the GND terminal current, and power the load.
8.2.2 Detailed Design Procedure
8.2.2.1 Input and Output Capacitor Requirements
Although an input capacitor is not required for stability, it is good analog design practice to connect a 0.1-μF to 1μF low ESR capacitor across the input supply near the regulator. This counteracts reactive input sources and
improve transient response, noise rejection, and ripple rejection. A higher-value capacitor may be necessary if
large, fast rise-time load transients are anticipated or the device is located several inches from the power source.
If source impedance is not sufficiently low, a 0.1-μF input capacitor may be necessary to ensure stability.
The TPS799xx-Q1 is designed to be stable with standard ceramic capacitors of values 2.2 μF or larger. X5R and
X7R type capacitors are best as they have minimal variation in value and ESR over temperature. Maximum ESR
should be
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