TPS7A02
SBVS277C – JULY 2019 – REVISED SEPTEMBER 2022
TPS7A02 Nanopower IQ, 25-nA, 200-mA, Low-Dropout Voltage Regulator With Fast
Transient Response
1 Features
3 Description
•
•
•
The TPS7A02 is an ultra-small, ultra-low quiescent
current low-dropout linear regulator (LDO) that can
source 200 mA with excellent transient performance.
•
•
•
•
•
•
The TPS7A02, with an ultra-low IQ of 25 nA, is
designed specifically for applications where very-low
quiescent current is a critical parameter. This device
maintains low IQ consumption even in dropout mode
to further increase battery life. When in shutdown or
disabled mode, the device consumes ultra-low,
3-nA IQ that helps increase the shelf life of the battery.
The TPS7A02 has an output range of 0.8 V to 5.0
V available in 50-mV steps to support the lower core
voltages of modern microcontrollers (MCUs).
2 Applications
Wearables electronics
Thermostats, smoke and heat detectors
Gas, heat, and water meters
Blood glucose monitors and pulse oximeters
Residential circuit breakers and fault indicators
Building security and video surveillance devices
EPOS card readers
The TPS7A02 is fully specified for TJ = –40°C to
+125°C operation.
Package Information(1)
PART NUMBER
TPS7A02
(1)
400
250
350
200
300
150
250
100
200
50
150
0
100
-50
50
-100
0
-150
-50
-200
-100
-250
VOUT
IOUT -300
-350
700 800
-150
-200
-200 -100
0
100
200 300 400
Time (µs)
500
600
PACKAGE
BODY SIZE (NOM)
DQN (X2SON, 4)
1.00 mm × 1.00 mm
YCH (DSBGA, 4)
0.64 mm × 0.64 mm
DBV (SOT-23, 5)
2.90 mm × 1.60 mm
For all available packages, see the package option
addendum at the end of the data sheet.
102
100
Output Current (mA)
AC-Coupled Output Voltage (mV)
•
•
•
•
•
•
•
The TPS7A02 features a smart enable circuit with an
internally controlled pulldown resistor that keeps the
LDO disabled even when the EN pin is left floating
and helps minimize the external components used to
pulldown the EN pin. This circuit also helps minimize
the current drawn through the external pulldown
circuit when the device is enabled.
Load Transient Response (VIN = VOUT + 1 V, COUT =
1 µF, IOUT = 1 mA to 50 mA in 1 µs)
Current Efficiency (%)
•
Ultra-low IQ: 25 nA (typ), even in dropout
Shutdown IQ: 3 nA (typ)
Excellent transient response (1 mA to 50 mA)
– < 10-µs settling time
– 100-mV undershoot
Packages:
– 1.0-mm × 1.0-mm X2SON
– SOT23-5
– 0.64-mm × 0.64-mm DSBGA
Input voltage range: 1.5 V to 6.0 V
Output voltage range: 0.8 V to 5.0 V (fixed)
Output accuracy: 1.5% over temperature
Smart enable pulldown
Very low dropout:
– 270 mV (max) at 200 mA (VOUT = 3.3 V)
Stable with a 1-µF or larger capacitor
98
96
94
92
90
88
TJ
-55°C
-40°C
86
84
0.001
0.01
0°C
25°C
85°C
125°C
0.1
1
Output Current (mA)
10
140°C
100
Curr
Ground Current Efficiency vs Output Current
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS7A02
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SBVS277C – JULY 2019 – REVISED SEPTEMBER 2022
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................6
6.6 Switching Characteristics............................................7
6.7 Typical Characteristics................................................ 8
7 Detailed Description......................................................18
7.1 Overview................................................................... 18
7.2 Functional Block Diagram......................................... 18
7.3 Feature Description...................................................19
7.4 Device Functional Modes..........................................22
8 Application and Implementation.................................. 23
8.1 Application Information............................................. 23
8.2 Typical Application.................................................... 26
8.3 Power Supply Recommendations.............................27
8.4 Layout....................................................................... 27
9 Device and Documentation Support............................29
9.1 Device Support......................................................... 29
9.2 Receiving Notification of Documentation Updates....29
9.3 Support Resources................................................... 29
9.4 Trademarks............................................................... 29
9.5 Electrostatic Discharge Caution................................29
9.6 Glossary....................................................................29
10 Mechanical, Packaging, and Orderable
Information.................................................................... 29
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (March 2020) to Revision C (September 2022)
Page
• Changed YCH (DGBGA) package from preview to production data.................................................................. 1
Changes from Revision A (December 2019) to Revision B (March 2020)
Page
• Changed DBV (SOT23-5) package from preview to production data.................................................................1
2
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5 Pin Configuration and Functions
OUT
1
4
IN
Thermal Pad
GND
2
3
EN
IN
1
GND
2
EN
3
Not to scale
5
OUT
4
NC
Not to scale
Figure 5-1. DQN Package, 1-mm × 1-mm, 4-Pin
X2SON (Top View)
Figure 5-2. DBV Package, 5-Pin SOT-23 (Top View)
Table 5-1. Pin Functions: DQN, DBV
PIN
DQN
DBV
I/O(1)
EN
3
3
Input
GND
2
2
—
NAME
DESCRIPTION
Enable pin. Driving this pin to logic high enables the device; driving this pin to logic low
or floating this pin disables the device. This pin features an internal pulldown resistor,
which is disconnected when EN is driven high externally and the device has started up.
Ground pin. This pin must be connected to ground on the board.
Input pin. For best transient response and to minimize input impedance, use
the recommended value or larger ceramic capacitor from IN to ground; see the
Recommended Operating Conditions table. Place the input capacitor as close to the
input of the device as possible.
IN
4
1
Input
NC
—
4
—
No connect pin. This pin is not internally connected. Connect to ground or leave floating.
OUT
1
5
Output
Regulated output pin. A 0.5-µF or greater effective capacitance is required from OUT to
ground for stability. For best transient response, use a 1-µF or larger ceramic capacitor
from OUT to ground. Place the output capacitor as close to output of the device as
possible; see the Recommended Operating Conditions table.
––
—
Thermal pad
(1)
Connect the thermal pad to a large-area ground plane. The thermal pad is internally
connect to ground.
NC = No internal connection.
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1
2
A
IN
OUT
B
EN
GND
1
2
B
EN
GND
A
IN
OUT
Not to scale
Not to scale
Figure 5-3. YCH Package, 4-Pin DSBGA, 0.35-mm
Pitch (Top View)
Figure 5-4. YCH Package, 4-Pin DSBGA, 0.35-mm
Pitch (Bottom View)
Table 5-2. Pin Functions: YCH
PIN
YCH
NAME
I/O
DESCRIPTION
A1
IN
Input
Input pin. For best transient response and to minimize input impedance, use the recommended
value or larger ceramic capacitor from IN to ground; see the Recommended Operating
Conditions table. Place the input capacitor as close to input of the device as possible.
A2
OUT
Output
Regulated output pin. A 0.5-µF or greater effective capacitance is required from OUT to ground
for stability. For best transient response, use a 1-µF or larger ceramic capacitor from OUT
to ground. Place the output capacitor as close to output of the device as possible; see the
Recommended Operating Conditions table.
B1
EN
Input
B2
GND
—
Enable pin. Driving this pin to logic high enables the device; driving this pin to logic low or floating
this pin disables the device. This pin features an internal pulldown resistor, which is disconnected
when EN is driven high externally and the device has started up.
Ground pin. This pin must be connected to ground and the thermal pad.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
Voltage
Current
(2)
MAX
–0.3
6.5
VEN
–0.3
6.5
VOUT
–0.3
VIN + 0.3 or 5.5(2)
Maximum output
Temperature
(1)
MIN
VIN
UNIT
V
Internally limited
A
Operating junction, TJ
–40
150
Storage, Tstg
–65
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
Maximum is VIN + 0.3 V or 5.5 V, whichever is smaller.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
4
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±1000
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safemanufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safemanufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
over operating junction temperature range (unless otherwise noted)
MIN
VIN
Input voltage
VEN
NOM
MAX
UNIT
1.5
6.0
V
Enable voltage
0
6.0
V
VOUT
Output voltage
0.8
5.0
V
IOUT
Output current
0
200
mA
CIN
Input capacitor
COUT
Output capacitor(1) (2)
FEN
EN toggle frequency
TJ
Operating junction temperature
(1)
(2)
1
1
µF
1
–40
22
µF
10
kHz
125
°C
Effective output capacitance of 0.5 µF minimum required for stability.
22 µF is the maximum derated capacitance that can be used for stability.
6.4 Thermal Information
TPS7A02
THERMAL METRIC(1)
DQN (X2SON)
DBV (SOT-23-5)
YCH (DSBGA)
UNIT
4 PINS
5 PINS
4 PINS
RθJA
Junction-to-ambient thermal resistance
179.1
181.9
201.1
°C/W
RθJC(top)
Junction-to-case(top) thermal resistance
137.6
53.0
2.3
°C/W
RθJB
Junction-to-board thermal resistance
116.3
88.1
67.3
°C/W
ψJT
Junction-to-top characterization parameter
6.1
27.1
1.1
°C/W
ψJB
Junction-to-board characterization parameter
116.3
52.7
67.2
°C/W
RθJC(bot)
Junction-to-case(bottom) thermal resistance
112.3
N/A
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
Specified at TJ = –40°C to +125°C, VIN = VOUT(nom) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA, VEN = VIN, and CIN =
COUT = 1 µF (unless otherwise noted). Typical values are at TJ = 25°C.
PARAMETER
Nominal accuracy
Accuracy over
temperature
TEST CONDITIONS
MIN
TJ = 25°C, VOUT ≥ 1.5 V, 1 µA(3) ≤ IOUT ≤ 1 mA
–15
15
mV
1.5
%
–20
20
mV
5
mV
TJ = –40°C to +125°C
VOUT < 1.5 V
ΔVOUT(ΔIOUT)
Load regulation(2)
1 mA ≤ IOUT ≤ 200 mA,
VIN = VOUT(nom) + 0.5 V(1)
IGND
Ground current
IOUT = 0 mA
IGND/IOUT
Ground current vs
load current
TJ = –40°C to +125°C
TJ = –40°C to +85°C
20
TJ = –40°C to +125°C
TJ = 25°C
25
TJ = –40°C to +85°C
46
60
5 µA ≤ IOUT < 1 mA
1 mA ≤ IOUT < 100 mA
38
50
mV
nA
1
TJ = 25°C
0.25
IOUT ≥ 100 mA
%
0.15
IGND(DO)
Ground current in
dropout(3)
IOUT = 0 mA, VIN = 95% x VOUT (NOM)
ISHDN
Shutdown current
VEN = 0 V, 1.5 V ≤ VIN ≤ 5.0 V, TJ = 25°C
Output current limit VOUT = 90% × VOUT(nom)
TJ = 25°C
VOUT < 2.5V,
VIN = VOUT(nom) +
VDO(max) + 1.0 V
VOUT ≥ 2.5V,
VIN = VOUT(nom) +
VDO(max) + 0.5 V
25
nA
3
10
nA
240
450
750
mA
240
450
750
mA
Short-circuit current
VOUT = 0 V
limit
65
TJ = –40°C to +85°C
Dropout voltage(4)
TJ = –40°C to +125°C
6
%
–1.5
Line regulation
VDO
1
VOUT ≥ 1.5 V
ΔVOUT(ΔVIN)
ISC
MAX UNIT
TJ = 25°C; VOUT < 1.5 V
VOUT(nom) + 0.5 V ≤ VIN ≤ 6.0 V(1)
ICL
TYP
–1
mA
0.8 V ≤ VOUT < 1.0 V
1050
1.0 V ≤ VOUT < 1.2 V
790
1.2 V ≤ VOUT < 1.5 V
650
1.5 V ≤ VOUT < 1.8 V
490
1.8 V ≤ VOUT < 2.5 V
400
2.5 V ≤ VOUT < 3.3 V
310
3.3 V ≤ VOUT ≤ 5.0 V
270
0.8 V ≤ VOUT < 1.0 V
1100
1.0 V ≤ VOUT < 1.2 V
850
1.2 V ≤ VOUT < 1.5 V
700
1.5 V ≤ VOUT < 1.8 V
560
1.8 V ≤ VOUT < 2.5 V
450
2.5 V ≤ VOUT < 3.3 V
360
3.3 V ≤ VOUT ≤ 5.0 V
310
PSRR
Power-supply
rejection ratio
f = 1 kHz, IOUT = 30 mA
VN
Output voltage
noise
BW = 10 Hz to 100 kHz, VOUT = 0.8 V, IOUT = 30 mA
VUVLO
UVLO threshold
VUVLO(HYST)
UVLO hysteresis
55
dB
130
µVRMS
VIN rising
1.23
1.3
1.47
VIN falling
1.0
1.12
1.41
VIN hysteresis
180
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V
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6.5 Electrical Characteristics (continued)
Specified at TJ = –40°C to +125°C, VIN = VOUT(nom) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA, VEN = VIN, and CIN =
COUT = 1 µF (unless otherwise noted). Typical values are at TJ = 25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
VEN(HI)
EN pin logic high
voltage
VEN(LOW)
EN pin logic low
voltage
IEN
EN pin leakage
current
VEN = VIN = 6.0 V
REN(PULLDOWN)
Smart enable
pulldown resistor
VEN = 0.3 V
RPULLDOWN
Pulldown resistor
VIN = 3.3 V, device disabled
TSD(shutdown)
Thermal shutdown
temperature
Shutdown, temperature increasing
170
TSD(reset)
Thermal shutdown
reset temperature
Reset, temperature decreasing
145
(1)
(2)
(3)
(4)
MAX UNIT
1.1
V
0.3
V
10
nA
500
KΩ
60
Ω
°C
VIN = 2.0 V for VOUT ≤ 1.5 V.
Load Regulation is normalized to the output voltage at IOUT = 1 mA.
Specified by design
Dropout is measured by ramping VIN down until VOUT = VOUT (nom) x 95%, with IOUT = 200 mA.
6.6 Switching Characteristics
Specified at TJ = –40°C to +125°C, VIN = VOUT(nom) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA, VEN = VIN, and CIN =
COUT = 1 µF (unless otherwise noted). Typical values are at TJ = 25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
500
800
1.5V < VOUT ≤ 3.0 V
750
1200
3.0V < VOUT ≤ 5.0 V
1200
1600
0.8V ≤ VOUT ≤ 1.5 V
tSTR
Start-up time
From EN assertion to VOUT = 90% × VOUT(nom)
UNIT
µs
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6.7 Typical Characteristics
at operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(nom) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA,
VEN = VIN, and CIN = COUT = 1 µF (unless otherwise noted)
60
-55°C
-40°C
85°C
Quiescent Current (nA)
Quiescent Current (nA)
50
TJ
0°C
25°C
40
30
20
10
0
1.5
2
2.5
3
3.5
4
4.5
Input Voltage (V)
5
5.5
6
700
650
600
550
500
450
400
350
300
250
200
150
100
50
0
1.5
TJ
125°C
140°C
2
2.5
5
5.5
6
180
200
Figure 6-2. IQ vs VIN and Temperature
Figure 6-1. IQ vs VIN and Temperature
500000
500
-55°C
-40°C
0°C
TJ
25°C
85°C
125°C
TJ
450
140°C
-55°C
-40°C
400
Ground Current (PA)
Ground Current (nA)
3.5
4
4.5
Input Voltage (V)
IOUT = 0 mA, VEN = VIN
IOUT = 0 mA, VEN = VIN
100000
3
10000
1000
0°C
25°C
85°C
125°C
140°C
350
300
250
200
150
100
100
50
10
0.001
0
0.01
0.1
1
Output Current (mA)
10
0
100200
20
40
60
80 100 120 140
Output Current (mA)
VOUT = 1.8 V, VIN = VEN = 2.3 V
VOUT = 1.8 V, VIN = VEN = 2.3 V
Figure 6-3. IQ vs IOUT and Temperature up to 200 mA
Figure 6-4. IQ vs IOUT and Temperature Up to 200 mA
5000
25
TJ
-55°C
-40°C
0°C
25°C
TJ
85°C
125°C
140°C
-55°C
-40°C
20
Ground Current (PA)
Ground Current (nA)
4000
3000
2000
1000
0°C
25°C
85°C
125°C
140°C
15
10
5
0
0
0.2
0.4
0.6
Output Current (mA)
0.8
1
0
1
VOUT = 1.8 V, VIN = VEN = 2.3 V
3
5
7
Output Current (mA)
9
10
VOUT = 1.8 V, VIN = VEN = 2.3 V
Figure 6-5. IQ vs IOUT and Temperature Up to 1 mA
8
160
Figure 6-6. IQ vs IOUT and Temperature for 1 mA to 10 mA
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6.7 Typical Characteristics (continued)
at operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(nom) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA,
VEN = VIN, and CIN = COUT = 1 µF (unless otherwise noted)
60
300
85°C
TJ
125°C
140°C
250
Quiescent Current (nA)
50
Quiescent Current (nA)
TJ
0°C
25°C
-55°C
-40°C
40
30
20
200
150
100
50
10
0
1.5
2
2.5
3
3.5
Input Voltage (V)
4
4.5
0
1.5
5
2
2.5
4
4.5
5
VOUT = 5.0 V, VEN = VIN
VOUT = 5.0 V, VEN = VIN
Figure 6-8. IQ in Dropout vs VIN and Temperature
Figure 6-7. IQ in Dropout vs VIN and Temperature
6
4000
TJ
-55°C
-40°C
0°C
25°C
85°C
125°C
TJ
-55°C
-40°C
140°C
5
3000
Quiescent Current (nA)
Quiescent Current (nA)
3
3.5
Input Voltage (V)
2000
1000
0°C
25°C
4
3
2
1
0
1.5
2
2.5
3
3.5
4
4.5
Input Voltage (V)
5
5.5
0
1.5
6
2
2.5
3
IOUT = 0 mA, VEN = 1.1 V
TJ
AC-Coupled Output Voltage (mV)
250
200
150
100
50
400
250
350
200
300
150
250
100
200
50
150
0
100
-50
50
-100
0
-150
-50
-200
-100
-250
-150
2
2.5
3
3.5
4
4.5
Input Voltage (V)
5
6
5.5
6
-200
-200 -100
0
100
200 300 400
Time (µs)
500
600
Output Current (mA)
Quiescent Current (nA)
140°C
300
0
1.5
5.5
Figure 6-10. ISHDN vs VIN and Temperature
400
85°C
125°C
5
VEN = 0 V
Figure 6-9. IQ vs VIN and Temperature
350
3.5
4
4.5
Input Voltage (V)
VOUT
IOUT -300
-350
700 800
VOUT = 1.8 V, VIN = 2.8 V, COUT = 1 µF, tr = tf = 1 µs
VEN = 0 V
Figure 6-11. ISHDN vs VIN and Temperature
Figure 6-12. IOUT Transient From 1 mA to 50 mA
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6.7 Typical Characteristics (continued)
400
250
200
350
200
300
150
300
150
250
100
250
100
200
50
200
50
150
0
150
0
100
-50
100
-50
50
-100
0
-150
-50
-200
-100
-250
-150
-200
-200 -100
0
100
200 300 400
Time (µs)
500
600
AC-Coupled Output Voltage (mV)
250
350
VOUT
IOUT -300
-350
700 800
-100
0
-150
-50
-200
-100
-250
-150
-200
-200 -100
Load
0
100
200 300 400
Time (µs)
500
600
VOUT
IOUT -300
-350
700 800
VOUT = 1.8 V, VIN = 2.8 V, COUT = 1 µF, tr = tf = 1 µs
VOUT = 1.8 V, VIN = 2.8 V, COUT = 1 µF, tr = tf = 1 µs
Figure 6-14. IOUT Transient From 1 mA to 200 mA
Figure 6-13. IOUT Transient From 1 mA to 100 mA
200
100
75
175
75
200
50
150
50
160
25
125
25
120
0
100
0
80
-25
40
-50
0
-75
-40
-100
-80
-125
-120
-150
-160
-200
-60
-40
-20
0
20
40
60
Time (µs)
80
100
AC-Coupled Output Voltage (mV)
100
240
75
-25
50
-50
25
-75
0
-100
-25
-125
-50
-150
VOUT
IOUT -175
-200
170 180
-75
VOUT
IOUT -175
-200
120 140
-100
80
90
100
110
120 130 140
Time (ms)
150
160
Output Current (mA)
280
Output Current (mA)
AC-Coupled Output Voltage (mV)
50
Output Current (mA)
400
Output Current (mA)
AC-Coupled Output Voltage (mV)
at operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(nom) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA,
VEN = VIN, and CIN = COUT = 1 µF (unless otherwise noted)
Load
VOUT = 1.8 V, VIN = 2.8 V, COUT = 1 µF, tr = tf = 1 µs
Load
VOUT = 1.8 V, VIN = 2.8 V, COUT = 1 µF, tr = tf = 1 µs
Figure 6-16. IOUT Transient From 50 mA to 0 mA
200
200
150
175
150
300
100
150
100
240
50
125
50
180
0
100
0
120
-50
60
-100
0
-150
-60
-200
-120
-250
-180
-300
-240
-300
-80
-60
-40
-20
0
20
40
Time (µs)
60
80
IOUT
VOUT -350
-400
100 120
75
-50
50
-100
25
-150
0
-200
-25
-250
-50
-300
VOUT
IOUT -350
-400
80
90
-75
-100
-10
Load
VOUT = 1.8 V, VIN = 2.8 V, COUT = 1 µF, tr = tf = 1 µs
Figure 6-17. IOUT Transient From 0 mA to 100 mA
10
AC-Coupled Output Voltage (mV)
200
360
0
10
20
30
40
50
Time (ms)
60
70
Output Current (mA)
420
Output Current (mA
)AC-Coupled Output Voltage (mV)
Figure 6-15. IOUT Transient From 0 mA to 50 mA
Load
VOUT = 1.8 V, VIN = 2.8 V, COUT = 1 µF, tr = tf = 1 µs
Figure 6-18. IOUT Transient From 100 mA to 0 mA
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6.7 Typical Characteristics (continued)
400
400
250
350
300
300
200
300
200
240
150
250
100
180
100
120
50
200
0
60
0
150
-100
100
-200
0
-50
-60
-100
-120
-150
-180
-200
VOUT
IOUT -250
-300
60
70
-240
-300
-30
-20
-10
0
10
20
30
Time (µs)
40
50
)AC-Coupled Output Voltage (mV)
300
360
50
-300
0
-400
-50
-500
-100
-600
-150
-200
-10
Load
0
10
20
VOUT = 1.8 V, VIN = 2.8 V, COUT = 1 µF, tr = tf = 1 µs
30
40
Time (ms)
50
60
Output Current (mA
420
Output Current (mA)
AC-Coupled Output Voltage (mV)
at operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(nom) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA,
VEN = VIN, and CIN = COUT = 1 µF (unless otherwise noted)
VOUT
IOUT -700
-800
70
80
VOUT = 1.8 V, VIN = 2.8 V, COUT = 1 µF, tr = tf = 1 µs
Figure 6-19. IOUT Transient From 0 mA to 200 mA
Figure 6-20. IOUT Transient From 200 mA to 0 mA
125
4.5
100
3
1.5
50
0
25
-1.5
0
-3
-25
-4.5
VOUT
VIN
-50
-40
0
40
80
120 160 200
Time (µs)
240
280
320
10
350
7.5
300
5
250
2.5
200
0
150
-2.5
100
-5
50
-7.5
0
-10
-50
-12.5
-100
-15
VOUT
VIN
-150
-6
360
-200
-200
-100
-17.5
0
100
Line
VOUT = 1.8 V, IOUT = 200 mA, COUT = 1 µF, slew rate = 1 V/µs
200 300
Time (µs)
400
500
600
-20
700
Line
VOUT = 1.8 V, IOUT = 1 mA, COUT = 1 µF, slew rate = 1 V/µs
Figure 6-21. VIN Transient From 2.8 V to 4.8 V
Figure 6-22. VIN Transient From 2.8 V to 6.0 V
150
10
5
125
7.5
4.5
5
4.5
4
4
5
2.5
50
0
25
-2.5
0
3.5
3.5
3
3
2.5
2.5
2
2
1.5
1.5
Input Voltage (V)
75
Output Voltage (V)
100
Input Voltage (V)
AC-Coupled Output Voltage (mV)
400
Input Voltage (V)
75
AC-Coupled Output Voltage (mV)
6
Input Voltage (V)
AC-Coupled Output Voltage (mV)
150
-5
1
-25
-7.5
VOUT
VIN
-50
-40
-20
0
20
40
60
80
Time (µs)
100
120
140
-10
160
0.5
0
-40
Line
VOUT = 1.8 V, IOUT = 200 mA, COUT = 1 µF, slew rate = 1 V/µs
Figure 6-23. VIN Transient From 2.8 V to 6.0 V
1
VOUT
VIN
0
40
0.5
80
120 160 200
Time (µs)
240
280
320
0
360
Drop
VOUT = 1.8 V, IOUT = 100 mA, COUT = 1 µF, slew rate = 1 V/µs
Figure 6-24. VIN Transient From 1.5 V to 4.5 V
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6.7 Typical Characteristics (continued)
at operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(nom) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA,
VEN = VIN, and CIN = COUT = 1 µF (unless otherwise noted)
10
0.3
-55°C
-40°C
6
0°C
25°C
85°C
125°C
-55°C
-40°C
140°C
Output Voltage Accuracy (%)
Change in Output Voltage (mV)
TJ
TJ
8
4
2
0
-2
-4
-6
0°C
25°C
85°C
125°C
140°C
0.1
-0.1
-0.3
-8
-0.5
-10
2
2.5
3
3.5
4
4.5
Input Voltage (V)
5
5.5
2
6
2.5
3
3.5
4
4.5
Input Voltage (V)
0.3
20
VOUT %
TJ
Change in Output Voltage (mV)
Output Voltage Accuracy %)
6
Figure 6-26. Output Accuracy vs VIN and Temperature
Figure 6-25. Line Regulation vs VIN and Temperature
0.1
-0.1
-0.3
-0.5
-60
-40
-20
0
20
40
60
80
Temperature (qC)
100
120
-55°C
-40°C
15
0°C
25°C
85°C
125°C
140°C
10
5
0
-5
-10
-15
140150
5
5.2
VOUT = 1.8 V, IOUT = 1 mA
5.4
5.6
Input Voltage (V)
5.8
6
VOUT = 5.0 V, IOUT = 1 mA
Figure 6-27. Output Accuracy vs Temperature
Figure 6-28. Line Regulation vs VIN and Temperature
0.5
0.5
VOUT %
TJ
-55°C
-40°C
0°C
25°C
85°C
125°C
140°C
Output Voltage Accuracy %)
Output Voltage Accuracy (%)
5.5
VOUT = 1.8 V, IOUT = 1 mA
VOUT = 1.8 V, IOUT = 1 mA
0.3
0.1
-0.1
-0.3
5
5.2
5.4
5.6
Input Voltage (V)
5.8
6
0.3
0.1
-0.1
-0.3
-0.5
-60
-40
-20
0
20
40
60
80
Temperature (qC)
100
120
140150
VOUT = 5.0 V, IOUT = 1 mA
VOUT = 5.0 V, IOUT = 1 mA
Figure 6-29. Output Accuracy vs VIN and Temperature
12
5
Figure 6-30. Output Accuracy vs Temperature
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6.7 Typical Characteristics (continued)
at operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(nom) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA,
VEN = VIN, and CIN = COUT = 1 µF (unless otherwise noted)
550
10
5
0°C
25°C
85°C
125°C
TJ
500
140°C
-55°C
-40°C
450
Dropout Voltage (mV)
Change in Output Voltage (mV)
TJ
-55°C
-40°C
0
-5
-10
0°C
25°C
85°C
125°C
140°C
400
350
300
250
200
150
100
-15
50
-20
0
20
40
60
80 100 120 140
Output Current (mA)
160
180
0
200
0
20
40
60
80 100 120 140
Output Current (mA)
VOUT = 1.8 V
180
200
VOUT = 1.8 V
Figure 6-31. Load Regulation vs VIN and Temperature
Figure 6-32. Dropout vs IOUT and Temperature
600
300
280
260
240
220
200
180
160
140
120
100
80
60
40
20
0
TJ
-55°C
-40°C
0°C
25°C
85°C
125°C
TJ
140°C
-55°C
-40°C
Dropout Voltage (mV)
Dropout Voltage (mV)
160
0
20
40
60
80 100 120 140
Output Current (mA)
160
180
0°C
25°C
85°C
125°C
140°C
400
200
200
0
2
VOUT = 5.0 V
2.5
3
3.5
4
Input Voltage (V)
4.5
5
IOUT = 200 mA
Figure 6-33. Dropout vs IOUT and Temperature
Figure 6-34. Dropout vs VIN and Temperature
300
1.2
TJ
TJ
-55°C
-40°C
0°C
25°C
85°C
125°C
140°C
-55°C
-40°C
1
Output Voltage (V)
Dropout Voltage (mV)
250
200
150
100
0°C
25°C
85°C
125°C
140°C
0.8
0.6
0.4
0.2
50
0
1.5
0
2
2.5
3
3.5
Input Voltage (V)
4
4.5
5
0
50 100 150 200 250 300 350 400 450 500 550 600
Output Current (mA)
VOUT = 0.8 V
IOUT = 50 mA
Figure 6-35. Dropout vs VIN and Temperature
Figure 6-36. Foldback Current Limit vs IOUT and Temperature
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6.7 Typical Characteristics (continued)
at operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(nom) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA,
VEN = VIN, and CIN = COUT = 1 µF (unless otherwise noted)
0.9
2.5
-55°C
-40°C
85°C
125°C
VEN(LOW)
VEN(HIGH)
0.85
Enable Voltage (V)
Output Voltage (V)
2
TJ
0°C
25°C
1.5
1
0.5
0.8
0.75
0.7
0.65
0.6
-60
0
0
50 100 150 200 250 300 350 400 450 500 550 600
Output Current (mA)
-40
-20
0
100
120
140150
VOUT = 0.8 V
VOUT = 1.8 V
Figure 6-38. EN High and Low Threshold vs Temperature
Figure 6-37. Foldback Current Limit vs IOUT and Temperature
1.5
1.1
VEN(LOW)
VEN(HIGH)
1.05
VUVLO(HIGH)
VUVLO(LOW)
1.45
1
1.4
UVLO Voltage (V)
Enable Voltage (V)
20
40
60
80
Temperature (qC)
0.95
0.9
0.85
0.8
1.35
1.3
1.25
1.2
0.75
1.15
0.7
-60
-40
-20
0
20
40
60
80
Temperature (qC)
100
120
140150
1.1
-60
-40
-20
0
VOUT = 5.0 V
20
40
60
80
Temperature (qC)
100
120
140150
VOUT = 5.0 V, IOUT = 1 mA
Figure 6-39. EN High and Low Threshold vs Temperature
Figure 6-40. UVLO Rising and Falling Threshold vs Temperature
70
580
0.8V
570
5.0V
Pulldown Resistor (ohm)
Pulldown Resistor (ohm)
65
VOUT
1.8V
60
55
50
5.0V
560
550
540
530
520
510
500
480
-60
-40
-20
0
20
40
60
80
Temperature (qC)
-40
-20
0
20
40
60
80
Temperature (qC)
100 120 140 160
100 120 140 160
Figure 6-41. Pulldown Resistor vs Temperature and VOUT
14
VOUT
1.8V
490
45
40
-60
0.8V
Figure 6-42. Smart Enable Pulldown Resistor vs Temperature
and VOUT
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6.7 Typical Characteristics (continued)
100
100
90
90
Power Supply Rejection Ratio (dB)
Power Supply Rejection Ratio (dB)
at operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(nom) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA,
VEN = VIN, and CIN = COUT = 1 µF (unless otherwise noted)
80
70
60
50
40
30
20
10
0
10
0 mA
1 mA
100
IOUT
10 mA
20 mA
1k
100 mA
200 mA
10k
100k
Frequency (Hz)
1M
80
70
60
50
40
30
20
10
0
10
10M
90
90
Power Supply Rejection Ratio (dB)
Power Supply Rejection Ratio (dB)
100
80
70
60
50
40
30
0
10
2.3 V
2.8 V
VIN
3.8 V
4.8 V
100
1k
6.0 V
10k
100k
Frequency (Hz)
1M
40
30
20
VIN
2.8 V
3.8 V
10
100
2
1
0.5
0.2
Output Voltage Noise (PV —Hz)
Output Voltage Noise (PV —Hz)
4.8 V
6.0 V
1k
50
30
20
1M
10M
D001
5
3
2
1
0.5
0.3
0.2
0.1
0.1
0.05
10
10M
IOUT
100 PA, RMS Noise = 117.5 PV RMS
1 mA, RMS Noise = 269.5 PV RMS
10
0.05
10
VIN = VOUT+ 1.0 V, IOUT = 1 mA, COUT = 1 µF
Figure 6-47. Output Noise vs Frequency and VOUT
10k
100k
Frequency (Hz)
Figure 6-46. PSRR vs Frequency and VIN
5
1M
D001
VOUT = 1.8 V, IOUT = 200 mA, COUT = 1 µF
10
10k
100k
Frequency (Hz)
10M
50
D001
VOUT
1.8 V, RMS Noise = 269.5 PV RMS
5.0 V, RMS Noise = 710 PV RMS
1k
1M
60
0
10
10M
100
100
10k
100k
Frequency (Hz)
70
Figure 6-45. PSRR vs Frequency and VIN
20
1k
80
VOUT = 1.8 V, IOUT = 100 mA, COUT = 1 µF
50
100
6.0 V
Figure 6-44. PSRR vs Frequency and VIN
Figure 6-43. PSRR vs Frequency and IOUT
100
10
VIN
3.8 V
4.8 V
VOUT = 1.8 V, IOUT = 20 mA, COUT = 1 µF
VIN = 2.8 V, VOUT = 1.8 V, COUT = 1 µF
20
2.3 V
2.8 V
100
1k
10k
100k
Frequency (Hz)
1M
10M
VOUT = 1.8 V, VIN = 2.8 V, COUT = 1 µF
Figure 6-48. Output Noise vs Frequency and IOUT
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6.7 Typical Characteristics (continued)
5
50
30
20
COUT
1 PF, RMS Noise = 269.5 PVRMS
22 PF, RMS Noise = 301.1 PVRMS
10
VOUT
VEN = VIN
4
3
5
3
2
Voltage (V)
Output Voltage Noise (PV —Hz)
at operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(nom) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA,
VEN = VIN, and CIN = COUT = 1 µF (unless otherwise noted)
1
0.5
0.3
0.2
2
1
0
-1
0.1
0.05
10
100
1k
10k
100k
Frequency (Hz)
1M
-2
-450 -300 -150
10M
VOUT = 1.8 V, VIN = 2.8 V, IOUT = 1 mA
Voltage (V)
Voltage (V)
Star
VOUT
VEN
VIN
5
2
1
3
2
0
1
-1
0
0
150 300 450
Time (ms)
600
750
-1
-600 -400 -200
900 1050
0
Star
VOUT = 1.8 V, IOUT = 200 mA, COUT = 1 µF
200 400 600
Time (ms)
800 1000 1200 1400
Star
VOUT = 1.8 V, IOUT = 200 mA, COUT = 1 µF
Figure 6-51. Startup With VEN Before VIN
Figure 6-52. Startup With VEN After VIN
5.5
10
VOUT
VEN
VIN
VOUT
VEN
VIN
9
8
4
7
Voltage (V)
3.5
Voltage (V)
900 1050
4
-2
-450 -300 -150
3
2.5
2
1.5
6
5
4
3
1
2
0.5
1
0
0
-0.5
-450 -300 -150
0
150 300 450
Time (Ps)
600
750
900 1050
-1
-800 -400
Star
VOUT = 1.8 V, IOUT = 0 mA, COUT = 1 µF
Figure 6-53. Startup With VEN After VIN
16
750
6
VOUT
VEN
VIN
3
5
600
Figure 6-50. Startup With VEN = VIN
5
4.5
150 300 450
Time (ms)
VOUT = 1.8 V, IOUT = 200 mA, COUT = 1 µF
Figure 6-49. Output Noise vs Frequency and COUT
4
0
0
400
800 1200 1600 2000 2400 2800 3200
Time (ms)
Star
VOUT = 5.0 V, IOUT = 200 mA, COUT = 1 µF
Figure 6-54. Startup With VEN After VIN
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6.7 Typical Characteristics (continued)
at operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(nom) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA,
VEN = VIN, and CIN = COUT = 1 µF (unless otherwise noted)
9
40
8
30
7
6
20
6
100
5
10
5
0
4
0
4
-100
3
-10
3
-200
2
-20
2
-300
1
-30
1
-400
0
-40
-1
-400
-200
0
200
400
600
Time (Ps)
800
1000
-50
1200
400
VIN
VEN
VOUT
IIN
300
200
0
-1
-400
Current (mA)
Voltage (V)
7
VIN
VEN
VOUT
IIN
Current (mA)
50
8
Voltage (V)
9
-500
-200
Star
VOUT = 1.8 V, IOUT = 0 mA
0
200
400
600
Time (Ps)
800
1000
-600
1200
VOUT = 1.8 V, IOUT = 0 mA
Figure 6-55. Startup Inrush Current With COUT= 1 µF
Figure 6-56. Startup Inrush Current With COUT= 22 µF
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7 Detailed Description
7.1 Overview
The TPS7A02 is a ultra-low IQ linear voltage regulator that is optimized for excellent transient performance.
These characteristics make the device ideal for most battery-powered applications.
This low-dropout linear regulator (LDO) offers active discharge, foldback current limit, shutdown, and thermal
protection capability.
7.2 Functional Block Diagram
Current
Limit
IN
1.2-V
Bandgap
OUT
+
Active Discharge
P-Version Only
±
±
Error
Amp
+
UVLO
Thermal
Shutdown
EN
Internal
Controller
Smart
Enable
Resistor
GND
18
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7.3 Feature Description
7.3.1 Excellent Transient Response
The TPS7A02 includes several innovative circuits to ensure excellent transient response. Dynamic biasing
increases the IQ for a short duration during transients to extend the closed-loop bandwidth and improve the
output response time to transients.
Adaptive biasing increases the IQ as the DC load current increases, extending the bandwidth of the loop. The
response time across the output voltage range is constant because a buffered reference topology is used, which
keeps the control loop in unity gain at any output voltage.
These features give the device a wide loop bandwidth during transients that ensures excellent transient
response while maintaining low IQ in steady-state conditions.
7.3.2 Active Discharge (P-Version Only)
The device has an internal pulldown MOSFET that connects a RPULLDOWN resistor to ground when the device is
disabled to actively discharge the output voltage. The active discharge circuit is activated by the enable pin or by
the undervoltage lockout (UVLO).
Do not rely on the active discharge circuit for discharging a large amount of output capacitance after the input
supply has collapsed because reverse current can possibly flow from the output to the input. This reverse current
flow can cause damage to the device. Limit reverse current to no more than 5% of the device rated current for a
short period of time.
7.3.3 Low IQ in Dropout
In most LDOs the IQ significantly increases when the device is placed into dropout, which is especially true for
low IQ LDOs. The TPS7A02 helps to reduce the battery discharge by detecting when the device is operating in
dropout conditions and maintaining a low IQ.
7.3.4 Smart Enable
The enable (EN) input polarity is active high. The output voltage is enabled when the voltage of the enable input
is greater than VEN(HI) and disabled when the enable input voltage is less than VEN(LOW). If independent control
of the output voltage is not needed, connect EN to IN.
This device has a smart enable circuit to reduce quiescent current. When the voltage on the enable pin is
driven above VEN(HI), as listed in the Electrical Characteristics table, the device is enabled and the smart enable
internal pulldown resistor (REN(PULLDOWN)) is disconnected. When the enable pin is floating, the REN(PULLDOWN) is
connected and pulls the enable pin low to disable the device. The REN(PULLDOWN) value is listed in the Electrical
Characteristics table.
This device has an internal pulldown circuit that activates when the device is disabled to actively discharge the
output voltage.
7.3.5 Dropout Voltage
Dropout voltage (VDO) is defined as the input voltage minus the output voltage (VIN – VOUT) at the rated output
current (IRATED), where the pass transistor is fully on. IRATED is the maximum IOUT listed in the Recommended
Operating Conditions table. The pass transistor is in the ohmic or triode region of operation, and acts as a
switch. The dropout voltage indirectly specifies a minimum input voltage greater than the nominal programmed
output voltage at which the output voltage is expected to stay in regulation. If the input voltage falls to less than
the nominal output regulation, then the output voltage falls as well.
For a CMOS regulator, the dropout voltage is determined by the drain-source on-state resistance (RDS(ON)) of the
pass transistor. Therefore, if the linear regulator operates at less than the rated current, the dropout voltage for
that current scales accordingly. The following equation calculates the RDS(ON) of the device.
RDS(ON) =
VDO
IRATED
(1)
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7.3.6 Foldback Current Limit
The device has an internal current limit circuit that protects the regulator during transient high-load current faults
or shorting events. The current limit is a hybrid brick-wall-foldback scheme. The current limit transitions from a
brick-wall scheme to a foldback scheme at the foldback voltage (VFOLDBACK). In a high-load current fault with
the output voltage above VFOLDBACK, the brick-wall scheme limits the output current to the current limit (ICL).
When the voltage drops below VFOLDBACK, a foldback current limit activates that scales back the current as the
output voltage approaches GND. When the output is shorted, the device supplies a typical current called the
short-circuit current limit (ISC). ICL and ISC are listed in the Electrical Characteristics table.
For this device, VFOLDBACK = 0.5 V.
The output voltage is not regulated when the device is in current limit. When a current limit event occurs, the
device begins to heat up because of the increase in power dissipation. When the device is in brick-wall current
limit, the pass transistor dissipates power [(VIN – V OUT) × ICL]. When the device output is shorted and the output
is below VFOLDBACK, the pass transistor dissipates power [(VIN – VOUT) × ISC]. If thermal shutdown is triggered,
the device turns off. After the device cools down, the internal thermal shutdown circuit turns the device back on.
If the output current fault condition continues, the device cycles between current limit and thermal shutdown. For
more information on current limits, see the Know Your Limits application report.
Figure 7-1 shows a diagram of the foldback current limit.
VOUT
Brickwall
VOUT(NOM)
VFOLDBACK
Foldback
IOUT
0V
0 mA
ISC
IRATED
ICL
Figure 7-1. Foldback Current Limit
7.3.7 Undervoltage Lockout (UVLO)
The device has an independent undervoltage lockout (UVLO) circuit that monitors the input voltage, allowing a
controlled and consistent turn on and off of the output voltage. To prevent the device from turning off if the input
drops during turn on, the UVLO has hysteresis as specified in the Electrical Characteristics table.
7.3.8 Thermal Shutdown
The device contains a thermal shutdown protection circuit to disable the device when the junction temperature
(TJ) of the pass transistor rises to TSD(shutdown) (typical). Thermal shutdown hysteresis assures that the device
resets (turns on) when the temperature falls to TSD(reset) (typical).
20
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The thermal time-constant of the semiconductor die is fairly short, thus the device may cycle on and off
when thermal shutdown is reached until power dissipation is reduced. Power dissipation during start up can
be high from large VIN – VOUT voltage drops across the device or from high inrush currents charging large
output capacitors. Under some conditions, the thermal shutdown protection disables the device before start up
completes.
For reliable operation, limit the junction temperature to the maximum listed in the Recommended Operating
Conditions table. Operation above this maximum temperature causes the device to exceed operational
specifications. Although the internal protection circuitry of the device is designed to protect against thermal
overall conditions, this circuitry is not intended to replace proper heat sinking. Continuously running the device
into thermal shutdown or above the maximum recommended junction temperature reduces long-term reliability.
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7.4 Device Functional Modes
7.4.1 Device Functional Mode Comparison
Table 7-1 shows the conditions that lead to the different modes of operation. See the Electrical Characteristics
table for parameter values.
Table 7-1. Device Functional Mode Comparison
PARAMETER
OPERATING MODE
VIN
VEN
IOUT
TJ
Normal operation
VIN > VOUT(nom) + VDO and VIN > VIN(min)
VEN > VEN(HI)
IOUT < IOUT(max)
TJ < TSD(shutdown)
Dropout operation
VIN(min) < VIN < VOUT(nom) + VDO
VEN > VEN(HI)
IOUT < IOUT(max)
TJ < TSD(shutdown)
VIN < VUVLO
VEN < VEN(LOW)
Not applicable
TJ > TSD(shutdown)
Disabled
(any true condition
disables the device)
7.4.2 Normal Operation
The device regulates to the nominal output voltage when the following conditions are met:
•
•
•
•
The input voltage is greater than the nominal output voltage plus the dropout voltage (VOUT(nom) + VDO)
The output current is less than the current limit (IOUT < ICL)
The device junction temperature is less than the thermal shutdown temperature (TJ < TSD)
The enable voltage has previously exceeded the enable rising threshold voltage and has not yet decreased
to less than the enable falling threshold
7.4.3 Dropout Operation
If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other
conditions are met for normal operation, the device operates in dropout mode. In this mode, the output voltage
tracks the input voltage. During this mode, the transient performance of the device becomes significantly
degraded because the pass transistor is in the ohmic or triode region, and acts as a switch. Line or load
transients in dropout can result in large output-voltage deviations.
When the device is in a steady dropout state (defined as when the device is in dropout, VIN < VOUT(NOM) + VDO,
directly after being in a normal regulation state, but not during start-up), the pass transistor is driven into the
ohmic or triode region. When the input voltage returns to a value greater than or equal to the nominal output
voltage plus the dropout voltage (VOUT(NOM) + VDO), the output voltage can overshoot for a short period of time
while the device pulls the pass transistor back into the linear region.
7.4.4 Disabled
The output of the device can be shutdown by forcing the voltage of the enable pin to less than the maximum
EN pin low-level input voltage (see the Electrical Characteristics table). When disabled, the pass transistor is
turned off, internal circuits are shutdown, and the output voltage is actively discharged to ground by an internal
discharge circuit from the output to ground.
22
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
8.1.1 Recommended Capacitor Types
The device is designed to be stable using low equivalent series resistance (ESR) ceramic capacitors at the input
and output. Multilayer ceramic capacitors have become the industry standard for these types of applications and
are recommended, but must be used with good judgment. Ceramic capacitors that employ X7R-, X5R-, and
C0G-rated dielectric materials provide relatively good capacitive stability across temperature, whereas the use of
Y5V-rated capacitors is discouraged because of large variations in capacitance.
Regardless of the ceramic capacitor type selected, the effective capacitance varies with operating voltage and
temperature. As a rule of thumb, expect the effective capacitance to decrease by as much as 50%. The input
and output capacitors recommended in the Recommended Operating Conditions table account for an effective
capacitance of approximately 50% of the nominal value.
8.1.2 Input and Output Capacitor Requirements
Although an input capacitor is not required for stability, good analog design practice is to connect a capacitor
from IN to GND. This capacitor counteracts reactive input sources and improves transient response, input ripple,
and PSRR. An input capacitor is recommended if the source impedance is more than 0.5 Ω. A higher value
capacitor may be necessary if large, fast rise-time load or line transients are anticipated or if the device is
located several inches from the input power source.
Dynamic performance of the device is improved with the use of an output capacitor. Use an output capacitor
within the range specified in the Recommended Operating Conditions table for stability.
8.1.3 Load Transient Response
The load-step transient response is the output voltage response by the LDO to a step in load current, whereby
output voltage regulation is maintained. There are two key transitions during a load transient response: the
transition from a light to a heavy load and the transition from a heavy to a light load. The regions shown in Figure
8-1 are broken down as follows. Regions A, E, and H are where the output voltage is in steady-state.
tAt
tCt
tDt
B
tEt
tGt
tHt
F
Figure 8-1. Load Transient Waveform
During transitions from a light load to a heavy load, the:
•
•
Initial voltage dip is a result of the depletion of the output capacitor charge and parasitic impedance to the
output capacitor (region B)
Recovery from the dip results from the LDO increasing the sourcing current, and leads to output voltage
regulation (region C)
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During transitions from a heavy load to a light load, the:
•
•
Initial voltage rise results from the LDO sourcing a large current, and leads to the output capacitor charge to
increase (region F)
Recovery from the rise results from the LDO decreasing the sourcing current in combination with the load
discharging the output capacitor (region G)
A larger output capacitance reduces the peaks during a load transient but slows down the response time of the
device. A larger DC load also reduces the peaks because the amplitude of the transition is lowered and a higher
current discharge path is provided for the output capacitor.
8.1.4 Undervoltage Lockout (UVLO) Operation
The UVLO circuit ensures that the device stays disabled before the input supply reaches the minimum
operational voltage range, and ensures that the device shuts down when the input supply collapses. Figure
8-2 shows the UVLO circuit response to various input voltage events. The diagram can be separated into the
following parts:
•
•
•
•
•
•
•
Region A: The device does not start until the input reaches the UVLO rising threshold.
Region B: Normal operation, regulating device.
Region C: Brownout event above the UVLO falling threshold (UVLO rising threshold – UVLO hysteresis). The
output may fall out of regulation but the device remains enabled.
Region D: Normal operation, regulating device.
Region E: Brownout event below the UVLO falling threshold. The device is disabled in most cases and the
output falls because of the load and active discharge circuit. The device is reenabled when the UVLO rising
threshold is reached by the input voltage and a normal start-up follows.
Region F: Normal operation followed by the input falling to the UVLO falling threshold.
Region G: The device is disabled when the input voltage falls below the UVLO falling threshold to 0 V. The
output falls because of the load and active discharge circuit.
UVLO Rising Threshold
UVLO Hysteresis
VIN
C
VOUT
tAt
tBt
tDt
tEt
tFt
tGt
Figure 8-2. Typical UVLO Operation
8.1.5 Power Dissipation (PD)
Circuit reliability demands that proper consideration be given to device power dissipation, location of the circuit
on the printed circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator
must be as free as possible of other heat-generating devices that cause added thermal stresses.
As a first-order approximation, power dissipation in the regulator depends on the input-to-output voltage
difference and load conditions. Use Equation 2 to approximate PD:
PD = (VIN – VOUT) × IOUT
(2)
Power dissipation can be minimized, and thus greater efficiency achieved, by proper selection of the system
voltage rails. Proper selection allows the minimum input-to-output voltage differential to be obtained. The low
dropout of the TPS7A02 allows for maximum efficiency across a wide range of output voltages.
24
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The main heat conduction path for the device is through the thermal pad on the package. As such, the thermal
pad must be soldered to a copper pad area under the device. This pad area contains an array of plated vias that
conduct heat to any inner plane areas or to a bottom-side copper plane.
The maximum power dissipation determines the maximum allowable junction temperature (TJ) for the device.
According to Equation 3, power dissipation and junction temperature are most often related by the junction-toambient thermal resistance (RθJA) of the combined PCB and device package and the temperature of the ambient
air (TA). Equation 4 rearranges Equation 3 for output current.
TJ = TA + (RθJA × PD)
(3)
IOUT = (TJ – TA) / [RθJA × (VIN – VOUT)]
(4)
Unfortunately, this thermal resistance (RθJA) is highly dependent on the heat-spreading capability built into the
particular PCB design, and therefore varies according to the total copper area, copper weight, and location of
the planes. The RθJA recorded in the Thermal Information table is determined by the JEDEC standard, PCB,
and copper-spreading area, and is only used as a relative measure of package thermal performance. For a
well-designed thermal layout, RθJA is actually the sum of the X2SON package junction-to-case (bottom) thermal
resistance (RθJC(bot)) plus the thermal resistance contribution by the PCB copper.
8.1.5.1 Estimating Junction Temperature
The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures
of the LDO when in-circuit on a typical PCB board application. These metrics are not strictly speaking thermal
resistances, but rather offer practical and relative means of estimating junction temperatures. These psi metrics
are determined to be significantly independent of the copper-spreading area. The key thermal metrics (ΨJT and
ΨJB) are used in accordance with Equation 5 and are given in the Thermal Information table.
ΨJT : TJ = TT + ΨJT × PD and ΨJB : TJ = TB + ΨJB × PD
(5)
where:
•
•
•
PD is the power dissipated as explained in Equation 2
TT is the temperature at the center-top of the device package, and
TB is the PCB surface temperature measured 1 mm from the device package and centered on the package
edge
8.1.5.2 Recommended Area for Continuous Operation
The operational area of an LDO is limited by the dropout voltage, output current, junction temperature, and input
voltage. The recommended area for continuous operation for a linear regulator is given in Figure 8-3 and can be
separated into the following parts:
•
•
•
•
Dropout voltage limits the minimum differential voltage between the input and the output (VIN – VOUT) at a
given output current level. See the Dropout Operation section for more details.
The rated output currents limits the maximum recommended output current level. Exceeding this rating
causes the device to fall out of specification.
The rated junction temperature limits the maximum junction temperature of the device. Exceeding this rating
causes the device to fall out of specification and reduces long-term reliability.
– The shape of the slope is given by Equation 4. The slope is nonlinear because the maximum rated
junction temperature of the LDO is controlled by the power dissipation across the LDO; thus when VIN –
VOUT increases the output current must decrease.
The rated input voltage range governs both the minimum and maximum of VIN – VOUT.
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Output Current (A)
Figure 8-3 shows the recommended area of operation for this device on a JEDEC-standard high-K board with a
RθJA as given in the Thermal Information table.
Output current limited by
dropout
Rated output
current
Output current limited by thermals
Limited by
maximum VIN
Limited by
minimum VIN
VIN ± VOUT (V)
Figure 8-3. Region Description of Continuous Operation Regime
8.2 Typical Application
CIN
IN
OUT
COUT
Device
VBAT
Load
EN
GND
Figure 8-4. Operation From a Battery Input Supply
8.2.1 Design Requirements
Table 8-1. Design Parameters
PARAMETER
DESIGN REQUIREMENT
Input voltage
1.8 V to 3.0 V (two 1.5-V batteries)
Output voltage
1.0 V, ±1%
Input current
200 mA, maximum
Output load
10-mA DC
Maximum ambient temperature
70°C
8.2.2 Detailed Design Procedure
For this design example, the 1.0-V, fixed-version TPS7A0210 is selected. A dual AA Alkaline battery was used,
thus a 1.0-µF input capacitor is recommended to minimize transient currents drawn from the battery. A 1.0-µF
output capacitor is also recommended for excellent load transient response. The dropout voltage (VDO) is kept
within the TPS7A02 dropout voltage specification for the 1.0-V output voltage option to keep the device in
regulation under all load and temperature conditions for this design. Use the recommend 1-µF input and output
capacitor because the input source has a high equivalent series resistor (ESR) of 600 mΩ (typ). The very small
ground current consumed by the regulator maintains a high current efficiency as compared to the load current
consumed by the system, as shown in Figure 8-5 which allows for long battery life. Equation 6 can be used to
calculate the current efficiency (Iη) of this system.
Iη(%) = IOUT / (IOUT + IQ) × 100
26
(6)
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8.2.3 Application Curve
102
Current Efficiency (%)
100
98
96
94
92
90
88
TJ
-55°C
-40°C
86
84
0.001
0.01
0°C
25°C
85°C
125°C
0.1
1
Output Current (mA)
140°C
10
100
Curr
Figure 8-5. Current Efficiency vs IOUT and Temperature
8.3 Power Supply Recommendations
This device is designed to operate from an input supply voltage range of 1.5 V to 6.0 V. The input supply must
be well regulated and free of spurious noise. To ensure that the output voltage is well regulated and dynamic
performance is optimum, the input supply must be at least VOUT(nom) + 0.5 V. TI highly recommends using a 1-µF
or greater input capacitor to reduce the impedance of the input supply, especially during transients.
8.4 Layout
8.4.1 Layout Guidelines
•
•
•
•
Place input and output capacitors as close to the device as possible.
Use copper planes for device connections to optimize thermal performance.
Place thermal vias around the device to distribute the heat.
Do not place a thermal via directly beneath the thermal pad of the DQN package. A via can wick solder or
solder paste away from the thermal pad joint during the soldering process, leading to a compromised solder
joint on the thermal pad.
8.4.2 Layout Examples
VOUT
VIN
1
4
COUT
CIN
2
3
GND PLANE
Represents via used for
application specific connections
Figure 8-6. Layout Example for the DQN Package
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VOUT
VIN
5
1
CIN
COUT
2
4
3
GND PLANE
Represents via used for
application specific connections
Figure 8-7. Layout Example for the DBV Package
IN
A1
CIN
OUT
A2
COUT
Via
B1
EN
B2
GND
Figure 8-8. Layout Example for the YCH Package
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9 Device and Documentation Support
9.1 Device Support
9.1.1 Device Nomenclature
Table 9-1. Device Nomenclature(1) (2)
(1)
(2)
PRODUCT
VOUT
TPS7A02 xx(x)Pyyyz
XX(X) is the nominal output voltage. For output voltages with a resolution of 100 mV, two digits are used
in the ordering number; otherwise, three digits are used (for example, 28 = 2.8 V; 125 = 1.25 V).
P indicates an active output discharge feature. All members of the TPS7A02 family actively discharge
the output when the device is disabled.
YYY is the package designator.
Z is the package quantity. R is for reel (3000 pieces), T is for tape (250 pieces).
For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the
device product folder on www.ti.com.
Output voltages from 1.0 V to 3.3 V in 50-mV increments are available. Contact the factory for details and availability.
9.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
9.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
9.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
9.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
9.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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11-Dec-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TPS7A0210PDQNR
ACTIVE
X2SON
DQN
4
3000
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
GH
Samples
TPS7A0212PDBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
21GF
Samples
TPS7A0212PYCHR
ACTIVE
DSBGA
YCH
4
12000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
A
Samples
TPS7A0215PDBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
21KF
Samples
TPS7A0215PDQNR
ACTIVE
X2SON
DQN
4
3000
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
F3
Samples
TPS7A02175PYCHR
ACTIVE
DSBGA
YCH
4
12000
RoHS & Green
Level-1-260C-UNLIM
-40 to 125
S
Samples
TPS7A02185PDQNR
ACTIVE
X2SON
DQN
4
3000
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
HO
Samples
TPS7A0218DBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
2CDT
Samples
TPS7A0218PDBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
21LF
Samples
TPS7A0218PDQNR
ACTIVE
X2SON
DQN
4
3000
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
F4
Samples
TPS7A0218PYCHR
ACTIVE
DSBGA
YCH
4
12000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
B
Samples
TPS7A0220PDBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
22MT
Samples
TPS7A0220PDQNR
ACTIVE
X2SON
DQN
4
3000
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
F5
Samples
TPS7A0222DQNR
ACTIVE
X2SON
DQN
4
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
IN
Samples
TPS7A0222PDBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
21HF
Samples
TPS7A0222PDQNR
ACTIVE
X2SON
DQN
4
3000
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
GI
Samples
TPS7A0223PDBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
Level-1-260C-UNLIM
-40 to 125
21IF
Samples
TPS7A0223PDQNR
ACTIVE
X2SON
DQN
4
3000
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
F6
Samples
TPS7A0225PDBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
Level-1-260C-UNLIM
-40 to 125
21DF
Samples
TPS7A0225PDQNR
ACTIVE
X2SON
DQN
4
3000
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
F7
Samples
SNAGCU
NIPDAU | SN
NIPDAU | SN
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
11-Dec-2022
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TPS7A0225PYCHR
ACTIVE
DSBGA
YCH
4
12000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
C
Samples
TPS7A0228DBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
29PT
Samples
TPS7A0228DQNR
ACTIVE
X2SON
DQN
4
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
IE
Samples
TPS7A0228PDBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
21EF
Samples
TPS7A0228PDQNR
ACTIVE
X2SON
DQN
4
3000
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
F8
Samples
TPS7A0228PYCHR
ACTIVE
DSBGA
YCH
4
12000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
D
Samples
TPS7A0230PDBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
21MF
Samples
TPS7A0230PDQNR
ACTIVE
X2SON
DQN
4
3000
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
F9
Samples
TPS7A0230PYCHR
ACTIVE
DSBGA
YCH
4
12000
RoHS & Green
Level-1-260C-UNLIM
-40 to 125
F
Samples
TPS7A0231PDQNR
ACTIVE
X2SON
DQN
4
3000
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
GJ
Samples
TPS7A0233DBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
29QT
Samples
TPS7A0233DQNR
ACTIVE
X2SON
DQN
4
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
IF
Samples
TPS7A0233PDBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
21FF
Samples
TPS7A0233PDQNR
ACTIVE
X2SON
DQN
4
3000
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
FA
Samples
TPS7A0233PYCHR
ACTIVE
DSBGA
YCH
4
12000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
G
Samples
TPS7A0236PDBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
(21FF, 21JF)
Samples
SNAGCU
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
11-Dec-2022
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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