TPS7A0508PDBZR

Product Folder Order Now Support & Community Tools & Software Technical Documents TPS7A05 SBVS254D – FEBRUARY 2018 – REVISED AUGUST 2019 TPS7A05 1-µA Ultralow IQ, 200-mA, Low-Dropout Regulator in a Small-Size Package 1 Features 3 Description • The TPS7A05 is an ultra-small, low quiescent current low-dropout regulator (LDO) that can source 200 mA with excellent transient performance. This device has an output range of 0.8 V to 3.3 V with a typical 1% accuracy. 1 • • • • • • • • • Ultralow IQ: 1 µA (typ), 3 µA (max) – IGND: 6 µA (typ) at 200 mA Excellent transient response Packages: – 1.0-mm × 1.0-mm X2SON (4) – 0.65-mm × 0.65-mm DSBGA (4) – SOT-23 (5) – SOT-23 (3) Input voltage range: 1.4 V to 5.5 V Output accuracy: 1% typical, 3% maximum Available in fixed-output voltage: – 0.8 V to 3.3 V Very low dropout: – 235 mV (max) at 200 mA (3.3 VOUT) Active output discharge Foldback current limit Stable with a 0.47-µF or larger capacitor The TPS7A05, with ultralow IQ (1 µA), consumes very-low quiescent current for extending battery life in battery-powered applications. The device can be operated from rechargeable Li-Ion batteries, Liprimary battery chemistries such as Li-SOCl2, LiMnO2, as well as two- or three-cell alkaline batteries. The TPS7A05 is available with an active pulldown circuit to quickly discharge the output when disabled. The TPS7A05 is fully specified for TJ = –40°C to +125°C operation, and is available in standard X2SON (DQN), SOT-23 (DBV and DBZ), and DSBGA (YKA) packages. Device Information(1) PART NUMBER 2 Applications • • • • • • • TPS7A05 Wearable electronics Ultrabooks, tablets, E-readers Always-on power supplies Set-top boxes Gaming controllers, remote controls, toys, drones Wireless handsets and smart phones Portable and battery-powered equipment PACKAGE BODY SIZE (NOM) X2SON (4) 1.00 mm × 1.00 mm DSBGA (4) 0.65 mm × 0.65 mm SOT-23 (5) 2.90 mm × 1.60 mm SOT-23 (3) 2.90 mm x 1.60 mm (1) For all available packages, see the package option addendum at the end of the data sheet. Typical Application Circuit Ground Current vs Output Current 7 TPS7A05 CIN EN ON OFF OUT GND 6 COUT Ground Current (PA) IN 5 4 3 2 1 0 0 20 40 60 80 100 120 140 Output Current (mA) 160 180 200 D043 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPS7A05 SBVS254D – FEBRUARY 2018 – REVISED AUGUST 2019 www.ti.com Table of Contents 1 2 3 4 5 6 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 6.1 6.2 6.3 6.4 6.5 6.6 6.7 7 1 1 1 2 4 6 Absolute Maximum Ratings ...................................... 6 ESD Ratings.............................................................. 6 Recommended Operating Conditions....................... 6 Thermal Information .................................................. 6 Electrical Characteristics........................................... 7 Switching Characteristics .......................................... 9 Typical Characteristics ............................................ 10 Detailed Description ............................................ 18 7.1 Overview ................................................................. 18 7.2 Functional Block Diagram ....................................... 18 7.3 Feature Description................................................. 19 7.4 Device Functional Modes........................................ 21 8 Application and Implementation ........................ 22 8.1 Application Information............................................ 22 8.2 Typical Application .................................................. 27 9 Power Supply Recommendations...................... 27 10 Layout................................................................... 28 10.1 Layout Guidelines ................................................. 28 10.2 Layout Example .................................................... 28 11 Device and Documentation Support ................. 29 11.1 11.2 11.3 11.4 11.5 11.6 11.7 Device Support...................................................... Documentation Support ........................................ Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 29 29 29 29 29 29 29 12 Mechanical, Packaging, and Orderable Information ........................................................... 30 4 Revision History Changes from Revision C (April 2019) to Revision D Page • Changed DBZ package from APL to production data ............................................................................................................ 1 • Added DBZ package to Load Regulation parameter in Electrical Characteristics table ....................................................... 7 • Added DBZ package to Dropout voltage parameter in Electrical Characteristics table ......................................................... 8 • Added condition statement to IQ vs VIN and Temperature figure ......................................................................................... 10 Changes from Revision B (August 2018) to Revision C • Page Added DBZ package to document as APL release................................................................................................................ 1 Changes from Revision A (May 2018) to Revision B Page • Changed 1-mm × 1-mm to Small-Size in document title ....................................................................................................... 1 • Changed YKA (DSBGA) package status to production data ................................................................................................ 1 • Added Accuracy for 1.825 V in Electrical Characteristics table ............................................................................................. 7 • Changed Output current limit in Electrical Characteristics table ............................................................................................ 7 • Added Output current limit for +85°C in Electrical Characteristics table ................................................................................ 7 • Changed Short-circuit current limit in Electrical Characteristics table .................................................................................... 7 • Added Dropout voltage for 1.825 V in Electrical Characteristics table................................................................................... 8 • Changed y-axis scaling and added conditions for IOUT Transient 0 mA to 100 mA figure ................................................... 10 • Changed y-axis scaling and added conditions for IOUT Transient 0 mA to 200 mA figure .................................................. 11 • Added IOUT Transient 0 mA to 50 mA figure to IOUT Transient 3 µA to 3 mA figure ............................................................. 11 • Added slew rate condition to VIN Transient figures (IOUT = 100 mA and IOUT = 200 mA) ..................................................... 12 • Added VIN Transient figures (IOUT = 150 mA and IOUT = 20 mA) .......................................................................................... 13 • Added VIN condition to PSRR vs Frequency and IOUT figure (VOUT = 1.8 V) ........................................................................ 16 2 Submit Documentation Feedback Copyright © 2018–2019, Texas Instruments Incorporated Product Folder Links: TPS7A05 TPS7A05 www.ti.com SBVS254D – FEBRUARY 2018 – REVISED AUGUST 2019 Changes from Original (February 2018) to Revision A • Page Released to production .......................................................................................................................................................... 1 Submit Documentation Feedback Copyright © 2018–2019, Texas Instruments Incorporated Product Folder Links: TPS7A05 3 TPS7A05 SBVS254D – FEBRUARY 2018 – REVISED AUGUST 2019 www.ti.com 5 Pin Configuration and Functions DQN Package 1-mm × 1-mm, 4-Pin X2SON Top View OUT 1 4 IN 3 EN Pad GND 2 Not to scale DBV Package 5-Pin SOT-23 Top View IN 1 GND 2 EN 3 DBZ Package 3-Pin SOT-23 Top View 5 OUT GND 1 3 4 NC OUT 2 Not to scale Not to scale YKA Package 4-Pin DSBGA, 0.35-mm Pitch Top View 1 2 A IN OUT B EN GND YKA Package 4-Pin DSBGA, 0.35-mm Pitch Bottom View Not to scale 4 IN 1 2 B EN GND A IN OUT Not to scale Submit Documentation Feedback Copyright © 2018–2019, Texas Instruments Incorporated Product Folder Links: TPS7A05 TPS7A05 www.ti.com SBVS254D – FEBRUARY 2018 – REVISED AUGUST 2019 Pin Functions PIN NAME IN DQN 4 DBV 1 DBZ 3 YKA A1 I/O DESCRIPTION Input Input pin. For best transient response and to minimize input impedance, use the recommended value or larger ceramic capacitor from IN to ground as listed in the Recommended Operating Conditions table. Place the input capacitor as close to input of the device as possible. Enable pin. Driving this pin to logic high enables the device; driving this pin to logic low disables the device. If enable functionality is not required, this pin must be connected to IN. VEN must not exceed VIN. EN 3 3 — B1 Input GND 2 2 1 B2 — Ground pin. This pin must be connected to ground on the board. OUT 1 5 2 A2 Output Regulated output pin. A capacitor is required from OUT to ground for stability. For best transient response, use the nominal recommended value or larger ceramic capacitor from OUT to ground. Follow the recommended capacitor value as listed in the Recommended Operating Conditions table. Place the output capacitor as close to output of the device as possible. NC — 4 — — — No connect pin. This pin is not internally connected. Connect to ground or leave floating. Pad — — — — Connect the thermal pad to a large-area ground plane. This pad is not an electrical connection to the device ground. Thermal pad Submit Documentation Feedback Copyright © 2018–2019, Texas Instruments Incorporated Product Folder Links: TPS7A05 5 TPS7A05 SBVS254D – FEBRUARY 2018 – REVISED AUGUST 2019 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings Over operating free-air temperature range (unless otherwise noted) (1) Voltage (2) Current (2) (3) MAX –0.3 6.0 EN –0.3 VIN + 0.3 OUT –0.3 VIN + 0.3 or 3.6 (3) Maximum output current Temperature (1) MIN IN UNIT V Internally limited A Operating junction temperature, TJ –40 125 Storage temperature, Tstg –65 150 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages with respect to GND. VIN + 0.3 V or 3.6 V (whichever is smaller) 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±1000 Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±500 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions MIN VIN Input supply voltage VEN Enable supply voltage VOUT Nominal output voltage range IOUT Output current (1) CIN Input capacitor COUT Output capacitor 0.47 TJ Operating junction temperature –40 (1) NOM MAX UNIT 1.4 5.5 V 0 VIN V 0.8 3.3 V 0 200 mA 1 µF 1 22 µF 125 °C Output current of 10 µA minimum required to meet output voltage accuracy specification. 6.4 Thermal Information TPS7A05 THERMAL METRIC (1) DBZ (SOT-23) DBV (SOT-23) DQN (X2SON) YKA (DSBGA) UNIT 3 PINS 5 PINS 4 PINS 4 PINS RθJA Junction-to-ambient thermal resistance 267.3 185.6 144.1 198.0 °C/W RθJC(top) Junction-to-case (top) thermal resistance 103.5 104.3 137.9 2.1 °C/W RθJB Junction-to-board thermal resistance 98.0 54.5 83.5 66.9 °C/W ΨJT Junction-to-top characterization parameter 9.2 31.0 5.3 0.9 °C/W YJB Junction-to-board characterization parameter 97.4 54.5 83.8 76.0 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance n/a n/a 71.8 n/a °C/W (1) 6 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Documentation Feedback Copyright © 2018–2019, Texas Instruments Incorporated Product Folder Links: TPS7A05 TPS7A05 www.ti.com SBVS254D – FEBRUARY 2018 – REVISED AUGUST 2019 6.5 Electrical Characteristics specified at TJ = –40°C to +125°C, VIN = VOUT(nom) + 0.5 V or 1.4 V (whichever is greater), IOUT = 1 mA, VEN = VIN, CIN = 1 µF, and COUT = 1 µF (unless otherwise noted); typical values are at TJ = 25°C. PARAMETER Nominal accuracy (1) Accuracy over temperature (1) TEST CONDITIONS MIN VOUT ≥ 1.0 V, TJ = 25°C VOUT < 1.0 V, TJ = 25°C Line regulation –10 10 –2% 2% VOUT ≥ 1.0 V –3% 3% VOUT < 1.0 V, TJ = –40°C to +85°C –20 20 VOUT < 1.0 V –30 30 –0.9% 0.9% VOUT(nom) + 0.5 V ≤ VIN ≤ 5.5 V (2), TJ = –40°C to +85°C Load regulation (3) 5 16.5 mV mV mV 18 100 μA ≤ IOUT ≤ 200 mA, VIN = VOUT(nom) + VDO(max) + 0.1 V, TJ = –40°C to +85°C DBV, DQN, YKA 20 43 DBZ 27 50 100 μA ≤ IOUT ≤ 200 mA, VIN = VOUT(nom) + VDO(max) + 0.1 V DBV, DQN, YKA mV 55 DBZ 62 TJ = 25°C, IOUT = 1 µA 0.6 IGND Ground current ISHDN Shutdown current VEN = 0.4 V, 1.4 V ≤ VIN ≤ 5.5 V, TJ = 25°C ICL Output current limit VOUT = 90% × VOUT(nom), VIN = VOUT(nom) + VDO(max) + 0.5 V ICL Output current limit VOUT = 90% × VOUT(nom), VIN = VOUT(nom) + VDO(max) + 0.5 V, TJ = 0°C to +85°C ISC Short-circuit current limit VOUT = 0 V 1 IOUT = 1 µA, TJ = –40°C to +85°C 1.3 2 IOUT = 1 µA (1) (2) (3) UNIT 1% VOUT(nom) + 0.5 V ≤ VIN ≤ 5.5 V (2) ΔVOUT(ΔIOUT) MAX VOUT ≥ 1.0 V, TJ = –40°C to +85°C VOUT = 1.825 V, TJ = +10℃ to +45℃, IOUT = 100 µA ΔVOUT(ΔVIN) TYP –1% µA 3 100 300 nA 210 450 700 mA 250 450 700 mA 65 150 mA IOUT ≥ 10 µA required to meet accuracy specifications. VIN = 1.4 V for VOUT ≤ 0.9 V. Load Regulation is normalized to the output voltage at IOUT = 1 mA. Submit Documentation Feedback Copyright © 2018–2019, Texas Instruments Incorporated Product Folder Links: TPS7A05 7 TPS7A05 SBVS254D – FEBRUARY 2018 – REVISED AUGUST 2019 www.ti.com Electrical Characteristics (continued) specified at TJ = –40°C to +125°C, VIN = VOUT(nom) + 0.5 V or 1.4 V (whichever is greater), IOUT = 1 mA, VEN = VIN, CIN = 1 µF, and COUT = 1 µF (unless otherwise noted); typical values are at TJ = 25°C. PARAMETER TEST CONDITIONS IOUT = 200 mA, TJ = –40°C to +85°C MIN TYP 915 1.0 V ≤ VOUT < 1.2 V 758 1.2 V ≤ VOUT < 1.5 V 609 1.5 V ≤ VOUT < 1.8 V 469 1.8 V ≤ VOUT < 2.5 V 341 2.5 V ≤ VOUT < 3.3 V 275 VOUT = 3.3 V Dropout voltage (4) VDO IOUT = 200 mA IOUT = 200 mA, TJ = –40°C to +85°C, DBZ Package IOUT = 200 mA, DBZ Package IOUT = 100 µA, TJ = +10℃ to +45℃ Power-supply rejection ratio PSRR MAX 0.8 V ≤ VOUT < 1.0 V UNIT 212 0.8 V ≤ VOUT < 1.0 V 1004 1.0 V ≤ VOUT < 1.2 V 837 1.2 V ≤ VOUT < 1.5 V 679 1.5 V ≤ VOUT < 1.8 V 525 1.8 V ≤ VOUT < 2.5 V 382 2.5 V ≤ VOUT < 3.3 V 308 VOUT = 3.3 V 235 1.8 V ≤ VOUT < 2.5 V 351 2.5 V ≤ VOUT < 3.3 V 285 VOUT = 3.3 V 222 1.8 V ≤ VOUT < 2.5 V 392 2.5 V ≤ VOUT < 3.3 V 318 VOUT = 3.3 V 245 VOUT = 1.825 V mV 20 f = 1 kHz, IOUT = 30 mA 40 f = 500 kHz, IOUT = 30 mA 30 f = 1 MHz, IOUT = 30 mA 40 dB VN Output voltage noise BW = 10 Hz to 100 kHz, VOUT = 1.2 V, IOUT = 30 mA VUVLO UVLO threshold VIN rising VUVLO(HYST) UVLO hysteresis VIN falling VUVLO UVLO threshold VIN falling VEN(HI) EN pin logic high voltage VEN(LO) EN pin logic low voltage IEN EN pin current VEN = VIN = 5.5 V 10 nA RPULLDOWN Pulldown resistor VIN = 3.3 V, P version only 120 Ω Tsd Thermal shutdown temperature Shutdown, temperature increasing 160 Reset, temperature decreasing 140 (4) 8 180 1.21 1.3 µVRMS 1.37 40 1.17 V mV 1.33 0.9 V V 0.4 V °C Dropout is measured by ramping VIN down until VOUT = VOUT(nom) – 5%. Submit Documentation Feedback Copyright © 2018–2019, Texas Instruments Incorporated Product Folder Links: TPS7A05 TPS7A05 www.ti.com SBVS254D – FEBRUARY 2018 – REVISED AUGUST 2019 6.6 Switching Characteristics specified at TJ = –40 to +125°C, VIN = VOUT(nom) + VDO(max) + 0.5 V, IOUT = 10 mA, CIN = 1 µF, and COUT = 1 µF (unless otherwise noted); typical values are at TJ = 25°C. PARAMETER tSTR (1) Start-up time (1) TEST CONDITIONS From EN assertion to VOUT = 95% × VOUT(nom) , VOUT = 1.8 V MIN TYP MAX 1.5 2.8 UNIT ms See the Special Considerations When Ramping Down IN and Enable section for details on minimum ramp down rates to ensure specified start-up time. Submit Documentation Feedback Copyright © 2018–2019, Texas Instruments Incorporated Product Folder Links: TPS7A05 9 TPS7A05 SBVS254D – FEBRUARY 2018 – REVISED AUGUST 2019 www.ti.com 6.7 Typical Characteristics at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA, VEN = VIN, CIN = 1 µF, and COUT = 1 µF (unless otherwise noted) 2.25 -40°C 0°C Quiescent Current (PA) 2 Quiescent Current in Shutdown (nA) 550 TJ 25°C 85°C 125°C 1.75 1.5 1.25 1 0.75 0.5 1 1.5 2 2.5 3 3.5 4 Input Voltage (V) 4.5 5 TJ 500 -40°C 85°C 400 350 300 250 200 150 100 2 2.5 D001 VOUT = 3.3 V, includes IQ in dropout 3 3.5 4 Input Voltage (V) 4.5 5 5.5 D002 VEN < 0.4 V Figure 1. IQ vs VIN and Temperature Figure 2. ISHDN vs VIN and Temperature 4 3500 TJ 125°C 3000 Ground Current (PA) Quiescent Current in Shutdown (nA) 25°C 450 50 1.5 5.5 0°C 2500 2000 3 2 1 1500 1000 1.5 0 2 2.5 3 3.5 4 Input Voltage (V) 4.5 5 5.5 0 1 2 3 D044 4 5 6 7 Output Current (mA) 8 9 10 D042 VEN < 0.4 V Figure 3. ISHDN vs VIN and Temperature Figure 4. IGND vs IOUT up to 10 mA 7 300 550 VOUT IOUT Ground Current (PA) 6 5 4 3 2 1 0 100 500 450 0 400 -100 350 -200 300 -300 250 -400 200 -500 150 -600 100 -700 50 -800 0 -900 0 20 40 60 80 100 120 140 Output Current (mA) 160 180 200 0 100 D043 200 300 400 500 600 Time (µs) 700 800 Output Current (mA) AC-Coupled Output Voltage (mV) 200 -50 900 1000 D036 Output current slew rate = 3.3 mA/µs Figure 5. IGND vs IOUT up to 200 mA 10 Submit Documentation Feedback Figure 6. IOUT Transient 0 mA to 100 mA Copyright © 2018–2019, Texas Instruments Incorporated Product Folder Links: TPS7A05 TPS7A05 www.ti.com SBVS254D – FEBRUARY 2018 – REVISED AUGUST 2019 Typical Characteristics (continued) at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA, VEN = VIN, CIN = 1 µF, and COUT = 1 µF (unless otherwise noted) VOUT IOUT 100 550 300 500 200 450 400 -100 350 -200 300 -300 250 -400 200 -500 150 -600 100 -700 50 -800 0 -900 0 100 200 300 400 500 600 Time (µs) 700 800 -50 900 1000 550 VOUT IOUT 100 400 -100 350 -200 300 -300 250 -400 200 -500 150 -600 100 -700 50 -800 0 -900 0 50 100 350 400 450 -50 500 D045 600 500 400 450 550 VOUT IOUT 200 500 450 0 400 -100 350 -200 300 -300 250 -400 200 -500 150 -600 100 -700 50 -800 0 -1600 0 -900 -50 500 -1800 -50 500 0 50 100 150 200 250 300 Time (µs) 350 400 450 0 400 -200 350 -400 300 -600 250 -800 200 -1000 150 -1200 100 -1400 50 0 50 Output current slew rate = 100 mA/µs Figure 9. IOUT Transient 0 mA to 100 mA 300 500 200 450 -200 350 -400 300 -600 250 -800 200 -1000 150 -1200 100 -1400 50 -1600 -1800 50 100 150 200 250 300 Time (µs) 350 400 350 400 450 D047 450 550 VOUT IOUT 100 500 450 0 400 -100 350 -200 300 -300 250 -400 200 -500 150 -600 100 -700 50 0 -800 0 -50 500 -900 0 50 D048 Output current slew rate = 200 mA/µs 100 150 200 250 300 Time (µs) 350 400 450 Output Current (mA) 400 Output Current (mA) 0 0 200 250 300 Time (µs) Figure 10. IOUT Transient 0 mA to 150 mA 550 AC-Coupled Output Voltage (mV) VOUT IOUT 200 150 Output current slew rate = 150 mA/µs 600 400 100 D046 Output Current (mA) AC-Coupled Output Voltage (mV) VOUT IOUT Figure 8. IOUT Transient 0 mA to 50 mA 550 Output Current (mA) AC-Coupled Output Voltage (mV) 200 250 300 Time (µs) Output current slew rate = 50 mA/µs Figure 7. IOUT Transient 0 mA to 200 mA AC-Coupled Output Voltage (mV) 150 D008 300 100 450 0 Output current slew rate = 6.6 mA/µs 200 500 Output Current (mA) 0 Output Current (mA) AC-Coupled Output Voltage (mV) 200 AC-Coupled Output Voltage (mV) 300 -50 500 D049 Output current slew rate = 50 mA/µs Figure 11. IOUT Transient 0 mA to 200 mA Figure 12. IOUT Transient 1 mA to 50 mA Submit Documentation Feedback Copyright © 2018–2019, Texas Instruments Incorporated Product Folder Links: TPS7A05 11 TPS7A05 SBVS254D – FEBRUARY 2018 – REVISED AUGUST 2019 www.ti.com Typical Characteristics (continued) at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA, VEN = VIN, CIN = 1 µF, and COUT = 1 µF (unless otherwise noted) VOUT IOUT 100 550 600 500 400 450 550 VOUT IOUT 200 350 -200 300 -300 250 -400 200 -500 150 -600 100 -700 50 -800 0 -1600 0 -900 -50 500 -1800 -50 500 100 150 200 250 300 Time (µs) 350 400 450 400 -200 350 -400 300 -600 250 -800 200 -1000 150 -1200 100 -1400 50 0 50 Figure 13. IOUT Transient 1 mA to 100 mA VOUT IOUT 300 -600 250 -800 200 -1000 150 -1200 100 -1400 50 -1600 0 -1800 150 200 250 300 Time (µs) 350 400 450 AC-Coupled Output Voltage (mV) -400 100 -50 500 70 20 10 50 0 40 -10 30 -20 20 -30 10 -40 0 0 20 Figure 15. IOUT Transient 1 mA to 200 mA 1800 0 1200 -100 900 -200 600 -300 300 -400 0 400 500 600 Time (µs) 700 800 80 100 120 Time (ms) 140 160 180 -10 200 D053 -300 900 1000 2100 VOUT VIN 200 100 1500 0 1200 -100 900 -200 600 -300 300 -400 0 -500 0 100 D012 IOUT = 100 mA, input voltage slew rate = 0.6 V/µs 1800 200 300 400 500 600 Time (µs) 700 800 Change in Input Voltage (mV) 1500 Change in Input Voltage (mV) 100 300 60 300 AC-Coupled Output Voltage (mV) VOUT VIN 200 40 Figure 16. IOUT Transient 3 µA to 3 mA 2100 100 60 CIN = COUT = 10 µF, output current slew rate = 3 mA/µs 300 0 D051 VOUT IOUT D052 -500 450 -50 Output current slew rate = 200 mA/µs 200 400 Output Current (mA) 400 350 Output Current (mA) AC-Coupled Output Voltage (mV) 450 0 50 350 30 500 -200 0 200 250 300 Time (µs) Figure 14. IOUT Transient 1 mA to 150 mA 550 200 150 Output current slew rate = 150 mA/µs 600 400 100 D050 Exce Output Current (mA) -100 50 0 Output current slew rate = 100 mA/µs AC-Coupled Output Voltage (mV) 450 400 0 -300 900 1000 D011 IOUT = 200 mA, input voltage slew rate = 0.6 V/µs Figure 17. VIN Transient 12 500 0 Output Current (mA) AC-Coupled Output Voltage (mV) 200 AC-Coupled Output Voltage (mV) 300 Figure 18. VIN Transient Submit Documentation Feedback Copyright © 2018–2019, Texas Instruments Incorporated Product Folder Links: TPS7A05 TPS7A05 www.ti.com SBVS254D – FEBRUARY 2018 – REVISED AUGUST 2019 Typical Characteristics (continued) at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA, VEN = VIN, CIN = 1 µF, and COUT = 1 µF (unless otherwise noted) 200 3000 2500 0 2000 -100 1500 -200 1000 -300 500 -400 0 -500 200 400 600 -500 800 1000 1200 1400 1600 1800 2000 Time (µs) D054 3500 VOUT VIN 100 3000 50 2500 0 2000 -50 1500 -100 1000 -150 500 -200 0 -250 0 200 IOUT = 150 mA, input voltage slew rate = 0.1 V/µs 400 600 Figure 19. VIN Transient Figure 20. VIN Transient 600 TJ 25°C 85°C -40°C 0°C 125°C 400 300 200 100 TJ 25°C 85°C -40°C 0°C 500 Dropout Voltage (mV) 500 Dropout Voltage (mV) -500 800 1000 1200 1400 1600 1800 2000 Time (µs) D055 IOUT = 20 mA, input voltage slew rate = 0.01 V/µs 600 125°C 400 300 200 100 0 0 0 25 50 75 100 125 Load Current (mA) 150 175 200 0 25 50 D013 VOUT = 1.8 V 75 100 125 Load Current (mA) 150 175 200 D014 VOUT = 3.3 V Figure 21. Dropout vs IOUT and Temperature Figure 22. Dropout vs IOUT and Temperature 10 600 TJ -40°C 0°C 25°C 85°C 125°C 400 9 Change in Output Voltage (mV) 500 Dropout Voltage (mV) Change in Input Voltage (mV) 100 0 150 AC-Coupled Output Voltage (mV) 3500 VOUT VIN Change in Input Voltage (mV) AC-Coupled Output Voltage (mV) 300 300 200 100 TJ 25°C 85°C -40°C 0°C 8 125°C 7 6 5 4 3 2 1 0 0 1.6 -1 1.8 2 2.2 2.4 2.6 Input Voltage (V) 2.8 3 3.2 1 1.5 D027 2 2.5 3 3.5 4 Input Voltage (V) 4.5 5 5.5 D009 VOUT = 0.8 V Figure 23. Dropout vs VIN and Temperature Figure 24. Line Regulation VIN and Temperature Submit Documentation Feedback Copyright © 2018–2019, Texas Instruments Incorporated Product Folder Links: TPS7A05 13 TPS7A05 SBVS254D – FEBRUARY 2018 – REVISED AUGUST 2019 www.ti.com Typical Characteristics (continued) at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA, VEN = VIN, CIN = 1 µF, and COUT = 1 µF (unless otherwise noted) 14 TJ 25°C 85°C -40°C 0°C 1 125°C Change in Output Voltage (mV) Output Voltage Accuracy ( ) 1.2 0.8 0.6 0.4 0.2 0 -0.2 TJ 25°C 85°C -40°C 0°C 12 10 8 6 4 2 0 -2 1 1.5 2 2.5 3 3.5 4 Input Voltage (V) 4.5 5 5.5 2 2.5 3 D006 VOUT = 0.8 V Figure 25. Output Accuracy VIN and Temperature 5 5.5 D004 Figure 26. Line Regulation VIN and Temperature 0.8 125°C Change in Output Voltage (mV) Output Voltage Accuracy ( ) 4.5 6 TJ 25°C 85°C -40°C 0°C 0.6 0.4 0.2 0 -0.2 0 -6 -12 TJ -40°C 0°C 25°C 85°C 125°C -18 -24 -30 2 2.5 3 3.5 4 Input Voltage (V) 4.5 5 0 5.5 20 40 60 D005 TJ -40°C 0°C Voltage (V) 25°C 85°C 1.5 1 0.5 0 0 50 100 150 160 180 200 Figure 28. Load Regulation vs IOUT and Temperature Figure 27. Output Accuracy VIN and Temperature 2.5 2 80 100 120 140 Output Current (mA) VOUT = 1.8 V VOUT = 1.8 V Output Voltage (V) 3.5 4 Input Voltage (V) VOUT = 1.8 V 1 200 250 300 350 Output Current (mA) 400 450 500 3 2.8 2.6 2.4 2.2 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 -0.2 VEN VIN VOUT 0 0.5 D003 VOUT = 1.8 V 1 1.5 2 2.5 3 Time (ms) 3.5 4 4.5 5 D029 VOUT = 0.8 V, IOUT = 1 mA Figure 29. Foldback Current Limit vs IOUT and Temperature 14 125°C Submit Documentation Feedback Figure 30. Startup With VEN = VIN Copyright © 2018–2019, Texas Instruments Incorporated Product Folder Links: TPS7A05 TPS7A05 www.ti.com SBVS254D – FEBRUARY 2018 – REVISED AUGUST 2019 Typical Characteristics (continued) 3 2.8 2.6 2.4 2.2 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 -0.2 Voltage (V) Voltage (V) at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA, VEN = VIN, CIN = 1 µF, and COUT = 1 µF (unless otherwise noted) VEN VIN VOUT 0 0.5 1 1.5 2 2.5 3 Time (ms) 3.5 4 4.5 3 2.8 2.6 2.4 2.2 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 -0.2 5 VEN VIN VOUT 0 0.5 1 VOUT = 0.8 V, IOUT = 30 mA VEN VIN VOUT 1 1.5 2 2.5 3 Time (ms) 3.5 3.5 4 4.5 5 D031 4 4.5 3 2.8 2.6 2.4 2.2 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 -0.2 5 VEN VIN VOUT 0 0.5 1 1.5 2 D032 VOUT = 0.8 V, IOUT = 1 mA 2.5 3 Time (ms) 3.5 4 4.5 5 D033 VOUT = 0.8 V, IOUT = 30 mA Figure 33. Startup With Separate VIN and VEN Figure 34. Startup With Separate VIN and VEN 60 3 2.8 2.6 2.4 2.2 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 -0.2 Power Supply Rejection Ratio (dB) Voltage (V) 2.5 3 Time (ms) Figure 32. Startup With VEN = VIN Voltage (V) Voltage (V) Figure 31. Startup With VEN = VIN 0.5 2 VOUT = 1.8 V, IOUT = 30 mA 3 2.8 2.6 2.4 2.2 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 -0.2 0 1.5 D030 VEN VIN VOUT 0 0.5 1 1.5 2 2.5 3 Time (ms) 3.5 4 4.5 5 55 50 45 40 35 30 25 20 15 10 VIN 1.4 V 1.5 V 1.6 V 1.8 V 5 10 D034 VOUT = 1.8 V, IOUT = 30 mA 100 1k 10k 100k Frequency (Hz) 1M 10M D022 VOUT = 0.8 V, IOUT = 200 mA, COUT = 1 µF, CIN = 0 µF Figure 35. Startup With Separate VIN and VEN Figure 36. PSRR vs Frequency and VIN Submit Documentation Feedback Copyright © 2018–2019, Texas Instruments Incorporated Product Folder Links: TPS7A05 15 TPS7A05 SBVS254D – FEBRUARY 2018 – REVISED AUGUST 2019 www.ti.com Typical Characteristics (continued) at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA, VEN = VIN, CIN = 1 µF, and COUT = 1 µF (unless otherwise noted) 60 VIN 2.2 V 2.3 V 2.4 V 2.5 V 50 45 40 2.8 V 3.3 V 3.6 V Power Supply Rejection Ratio (dB) Power Supply Rejection Ratio (dB) 55 35 30 25 20 15 10 5 0 10 100 1k 10k 100k Frequency (Hz) 1M VIN 3.6 V 3.8 V 4.0 V 50 40 30 20 10 0 10 10M 100 Power Supply Rejection Ratio (dB) Power Supply Rejection Ratio (dB) 1k 10k 100k Frequency (Hz) 1M 10M 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 10 100 1k 10k 100k Frequency (Hz) 1M 10M D015 Figure 40. PSRR vs Frequency and IOUT 20 10 Output Voltage Noise (PV —Hz) Power Supply Rejection Ratio (dB) D020 VOUT = 1.8 V, VIN = 2.8 V, COUT = 1 µF, CIN = 0 µF Figure 39. PSRR vs Frequency and IOUT IOUT 0 mA 10 mA 50 mA 100 mA 150 mA 200 mA 100 5 2 1 0.5 0.2 0.1 0.05 VIN 2.2 V 2.8 V 0.02 0.01 1k 10k 100k Frequency (Hz) 1M 10M 0.005 10 100 D019 VOUT = 3.3 V, VIN = 3.8 V, COUT = 1 µF, CIN = 0 µF Figure 41. PSRR vs Frequency and IOUT 16 10M IOUT 0 mA 10 mA 50 mA 100 mA 150 mA 200 mA D021 VOUT = 0.8 V, VIN = 1.4 V, COUT = 1 µF, CIN = 0 µF 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 10 1M Figure 38. PSRR vs Frequency and VIN IOUT 0 mA 10 mA 50 mA 100 mA 100 10k 100k Frequency (Hz) VOUT = 3.3 V, IOUT = 200 mA, COUT = 1 µF, CIN = 0 µF Figure 37. PSRR vs Frequency and VIN 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 10 1k D016 VOUT = 1.8 V, IOUT = 200 mA, COUT = 1 µF, CIN = 0 µF 4.2 V 4.6 V 3.3 V 5.5 V 1k 10k 100k Frequency (Hz) 1M 10M D025 VOUT = 1.8 V, IOUT = 200 mA, COUT = 1 µF Figure 42. Output Noise vs Frequency and VIN Submit Documentation Feedback Copyright © 2018–2019, Texas Instruments Incorporated Product Folder Links: TPS7A05 TPS7A05 www.ti.com SBVS254D – FEBRUARY 2018 – REVISED AUGUST 2019 Typical Characteristics (continued) at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA, VEN = VIN, CIN = 1 µF, and COUT = 1 µF (unless otherwise noted) 20 10 IOUT 50 mA 100 mA 5 5 150 mA 200 mA Output Voltage Noise (PV —Hz) Output Voltage Noise (PV —Hz) 10 2 1 0.5 0.2 0.1 0.05 0.02 2 1 0.5 0.2 0.1 0.05 COUT 1.0 µF 10 µF 0.02 0.01 0.01 0.005 10 0.005 10 100 1k 10k 100k Frequency (Hz) 1M 10M 100 VOUT = 1.8 V, VIN = 2.8 V, COUT = 1 µF 10k 100k Frequency (Hz) 1M 10M D026 VOUT = 1.8 V, VIN = 2.8 V, IOUT = 200 mA Figure 43. Output Noise vs Frequency and IOUT Figure 44. Output Noise vs Frequency and COUT 1.3 20 VUVLO, Rising VUVLO, Falling 10 5 1.28 2 Input Voltage (V) Output Voltage Noise (PV —Hz) 1k D024 1 0.5 0.2 0.1 0.05 VOUT 0.8 V 1.8 V 3.3 V 0.02 0.01 0.005 10 100 1.26 1.24 1k 10k 100k Frequency (Hz) 1M 10M 1.22 -40 -20 0 20 D028 40 60 80 Temperature (qC) 100 120 140 D035 VIN = VOUT + 1 V, IOUT = 200 mA, COUT = 1 µF Figure 45. Output Noise vs Frequency and VOUT Figure 46. UVLO VIN Rising and Falling Thresholds vs Temperature 0.68 VEN(HI) VEN(LO) Enable Voltage (V) 0.66 0.64 0.62 0.6 0.58 0.56 0.54 -40 -20 0 20 40 60 80 Temperature (qC) 100 120 140 D037 Figure 47. Enable High and Low Thresholds vs Temperature Submit Documentation Feedback Copyright © 2018–2019, Texas Instruments Incorporated Product Folder Links: TPS7A05 17 TPS7A05 SBVS254D – FEBRUARY 2018 – REVISED AUGUST 2019 www.ti.com 7 Detailed Description 7.1 Overview The TPS7A05 is a ultra-low IQ linear voltage regulator that is optimized for excellent transient performance. These characteristics make the TPS7A05 ideal for most battery-powered applications. This low-dropout regulator (LDO) offers foldback current limit, shutdown, thermal protection, and optional active discharge. 7.2 Functional Block Diagram Current Limit IN 1.2-V Bandgap OUT + Active Discharge P-Version Only ± ± Error Amp + UVLO Internal Controller Thermal Shutdown EN GND 18 Submit Documentation Feedback Copyright © 2018–2019, Texas Instruments Incorporated Product Folder Links: TPS7A05 TPS7A05 www.ti.com SBVS254D – FEBRUARY 2018 – REVISED AUGUST 2019 7.3 Feature Description 7.3.1 Excellent Transient Response The device includes several innovative circuits to ensure excellent transient response. Dynamic biasing increases the IQ for a short duration during transients to extend the closed-loop bandwidth and improve the device response time during transients. Adaptive biasing increases the IQ as the dc load current increases, extending the bandwidth of the control loop. The device response time across the output voltage range is constant because of the use of a buffered reference topology, which keeps the control loop in unity gain at any output voltage. These features give the device a wide loop bandwidth during transients that ensure excellent transient response while maintaining the device low IQ in steady-state conditions; see the Application and Implementation section for more details. 7.3.2 Active Discharge Devices with this option have an internal pulldown MOSFET that connects a 120-Ω resistor to ground when the device is disabled to actively discharge the output voltage. The active discharge circuit is activated when the device is disabled, in undervoltage lockout (UVLO), or in thermal shutdown. The discharge time after disabling depends on the output capacitance (COUT) and the load resistance (RL) in parallel with the 120-Ω pulldown resistor. Equation 1 calculates the time constant: 120 · RL t= · COUT 120 + RL (1) Do not rely on the active discharge circuit for discharging a large amount of output capacitance after the input supply has collapsed because reverse current can flow from the output to the input. This reverse current flow can cause damage to the device. Limit reverse current to no more than 5% of the device-rated current. 7.3.3 Low IQ in Dropout In most LDOs the IQ significantly increases when the device is placed into dropout, which is especially true for low IQ LDOs with adaptive biasing. The TPS7A05 detects when operating in dropout and disables the adaptive biasing, minimizing the IQ increase. 7.3.4 Undervoltage Lockout (UVLO) The undervoltage lockout (UVLO) circuit monitors the input voltage (VIN) to prevent the device from turning on before VIN rises above the lockout voltage. The UVLO circuit also disables the output of the device when VIN falls below the lockout voltage. If the device includes the optional active discharge, the output is connected to ground with a 120-Ω pulldown resistor when VIN is below the lockout voltage; see the Application and Implementation section for more details. 7.3.5 Enable The enable pin for the device is active high. The output of the device is turned on when the enable pin voltage is greater than the EN pin logic high voltage, and the output of the device is turned off when the enable pin voltage is less than the EN pin logic low voltage. A voltage less than the EN pin logic low voltage on the enable pin disables all internal circuits. At the next turn-on, any voltage on the EN pin below the logic low voltage ensures a normal start-up waveform with start-up ramp rate control, provided there is enough time to discharge the output capacitance. If shutdown capability is not required, connect EN to IN. VEN must not exceed VIN. 7.3.6 Internal Foldback Current Limit The internal foldback current-limit circuit is used to protect the LDO against high-load current faults or shorting events. The foldback mechanism lowers the current limit as the output voltage decreases, and limits power dissipation during short-circuit events while still allowing for the device to operate at its rated output current; see Figure 29. Submit Documentation Feedback Copyright © 2018–2019, Texas Instruments Incorporated Product Folder Links: TPS7A05 19 TPS7A05 SBVS254D – FEBRUARY 2018 – REVISED AUGUST 2019 www.ti.com Feature Description (continued) A foldback example for this device is that when VOUT is 90% of VOUT(nom) the current limit is ICL(typical); however, if VOUT is forced to 0 V the current limit is ISC (typical). In many LDOs the foldback current limit can prevent start-up into a constant-current load or a negatively-biased output. The foldback mechanism for this device goes into a brick-wall current limit when VOUT > 500 mV (typ), thus limiting current to ICL(typical) and, when VOUT is approximately 0 V, current is limited to ISC (typical) to ensure normal start-up into a variety of loads. The foldback current limit is disengaged when IOUT < 1 mA (typical) to reduce IQ. As such, the current-limit loop takes longer to respond to a current-limit event when IOUT < 1 mA (typ). Thermal shutdown can activate during a current-limit event because of the high power dissipation typically found in these conditions. To ensure proper operation of the current limit, minimize the inductances to the input and load. Continuous operation in current limit is not recommended. 7.3.7 Thermal Shutdown The device contains a thermal shutdown protection circuit to disable the device when thermal junction temperature (TJ) of the main pass-FET rises to Tsd(Shutdown) (typical). Thermal shutdown hysteresis assures that the LDO resets again (turns on) when the temperature falls to Tsd(Reset) (typical). The thermal time-constant of the semiconductor die is fairly short, and thus the device may cycle on and off when thermal shutdown is reached until power dissipation is reduced. For reliable operation, limit the junction temperature to a maximum of 125°C. Operation above 125°C causes the device to exceed its operational specifications. Although the internal protection circuitry of the device is designed to protect against thermal overload conditions, this circuitry is not intended to replace proper heat sinking. Continuously running the device into thermal shutdown or above a junction temperature of 125°C reduces longterm reliability. A fast start-up when TJ > Tsd(Reset) (typical, outside of the specified operating range) causes the device thermal shutdown to assert at Tsd(Reset) and prevents the device from turning on until the junction temperature is reduced below Tsd(Shutdown). 20 Submit Documentation Feedback Copyright © 2018–2019, Texas Instruments Incorporated Product Folder Links: TPS7A05 TPS7A05 www.ti.com SBVS254D – FEBRUARY 2018 – REVISED AUGUST 2019 7.4 Device Functional Modes The device has several modes of operation,: • • • Normal operation: The device regulates to the nominal output voltage Dropout operation: The pass element operates as a resistor and the output voltage is set as VIN – VDO Shutdown: The output of the device is disabled and the discharge circuit is activated Table 1 shows the conditions that lead to the different modes of operation. See the Electrical Characteristics table for parameter values. Table 1. Device Functional Mode Comparison PARAMETER OPERATING MODE VIN VEN IOUT TJ Normal mode VIN > VOUT(nom) + VDO and VIN > VIN(min) VEN > VEN(HI) IOUT < IOUT(max) TJ < Tsd(Shutdown) Dropout mode VIN(min) < VIN < VOUT(nom) + VDO VEN > VEN(HI) IOUT < IOUT(max) TJ < Tsd(Shutdown) VIN < VUVLO VEN < VEN(LO) — TJ > Tsd(Shutdown) Disabled mode (any true condition disables the device) 7.4.1 Normal Mode The device regulates the output to the nominal output voltage when all normal mode conditions in Table 1 are met. 7.4.2 Dropout Mode The device is not in regulation, and the output voltage tracks the input voltage minus the voltage drop across the pass transistor of the device. In this mode, the PSRR, noise, and transient performance of the device are significantly degraded. 7.4.3 Disable Mode In this mode, the pass element is turned off, the internal circuits are shut down, and the output voltage is actively discharged to ground by an internal resistor. Submit Documentation Feedback Copyright © 2018–2019, Texas Instruments Incorporated Product Folder Links: TPS7A05 21 TPS7A05 SBVS254D – FEBRUARY 2018 – REVISED AUGUST 2019 www.ti.com 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information 8.1.1 Recommended Capacitor Types The device is designed to be stable using low equivalent series resistance (ESR) ceramic capacitors at the input and output. Multilayer ceramic capacitors have become the industry standard for these types of applications and are recommended, but must be used with good judgment. Ceramic capacitors that employ X7R-, X5R-, and COG-rated dielectric materials provide relatively good capacitive stability across temperature, whereas the use of Y5V-rated capacitors is discouraged because of large variations in capacitance. Regardless of the ceramic capacitor type selected, the effective capacitance varies with operating voltage and temperature. As a rule of thumb, assume effective capacitance to decrease by as much as 50%. The input and output capacitors recommended in the Recommended Operating Conditions table account for an effective capacitance of approximately 50% of the nominal value. 8.1.2 Input and Output Capacitor Requirements Although an input capacitor is not required for stability, good analog design practice is to connect a capacitor from IN to GND. This capacitor counteracts reactive input sources and improves transient response, input ripple, and PSRR. An input capacitor is recommended if the source impedance is more than 0.5 Ω. A higher value capacitor may be necessary if large, fast rise-time load or line transients are anticipated or if the device is located several inches from the input power source. Dynamic performance of the device is improved with the use of an output capacitor. Use an output capacitor within the range specified in the Recommended Operating Conditions table for stability. 8.1.3 Special Considerations When Ramping Down VIN and Enable Care must be taken when ramping down voltage on the IN and EN pins to power-down the device when the operating free-air temperature is less than 15°C. The minimum ramp-down time for the IN pin is 10 ms. The minimum ramp-down time for the EN pin is 100 µs. Ramping at faster rates can cause the regulator to exhibit undesired startup behavior on the next power-on. If VIN is ramped down faster than 10 ms, the next startup may exhibit a partial startup, shutoff, followed by a normal soft-start startup. Figure 48 shows this response. 4 VEN VIN VOUT 3.5 3 Voltage (V) 2.5 2 1.5 1 0.5 0 -0.5 -1 0 1 2 3 4 5 6 Time (ms) 7 8 9 10 D040 Figure 48. Partial Startup, Shutdown, Normal Startup With VEN = VIN 22 Submit Documentation Feedback Copyright © 2018–2019, Texas Instruments Incorporated Product Folder Links: TPS7A05 TPS7A05 www.ti.com SBVS254D – FEBRUARY 2018 – REVISED AUGUST 2019 Application Information (continued) If the EN pin is ramped down faster than 100 µs, the next startup may exhibit a delay time of up to 130 ms before the output ramps up with a normal soft-start startup. Figure 49 shows this delay. 4 3.5 3 Voltage (V) 2.5 2 1.5 1 0.5 VOUT VIN 0 -0.5 -1 0 100 200 300 400 500 600 Time (ms) 700 800 900 1000 D041 Figure 49. Long Delay to Startup With VEN = VIN Fast ramp downs of VIN and the EN pin charge internal high-impedance nodes in the device, which take extended time to discharge below 15°C. To avoid these startup behaviors, follow the recommended minimum ramp down times for VIN and the EN pin. 8.1.4 Load Transient Response The load-step transient response is the output voltage response by the LDO to a step in load current, whereby output voltage regulation is maintained. See Figure 6 for typical load transient response. There are two key transitions during a load transient response: the transition from a light to a heavy load and the transition from a heavy to a light load. The regions in Figure 50 are broken down as described in this section. Regions A, E, and H are where the output voltage is in steady-state. During transitions from a light load to a heavy load, the: • • Initial voltage dip is a result of the depletion of the output capacitor charge and parasitic impedance to the output capacitor (region B) Recovery from the dip results from the LDO increasing its sourcing current, and leads to output voltage regulation (region C) During transitions from a heavy load to a light load, the: • • Initial voltage rise results from the LDO sourcing a large current, and leads to the output capacitor charge to increase (region F) Recovery from the rise results from the LDO decreasing its sourcing current in combination with the load discharging the output capacitor (region G) A larger output capacitance reduces the peaks during a load transient but slows down the response time of the device. A larger dc load also reduces the peaks because the amplitude of the transition is lowered and a higher current discharge path is provided for the output capacitor. tAt tCt B tDt tEt tGt tHt F Figure 50. Load Transient Waveform Submit Documentation Feedback Copyright © 2018–2019, Texas Instruments Incorporated Product Folder Links: TPS7A05 23 TPS7A05 SBVS254D – FEBRUARY 2018 – REVISED AUGUST 2019 www.ti.com Application Information (continued) 8.1.5 Dropout Voltage The device uses a PMOS pass transistor to achieve low dropout. When (VIN – VOUT) is less than the dropout voltage (VDO), the PMOS pass transistor is in the linear region of operation, and the input-to-output resistance of the device is the drain-to-source resistance of the PMOS pass transistor. VDO scales with the output current and changes with temperature because the PMOS pass transistor functions like a resistor in dropout mode. For a graph of dropout voltage, see Figure 22. As with any linear regulator, PSRR and the transient response degrade as (VIN – VOUT) approaches dropout operation. See Figure 23 for dropout performance. 8.1.5.1 Behavior When Transitioning From Dropout Into Regulation Some applications may have transients that place the device into dropout, especially as this device can be powered from a battery with high ESR. A typical application with these conditions is using a stack of two 1.55-V coin-cell batteries with an ESR of 30 Ω to create a 2.5-V rail and experiencing a load transient from 1 µA to 25 mA. This load transient causes the input supply to drop 750 mV, placing the device into dropout. The load transient saturates the output stage of the error amplifier when the pass element is driven fully on, making the pass element function like a resistor from VIN to VOUT. The error amplifier response time to this load transient is limited because the error amplifier must first recover from saturation and then place the pass element back into active mode. During this time VOUT overshoots because the pass element is functioning as a resistor from VIN to VOUT. This device uses a loop pulldown circuit to help mitigate the overshoot. If operating under these conditions, applying a higher dc load or increasing the output capacitance reduces the overshoot because these solutions provide a path to dissipate the excess charge. 8.1.5.2 Behavior of Output Resulting From Line Transient When in Dropout The output deviation resulting from a line transient can be significantly higher when the device is operating in dropout. As explained in the Dropout Voltage section, the response time of the error amplifier is limited when in dropout, so the output deviation is larger and can exceed twice the regulated output voltage. Care must be taken in applications where line transients are expected when the device is operating in dropout. 8.1.6 Undervoltage Lockout (UVLO) Operation The UVLO circuit ensures that the device stays disabled before its input supply reaches the minimum operational voltage range, and ensures that the device shuts down when the input supply collapses. See Figure 46 for rising and falling thresholds. Figure 51 depicts the UVLO circuit response to various input voltage events. The diagram can be separated into the following parts: • • • • • • • 24 Region A: The device does not start until the input reaches the UVLO rising threshold Region B: Normal operation, regulating device Region C: Brownout event above the UVLO falling threshold (UVLO rising threshold – UVLO hystersis). The output may fall out of regulation but the device is still enabled. Region D: Normal operation, regulating device Region E: Brownout event below the UVLO falling threshold. The device is disabled in most cases and the output falls as a result of the load and active discharge circuit. The device is re-enabled when the UVLO rising threshold is reached by the input voltage and a normal start-up follows. Region F: Normal operation followed by the input falling to the UVLO falling threshold Region G: The device is disabled as the input voltage falls below the UVLO falling threshold to 0 V. The output falls as a result of the load and active discharge circuit. Submit Documentation Feedback Copyright © 2018–2019, Texas Instruments Incorporated Product Folder Links: TPS7A05 TPS7A05 www.ti.com SBVS254D – FEBRUARY 2018 – REVISED AUGUST 2019 Application Information (continued) UVLO Rising Threshold UVLO Hysteresis VIN C VOUT tAt tBt tDt tEt tFt tGt Figure 51. Typical UVLO Operation 8.1.7 Power Dissipation (PD) Circuit reliability demands that proper consideration be given to device power dissipation, location of the circuit on the printed circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator must be as free as possible of other heat-generating devices that cause added thermal stresses. Equation 2 calculates the maximum allowable power dissipation for the device in a given package: PD-MAX = ((TJ – TA) / RθJA) (2) Equation 3 represents the actual power being dissipated in the device: PD = (VIN - VOUT) × IOUT (3) An important note is that power dissipation can be minimized, and thus greater efficiency achieved, by proper selection of the system voltage rails. Proper selection allows the minimum input-to-output voltage differential to be obtained. The low dropout of the TPS7A05 allows for maximum efficiency across a wide range of output voltages. The main heat conduction path for the device depends on the ambient temperature and the thermal resistance across the various interfaces between the die junction and ambient air. The maximum power dissipation determines the maximum allowable junction temperature (TJ) for the device. According to Equation 4, maximum power dissipation and junction temperature are most often related by the junction-to-ambient thermal resistance (RθJA) of the combined PCB and device package and the temperature of the ambient air (TA). The equation is rearranged in Equation 5 for output current. TJ = TA + (RθJA × PD) IOUT = (TJ – TA) / [RθJA × (VIN – VOUT)] (4) (5) Unfortunately, this thermal resistance (RθJA) is highly dependent on the heat-spreading capability built into the particular PCB design, and therefore varies according to the total copper area, copper weight, and location of the planes. The RθJA recorded in the Thermal Information table is determined by the JEDEC standard, PCB, and copper-spreading area, and is only used as a relative measure of package thermal performance. For a welldesigned thermal layout, RθJA is actually the sum of the DQN package junction-to-case (bottom) thermal resistance (RθJC(bot)) plus the thermal resistance contribution by the PCB copper. Submit Documentation Feedback Copyright © 2018–2019, Texas Instruments Incorporated Product Folder Links: TPS7A05 25 TPS7A05 SBVS254D – FEBRUARY 2018 – REVISED AUGUST 2019 www.ti.com Application Information (continued) 8.1.7.1 Estimating Junction Temperature The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures of the LDO when in-circuit on a typical PCB board application. These metrics are not strictly speaking thermal resistances, but rather offer practical and relative means of estimating junction temperatures. These psi metrics are determined to be significantly independent of the copper-spreading area. The key thermal metrics (ΨJT and ΨJB) are used in accordance with Equation 6 and are given in the Thermal Information table. ΨJT : TJ = TT + ΨJT × PD and ΨJB : TJ = TB + ΨJB × PD where: • • • PD is the power dissipated as explained in Equation 3 TT is the temperature at the center-top of the device package, and TB is the PCB surface temperature measured 1 mm from the device package and centered on the package edge (6) 8.1.7.2 Recommended Area for Continuous Operation The operational area of an LDO is limited by the dropout voltage, output current, junction temperature, and input voltage. The recommended area for continuous operation for a linear regulator is shown in Figure 52 and can be separated into the following regions: • • • Output Current (A) • Dropout voltage limits the minimum differential voltage between the input and the output (VIN – VOUT) at a given output current level; see the Dropout Voltage section for more details. The rated output currents limits the maximum recommended output current level. Exceeding this rating causes the device to fall out of specification. The rated junction temperature limits the maximum junction temperature of the device. Exceeding this rating causes the device to fall out of specification and reduces long-term reliability. – Equation 5 provides the shape of the slope. The slope is nonlinear because the maximum rated junction temperature of the LDO is controlled by the power dissipation across the LDO, thus when VIN – VOUT increases the output current must decrease. The rated input voltage range governs both the minimum and maximum of VIN – VOUT. Output Current Limited by Dropout Rated Output Current Output Current Limited by Thermals Limited by Maximum VIN Limited by Minimum VIN VIN ± VOUT (V) Figure 52. Region Description for Continuous Operation 26 Submit Documentation Feedback Copyright © 2018–2019, Texas Instruments Incorporated Product Folder Links: TPS7A05 TPS7A05 www.ti.com SBVS254D – FEBRUARY 2018 – REVISED AUGUST 2019 8.2 Typical Application IN CIN OUT COUT TPS7A05 VBAT Load EN GND Figure 53. Operation From the Battery Input Supply 8.2.1 Design Requirements Table 2 summarizes the design requirements for Figure 53. Table 2. Design Parameters PARAMETER DESIGN REQUIREMENT Input voltage 3.0 V to 2.0 V (CR2032 battery) Output voltage 1.0 V, ±2% (TJ from –40 to +85ºC) Output load 10 mA 8.2.2 Design Considerations For this design example, the 1.0-V, fixed-version TPS7A0510 device is selected. A single CR2032 coin-cell battery was used, thus a 1.0-µF input capacitor is recommended to minimize transient currents drawn from the battery. A 1.0-µF output capacitor is also recommended for excellent load transient response. The dropout voltage (VDO) is kept within the TPS7A05 dropout voltage specification for the 1.0-V output voltage option to keep the device in regulation under all load and temperature conditions for this design. The very small ground current consumed by the regulator shown in Figure 54 allows for long battery life. 8.2.3 Application Curve Ground Current (PA) 4 3 2 1 0 0 1 2 3 4 5 6 7 Output Current (mA) 8 9 10 D042 Figure 54. IGND vs IOUT at 25°C 9 Power Supply Recommendations This device is designed to operate from an input supply voltage range of 1.4 V to 5.5 V. The input supply must be well regulated and free of spurious noise. To ensure that the output voltage is well regulated and dynamic performance is optimum, the input supply must be at least VOUT(nom) + 0.5 V. A 1 µF or greater input capacitor is recommended to be used to reduce the impedance of the input supply, especially during transients. Submit Documentation Feedback Copyright © 2018–2019, Texas Instruments Incorporated Product Folder Links: TPS7A05 27 TPS7A05 SBVS254D – FEBRUARY 2018 – REVISED AUGUST 2019 www.ti.com 10 Layout 10.1 Layout Guidelines • • • • Place input and output capacitors as close to the device as possible Use copper planes for device connections to optimize thermal performance Place thermal vias around the device to distribute heat Do not place a thermal via directly beneath the thermal pad of the DQN package. A via can wick solder or solder paste away from the thermal pad joint during the soldering process, leading to a compromised solder joint on the thermal pad. 10.2 Layout Example OUT A2 IN A1 CIN COUT Via B1 EN B2 GND Figure 55. Layout Example for the YKA Package VOUT VIN 1 CIN 5 COUT 2 3 4 EN GND PLANE Represents via used for application specific connections Figure 56. Layout Example for the DBV Package VOUT VIN 1 4 COUT CIN 2 3 EN GND PLANE Represents via used for application specific connections Figure 57. Layout Example for the DQN Package 28 Submit Documentation Feedback Copyright © 2018–2019, Texas Instruments Incorporated Product Folder Links: TPS7A05 TPS7A05 www.ti.com SBVS254D – FEBRUARY 2018 – REVISED AUGUST 2019 11 Device and Documentation Support 11.1 Device Support 11.1.1 Spice Models SPICE models for the TPS7A05 are available through the product folder under Tools & software. 11.1.2 Device Nomenclature Table 3. Device Nomenclature (1) (2) (1) (2) PRODUCT VOUT TPS7A05xx(x)Pyyyz xx(x) is the nominal output voltage. For output voltages with a resolution of 100 mV, two digits are used in the ordering number; otherwise, three digits are used (for example, 28 = 2.8 V; 125 = 1.25 V). P is optional; P indicates an active output discharge feature. yyy is the package designator. z is the package quantity. R is for reel (3000 pieces), T is for tape (250 pieces). For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the device product folder on www.ti.com. Output voltages from 1.0 V to 3.3 V in 50-mV increments are available. Contact the factory for details and availability. 11.2 Documentation Support 11.2.1 Related Documentation For related documentation see the following: Universal Low-Dropout (LDO) Linear Voltage Regulator MultiPkgLDOEVM-823 Evaluation Module 11.3 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 11.4 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.5 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 11.6 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 11.7 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. Submit Documentation Feedback Copyright © 2018–2019, Texas Instruments Incorporated Product Folder Links: TPS7A05 29 TPS7A05 SBVS254D – FEBRUARY 2018 – REVISED AUGUST 2019 www.ti.com 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 30 Submit Documentation Feedback Copyright © 2018–2019, Texas Instruments Incorporated Product Folder Links: TPS7A05 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TPS7A0508PDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 1C6F TPS7A0508PDBVT ACTIVE SOT-23 DBV 5 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 1C6F TPS7A0508PDBZR ACTIVE SOT-23 DBZ 3 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 1QMW TPS7A0508PDBZT ACTIVE SOT-23 DBZ 3 250 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 1QMW TPS7A0508PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 6G TPS7A0508PDQNT ACTIVE X2SON DQN 4 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 6G TPS7A0508PYKAR ACTIVE DSBGA YKA 4 12000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 3 TPS7A0510PDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 1IKF TPS7A0510PDBVT ACTIVE SOT-23 DBV 5 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 1IKF TPS7A0510PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 C7 TPS7A0510PDQNT ACTIVE X2SON DQN 4 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 C7 TPS7A0510PYKAR ACTIVE DSBGA YKA 4 12000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 L TPS7A0511PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 HK TPS7A0512PDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 1ILF TPS7A0512PDBVT ACTIVE SOT-23 DBV 5 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 1ILF TPS7A0512PDBZR ACTIVE SOT-23 DBZ 3 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 1QOW TPS7A0512PDBZT ACTIVE SOT-23 DBZ 3 250 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 1QOW TPS7A0512PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 C8 TPS7A0512PDQNT ACTIVE X2SON DQN 4 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 C8 TPS7A0512PYKAR ACTIVE DSBGA YKA 4 12000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 M Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 10-Dec-2020 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TPS7A0515PDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 1IMF TPS7A0515PDBVT ACTIVE SOT-23 DBV 5 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 1IMF TPS7A0515PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 C9 TPS7A0515PDQNT ACTIVE X2SON DQN 4 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 C9 TPS7A0515PYKAR ACTIVE DSBGA YKA 4 12000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 N TPS7A051825PYKAR ACTIVE DSBGA YKA 4 12000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 P TPS7A0518PDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 1INF TPS7A0518PDBVT ACTIVE SOT-23 DBV 5 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 1INF TPS7A0518PDBZR ACTIVE SOT-23 DBZ 3 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 1QQW TPS7A0518PDBZT ACTIVE SOT-23 DBZ 3 250 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 1QQW TPS7A0518PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 CA TPS7A0518PDQNT ACTIVE X2SON DQN 4 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 CA TPS7A0518PYKAR ACTIVE DSBGA YKA 4 12000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 P TPS7A0520PDBZR ACTIVE SOT-23 DBZ 3 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 1U8W TPS7A0520PDBZT ACTIVE SOT-23 DBZ 3 250 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 1U8W TPS7A0520PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 G1 TPS7A0522PDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 1P3F TPS7A0522PDBVT ACTIVE SOT-23 DBV 5 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 1P3F TPS7A0522PDBZR ACTIVE SOT-23 DBZ 3 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 1U9W TPS7A0522PDBZT ACTIVE SOT-23 DBZ 3 250 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 1U9W TPS7A0525PDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 1IOF Addendum-Page 2 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 10-Dec-2020 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TPS7A0525PDBVT ACTIVE SOT-23 DBV 5 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 1IOF TPS7A0525PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 CB TPS7A0525PDQNT ACTIVE X2SON DQN 4 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 CB TPS7A0525PYKAR ACTIVE DSBGA YKA 4 12000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 Q TPS7A0527PDBZR ACTIVE SOT-23 DBZ 3 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 1UAW TPS7A0527PDBZT ACTIVE SOT-23 DBZ 3 250 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 1UAW TPS7A05285PDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 1IRF TPS7A05285PDBVT ACTIVE SOT-23 DBV 5 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 1IRF TPS7A05285PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 CC TPS7A05285PDQNT ACTIVE X2SON DQN 4 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 CC TPS7A05285PYKAR ACTIVE DSBGA YKA 4 12000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 R TPS7A0528PDBZR ACTIVE SOT-23 DBZ 3 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 1QSW TPS7A0528PDBZT ACTIVE SOT-23 DBZ 3 250 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 1QSW TPS7A0528PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 DH TPS7A0528PDQNT ACTIVE X2SON DQN 4 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 DH TPS7A0530PDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 1QWF TPS7A0530PDBVT ACTIVE SOT-23 DBV 5 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 1QWF TPS7A0530PDBZR ACTIVE SOT-23 DBZ 3 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 1QUW TPS7A0530PDBZT ACTIVE SOT-23 DBZ 3 250 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 1QUW TPS7A0530PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 DG TPS7A0530PDQNT ACTIVE X2SON DQN 4 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 DG Addendum-Page 3 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 10-Dec-2020 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TPS7A0530PYKAR ACTIVE DSBGA YKA 4 12000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 W TPS7A0531PDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 1P4F TPS7A0531PDBVT ACTIVE SOT-23 DBV 5 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 1P4F TPS7A0531PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 I6 TPS7A0533PDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 1IPF TPS7A0533PDBVT ACTIVE SOT-23 DBV 5 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 1IPF TPS7A0533PDBZR ACTIVE SOT-23 DBZ 3 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 1QVW TPS7A0533PDBZT ACTIVE SOT-23 DBZ 3 250 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 1QVW TPS7A0533PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 CD TPS7A0533PDQNT ACTIVE X2SON DQN 4 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 CD TPS7A0533PYKAR ACTIVE DSBGA YKA 4 12000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 S (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of