TPS7A14
SBVS400D – DECEMBER 2021 – REVISED AUGUST 2023
TPS7A14 1-A, Low VIN, Low VOUT, Ultra-Low Dropout Regulator
1 Features
3 Description
•
•
The TPS7A14 is a small, ultra low-dropout regulator
(LDO) with excellent transient response. This device
can source 1 A with outstanding ac performance (load
and line transient responses). The input voltage range
is 0.7 V to 2.2 V, and the output range is 0.5 V to
2.0 V with a very high accuracy of 1% over load, line,
and temperature.
•
•
•
•
•
•
•
Ultra-low input voltage range: 0.7 V to 2.2 V
High efficiency:
– Dropout voltage at 1 A: 70 mV (max, YBK)
– Specified for VIN = VOUT +100 mV
Excellent load transient response:
– 20 mV for ILOAD = 3 mA to 600 mA in 20 µs
Accuracy over load, line, and temperature: 1%
High PSRR:
– 80 dB at 1 kHz (VOUT = 0.8 V, IOUT = 500 mA)
Available in fixed-output voltages:
– 0.5 V to 2.0 V (in 25-mV steps)
VBIAS range: 2.2 V to 5.5 V
Packages:
– 6-pin DSBGA: 0.71 mm × 1.16 mm
– 6-pin WSON: 2 mm × 2 mm
Active output discharge
2 Applications
•
•
•
•
•
•
Camera modules
Wireless headphones and earbuds
Smart watch and fitness trackers
Smart phones and tablets
Portable medical devices
Solid state drives (SSDs)
The primary power path is through the IN pin and can
be connected to a power supply as low as 50 mV
above the output voltage. All electrical characteristics
(including excellent output voltage tolerance, transient
response, and PSRR) are specified for input voltages
100 mV greater than the output voltage, thereby
yielding high practical efficiency. This regulator
supports very low input voltages with the use of a
higher, externally supplied VBIAS rail that is used to
power the internal circuitry of the LDO. For example,
the supply voltage to the IN pin can be the output
of a high-efficiency, DC/DC step-down regulator and
the BIAS pin supply voltage can be a rechargeable
battery.
The TPS7A14 is equipped with an active pulldown
circuit to quickly discharge the output when disabled,
and provides a known start-up state.
The TPS7A14 is available in a 2-mm × 2-mm, 6-pin
WSON package and an ultra-small 0.71-mm × 1.16mm, 6-bump WCSP package.
Package Information
PART NUMBER
TPS7A14
(1)
(2)
PACKAGE(1)
PACKAGE SIZE(2)
YBK (WCSP, 6)
1.16 mm × 0.71 mm
DRV (WSON, 6)
2 mm × 2 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
The package size (length × width) is a nominal value and
includes pins, where applicable.
CBIAS
OUT
Standalone
DC/DC Converter
Or PMU
BIAS
IN
IN
COUT
TPS7A14
EN
GND
VOUT
OUT
CIN
SENSE
GND
Typical Application Circuit
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS7A14
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SBVS400D – DECEMBER 2021 – REVISED AUGUST 2023
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings........................................ 5
6.2 ESD Ratings............................................................... 5
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................6
6.5 Electrical Characteristics.............................................6
6.6 Switching Characteristics............................................8
6.7 Typical Characteristics................................................ 9
7 Detailed Description......................................................14
7.1 Overview................................................................... 14
7.2 Functional Block Diagram......................................... 14
7.3 Feature Description...................................................15
7.4 Device Functional Modes..........................................17
8 Application and Implementation.................................. 18
8.1 Application Information............................................. 18
8.2 Typical Application.................................................... 22
8.3 Power Supply Recommendations.............................23
8.4 Layout....................................................................... 24
9 Device and Documentation Support............................25
9.1 Device Support......................................................... 25
9.2 Documentation Support............................................ 25
9.3 Receiving Notification of Documentation Updates....25
9.4 Support Resources................................................... 25
9.5 Trademarks............................................................... 25
9.6 Electrostatic Discharge Caution................................25
9.7 Glossary....................................................................25
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (July 2023) to Revision D (August 2023)
Page
• Changed DRV (WSON) package from Advance Information to Production Data ............................................. 1
• Changed specifications for DRV package.......................................................................................................... 6
• Added Output Noise vs Frequency and IOUT curve for the DRV package.......................................................... 9
• Added Recommended Layout (DRV Package) figure...................................................................................... 24
Changes from Revision B (May 2022) to Revision C (July 2023)
Page
• Added DRV (WSON) package to document as Advance Information ...............................................................1
• Changed fixed-output voltages from 0.5 V to 2.05 V to 0.5 V to 2.0 V throughout document............................1
• Changed description of packages in last paragraph of Description section....................................................... 1
2
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5 Pin Configuration and Functions
1
2
A
OUT
IN
B
SENSE
EN
C
GND
BIAS
Not to scale
Figure 5-1. YBK Package, 6-Pin WCSP (Top View)
Table 5-1. Pin Functions: YBK Package
PIN
TYPE
DESCRIPTION
OUT
Output
Regulated output pin. A 2.2-µF or greater capacitance is required from OUT to ground for stability.
For best transient response, use an 8-µF (nominal) or larger ceramic capacitor from OUT to
ground. Place the output capacitor as close to OUT as possible.
A2
IN
Input
Input pin. A 0.75-µF or greater capacitance is required from IN to ground for stability. Place the
input capacitor as close to IN as possible.
B1
SENSE
Input
SENSE input. This pin is a feedback input to the regulator for SENSE connections. Connecting
SENSE to the load helps eliminate voltage errors resulting from trace resistance between OUT
and the load.
B2
EN
Input
Enable pin. Driving this pin to logic high enables the LDO. Driving this pin to logic low disables the
LDO. If enable functionality is not required, EN must be connected to IN or BIAS.
C1
GND
—
C2
BIAS
Input
NO.
NAME
A1
Ground pin. This pin must be connected to ground.
BIAS pin. This pin enables operation in low-input voltage, low-output voltage (LILO) conditions.
For best performance, use 0.47-µF or larger ceramic capacitor from BIAS to ground. Place the
bias capacitor as close to BIAS as possible.
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OUT
SENSE
EN
1
6
IN
2 Thermal 5
Pad
GND
3
BIAS
4
Figure 5-2. DRV Package, 6-Pin WSON With Exposed Thermal Pad (Top View)
Table 5-2. Pin Functions: DRV Package
PIN
NO.
NAME
DESCRIPTION
Regulated output pin. A 2.2-µF or greater capacitance is required from OUT to ground for stability.
For best transient response, use an 8-µF (nominal) or larger ceramic capacitor from OUT to
ground. Place the output capacitor as close to OUT as possible.
1
OUT
Output
2
SENSE
Input
SENSE input. This pin is a feedback input to the regulator for SENSE connections. Connecting
SENSE to the load helps eliminate voltage errors resulting from trace resistance between OUT
and the load.
3
EN
Input
Enable pin. Driving this pin to logic high enables the LDO. Driving this pin to logic low disables the
LDO. If enable functionality is not required, EN must be connected to IN or BIAS.
4
BIAS
Input
BIAS pin. This pin enables operation in LILO conditions. For best performance, use 0.47-µF or
larger ceramic capacitor from BIAS to ground. Place the bias capacitor as close to BIAS as
possible.
5
GND
—
6
IN
Input
Thermal Pad
4
TYPE
—
Ground pin. This pin must be connected to ground.
Input pin. A 0.75-µF or greater capacitance is required from IN to ground for stability. Place the
input capacitor as close to IN as possible.
The thermal pad is electrically connected to the GND node. Connect to the GND plane for
improved thermal performance.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range unless otherwise noted.(1)
Voltage
Current
(2)
MAX
–0.3
2.4
Enable, VEN
–0.3
6.0
Bias, VBIAS
–0.3
6.0
Sense, VSENSE
–0.3
VIN + 0.3 (2)
Output, VOUT
–0.3
VIN + 0.3 (2)
Maximum output
Temperature
(1)
MIN
Input, VIN
UNIT
V
Internally limited
A
Operating junction, TJ
–40
150
°C
Storage, Tstg
–65
150
°C
Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute maximum ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If briefly operating outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not
sustain damage, but it may not be fully functional. Operating the device in this manner may affect device reliability, functionality,
performance, and shorten the device lifetime.
The absolute maximum rating is 2.4 V or (VIN + 0.3 V), whichever is less.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±3000
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
±750
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating junction temperature range (unless otherwise noted).(1)
MIN
VIN
NOM
MAX
UNIT
Input voltage
0.7
2.2
V
VBIAS
Bias voltage
Greater of 2.2 or
VOUT(NOM) + 1.4
5.5
V
VOUT
Output voltage
0.5
2.0
V
IOUT
Peak output current
0
1
A
(2)
CIN
Input capacitance
CBIAS
Bias capacitance (4)
COUT
Output capacitance, DRV package
2.2
22
COUT
Output capacitance, YBK package
2.2
47
µF
ESR
Output capacitor series resistance
100
mΩ
TJ
Operating junction temperature
125
℃
(1)
(2)
(3)
0.75
µF
0.1
–40
µF
µF
All voltages are with respect to GND.
An input capacitor is required to counteract the effect of source resistance and inductance, which may in some cases cause symptoms
of system level instability such as ringing or oscillation, especially in the presence of load transients. A larger input capacitor may be
necessary depending on the source impedance and system requirements.
A BIAS input capacitor is not required for LDO stability. However, a capacitor with a derated value of at least 0.1 µF is recommended to
maintain transient, PSRR, and noise performance.
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6.4 Thermal Information
TPS7A14
THERMAL METRIC(1)
WSON
DSBGA
6 PINS
6 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
72.7
136.7
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
84.9
1.1
°C/W
RθJB
Junction-to-board thermal resistance
32.7
38.1
°C/W
ψJT
Junction-to-top characterization parameter
3.2
0.5
°C/W
ψJB
Junction-to-board characterization parameter
32.6
38.1
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
16.8
n/a
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
specified at TJ = –40°C to +125°C, VIN = VOUT(NOM) + 0.1 V, VBIAS = greater of 2.2 V or VOUT(NOM) + 1.4 V, IOUT = 1 mA, VEN =
1.0 V, CIN = 1 μF, COUT = 2.2 μF, and CBIAS = 0.1 μF (unless otherwise noted); all typical values are at TJ = 25°C
PARAMETER
VOUT
Accuracy over temperature
VOUT(NOM) + 0.1 V ≤ VIN
≤ 2.2 V,
Greater of 2.2 V or
VOUT(NOM) + 1.4 V ≤
VBIAS ≤ 5.5 V,
1 mA ≤ IOUT ≤ 1 A
MIN
TYP
MAX
TJ = –40°C to +125°C,
DRV package
–1.25
1
TJ = –40°C to +125°C,
YBK package
–1.5
1
TJ = –40°C to +85°C
–1
1
VOUT(NOM) + 0.1 V ≤ VIN ≤ 2.2 V, DRV package
–3
3
VOUT(NOM) + 0.1 V ≤ VIN ≤ 2.2 V, TJ = –40°C to
+85°C, YBK package
–2.5
2.5
ΔVOUT / ΔVIN
VIN line regulation
VOUT(NOM) + 1.4 V ≤ VBIAS ≤ 5.5 V, DRV package
–3
±0.15
3
ΔVOUT / ΔVBIAS
VBIAS line regulation
VOUT(NOM) + 1.4 V ≤ VBIAS ≤ 5.5 V, TJ = –40°C to
+85°C, YBK package
–2.5
±0.15
2.5
ΔVOUT / ΔIOUT
Load regulation
1 mA ≤ IOUT ≤ 1 A
IQ(BIAS)
Bias pin current
IQ(IN)
Input pin current(1)
IGND
Ground pin current
ISHDN(BIAS)
ISHDN(IN)
VBIAS shutdown current
VIN shutdown current
43
26
IOUT = 1 A, DRV package
17
IOUT = 1 A, TJ = –40°C to +85°C, YBK package
12
IOUT = 0 mA, DRV package
118
IOUT = 0 mA, TJ = –40°C to +85°C
5.7
IOUT = 1 A, DRV package
480
660
IOUT = 1 A, TJ = –40°C to +85°C
480
620
VIN = 2.2 V, VBIAS = 5.5 V, VEN ≤ 0.2 V, DRV
package
0.3
9
VIN = 2.2 V, VBIAS = 5.5 V, VEN ≤ 0.2 V, TJ = –40°C
to +85°C
0.3
3.8
VIN = 1.8 V, VBIAS = 5.5 V, VEN ≤ 0.2 V, DRV
package
1
41
VIN = 1.8 V, VBIAS = 5.5 V, VEN ≤ 0.2 V, TJ = –40°C
to +85°C
1
9.2
1.6
2.45
Output current limit
VOUT = 0.95 × VOUT(NOM)
Short circuit current limit
VOUT = 0 V
VIN = 0.95 x VOUT(NOM),
IOUT = 1 A
%
mV
mV
µA
mA
µA
µA
µA
µA
1.035
600
A
mA
TJ = –40°C to + 125°C
99
TJ = –40°C to + 85°C,
DRV package
77
TJ = –40°C to + 85°C,
YBK package
70
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UNIT
%/A
IOUT = 0 mA, TJ = –40°C to +85°C, YBK package
ISC
VIN dropout voltage(2)
0.2
IOUT = 0 mA, DRV package
ICL
VDO(IN)
6
TEST CONDITIONS
mV
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6.5 Electrical Characteristics (continued)
specified at TJ = –40°C to +125°C, VIN = VOUT(NOM) + 0.1 V, VBIAS = greater of 2.2 V or VOUT(NOM) + 1.4 V, IOUT = 1 mA, VEN =
1.0 V, CIN = 1 μF, COUT = 2.2 μF, and CBIAS = 0.1 μF (unless otherwise noted); all typical values are at TJ = 25°C
PARAMETER
VDO(BIAS)
VBIAS dropout voltage(2)
TEST CONDITIONS
VBIAS = greater of 1.7V or VOUT(nom) + 0.6 V,
VSENSE = 0.95 x VOUT(nom), IOUT = 1 A, YBK
package
1.1
f = 10 kHz
VIN power-supply rejection
ratio
f = 100 kHz
f = 1 MHz
f = 1 MHz,
VIN = VOUT + 150 mV
Vn
Output voltage noise
VUVLO(BIAS)
Bias supply UVLO
VUVLO_HYST(BIAS)
Bias supply hysteresis
VUVLO(IN)
Input supply UVLO
VUVLO_HYST(IN)
Input supply hysteresis
IOUT = 3 mA
90
IOUT = 500 mA
80
IOUT = 1 A
80
IOUT = 3 mA
90
IOUT = 500 mA
80
IOUT = 1 A
70
IOUT = 3 mA
70
IOUT = 500 mA
60
IOUT = 1 A
50
IOUT = 3 mA
60
IOUT = 500 mA
43
IOUT = 1 A
33
IOUT = 3 mA
60
IOUT = 500 mA
24
IOUT = 1 A
15
IOUT = 3 mA
69
IOUT = 500 mA
42
IOUT = 1 A
33
Start-up
VEN(HI)
EN pin logic high voltage(4)
VEN(LOW)
EN pin logic low voltage(4)
IEN
EN pin current
RPULLDOWN
Pulldown resistor
TSD
Thermal shutdown
temperature
dB
65
IOUT = 500 mA
45
f = 1 MHz
25
Bandwidth = 10 Hz to 100 kHz,
VOUT = 0.8 V, 5mA ≤ IOUT ≤ 1 A
7.2
dB
µVRMS
VBIAS rising
1.15
1.42
1.7
VBIAS falling
1.0
1.3
1.63
VBIAS hysteresis
100
584
603
623
VIN falling
530
552
566
VIN hysteresis
V
mV
VIN rising
50
time(3)
tSTR
(1)
(2)
(3)
(4)
f = 100 kHz
UNIT
V
f = 1 kHz
VBIAS power-supply rejection
ratio
MAX
1.115
f = 1 kHz
VBIAS PSRR
TYP
VBIAS = greater of 1.7V or VOUT(nom) + 0.6 V,
VSENSE = 0.95 x VOUT(nom), IOUT = 1 A, DRV
package
f = 100 Hz
VIN PSRR
MIN
mV
mV
186
µs
0.6
6
V
0
0.25
V
EN = 5.5 V, DRV package
-25
10
25
EN = 5.5 V, TJ = –40°C to +85°C
-20
10
20
VIN = 0.9 V, VOUT(nom) = 0.8 V, VBIAS = 1 V,
VEN = 0 V, P version only
36
Shutdown, temperature rising
165
Reset, temperature falling
140
nA
Ω
°C
This is the current flowing from VIN to GND.
Dropout is not measured for VOUT < 0.6 V. VBIAS dropout applies only for VBIAS of 2.2 V or greater.
Startup time = time from EN assertion to 0.95 × VOUT(NOM).
An input voltage within the minimum to maximum range is interpreted as the correct logic level.
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6.6 Switching Characteristics
specified at TJ = –40°C to +125°C, VIN = VOUT(NOM) + 0.1 V, VBIAS = greater of 2.2 V or VOUT(NOM) + 1.4 V, IOUT = 1 mA,
VEN = 1.0 V, CIN = 1 μF, COUT = 2.2 μF, and CBIAS = 0.1 μF (unless otherwise noted); all typical values are at TJ = 25°C; all
transients values are over multiple load or line pulses with periods of 100µs on (high load) and 100µs off (low load)
PARAMETER
ΔVOUT
ΔVOUT
Line transient(1)
Load transient(1)
TEST CONDITIONS
VIN = (VOUT(NOM) +
0.1 V) to 2.1 V
Transition time, tR = 1 V / µs
VIN = 2.1 V to
(VOUT(NOM) + 0.1 V)
Transition time, tF = 1 V / µs
IOUT = 3 mA to 600 mA Transition time, t = 20 µs, t = 20 µs, t
R
F
OFF =
I
= 600 mA to 3 mA 200 µs, tON = 1 ms, CIN = 5 μF, COUT = 5 μF
OUT
(1)
8
MIN
TYP
MAX
UNIT
1
% VOUT
–1
–2
2
% VOUT
This specification is verified by design.
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6.7 Typical Characteristics
at operating temperature TJ = 25°C, VOUT(NOM) = 0.8 V, VIN = VOUT(NOM) + 0.1 V, VBIAS = VOUT(NOM) + 1.4 V, IOUT = 1 mA, VEN
= VIN, CIN = 2.2 µF, COUT = 2.2 µF, and CBIAS = 0.47 µF (unless otherwise noted)
Figure 6-1. Output Voltage Accuracy vs VIN
Figure 6-2. Output Voltage Accuracy vs VBIAS
Figure 6-3. Output Voltage Accuracy vs IOUT
Figure 6-4. VIN Dropout Voltage vs IOUT
Figure 6-5. VBIAS Dropout Voltage vs IOUT
Figure 6-6. VBIAS Input Current vs VBIAS
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6.7 Typical Characteristics (continued)
at operating temperature TJ = 25°C, VOUT(NOM) = 0.8 V, VIN = VOUT(NOM) + 0.1 V, VBIAS = VOUT(NOM) + 1.4 V, IOUT = 1 mA, VEN
= VIN, CIN = 2.2 µF, COUT = 2.2 µF, and CBIAS = 0.47 µF (unless otherwise noted)
IOUT = 1 A
IOUT = 0 mA
Figure 6-7. VBIAS Input Current vs VBIAS
Figure 6-8. VIN Shutdown IQ vs VIN
IOUT = 0 A, VIN = 1 V
10
Figure 6-9. VBIAS Shutdown IQ vs VBIAS
Figure 6-10. VOUT Foldback Current Limit vs Output Current
Figure 6-11. Enable Threshold vs Temperature
Figure 6-12. VIN UVLO vs Temperature
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6.7 Typical Characteristics (continued)
at operating temperature TJ = 25°C, VOUT(NOM) = 0.8 V, VIN = VOUT(NOM) + 0.1 V, VBIAS = VOUT(NOM) + 1.4 V, IOUT = 1 mA, VEN
= VIN, CIN = 2.2 µF, COUT = 2.2 µF, and CBIAS = 0.47 µF (unless otherwise noted)
tr = 1 μs
Figure 6-13. VBIAS UVLO vs Temperature
Figure 6-14. Start-Up With VBIAS Before VIN
tr = 1 μs
tr = 1 μs
Figure 6-15. Start-Up With VIN Before VBIAS and VEN
Figure 6-16. Start-Up With VIN and VBIAS Before VEN
tr = 1 μs
tr = tf = 10 μs, IOUT = 1 mA
Figure 6-17. Start-Up With VIN and VEN Before VBIAS
Figure 6-18. Line Transient From 1 V to 2.2 V
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6.7 Typical Characteristics (continued)
at operating temperature TJ = 25°C, VOUT(NOM) = 0.8 V, VIN = VOUT(NOM) + 0.1 V, VBIAS = VOUT(NOM) + 1.4 V, IOUT = 1 mA, VEN
= VIN, CIN = 2.2 µF, COUT = 2.2 µF, and CBIAS = 0.47 µF (unless otherwise noted)
tr = tf = 10 μs, IOUT = 500 mA
tr = tf = 10 μs, IOUT = 1 A
Figure 6-19. Line Transient From 1 V to 2.2 V
Figure 6-20. Line Transient From 1 V to 2.2 V
tr = tf = 1 μs
tr = tf = 20 μs
Figure 6-21. Load Transient From 100 μA to 1 A
Figure 6-22. Load Transient From 100 μA to 1 A
CBIAS = 0 μF, IOUT = 1 A
CBIAS = 0 μF, IOUT = 1 A
Figure 6-23. PSRR vs Frequency and VIN – VOUT
12
Figure 6-24. PSRR vs Frequency and COUT
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6.7 Typical Characteristics (continued)
at operating temperature TJ = 25°C, VOUT(NOM) = 0.8 V, VIN = VOUT(NOM) + 0.1 V, VBIAS = VOUT(NOM) + 1.4 V, IOUT = 1 mA, VEN
= VIN, CIN = 2.2 µF, COUT = 2.2 µF, and CBIAS = 0.47 µF (unless otherwise noted)
CBIAS = 0 μF
CBIAS = 0 μF
Figure 6-25. PSRR vs Frequency and IOUT
Figure 6-26. PSRR vs Frequency and VBIAS – VOUT
YCK package, VOUT = 0.8 V
DRV package, VOUT = 1.8 V, BIAS = 5 V
Figure 6-27. Output Noise vs Frequency and IOUT
Figure 6-28. Output Noise vs Frequency and IOUT
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7 Detailed Description
7.1 Overview
The TPS7A14 is a low-input, ultra-low dropout, low-quiescent-current linear regulator that is optimized for
excellent transient performance. These characteristics make the device designed for most battery-powered
applications. The low operating VIN – VOUT, combined with the BIAS pin, dramatically improve the efficiency of
low-voltage output applications by powering the voltage reference and control circuitry and allowing the use of
a pre-regulated, low-voltage input supply (IN) for the main power path. This low-dropout regulator (LDO) offers
foldback current limit, shutdown, thermal protection, and an optional active discharge.
7.2 Functional Block Diagram
Current
Limit
IN
OUT
+
Overshoot
Pull-Down
–
BIAS
Bandgap
SENSE
+
–
Active Discharge
P-Version Only
UVLO
Internal
Controller
EN
GND
Thermal
Shutdown
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7.3 Feature Description
7.3.1 Excellent Transient Response
The TPS7A14 responds quickly to a change on the input supply (line transient) or the output current (load
transient) given the device high input impedance and low output impedance across frequency. This same
capability also means that this LDO has a high power-supply rejection ratio (PSRR) and, when coupled with a
low internal noise floor (en), the LDO can be used to create an excellent power supply with outstanding line and
load transient performance.
The choice of external component values optimizes the transient response; see the Input, Output, and Bias
Capacitor Requirements section for proper capacitor selection.
7.3.2 Global Undervoltage Lockout (UVLO)
The TPS7A14 uses two undervoltage lockout circuits: one on the BIAS pin and one on the IN pin to prevent the
device from turning on before both VBIAS and VIN rise above their lockout voltages. The two UVLO signals are
connected internally through an AND gate, as shown in Figure 7-1, that turns off the device when the voltage on
either input is below their respective UVLO thresholds.
UVLO(IN)
Global UVLO
UVLO(BIAS)
Figure 7-1. Global UVLO circuit
7.3.3 Enable Input
The enable input (EN) is active high. Applying a voltage greater than VEN(HI) to EN enables the regulator output
voltage, and applying a voltage less than VEN(LOW) to EN disables the regulator output. If independent control of
the output voltage is not needed, connect EN to either IN or BIAS.
7.3.4 Internal Foldback Current Limit
The device has an internal current limit circuit that protects the regulator during transient high-load current faults
or shorting events. The current limit is a hybrid brick-wall foldback scheme. The current limit transitions from a
brick-wall scheme to a foldback scheme at the foldback voltage (VFOLDBACK). In a high-load current fault with
the output voltage above VFOLDBACK, the brick-wall scheme limits the output current to the current limit (ICL).
When the voltage drops below VFOLDBACK, a foldback current limit activates that scales back the current as the
output voltage approaches GND. When the output is shorted, the device supplies a typical current called the
short-circuit current limit (ISC). ICL and ISC are listed in the Electrical Characteristics table.
For this device, VFOLDBACK is approximately 60% × VOUT(nom).
The output voltage is not regulated when the device is in current limit. When a current limit event occurs, the
device begins to heat up because of the increase in power dissipation. When the device is in brick-wall current
limit, the pass transistor dissipates power [(VIN – V OUT) × ICL]. When the device output is shorted and the output
is below VFOLDBACK, the pass transistor dissipates power [(VIN – VOUT) × ISC]. If thermal shutdown is triggered,
the device turns off. After the device cools down, the internal thermal shutdown circuit turns the device back on.
If the output current fault condition continues, the device cycles between current limit and thermal shutdown. For
more information on current limits, see the Know Your Limits application report.
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Figure 7-2 shows a diagram of the foldback current limit.
VOUT
Brickwall
VOUT(NOM)
VFOLDBACK
Foldback
IOUT
0V
0 mA
ISC
IRATED
ICL
Figure 7-2. Foldback Current Limit
7.3.5 Active Discharge
The active discharge function uses an internal MOSFET that connects a resistor (RPULLDOWN) to ground when
the LDO is disabled in order to actively discharge the output voltage. The active discharge circuit is activated by
driving EN to logic low to disable the device, when the voltage at IN or BIAS is below the UVLO threshold, or
when the regulator is in thermal shutdown.
The discharge time after disabling the device depends on the output capacitance (COUT) and the load resistance
(RL) in parallel with the pulldown resistor.
Do not rely on the active discharge circuit for discharging a large amount of output capacitance after the input
supply has collapsed because reverse current can flow from the output to the input. This reverse current flow
can cause damage to the device. Limit reverse current to no more than 5% of the rated output current for a short
period of time.
7.3.6 Thermal Shutdown
The internal thermal shutdown protection circuit disables the output when the thermal junction temperature (TJ )
of the pass transistor rises to the thermal shutdown temperature threshold, TSD(shutdown) (typical). The thermal
shutdown circuit hysteresis makes sure that the LDO resets (turns on) when the temperature falls to TSD(reset)
(typical).
The thermal time constant of the semiconductor die is fairly short; thus, the device can cycle on and off when
thermal shutdown is reached until the power dissipation is reduced. Power dissipation during start up can
be high from large VIN – VOUT voltage drops across the device or from high inrush currents charging large
output capacitors. Under some conditions, the thermal shutdown protection disables the device before start up
completes.
For reliable operation, limit the junction temperature to the maximum listed in the Recommended Operating
Conditions table. Operation above this maximum temperature causes the device to exceed operational
specifications. Although the internal protection circuitry is designed to protect against thermal overload
conditions, this circuitry is not intended to replace proper heat sinking. Continuously running the regulator into
thermal shutdown or above the maximum recommended junction temperature reduces long-term reliability.
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7.4 Device Functional Modes
Table 7-1 shows the conditions that lead to the different modes of operation. See the Electrical Characteristics
table for parameter values.
Table 7-1. Device Functional Mode Comparison
PARAMETER
OPERATING MODE
VIN
VBIAS
VEN
IOUT
TJ
Normal mode
VIN ≥ VOUT (nom) + VDO
and VIN ≥ VIN(min)
VBIAS ≥ VOUT + VDO(BIAS)
VEN ≥VIH(EN)
IOUT < ICL
TJ < TSD for
shutdown
Dropout mode
VIN(min) < VIN <
VOUT (nom) + VDO(IN)
VBIAS < VOUT + VDO(BIAS)
VEN > VIH(EN)
IOUT < ICL
TJ < TSD for
shutdown
VIN < VUVLO(IN)
VBIAS < VBIAS(UVLO)
VEN < VIL(EN)
—
TJ ≥ TSD for
shutdown
Disabled mode
(any true condition
disables the device)
7.4.1 Normal Operation
The device regulates to the nominal output voltage when the following conditions are met:
•
•
•
•
•
The input voltage is greater than the nominal output voltage plus the dropout voltage (VOUT(nom) + VDO)
The bias voltage is greater than the nominal output voltage plus the dropout voltage (VOUT(nom) + VDO)
The output current is less than the current limit (IOUT < ICL)
The device junction temperature is less than the thermal shutdown temperature ( TJ < TSD(shutdown))
The enable voltage has previously exceeded the enable rising threshold voltage and has not yet decreased
to less than the enable falling threshold
7.4.2 Dropout Operation
If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other
conditions are met for normal operation, the device operates in dropout mode. Similarly, if the bias voltage is
lower than the nominal output voltage plus the specified dropout voltage, but all other conditions are met for
normal operation, the device operates in dropout mode as well. In this mode, the output voltage tracks the input
voltage. During this mode, the transient performance of the device becomes significantly degraded because the
pass transistor is in the ohmic or triode region, and acts as a switch. Line or load transients in dropout can result
in large output voltage deviations.
When the device is in a steady dropout state, defined as when the device is in dropout, (VIN < VOUT + VDO or
VBIAS < VOUT + VDO directly after being in normal regulation state, but not during start up), the pass transistor
is driven into the ohmic or triode region. When the input voltage returns to a value greater than or equal to the
nominal output voltage plus the dropout voltage (VOUT(NOM) + VDO), the output voltage can overshoot for a short
time when the device pulls the pass transistor back into the linear region.
7.4.3 Disable Mode
The output of the device can be shutdown by forcing the voltage of the enable pin to less than VIL(EN) (see the
Electrical Characteristics table). When disabled, the pass transistor is turned off, internal circuits are shutdown,
and the output voltage is actively discharged to ground by an internal discharge circuit from the output to ground.
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
Successfully implementing an LDO in a system depends on the system requirements. This section discusses
key device features and how to best implement them to achieve a reliable design.
8.1.1 Recommended Capacitor Types
The regulator is designed to be stable using low equivalent series resistance (ESR) ceramic capacitors
at the input, output, and bias pins. Multilayer ceramic capacitors are the industry standard for use with
LDOs, but must be used with good judgment. Ceramic capacitors that use X7R-, X5R-, and COG-rated
dielectric materials provide relatively good capacitive stability across temperature, whereas the use of Y5V-rated
capacitors is discouraged because of large variations in capacitance. Regardless of the ceramic capacitor
type selected, ceramic capacitance varies with operating voltage and temperature. Generally, assume that
effective capacitance decreases by as much as 50%. The input, output, and bias capacitors recommended in
the Recommended Operating Conditions table account for an effective capacitance of approximately 50% of the
nominal value.
8.1.2 Input, Output, and Bias Capacitor Requirements
A minimum input ceramic capacitor is required for stability. A minimum output ceramic capacitor is also required
for stability, see the Recommended Operating Conditions table for the minimum capacitors values.
The input capacitor counteracts reactive input sources and improves transient response, input ripple, and PSRR.
A higher-value input capacitor can be necessary if large, fast rise-time load or line transients are anticipated,
or if the device is located several inches from the input power source. Dynamic performance of the device is
improved with the use of an output capacitor larger than the minimum value specified in the Recommended
Operating Conditions table.
Although a bias capacitor is not required, good design practice is to connect a 0.1-µF ceramic capacitor from
BIAS to GND. This capacitor counteracts reactive bias source if the source impedance is not sufficiently low.
Place the input, output, and bias capacitors as close as possible to the device to minimize trace parasitics.
If the BIAS source is susceptible to fast voltage drops (for example, a 2-V drop in less than 1 µs) when the LDO
load current is near the maximum value, the BIAS voltage drop can cause the output voltage to fall briefly. In
such cases, use a BIAS capacitor large enough to slow the voltage ramp rate to less than 0.5 V/µs. For smaller
or slower BIAS transients, any output voltage dips must be less than 5% of the nominal voltage.
8.1.3 Dropout Voltage
Dropout voltage (VDO) is defined as the input voltage minus the output voltage (VIN – VOUT) at the rated output
current (IRATED), where the pass transistor is fully on. IRATED is the maximum IOUT listed in the Recommended
Operating Conditions table. The pass transistor is in the ohmic or triode region of operation, and acts as a
switch. The dropout voltage indirectly specifies a minimum input voltage greater than the nominal programmed
output voltage at which the output voltage is expected to stay in regulation. If the input voltage falls to less than
the nominal output regulation, then the output voltage falls as well.
For a CMOS regulator, the dropout voltage is determined by the drain-source on-state resistance (RDS(ON)) of the
pass transistor. Therefore, if the linear regulator operates at less than the rated current, the dropout voltage for
that current scales accordingly. Use Equation 1 to calculate the RDS(ON) of the device.
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VDO
IRATED
(1)
The use of bias rail enables the TPS7A14 to achieve a lower dropout voltage between IN and OUT. However, a
minimum bias voltage above the nominal programmed output voltage must be maintained. Figure 6-13 specifies
the minimum VBIAS headroom required to maintain output regulation.
8.1.4 Behavior During Transition From Dropout Into Regulation
Some applications can have transients that place this device into dropout, especially when this device can be
powered from a battery with relatively high ESR. The load transient saturates the output stage of the error
amplifier when the pass transistor is driven fully on, making the pass transistor function like a resistor from VIN
to VOUT. The error amplifier response time to this load transient is extended because the error amplifier must
first recover from saturation and then must place the pass transistor back into active mode. During this recovery
period, VOUT overshoots because the pass transistor is functioning as a resistor from VIN to VOUT.
When VIN ramps up slowly for start up, the slow ramp-up voltage can place the device in dropout. As with many
other LDOs, the output can overshoot on recovery from this condition. However, this condition is easily avoided
through the use of the enable signal.
If operating under these conditions, apply a higher dc load current or increase the output capacitance to reduce
the overshoot. These approaches provide a path to absorb the excess charge.
8.1.5 Device Enable Sequencing Requirement
The IN, BIAS, and EN pin voltages can be sequenced in any order without causing damage to the device. Start
up is always monotonic regardless of the sequencing order or the ramp rates of the IN, BIAS, and EN pins. See
the Recommended Operating Conditions table for proper voltage ranges of the IN, BIAS, and EN pins.
8.1.6 Load Transient Response
The load-step transient response is the output voltage response by the LDO to a step in load current while
output voltage regulation is maintained. See Figure 6-21 and Figure 6-22 for typical load transient response
plots. There are two key transitions during a load transient response: the transition from a light to a heavy load,
and the transition from a heavy to a light load. The regions in Figure 8-1 are broken down as described in this
section. Regions A, E, and H are where the output voltage is in steady-state operation.
tAt
tCt
B
tDt
tEt
tGt
tHt
F
Figure 8-1. Load Transient Waveform
During transitions from a light load to a heavy load, the following behavior can be observed:
•
•
The initial voltage dip is a result of the depletion of the output capacitor charge and parasitic impedance to
the output capacitor (region B)
Recovery from the dip results from the LDO increasing the sourcing current, and leads to output voltage
regulation (region C)
During transitions from a heavy load to a light load, the following behavior can be observed:
•
•
The initial voltage rise results from the LDO sourcing a large current, and leads to an increase in the output
capacitor charge (region F)
Recovery from the rise results from the LDO decreasing the sourcing current in combination with the load
discharging the output capacitor (region G)
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A larger output capacitance reduces the peaks during a load transient but slows down the response time of the
device. A larger dc load also reduces the peaks because the amplitude of the transition is lowered and a higher
current discharge path is provided for the output capacitor.
8.1.7 Undervoltage Lockout Circuit Operation
The VIN UVLO circuit makes sure that the regulator remains disabled when the input supply voltage is below
the minimum operational voltage range, and makes sure that the regulator shuts down when the input supply
collapses. Similarly, the VBIAS UVLO circuit makes sure that the regulator remains disabled when the bias supply
voltage is less than the minimum operational voltage range, and makes sure that the regulator shuts down when
the bias supply collapses.
Figure 8-2 shows the UVLO circuit response to various input or bias voltage events. The diagram can be
separated into the following parts:
•
•
•
•
•
•
•
Region A: The output remains off while the input or bias voltage is below the UVLO rising threshold
Region B: Normal operation, regulating device
Region C: Brownout event above the UVLO falling threshold (UVLO rising threshold – UVLO hysteresis). The
output can possibly fall out of regulation but the device remains enabled.
Region D: Normal operation, regulating device
Region E: Brownout event below the UVLO falling threshold. The device is disabled in most cases and the
output falls as a result of the load and active discharge circuit. The device is re-enabled when the UVLO
rising threshold is reached and a normal start up follows.
Region F: Normal operation followed by the input or bias falling to the UVLO falling threshold
Region G: The device is disabled when the input or bias voltages fall below the UVLO falling threshold to 0 V.
The output falls as a result of the load and active discharge circuit.
UVLO Rising Threshold
UVLO Hysteresis
VIN / VBIAS
C
VOUT
tAt
tBt
tDt
tEt
tFt
tGt
Figure 8-2. Typical VIN or VBIAS UVLO Circuit Operation
8.1.8 Power Dissipation (PD)
Circuit reliability demands that proper consideration be given to device power dissipation, location of the circuit
on the printed circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator
must be as free as possible of other heat-generating devices that cause added thermal stresses.
Equation 2 calculates the maximum allowable power dissipation for the device in a given package:
PD-MAX = [(TJ – TA) / RθJA]
(2)
Equation 3 represents the actual power being dissipated in the device:
PD = ((IGND(IN) + IIN) × VIN + IGND(BIAS) × VBIAS ) – (IOUT × VOUT)
(3)
If the load current is much greater than IGND(IN) and IGND(BIAS) Equation 3 can be simplified as:
PD = (VIN – VOUT) × IOUT
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Power dissipation can be minimized, and thus greater efficiency achieved, by proper selection of the system
voltage rails. Proper selection allows the minimum input-to-output voltage differential to be obtained. The low
dropout of the TPS7A14 allows for maximum efficiency across a wide range of output voltages.
The main heat conduction path depends on the ambient temperature and the thermal resistance across the
various interfaces between the die junction and ambient air.
The maximum allowable junction temperature (TJ) determines the maximum power dissipation for the device.
According to Equation 5, maximum power dissipation and junction temperature are most often related by the
junction-to-ambient thermal resistance (RθJA) of the combined PCB and device package and the temperature of
the ambient air (TA). The equation is rearranged in Equation 6 for output current.
TJ = TA + (RθJA × PD)
(5)
IOUT = (TJ – TA) / [RθJA × (VIN – VOUT)]
(6)
Unfortunately, this thermal resistance (RθJA) is highly dependent on the heat-spreading capability built into the
particular PCB design, and therefore varies according to the total copper area, copper weight, and location of
the planes. The R θJA recorded in the Electrical Characteristics table is determined by the JEDEC standard, PCB,
and copper-spreading area, and is only used as a relative measure of package thermal performance. For a
well-designed thermal layout, RθJA is actually the sum of the YBK package junction-to-case (bottom) thermal
resistance (RθJC(bot)) plus the thermal resistance contribution by the PCB copper.
8.1.9 Estimating Junction Temperature
The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures
of the LDO when in-circuit on a typical PCB board application. These metrics are not strictly speaking thermal
resistances, but rather offer practical and relative means of estimating junction temperatures. These psi metrics
are determined to be significantly independent of the copper-spreading area. The key thermal metrics (ΨJT and
ΨJB) are used in accordance with Equation 7 and are given in the Electrical Characteristics table.
ΨJT : TJ = TT + ΨJT × PD and ΨJB : TJ = TB + ΨJB × PD
(7)
where:
•
•
•
PD is the power dissipated as explained in Equation 3 and the Power Dissipation (PD) section
TT is the temperature at the center-top of the device package
TB is the PCB surface temperature measured 1 mm from the device package and centered on the package
edge
8.1.10 Recommended Area for Continuous Operation
The operational area of an LDO is limited by the dropout voltage, output current, junction temperature, and input
voltage. The recommended area for continuous operation for a linear regulator is provided in Figure 8-3 and can
be separated into the following regions:
•
•
•
•
Dropout voltage limits the minimum differential voltage between the input and the output (VIN – VOUT) at a
given output current level; see the Dropout Operation section for more details.
The rated output current limits the maximum recommended output current level. Exceeding this rating causes
the device to fall out of specification.
The rated junction temperature limits the maximum junction temperature of the device. Exceeding this rating
causes the device to fall out of specification and reduces long-term reliability.
– Equation 6 provides the shape of the slope. The slope is nonlinear because the maximum rated junction
temperature of the LDO is controlled by the power dissipation across the LDO, thus when VIN – VOUT
increases the output current must decrease.
The rated input voltage range governs both the minimum and maximum of VIN – VOUT.
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Output Current (A)
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Output Current Limited
by Dropout
Rated Output
Current
Output Current Limited
by Thermals
Limited by
Maximum VIN
Limited by
Minimum VIN
VIN ± VOUT (V)
Figure 8-3. Continuous Operation Diagram With Description of Regions
8.2 Typical Application
CBIAS
IN
BIAS
OUT
IN
COUT
DC/DC Converter
Or PMU
TPS7A14
EN
GND
VOUT
OUT
CIN
SENSE
GND
Figure 8-4. High-Efficiency Supply From a Rechargeable Battery
8.2.1 Design Requirements
Table 8-1 lists the parameters for this design example.
Table 8-1. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
VIN
0.95 V
VBIAS
2.4 V to 5.5 V
VOUT
0.8 V
IOUT
600 mA (typical), 900 mA (peak)
8.2.2 Detailed Design Procedure
This design example is powered by a rechargeable battery that can be a building block in many portable
applications. Noise-sensitive portable electronics require an efficient, small-size solution for their power supply.
Traditional LDOs are known for their low efficiency in contrast to low-input, low-output voltage (LILO) LDOs such
as the TPS7A14. The use of a bias rail in the TPS7A14 allows the main power path of the LDO to operate
at a lower input voltage, thus reducing the voltage drop across the pass transistor and maximizing device
efficiency. Because the voltage drop across the pass transistor can be so low, the efficiency of the TPS7A14 can
approximate that of a dc-dc converter. Equation 8 calculates the efficiency for this design.
Efficiency = η = POUT / PIN × 100 % = (VOUT × IOUT) / (VIN × IIN + VBIAS × IBIAS) × 100 %
(8)
Equation 8 reduces to Equation 9 because the design example load current is much greater than the quiescent
current of the bias rail.
Efficiency = η = (VOUT × IOUT) / (VIN × IIN) × 100%
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8.2.3 Application Curve
VBIAS = VOUT(NOM) + 1.4 V, VEN = VIN, CIN = 2.2 µF, COUT = 2.2 µF, and CBIAS = 0.47 µF
Figure 8-5. VIN Dropout Voltage vs IOUT
8.3 Power Supply Recommendations
This device is designed to operate from an input supply voltage range of 0.6 V to 2.2 V and a bias supply voltage
range of 1.5 V to 5.5 V. The input and bias supplies must be well regulated and free of spurious noise. To make
sure that the output voltage is well regulated and dynamic performance is optimum, the input supply must be at
least VOUT(nom) + VDO and VBIAS = VOUT(nom) + VDO(BIAS).
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8.4 Layout
8.4.1 Layout Guidelines
For correct printed circuit board (PCB) layout, follow these guidelines:
•
•
•
Place input, output, and bias capacitors as close to the device as possible
Use copper planes for device connections to optimize thermal performance
Place thermal vias around the device to distribute heat
8.4.2 Layout Examples
Figure 8-6. Recommended Layout (YBK Package)
VOUT
VIN
CIN
VSENSE
Thermal
Pad
COUT
CBIAS
VEN
VBIAS
Ground
Figure 8-7. Recommended Layout (DRV Package)
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9 Device and Documentation Support
9.1 Device Support
9.1.1 Development Support
9.1.1.1 Evaluation Module
An evaluation module (EVM) is available to assist in the initial circuit performance evaluation using the
TPS7A14. The EVM can be requested at the Texas Instruments web site through the product folder or
purchased directly from the TI eStore.
9.1.2 Device Nomenclature
Table 9-1. Device Nomenclature(1)(2)
(1)
(2)
PRODUCT
DESCRIPTION
TPS7A14xx(x)(P)yyyz
xx(x) is the nominal output voltage. Two or more digits are used in the ordering number (for example, 09
= 0.9 V, 95 = 0.95 V, 125 = 1.25 V).
P indicates active pull down; if there is no P, then the device does not have the active pull down feature.
yyy is the package designator.
z is the package quantity. R indicates reel (12000 pieces for YBK package; 3000 pieces for DRV
package).
For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the
device product folder on www.ti.com.
Output voltages from 0.5 V to 2.0 V in 25-mV increments are available. Contact the factory for details and availability.
9.2 Documentation Support
9.2.1 Related Documentation
For related documentation see the following:
• Texas Instruments, Using New Thermal Metrics application report
• Texas Instruments, AN-1112 DSBGA Wafer Level Chip Scale Package application report
• Texas Instruments, TPS7A14EVM-058 Evaluation Module user guide
9.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
9.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
9.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
9.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
9.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
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TPS7A14
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SBVS400D – DECEMBER 2021 – REVISED AUGUST 2023
Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
26
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Copyright © 2023 Texas Instruments Incorporated
Product Folder Links: TPS7A14
TPS7A14
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SBVS400D – DECEMBER 2021 – REVISED AUGUST 2023
10.1 Mechanical Data
PACKAGE OUTLINE
YBK0006-C02
DSBGA - 0.33 mm max height
SCALE 12.000
DIE SIZE BALL GRID ARRAY
B
A
E
BALL A1
CORNER
D
0.33 MAX
C
SEATING PLANE
0.05 C
0.115
0.065
0.4 TYP
SYMM
C
D: Max = 1.18 mm, Min = 1.14 mm
SYMM
0.8 TYP
E: Max = 0.73 mm, Min = 0.69 mm
B
0.4 TYP
A
1
6X
0.015
0.22
0.18
C A B
2
0.2 TYP
4228735/A 05/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
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TPS7A14
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SBVS400D – DECEMBER 2021 – REVISED AUGUST 2023
EXAMPLE BOARD LAYOUT
YBK0006-C02
DSBGA - 0.33 mm max height
DIE SIZE BALL GRID ARRAY
(0.2) TYP
6X ( 0.2)
2
1
A
(0.4) TYP
SYMM
B
C
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 50X
0.0375 MAX
0.0375 MIN
METAL UNDER
SOLDER MASK
EXPOSED
METAL
( 0.2)
SOLDER MASK
OPENING
( 0.2)
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
DEFINED
(PREFERRED)
NON-SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4228735/A 05/2022
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
See Texas Instruments Literature No. SNVA009 (www.ti.com/lit/snva009).
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TPS7A14
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SBVS400D – DECEMBER 2021 – REVISED AUGUST 2023
EXAMPLE STENCIL DESIGN
YBK0006-C02
DSBGA - 0.33 mm max height
DIE SIZE BALL GRID ARRAY
(0.2) TYP
(R0.05) TYP
6X ( 0.21)
1
2
A
(0.4) TYP
SYMM
B
C
METAL
TYP
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.075 mm THICK STENCIL
SCALE: 50X
4228735/A 05/2022
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
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PACKAGE OPTION ADDENDUM
www.ti.com
9-Nov-2023
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TPS7A1408PDRVR
ACTIVE
WSON
DRV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
33PH
Samples
TPS7A1408PYBKR
ACTIVE
DSBGA
YBK
6
12000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
M8
Samples
TPS7A1409PDRVR
ACTIVE
WSON
DRV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
33QH
Samples
TPS7A1409PYBKR
ACTIVE
DSBGA
YBK
6
12000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
MD
Samples
TPS7A14105PDRVR
ACTIVE
WSON
DRV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
33SH
Samples
TPS7A1410PDRVR
ACTIVE
WSON
DRV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
33RH
Samples
TPS7A1411PYBKR
ACTIVE
DSBGA
YBK
6
12000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
P6
Samples
TPS7A1412PDRVR
ACTIVE
WSON
DRV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
33UH
Samples
TPS7A1412PYBKR
ACTIVE
DSBGA
YBK
6
12000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
MG
Samples
TPS7A1413PYBKR
ACTIVE
DSBGA
YBK
6
12000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
MH
Samples
TPS7A1418PDRVR
ACTIVE
WSON
DRV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
33WH
Samples
TPS7A1485PYBKR
ACTIVE
DSBGA
YBK
6
12000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
M9
Samples
XS7A1408PDRVR
ACTIVE
WSON
DRV
6
3000
TBD
Call TI
Call TI
-40 to 125
Samples
XS7A1418PDRVR
ACTIVE
WSON
DRV
6
3000
TBD
Call TI
Call TI
-40 to 125
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
9-Nov-2023
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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