TPS7A1601QDGNRQ1

Product Folder Sample & Buy Support & Community Tools & Software Technical Documents TPS7A1601-Q1, TPS7A1633-Q1, TPS7A1650-Q1 SBVS188D – MARCH 2012 – REVISED MAY 2016 TPS7A16xx-Q1 60-V, 5-µA IQ, 100-mA, Low-Dropout Voltage Regulator With Enable and Power-Good 1 Features 3 Description • • The TPS7A16xx-Q1 ultralow-power, low-dropout (LDO) voltage regulators offer the benefits of ultralow quiescent current, high input voltage, and miniaturized, high-thermal-performance packaging. 1 • • • • • • • • • • • Qualified for Automotive Applications AEC-Q100 Qualified With the Following Results: – Device Temperature Grade 1: –40°C to 125°C Ambient Operating Temperature Range – Device HBM ESD Classification Level H2 – Device CDM ESD Classification Level C3B Wide Input Voltage Range: 3 V to 60 V Ultralow Quiescent Current: 5 µA Quiescent Current at Shutdown: 1 µA Output Current: 100 mA Low Dropout Voltage: 60 mV at 20 mA Accuracy: 2% Available in: – Fixed Output Voltage: 3.3 V, 5 V – Adjustable Version From Approximately 1.2 to 18.5 V Power-Good With Programable Delay Current-Limit and Thermal Shutdown Protections Stable With Ceramic Output Capactors: ≥ 2.2 µF Package: High-Thermal-Performance MSOP-8 PowerPAD™ Package The TPS7A16xx-Q1 devices are designed for continuous or sporadic (power backup) batterypowered applications where ultralow quiescent current is critical to extending system battery life. The TPS7A16xx-Q1 devices offer an enable pin (EN) compatible with standard CMOS logic and an integrated open-drain active-high power-good output (PG) with a user-programmable delay. These pins are intended for use in microcontroller-based, batterypowered applications where power-rail sequencing is required. In addition, the TPS7A16xx-Q1 devices are ideal for generating a low-voltage supply from multicell solutions ranging from high-cell-count power-tool packs to automotive applications; not only can these devices supply a well-regulated voltage rail, but they can also withstand and maintain regulation during voltage transients. These features translate to simpler and more cost-effective, electrical surge-protection circuitry. Device Information(1) PART NUMBER 2 Applications TPS7A1601-Q1 • TPS7A1633-Q1 • • • High Cell-Count Battery Packs for Power Tools and Other Battery-Powered Microprocessor and Microcontroller Systems Car Audio, Navigation, Infotainment, and Other Automotive Systems Power Supplies for Notebook PCs, Digital TVs, and Private LAN Systems Smoke or CO2 Detectors and Battery-Powered Alarm or Security Systems PACKAGE BODY SIZE (NOM) HVSSOP (8) 3.00 mm x 3.00 mm TPS7A1650-Q1 (1) For all available packages, see the orderable addendum at the end of the datasheet. Typical Application Schematic VIN 60 V 12 V t VOUT VIN OUT IN VCC mC2 CIN VEN COUT EN DELAY CDELAY GND EN RPG TPS7A16XX-Q1 PG IO1 VPG mC1 IO3 IO2 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPS7A1601-Q1, TPS7A1633-Q1, TPS7A1650-Q1 SBVS188D – MARCH 2012 – REVISED MAY 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 4 4 4 4 5 6 Absolute Maximum Ratings ...................................... ESD Ratings ............................................................ Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Typical Characteristics .............................................. Detailed Description .............................................. 9 7.1 Overview ................................................................... 9 7.2 Functional Block Diagram ......................................... 9 7.3 Feature Description................................................... 9 7.4 Device Functional Modes........................................ 10 8 Application and Implementation ........................ 11 8.1 Application Information............................................ 11 8.2 Typical Applications ................................................ 11 9 Power Supply Recommendations...................... 17 10 Layout................................................................... 17 10.1 10.2 10.3 10.4 Layout Guidelines ................................................. Layout Example .................................................... Power Dissipation ................................................. Thermal Considerations ........................................ 17 18 19 19 11 Device and Documentation Support ................. 20 11.1 11.2 11.3 11.4 Related Links ........................................................ Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 20 20 20 20 12 Mechanical, Packaging, and Orderable Information ........................................................... 20 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (August 2014) to Revision D Page • Changed data sheet title ........................................................................................................................................................ 1 • Changed pinout drawing......................................................................................................................................................... 3 • Changed Handling Ratings table to ESD Ratings; moved storage temperature to Absolute Maximum Ratings ................. 4 • Changed maximum EN pin voltage and added a row for EN slew rate ................................................................................. 4 • Changed UNIT for accuracy on VOUT .................................................................................................................................... 5 • Changed Ground current to Quiescent current ...................................................................................................................... 5 • Changed Figure 2................................................................................................................................................................... 6 • Changed caption of Figure 3 .................................................................................................................................................. 6 • Changed and added text in Enable (EN)................................................................................................................................ 9 • Moved three paragraphs of text from Layout Example to Layout Guidelines ...................................................................... 17 Changes from Revision B (May 2012) to Revision C • Page Added Handling Rating table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ............................................................... 4 Changes from Revision A (March 2012) to Revision B • 2 Page Changed to AEC-Q100 Qualified With the Following Results................................................................................................ 1 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: TPS7A1601-Q1 TPS7A1633-Q1 TPS7A1650-Q1 TPS7A1601-Q1, TPS7A1633-Q1, TPS7A1650-Q1 www.ti.com SBVS188D – MARCH 2012 – REVISED MAY 2016 5 Pin Configuration and Functions DGN Package 8-Pin HVSSOP With Exposed Thermal Pad Top View OUT 1 FB/DNC 2 8 IN 7 DELAY 6 NC 5 EN Thermal PG 3 GND 4 Pad NC – No internal connection Pin Functions PIN NAME NO. I/O DESCRIPTION DELAY 7 O Delay pin. Connect a capacitor to GND to adjust the PG delay time; leave open if the reset function is not needed. EN 5 I Enable pin. This pin turns the regulator on or off. If VEN ≥ VEN_HI, the regulator is enabled. If VEN ≤ VEN_LO, the regulator is disabled. If not used, the EN pin can be connected to IN. Make sure that VEN ≤ VIN at all times. For the adjustable version (TPS7A1601-Q1), the feedback pin is the input to the control-loop error amplifier. This pin is used to set the output voltage of the device when the regulator output voltage is set by external resistors. For the fixed voltage versions: Do not connect to this pin. Do not route this pin to any electrical net, not even GND or IN. FB/DNC 2 I GND 4 — Ground pin Regulator input supply pin. A capacitor > 0.1 µF must be tied from this pin to ground to assure stability. It is recommended to connect a 10-µF ceramic capacitor from IN to GND (as close to the device as possible) to reduce circuit sensitivity to printed-circuit-board (PCB) layout, especially when long input tracer or high source impedances are encountered. IN 8 I NC 6 --- This pin can be left open or tied to any voltage between GND and IN. OUT 1 O Regulator output pin. A capacitor > 2.2 µF must be tied from this pin to ground to assure stability. It is recommended to connect a 10-µF ceramic capacitor from OUT to GND (as close to the device as possible) to maximize ac performance. PG 3 O Power-good pin. Open-collector output; leave open or connect to GND if the power-good function is not needed. --- Solder to printed circuit board (PCB) to enhance thermal performance. Although it can be left floating, it is highly recommended to connect the thermal pad to the GND plane. Thermal pad Copyright © 2012–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS7A1601-Q1 TPS7A1633-Q1 TPS7A1650-Q1 3 TPS7A1601-Q1, TPS7A1633-Q1, TPS7A1650-Q1 SBVS188D – MARCH 2012 – REVISED MAY 2016 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating ambient temperature range (unless otherwise noted) Voltage Current (2) MIN MAX IN pin to GND pin –0.3 62 OUT pin to GND pin –0.3 20 OUT pin to IN pin –62 0.3 FB pin to GND pin –0.3 3 FB pin to IN pin –62 0.3 EN pin to IN pin –62 0.3 EN pin to GND pin –0.3 62 PG pin to GND pin –0.3 5.5 DELAY pin to GND pin –0.3 5.5 Peak output Temperature (1) (1) UNIT V Internally limited Operating virtual junction, TJ, absolute maximum range (2) –40 150 Storage temperature range –65 150 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Permanent damage does not occur to the part operating within this range, though electrical performance is not guaranteed outside the operating ambient temperature range. 6.2 ESD Ratings MIN MAX UNIT –2 2 kV Corner pins (OUT, GND, IN, and EN) –750 750 Other pins –500 500 Human body model (HBM), per AEC Q100-002 (1) V(ESD) (1) Electrostatic discharge Charged device model (CDM), per AEC Q100-011 V AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification. 6.3 Recommended Operating Conditions over operating ambient temperature range (unless otherwise noted) MIN NOM MAX UNIT VIN Unregulated input 3 60 V VOUT Regulated output 1.2 18 V 0 VIN V 1.5 V/µs Voltage EN Slew rate, voltage ramp-up DELAY 0 5 V PG 0 5 V –40 150 °C TJ Operating junction temperature range 6.4 Thermal Information TPS7A16xx-Q1 THERMAL METRIC (1) DGN (HVSSOP) UNIT 8 PINS RθJA Junction-to-ambient thermal resistance 66.2 °C/W RθJC(top) Junction-to-case(top) thermal resistance 45.9 °C/W RθJB Junction-to-board thermal resistance 34.6 °C/W ψJT Junction-to-top characterization parameter 1.9 °C/W ψJB Junction-to-board characterization parameter 34.3 °C/W (1) 4 For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: TPS7A1601-Q1 TPS7A1633-Q1 TPS7A1650-Q1 TPS7A1601-Q1, TPS7A1633-Q1, TPS7A1650-Q1 www.ti.com SBVS188D – MARCH 2012 – REVISED MAY 2016 Thermal Information (continued) TPS7A16xx-Q1 THERMAL METRIC (1) DGN (HVSSOP) UNIT 8 PINS RθJC(bot) Junction-to-case(bottom) thermal resistance 14.9 °C/W 6.5 Electrical Characteristics At TA= –40°C to 125°C, VIN = VOUT(NOM) + 0.5 V or VIN = 3 V (whichever is greater), VEN = VIN, IOUT = 10 µA, CIN = 1 μF, COUT = 2.2 μF, and FB tied to OUT, unless otherwise noted. PARAMETER TEST CONDITIONS VIN Input voltage range VREF Internal reference VUVLO Undervoltage lockout threshold MIN TYP MAX 60 V 1.193 1.217 V 3 TA = 25°C, VFB = VREF, VIN = 3 V, IOUT = 10 μA 1.169 UNIT 2.7 V Output voltage range VIN ≥ VOUT(NOM) + 0.5 V VREF 18.5 Nominal accuracy TA = 25°C, VIN = 3 V, IOUT = 10 μA –2% 2% Overall accuracy VOUT(NOM) + 0.5 V ≤ VIN ≤ 60 V (1) 10 µA ≤ IOUT ≤ 100 mA –2% 2% ΔVO(ΔVI) Line regulation 3 V ≤ VIN ≤ 60 V ±1 %VOUT ΔVO(ΔIO) Load regulation 10 µA ≤ IOUT ≤ 100 mA ±1 %VOUT VIN = 4.5 V, VOUT(NOM) = 5 V, IOUT = 20 mA 60 mV VOUT VDO Dropout voltage ILIM Current limit VIN = 4.5 V, VOUT(NOM) = 5 V, IOUT = 100 mA VOUT = 90% VOUT(NOM), VIN = 3.0 V 3 V ≤ VIN ≤ 60 V, IOUT = 10 µA IQ Quiescent current ISHDN Shutdown supply current I FB Feedback current (2) IEN Enable current VEN_HI Enable high-level voltage VEN_LO Enable low- level voltage IOUT = 100 mA 3 V ≤ VIN ≤ 12 V, VIN = VEN 500 mV 225 400 mA 5 15 μA 5.0 μA –1 0.0 1 µA –1 0.01 1 μA OUT pin floating, VFB increasing, VIN ≥ VIN_MIN 85 OUT pin floating, VFB decreasing, VIN ≥ VIN_MIN 83 VHYS PG trip hysteresis VPG, LO PG output low voltage OUT pin floating, VFB = 80% VREF, IPG= 1mA IPG, LKG PG leakage current VPG= VOUT(NOM) IDELAY DELAY pin current V 2.3 –1 1 PSRR Power-supply rejection ratio TSD Thermal shutdown temperature TA Operating ambient temperature range μA 5 1.2 PG trip threshold (2) 265 0.59 VEN = 0.4 V VIT (1) 101 V VIN = 3 V, VOUT(NOM) = VREF, COUT = 10 μF, f = 100 Hz 0.3 V 95 %VOUT 93 %VOUT 4 %VOUT 0.4 V 1 μA 2 μA 50 dB Shutdown, temperature increasing 170 °C Reset, temperature decreasing 150 °C –40 125 °C Maximum input voltage is limited to 24 V because of the package power dissipation limitations at full load (P ≈ (VIN – VOUT) × IOUT = (24 V – VREF) × 50 mA ≈ 1.14 W). The device is capable of sourcing a maximum current of 50 mA at higher input voltages as long as the power dissipated is within the thermal limits of the package plus any external heatsinking. IFB > 0 flows out of the device. Copyright © 2012–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS7A1601-Q1 TPS7A1633-Q1 TPS7A1650-Q1 5 TPS7A1601-Q1, TPS7A1633-Q1, TPS7A1650-Q1 SBVS188D – MARCH 2012 – REVISED MAY 2016 www.ti.com 6.6 Typical Characteristics At TA = –40°C to 125°C, VIN = VOUT(NOM) + 0.5 V or VIN = 3 V (whichever is greater), VEN = VIN, IOUT = 10 µA, CIN = 1 μF, COUT = 2.2 μF, and FB tied to OUT, unless otherwise noted. 10 50 IOUT = 0mA − 40°C + 25°C + 85°C + 105°C + 125°C 30 20 − 40°C + 25°C + 85°C + 105°C + 125°C 8 7 ISHDN (µA) IQ (µA) 40 VEN = 0.4 V 9 6 5 4 3 2 10 1 0 0 10 20 30 40 Input Voltage (V) 50 0 60 0 − 40°C + 25°C + 85°C + 105°C + 125°C 80 50 60 + 105°C + 125°C − 40°C + 25°C + 85°C 900 800 700 VDROP (mV) 70 IGND (µA) 30 40 Input Voltage (V) 1000 90 60 50 40 600 500 400 30 300 20 200 10 100 0 0 10 20 30 40 50 60 70 Output Current (mA) 80 90 100 0 Figure 3. Quiescent Current vs Output Current 20 40 60 Output Current (mA) 80 100 Figure 4. Dropout Voltage vs Output Current 1.294 10 − 40°C + 25°C + 85°C + 105°C + 125°C − 40°C + 25°C + 85°C 7.5 + 105°C + 125°C 5 VOUT(NOM) (%) 1.244 VFB (V) 20 Figure 2. Shutdown Current vs Input Voltage Figure 1. Quiescent Current vs Input Voltage 100 0 10 1.194 2.5 0 −2.5 1.144 −5 −7.5 1.094 0 10 20 30 40 Input Voltage (V) 50 Figure 5. Feedback Voltage vs Input Voltage 6 Submit Documentation Feedback 60 −10 0 10 20 30 40 Input Voltage (V) 50 60 Figure 6. Line Regulation Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: TPS7A1601-Q1 TPS7A1633-Q1 TPS7A1650-Q1 TPS7A1601-Q1, TPS7A1633-Q1, TPS7A1650-Q1 www.ti.com SBVS188D – MARCH 2012 – REVISED MAY 2016 Typical Characteristics (continued) At TA = –40°C to 125°C, VIN = VOUT(NOM) + 0.5 V or VIN = 3 V (whichever is greater), VEN = VIN, IOUT = 10 µA, CIN = 1 μF, COUT = 2.2 μF, and FB tied to OUT, unless otherwise noted. 10 300 − 40°C + 25°C + 85°C 7.5 + 105°C + 125°C 250 200 2.5 ICL (mA) VOUT(NOM) (%) 5 0 −2.5 150 100 − 40°C + 25°C + 85°C + 105°C + 125°C −5 50 −7.5 −10 0 10 20 30 40 50 60 70 Output Current (mA) 80 90 0 100 0 4 6 8 Input Voltage (V) 10 12 Figure 8. Current Limit vs Input Voltage 95 2.5 93 2 PG Rising 91 1.5 VEN (V) VOUTNOM (%) Figure 7. Load Regulation 2 89 87 OFF−TO−ON 1 0.5 PG Falling 85 −40 −25 −10 5 20 35 50 65 Temperature (°C) 80 95 0 −40 −25 −10 110 125 Figure 9. Power-Good Threshold Voltage vs Temperature ON−TO−OFF 5 20 35 50 65 Temperature (°C) 80 95 110 125 Figure 10. Enable Threshold Voltage vs Temperature 100 10 90 80 1 Noise (µV/ Hz) PSRR (dB) 70 60 50 40 0.1 30 0.01 20 VIN = 3V VOUT = ~1.2V COUT = 10µF 10 0 10 100 VIN = 3V VOUT = 1.2V COUT = 2.2µF 1k Frequency (Hz) 10k Figure 11. Power-Supply Rejection Ratio Copyright © 2012–2016, Texas Instruments Incorporated 100k 0.001 10 100 1k 10k 100k Frequency (Hz) 1M 10M Figure 12. Output Spectral Noise Density Submit Documentation Feedback Product Folder Links: TPS7A1601-Q1 TPS7A1633-Q1 TPS7A1650-Q1 7 TPS7A1601-Q1, TPS7A1633-Q1, TPS7A1650-Q1 SBVS188D – MARCH 2012 – REVISED MAY 2016 www.ti.com Typical Characteristics (continued) At TA = –40°C to 125°C, VIN = VOUT(NOM) + 0.5 V or VIN = 3 V (whichever is greater), VEN = VIN, IOUT = 10 µA, CIN = 1 μF, COUT = 2.2 μF, and FB tied to OUT, unless otherwise noted. VIN (2 V/div) VPG (2 V/div) VIN = 1 V ® 6.5 V IOUT = 1 mA COUT = 10 mF CFF = 0 nF VOUT (1 V/div) Time (5 ms/div) Figure 13. Power-Good Delay 8 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: TPS7A1601-Q1 TPS7A1633-Q1 TPS7A1650-Q1 TPS7A1601-Q1, TPS7A1633-Q1, TPS7A1650-Q1 www.ti.com SBVS188D – MARCH 2012 – REVISED MAY 2016 7 Detailed Description 7.1 Overview The TPS7A16xx-Q1 family of devices is ultra low power, low-dropout (LDO) voltage regulators that offers the benefits of ultra-low quiescent current, high input voltage, and miniaturized, high thermal-performance packaging. TPS7A16xx-Q1 family also offers an enable pin (EN) and integrated open-drain active-high power-good output (PG) with a user-programmable delay. 7.2 Functional Block Diagram IN OUT UVLO Pass Device Thermal Shutdown Current Limit Enable Error Amp FB EN PG Power Good Control DELAY 7.3 Feature Description 7.3.1 Enable (EN) The enable terminal is a high-voltage-tolerant terminal. A high input on EN actives the device and turns on the regulator. For self-bias applications, connect this input to the VIN terminal. Ensure that VEN ≤ VIN at all times. When the enable signal is PWM pulses, the slew rate of the rising and falling edges must be less than 1.5 V/µs. Adding a 0.1-µF capacitor from the EN pin to GND is recommended. 7.3.2 Regulated Output (VOUT) The VOUT terminal is the regulated output based on the required voltage. The output has current limitation. During initial power up, the regulator has a soft start incorporated to control the initial current through the pass element. In the event that the regulator drops out of regulation, the output tracks the input minus a drop based on the load current. When the input voltage drops below the UVLO threshold, the regulator shuts down until the input voltage recovers above the minimum start-up level. 7.3.3 PG Delay Timer (DELAY) The power-good delay time (tDELAY) is defined as the time period from when VOUT exceeds the PG trip threshold voltage (VIT) to when the PG output is high. This power-good delay time is set by an external capacitor (CDELAY) connected from the DELAY pin to GND; this capacitor is charged from 0 V to ~1.8 V by the DELAY pin current (IDELAY) once VOUT exceeds the PG trip threshold (VIT). Copyright © 2012–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS7A1601-Q1 TPS7A1633-Q1 TPS7A1650-Q1 9 TPS7A1601-Q1, TPS7A1633-Q1, TPS7A1650-Q1 SBVS188D – MARCH 2012 – REVISED MAY 2016 www.ti.com 7.4 Device Functional Modes 7.4.1 Power-Good The power-good (PG) pin is an open-drain output and can be connected to any 5.5-V or lower rail through an external pullup resistor. When no CDELAY is used, the PG output is high-impedance when VOUT is greater than the PG trip threshold (VIT). If VOUT drops below VIT, the open-drain output turns on and pulls the PG output low. If output voltage monitoring is not needed, the PG pin can be left floating or connected to GND. To ensure proper operation of the power-good feature, maintain VIN ≥ 3 V (VIN_MIN). 7.4.1.1 Power-Good Delay and Delay Capacitor The power-good delay time (tDELAY) is defined as the time period from when VOUT exceeds the PG trip threshold voltage (VIT) to when the PG output is high. This power-good delay time is set by an external capacitor (CDELAY) connected from the DELAY pin to GND; this capacitor is charged from 0 V to ap 1.8 V by the DELAY pin current (IDELAY) once VOUT exceeds the PG trip threshold (VIT). When CDELAY is used, the PG output is high-impedance when VOUT exceeds VIT, and VDELAY exceeds VREF. The power-good delay time can be calculated using: tDELAY = (CDELAY × VREF)/IDELAY. For example, when CDELAY = 10 nF, the PG delay time is approximately 12 ms; that is, (10 nF × 1.193 V)/1 µA = 11.93 ms. 10 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: TPS7A1601-Q1 TPS7A1633-Q1 TPS7A1650-Q1 TPS7A1601-Q1, TPS7A1633-Q1, TPS7A1650-Q1 www.ti.com SBVS188D – MARCH 2012 – REVISED MAY 2016 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The TPS7A16xx-Q1 family of ultralow-power voltage regulators offers the benefit of ultralow quiescent current, high input voltage, and miniaturized, high-thermal-performance packaging. The TPS7A16xx-Q1 are designed for continuous or sporadic (power backup) battery-operated applications where ultralow quiescent current is critical to extending system battery life. 8.2 Typical Applications 8.2.1 TPS7A1601-Q1 Circuit as an Adjustable Regulator VIN VOUT OUT IN CIN CFF R1 COUT TPS7A1601-Q1 VEN EN RPG FB Where: R1 = R2 VOUT -1 VREF R2 DELAY GND VPG PG CDELAY Figure 14. TPS7A1601-Q1 Circuit as an Adjustable Regulator Schematic 8.2.1.1 Design Requirements Table 1. Design Parameters DESIGN PARAMETER EXAMPLE VALUE Input voltage range 5.5 V to 40 V Output voltage 5V Output current rating 100 mA Output capacitor range 2.2 μF to 100 μF Delay capacitor range 100 pF to 100 nF 8.2.1.2 Detailed Design Procedure 8.2.1.2.1 Adjustable Voltage Operation The TPS7A1601-Q1 has an output voltage range from 1.194 V to 20 V. The nominal output of the device is set by two external resistors, as shown in Figure 15: Copyright © 2012–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS7A1601-Q1 TPS7A1633-Q1 TPS7A1650-Q1 11 TPS7A1601-Q1, TPS7A1633-Q1, TPS7A1650-Q1 SBVS188D – MARCH 2012 – REVISED MAY 2016 www.ti.com VIN IN PG CIN 0.1 mF RPG 1 MW EN CDELAY 0.1 mF OUT COUT 2.2 mF R1 3.4 MW DELAY VOUT 5V FB GND R2 1.07 MW Figure 15. Adjustable Operation R1 and R2 can be calculated for any output voltage range using the formula shown in Equation 1: VOUT R1 = R2 -1 VREF (1) 8.2.1.2.1.1 Resistor Selection It is recommended to use resistors in the order of MΩ to keep the overall quiescent current of the system as low as possible (by making the current used by the resistor divider negligible compared to the quiescent current of the device). If greater voltage accuracy is required, take into account the voltage offset contributions as a result of feedback current and use 0.1% tolerance resistors. Table 2 shows the resistor combination to achieve an output for a few of the most common rails using commercially available 0.1% tolerance resistors to maximize nominal voltage accuracy, while adhering to the formula shown in Equation 1. Table 2. Selected Resistor Combinations VOUT R1 R2 VOUT/(R1 + R2) « IQ 1.194 V 0Ω ∞ 0 µA NOMINAL ACCURACY ±2% 1.8 V 1.18 MΩ 2.32 MΩ 514 nA ±(2% + 0.14%) 2..5 V 1.5 MΩ 1.37 MΩ 871 nA ±(2% + 0.16%) 3.3 V 2 MΩ 1.13 MΩ 1056 nA ±(2% + 0.35%) 5V 3.4 MΩ 1.07 MΩ 1115 nA ±(2% + 0.39%) 10 V 7.87 MΩ 1.07 MΩ 1115 nA ±(2% + 0.42%) 12 V 14.3 MΩ 1.58 MΩ 755 nA ±(2% + 0.18%) 15 V 42.2 MΩ 3.65 MΩ 327 nA ±(2% + 0.19%) 18 V 16.2 MΩ 1.15 MΩ 1038 nA ±(2% + 0.26%) Close attention must be paid to board contamination when using high-value resistors; board contaminants may significantly impact voltage accuracy. If board cleaning measures cannot be ensured, consider using a fixedvoltage version of the TPS7A16 or using resistors in the order of hundreds or tens of kΩ. 8.2.1.2.2 Capacitor Recommendations Low equivalent-series-resistance (ESR) capacitors should be used for the input, output, and feed-forward capacitors. Ceramic capacitors with X7R and X5R dielectrics are preferred. These dielectrics offer more stable characteristics. Ceramic X7R capacitors offer improved overtemperature performance, while ceramic X5R capacitors are the most cost-effective and are available in higher values. Note that high-ESR capacitors may degrade PSRR. 12 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: TPS7A1601-Q1 TPS7A1633-Q1 TPS7A1650-Q1 TPS7A1601-Q1, TPS7A1633-Q1, TPS7A1650-Q1 www.ti.com SBVS188D – MARCH 2012 – REVISED MAY 2016 8.2.1.2.3 Input and Output Capacitor Requirements The TPS7A16xx-Q1 ultralow-power, high-voltage linear regulators achieve stability with a minimum input capacitance of 0.1 µF and output capacitance of 2.2 µF; however, it is recommended to use a 10-µF ceramic capacitor to maximize ac performance. 8.2.1.2.4 Feed-Forward Capacitor (Only for Adjustable Version) Although a feed-forward capacitor (CFF) from OUT to FB is not needed to achieve stability, it is recommended to use a 0.01-µF feed-forward capacitor to maximize ac performance. 8.2.1.2.5 Transient Response As with any regulator, increasing the size of the output capacitor reduces over/undershoot magnitude but increases the duration of the transient response. 8.2.1.3 Application Curves Figure 16. CH1 is VOUT, CH2 is PG, CH4 is lout, VIN is 12 V and Ready Before EN Copyright © 2012–2016, Texas Instruments Incorporated Figure 17. CH1 is VOUT, CH2 is PG, CH3 is EN, CH4 is lout, VIN is 12 V Connected to EN Submit Documentation Feedback Product Folder Links: TPS7A1601-Q1 TPS7A1633-Q1 TPS7A1650-Q1 13 TPS7A1601-Q1, TPS7A1633-Q1, TPS7A1650-Q1 SBVS188D – MARCH 2012 – REVISED MAY 2016 www.ti.com 8.2.2 Automotive Applications The TPS7A16xx-Q1 maximum input voltage of 60 V makes it ideal for use in automotive applications where highvoltage transients are present. Events such as load-dump overvoltage (where the battery is disconnected while the alternator is providing current to a load) may cause voltage spikes from 25 V to 60 V. In order to prevent any damage to sensitive circuitry, local transient voltage suppressors can be used to cap voltage spikes to lower, more manageable voltages. The TPS7A16xx-Q1 can be used to simplify and lower costs in such cases. The very high voltage range allows this regulator not only to withstand the voltages coming out of these local transient voltage suppressors, but even replace them, thus lowering system cost and complexity. VIN 60 V 12 V t VOUT VIN OUT IN VCC mC2 CIN VEN COUT EN DELAY GND CDELAY EN RPG TPS7A16XX-Q1 PG IO1 VPG mC1 IO3 IO2 Figure 18. Low-Power Microcontroller Rail Sequencing in Automotive Applications Subjected to LoadDump Transients 8.2.2.1 Design Requirements Table 3. Design Parameters DESIGN PARAMETER EXAMPLE VALUE Input voltage range 5.5 V to 60 V Output voltage 5V Output current rating 100 mA Output capacitor range 2.2 μF to 100 μF Delay capacitor range 100 pF to 100 nF 8.2.2.2 Detailed Design Procedure See Capacitor Recommendations and Input and Output Capacitor Requirements. 8.2.2.2.1 Device Recommendations The output is fixed, so choose TPS7A1650-Q1. 8.2.2.3 Application Curves See Figure 16 and Figure 17. 14 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: TPS7A1601-Q1 TPS7A1633-Q1 TPS7A1650-Q1 TPS7A1601-Q1, TPS7A1633-Q1, TPS7A1650-Q1 www.ti.com SBVS188D – MARCH 2012 – REVISED MAY 2016 8.2.3 Multicell Battery Packs Currently, battery packs can employ up to a dozen cells in series that, when fully charged, may have voltages of up to 55 V. Internal circuitry in these battery packs is used to prevent overcurrent and overvoltage conditions that may degrade battery life or even pose a safety risk; this internal circuitry is often managed by a low-power microcontroller, such as TI’s MSP430™. See the overview for microcontrollers (MCU) for more information. The microcontroller continuously monitors the battery itself, whether the battery is in use or not. Although this microcontroller could be powered by an intermediate voltage taken from the multicell array, this approach unbalances the battery pack itself, degrading its life or adding cost to implement more complex cell balancing topologies. The best approach to power this microcontroller is to regulate down the voltage from the entire array to discharge every cell equally and prevent any balancing issues. This approach reduces system complexity and cost. TPS7A16xx-Q1 is the ideal regulator for this application because it can handle very high voltages (from the entire multicell array) and has very low quiescent current (to maximize battery life). Sensing Up To 42 V + Comparator Cell Balance TPS7A16XX-Q1 Voltage Sensing Microcontroller UART - Figure 19. Protection Based on Low-Power Microcontroller Power From Multicell Battery Packs 8.2.3.1 Design Requirements Table 4. Device Parameters DESIGN PARAMETER EXAMPLE VALUE Input voltage range 5.5 V to 55 V Output voltage 5V Output current rating 100 mA Output capacitor range 2.2 μF to 100 μF Delay capacitor range 100 pF to 100 nF 8.2.3.2 Detailed Design Procedure See Device Recommendations, Capacitor Recommendations, and Input and Output Capacitor Requirements. 8.2.3.3 Application Curves See Figure 16 and Figure 17. Copyright © 2012–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS7A1601-Q1 TPS7A1633-Q1 TPS7A1650-Q1 15 TPS7A1601-Q1, TPS7A1633-Q1, TPS7A1650-Q1 SBVS188D – MARCH 2012 – REVISED MAY 2016 www.ti.com 8.2.4 Battery-Operated Power Tools High-voltage multicell battery packs support high-power applications, such as power tools, with high current drain when in use, highly intermittent use cycles, and physical separation between battery and motor. In these applications, a microcontroller or microprocessor controls the motor. This microcontroller must be powered with a low-voltage rail coming from the high-voltage, multicell battery pack; as mentioned previously, powering this microcontroller or microprocessor from an intermediate voltage from the multicell array causes battery-pack life degradation or added system complexity because of cell balancing issues. In addition, this microcontroller or microprocessor must be protected from the high-voltage transients because of the motor inductance. The TPS7A16xx-Q1 can be used to power the motor-controlled microcontroller or microprocessor; its low quiescent current maximizes battery shelf life, and its very high-voltage capabilities simplify system complexity by replacing voltage suppression filters, thus lowering system cost. 100 W Transient LDO First Cell Optional Filter M 0.47 mF Second Cell MSP430 Microcontroller PWM Last Cell Figure 20. Low Power Microcontroller Power From Multi-Cell Battery Packs in Power Tools 8.2.4.1 Design Requirements Table 5. Design Parameters DESIGN PARAMETER EXAMPLE VALUE Input voltage range 5.5 V to 60 V Output voltage 5V Output current rating 100 mA Output capacitor range 2.2 μF to 100 μF Delay capacitor range 100 pF to 100 nF 8.2.4.2 Detailed Design Procedure See Device Recommendations, Capacitor Recommendations, and Input and Output Capacitor Requirements. 8.2.4.3 Application Curves See Figure 16 and Figure 17. 16 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: TPS7A1601-Q1 TPS7A1633-Q1 TPS7A1650-Q1 TPS7A1601-Q1, TPS7A1633-Q1, TPS7A1650-Q1 www.ti.com SBVS188D – MARCH 2012 – REVISED MAY 2016 9 Power Supply Recommendations Design of the device is for operation from an input voltage supply with a range between 3 V and 60 V. This input supply must be well regulated. TPS7A16xx-Q1 ultralow-power, high-voltage linear regulators achieve stability with a minimum input capacitance of 0.1 μF and output capacitance of 2.2 μF; however, it is recommended to use a 10-μF ceramic capacitor to maximize AC performance. 10 Layout 10.1 Layout Guidelines To improve ac performance such as PSRR, output noise, and transient response, it is recommended that the board be designed with separate ground planes for IN and OUT, with each ground plane connected only at the GND pin of the device. In addition, the ground connection for the output capacitor should connect directly to the GND pin of the device. Equivalent series inductance (ESL) and ESR must be minimized in order to maximize performance and ensure stability. Every capacitor must be placed as close as possible to the device and on the same side of the PCB as the regulator itself. Do not place any of the capacitors on the opposite side of the PCB from where the regulator is installed. The use of vias and long traces is strongly discouraged because they may impact system performance negatively and even cause instability. If possible, and to ensure the maximum performance denoted in this product data sheet, use the same layout pattern used for TPS7A16xx-Q1 evaluation board, available at www.ti.com. Layout is a critical part of good power-supply design. There are several signal paths that conduct fast-changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade the power-supply performance. To help eliminate these problems, the IN pin should be bypassed to ground with a low-ESR ceramic bypass capacitor with X5R or X7R dielectric. It may be possible to obtain acceptable performance with alternative PCB layouts; however, the layout and the schematic have been shown to produce good results and are meant as a guideline. Figure 21 shows the schematic for the suggested layout. Figure 22 and Figure 23 show the top and bottom printed circuit board (PCB) layers for the suggested layout. 10.1.1 Additional Layout Considerations The high impedance of the FB pin makes the regulator sensitive to parasitic capacitances that may couple undesirable signals from nearby components (especially from logic and digital ICs, such as microcontrollers and microprocessors); these capacitively-coupled signals may produce undesirable output voltage transients. In these cases, it is recommended to use a fixed-voltage version of the TPS7A16xx-Q1, or to isolate the FB node by flooding the local PCB area with ground-plane copper to minimize any undesirable signal coupling. Copyright © 2012–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS7A1601-Q1 TPS7A1633-Q1 TPS7A1650-Q1 17 TPS7A1601-Q1, TPS7A1633-Q1, TPS7A1650-Q1 SBVS188D – MARCH 2012 – REVISED MAY 2016 www.ti.com 10.2 Layout Example Figure 21. Schematic for Suggested Layout 1300 mil 2200 mil Figure 22. Suggested Layout: Top Layer 18 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: TPS7A1601-Q1 TPS7A1633-Q1 TPS7A1650-Q1 TPS7A1601-Q1, TPS7A1633-Q1, TPS7A1650-Q1 www.ti.com SBVS188D – MARCH 2012 – REVISED MAY 2016 Layout Example (continued) 1300 mil 2200 mil Figure 23. Suggested Layout: Bottom Layer 10.3 Power Dissipation The ability to remove heat from the die is different for each package type, presenting different considerations in the PCB layout. The PCB area around the device that is free of other components moves the heat from the device to the ambient air. Using heavier copper increases the effectiveness of removing heat from the device. The addition of plated through-holes to heat dissipating layers also improves the heatsink effectiveness. Power dissipation depends on input voltage and load conditions. Power dissipation (PD) is equal to the product of the output current times the voltage drop across the output pass element, as shown in Equation 2: PD = (VIN - VOUT) IOUT (2) 10.4 Thermal Considerations Thermal protection disables the output when the junction temperature rises to approximately 170°C, allowing the device to cool. When the junction temperature cools to approximately 150°C, the output circuitry is enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may cycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage as a result of overheating. Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate heat-spreading area. For reliable operation, junction temperature should be limited to a maximum of 125°C at the worst case ambient temperature for a given application. To estimate the margin of safety in a complete design (including the copper heat-spreading area), increase the ambient temperature until the thermal protection is triggered; use worst-case loads and signal conditions. For good reliability, thermal protection should trigger at least 45°C above the maximum expected ambient condition of the particular application. This configuration produces a worst-case junction temperature of 125°C at the highest expected ambient temperature and worstcase load. The internal protection circuitry of the TPS7A16xx-Q1 has been designed to protect against overload conditions. It was not intended to replace proper heatsinking. Continuously running the TPS7A16xx-Q1 into thermal shutdown degrades device reliability. Copyright © 2012–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS7A1601-Q1 TPS7A1633-Q1 TPS7A1650-Q1 19 TPS7A1601-Q1, TPS7A1633-Q1, TPS7A1650-Q1 SBVS188D – MARCH 2012 – REVISED MAY 2016 www.ti.com 11 Device and Documentation Support 11.1 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 6. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY TPS7A1601-Q1 Click here Click here Click here Click here Click here TPS7A1633-Q1 Click here Click here Click here Click here Click here TPS7A1650-Q1 Click here Click here Click here Click here Click here 11.2 Trademarks PowerPAD, MSP430 are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. 11.3 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.4 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and without revision of this document. For browser-based versions of this data sheet, see the left-hand navigation pane. 20 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: TPS7A1601-Q1 TPS7A1633-Q1 TPS7A1650-Q1 PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) TPS7A1601QDGNRQ1 ACTIVE HVSSOP DGN 8 2500 Green (RoHS & no Sb/Br) NIPDAUAG Level-2-260C-1 YEAR -40 to 125 PXZQ TPS7A1633QDGNRQ1 ACTIVE HVSSOP DGN 8 2500 Green (RoHS & no Sb/Br) NIPDAU Level-2-260C-1 YEAR -40 to 125 PXYQ TPS7A1650QDGNRQ1 ACTIVE HVSSOP DGN 8 2500 Green (RoHS & no Sb/Br) NIPDAUAG Level-2-260C-1 YEAR -40 to 125 PYAQ (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of