TPS7A1901DRBR

Product Folder Sample & Buy Support & Community Tools & Software Technical Documents TPS7A19 SBVS256A – MAY 2016 – REVISED SEPTEMBER 2016 TPS7A19 40-V, 450-mA, Wide VIN, Low IQ, Low-Dropout Voltage Regulator with Power Good 1 Features 3 Description • • • • • • • • The TPS7A19 is a low-dropout linear regulator (LDO) with a wide input voltage (VIN) range up to 40 V, capable of sourcing high output current (IOUT) up to 450 mA. This voltage regulator is ideal for generating a low-voltage supply from wide input-voltage rails. Not only does the TPS7A19 supply a well-regulated voltage rail, but the device also withstands and maintains regulation during voltage transients by acting as a simple surge protection circuit. 1 • • Wide Input Voltage Range: 4 V to 40 V Adjustable Output Voltage: 1.5 V to 18 V Output Current: 450 mA Low Quiescent Current (IQ): 15 µA Low Dropout Voltage: 450 mV (max) at 400 mA Power Good with Programmable Delay Thermal Shutdown and Overcurrent Protection Stable with Ceramic Output Capacitors: – 10 µF to 500 µF for VOUT ≥ 2.5 V – 22 µF to 500 µF for VOUT < 2.5 V Operating Temperature: –40°C to +125°C Package: 3-mm × 3-mm SON-8 2 Applications • • • • • Smart Grid Infrastructure and Metering Power Tools Motor Drives Access Control Systems Test and Measurement The TPS7A19 consumes only 15 µA of quiescent current (IQ) at light loads, thereby lowering the power consumption for always-on or battery-powered applications. The TPS7A19 features integrated thermal shutdown and overcurrent protection. The TPS7A19 also offers a power good output (PG) with a programmable delay that indicates when the output voltage is in regulation. This feature is useful for power-rail sequencing functions. This LDO is available in a small, 3-mm × 3-mm, thermally-enhanced, 8-pin SON package. Device Information(1) PART NUMBER TPS7A19 PACKAGE SON (8) BODY SIZE (NOM) 3.00 mm × 3.00 mm (1) For all available packages, see the package option addendum at the end of the data sheet. Typical Application Schematic Quiescent Current vs Input Voltage at VOUT = 1.5 V 25 IO PG IN OUT EN MSP430 VOUT VDD TPS7A19 FB DELAY GND Quiescent Current ( A) 4 V to 40 V VIN 20 15 10 ±40°C 5 25°C Copyright © 2016, Texas Instruments Incorporated 125°C 0 0 10 20 Input Voltage (V) 30 40 C003 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPS7A19 SBVS256A – MAY 2016 – REVISED SEPTEMBER 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 6.7 4 4 4 4 5 5 6 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Timing Requirements ................................................ Typical Characteristics .............................................. Detailed Description .............................................. 8 7.1 Overview ................................................................... 8 7.2 Functional Block Diagram ......................................... 8 7.3 Feature Description................................................... 8 7.4 Device Functional Modes........................................ 10 8 Application and Implementation ........................ 11 8.1 Application Information............................................ 11 8.2 Typical Application .................................................. 11 9 Power Supply Recommendations...................... 13 10 Layout................................................................... 13 10.1 Layout Guidelines ................................................. 13 10.2 Layout Example .................................................... 13 11 Device and Documentation Support ................. 14 11.1 11.2 11.3 11.4 11.5 11.6 11.7 Device Support...................................................... Documentation Support ....................................... Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 14 14 14 14 14 15 15 12 Mechanical, Packaging, and Orderable Information ........................................................... 15 4 Revision History Changes from Original (May 2016) to Revision A • 2 Page Changed from product preview to production data ................................................................................................................ 1 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS7A19 TPS7A19 www.ti.com SBVS256A – MAY 2016 – REVISED SEPTEMBER 2016 5 Pin Configuration and Functions DRB Package 8-Pin SON With Thermal Pad Top View DELAY 1 OUT 2 FB 3 GND 4 Thermal Pad 8 PG 7 IN 6 EN 5 GND Not to scale Pin Functions PIN NAME NO. I/O DESCRIPTION Delay pin. Connect a capacitor to GND to adjust the PG delay time; leave open if the PG function is not needed. DELAY 1 — EN 6 I Enable pin. This pin turns the regulator on or off. If VEN ≥ VEN_HI, the regulator is enabled. If VEN ≤ VEN_LO, the regulator is disabled. If not used, the EN pin can be connected to IN. FB 3 I Feedback pin. The feedback pin is the input to the control-loop error amplifier. GND 4,5 — IN 7 I Regulator input supply pin. OUT 2 O Regulator output pin. When the output voltage is larger than 2.5 V, connect a 10-μF to 500-μF ceramic capacitor with an equivalent series resistance (ESR) from 0.001 to 20 Ω to assure stability. When the output voltage is from 1.5 V to 2.5 V, the minimum, stable capacitor value should be 22 μF. PG 8 O Power good. This open-drain pin must be connected to VOUT through an external resistor. PG is pulled low when the output voltage goes below threshold. — Solder to printed-circuit-board (PCB) to enhance thermal performance. Although the thermal pad can be left floating, connect the thermal pad to the ground plane for optimal performance. Thermal pad Ground pin. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS7A19 3 TPS7A19 SBVS256A – MAY 2016 – REVISED SEPTEMBER 2016 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range –40°C to 125°C(unless otherwise noted) (1) Input Voltage (2) Output Current (2) (3) (4) MAX –0.3 45 OUT (3) –0.3 VIN + 0.3 DELAY (4) –0.3 45 FB, PG –0.3 22 Peak output Temperature (1) MIN IN, EN UNIT V Internally limited Operating junction, TJ –40 150 Storage, Tstg –65 150 °C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to GND. The absolute maximum rating is VIN + 0.3 V or 22 V, whichever is lower. The voltage at the DELAY pin must be lower than the VIN voltage. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000 Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±500 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VIN Input supply voltage 4 40 V VOUT Output voltage 1.5 18 V VEN Enable voltage 0 40 V TJ Operating junction temperature –40 125 °C 6.4 Thermal Information TPS7A19 THERMAL METRIC (1) DRB (VSON) UNIT 8 PINS RθJA Junction-to-ambient thermal resistance 48 °C/W RθJC(top) RθJB Junction-to-case (top) thermal resistance 56.3 °C/W Junction-to-board thermal resistance 22.4 °C/W ψJT Junction-to-top characterization parameter 0.9 °C/W ψJB Junction-to-board characterization parameter 22.5 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 4.6 °C/W (1) 4 For information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS7A19 TPS7A19 www.ti.com SBVS256A – MAY 2016 – REVISED SEPTEMBER 2016 6.5 Electrical Characteristics at TJ = –40°C to +125°C, VIN = 14 V , VEN = VIN, IOUT = 200 μA, CIN = 22 μF, and COUT = 47 μF (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY VOLTAGE AND CURRENT VIN Input voltage VOUT ≤ 3.5 V , IOUT = 0 mA to 450 mA 4 40 V VOUT ≥ 3.5 V , IOUT = 0 mA to 450 mA VOUT + 0.5 40 V VIN = 4 V to 40 V, VOUT = 1.5 V, VEN = 5 V, IOUT = 0.2 mA 15 25 VIN = 18.5 V to 40 V, VOUT = 18 V, VEN = 5 V, IOUT = 0.2 mA 25 40 4 µA 1.233 1.258 V 2.6 V IQ Quiescent current ISHDN Shutdown current VEN = 0 V, IOUT = 0 mA , VIN = 18 V, VOUT = 1.5 V VFB Feedback voltage Reference voltage for FB pin VIN_UVLO Undervoltage lockout Ramp VIN down until output is turned off UVLOHys Undervoltage detection hysteresis VIN rising 1.208 µA 1 V ENABLE INPUT (EN) VEN_LO Logic input low level VEN_HI Logic input high level IEN EN pin current 0 0.4 V 1 µA 1.7 V VEN = 40 V , VIN = 14 V REGULATED OUTPUT VOUT Regulated output (1) VIN = VOUT + 1 V to 40 V and VIN ≥ 4 V, IOUT = 100 µA to 450 mA ΔVO(ΔVI) Line regulation VIN = VOUT + 1 V to 40 V and VIN ≥ 4 V, IOUT = 100 mA 10 mV ΔVO(ΔIL) Load regulation IOUT = 1 mA to 450 mA, VIN = VOUT + 1 V and VIN ≥ 4 V 10 mV VDO Dropout voltage IOUT Output current –2% 2% VIN – VOUT, IOUT = 400 mA 240 450 VIN – VOUT, IOUT = 200 mA 160 300 VOUT in regulation 0 450 VOUT short to ground 140 360 VOUT = VOUT nominal × 0.9 470 850 ICL Output current-limit PSRR Power-supply ripple rejection (2) IOUT = 100 mA, COUT = 22 µF VOL PG output low voltage IOL = 0.5 mA IOH PG leakage current PG pulled to VOUTwith 10-kΩ resistor VT(PG) Power good threshold VOUT power-up Vhys Hysteresis VOUT power-down f = 100 Hz 60 f = 100 kHz 40 mV mA mA dB PG 89.6 91.6 0.4 V 1 µA 93.6 2 % of VOUT % of VOUT PG DELAY IDelay Delay capacitor charging current VT(PG_DLY) Delay pin comparator threshold voltage 5 9.5 14 µA 1 V 175 °C 24 °C TEMPERATURE Tsd Junction shutdown temperature Thys Hysteresis of thermal shutdown (1) (2) Temperature increasing Accuracy specification does not apply on any application condition that exceeds the power dissipation limit of the package under test. External resistor divider variation is not considered for accuracy measurement. Design information; not tested, specified by characterization. 6.6 Timing Requirements MIN TYP MAX UNIT TIMING FOR PG tPG_DLY Power good delay C = delay-capacitor value capacitance = 100 nF (1) 10.5 ms tPG-fixed Power good delay No capacitor on pin 325 µs tPG(HL) PG falling propagation delay VOUT low to PG low 180 µs (1) –6 Information only; not tested in production. The equation is based on: (C × 1) / (9.5 × 10 ) = tPG_DLY, where C = delay capacitor value capacitance; range = 100 pF to 500 nF. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS7A19 5 TPS7A19 SBVS256A – MAY 2016 – REVISED SEPTEMBER 2016 www.ti.com 6.7 Typical Characteristics at TJ = –40°C to +125°C, VIN = 14 V , VEN = VIN, IOUT = 200 μA, CIN = 22 μF, and COUT = 47 μF (unless otherwise noted) 1.60 160 140 1.56 1.54 1.52 1.50 1.48 1.46 ±40°C 1.44 Ground Current ( A) Output Voltage, Nominal (V) 1.58 25°C 1.42 120 100 80 60 ±40°C 40 25°C 20 125°C 125°C 1.40 0 0 5 10 15 20 25 30 35 40 0 50 100 Input Voltage (V) 150 200 250 300 350 400 450 C 02 0 Output Current (mA) VOUT = 1.5 V, IOUT = 100 mA VIN = 14 V, VOUT = 1.5 V Figure 1. Line Regulation Figure 2. Ground Current vs Output Current 25 160 Ground Current ( A) Quiescent Current ( A) 140 20 15 10 ±40°C 5 25°C 120 100 80 60 ±40°C 40 25°C 20 125°C 125°C 0 0 0 10 20 30 40 Input Voltage (V) 0 50 150 200 250 300 350 400 Output Current (mA) C003 VOUT = 1.5 V 450 C004 VIN = 24 V, VOUT = 18 V Figure 3. Quiescent Current vs Input Voltage Figure 4. Ground Current vs Output Current 35 400 30 350 Dropout Voltage (mV) Quiescent Current ( A) 100 25 20 15 10 ±40°C 25°C 5 300 250 200 150 ±40°C 100 25°C 50 125°C 125°C 0 0 15 20 25 30 35 Input Voltage (V) 40 45 0 50 100 150 200 250 300 350 400 450 Output Current (mA) C005 VOUT = 18 V Figure 5. Quiescent Current vs Input Voltage 6 Figure 6. Dropout Voltage vs Output Current Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS7A19 TPS7A19 www.ti.com SBVS256A – MAY 2016 – REVISED SEPTEMBER 2016 Typical Characteristics (continued) at TJ = –40°C to +125°C, VIN = 14 V , VEN = VIN, IOUT = 200 μA, CIN = 22 μF, and COUT = 47 μF (unless otherwise noted) 1.60 120 Power Supply Rejection Ratio (dB) 1.58 Output Voltage (V) 1.56 1.54 1.52 1.50 1.48 1.46 ±40°C 1.44 25°C 1.42 125°C 100 80 60 40 20 1.40 0 0 50 100 150 200 250 300 350 400 Output Current (mA) 10M100000000 100 1M 100 1k1000 10k10000100k 100000 1000000 10000000 1010 450 Frequency (Hz) C007 VIN = 14 V, VOUT = 1.5 V VOUT = 5 V, COUT = 47 µF, IOUT = 10 mA Figure 7. Load Regulation Figure 8. Power-Supply Rejection Ratio vs Frequency 220 630 620 610 Current Limit (mA) Current Limit (mA) 215 210 205 200 600 590 580 570 560 550 540 195 530 190 520 ±40 ±25 ±10 5 20 35 50 65 Temperature (ƒC) 80 95 110 125 ±40 ±25 ±10 Figure 9. Short to GND Current-Limit vs Temperature 5 20 35 50 65 80 95 110 125 Temperature (ƒC) C013 C014 Figure 10. Current-Limit vs Temperature Figure 11. Load Transient 10-µF Ceramic Output Capacitor Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS7A19 7 TPS7A19 SBVS256A – MAY 2016 – REVISED SEPTEMBER 2016 www.ti.com 7 Detailed Description 7.1 Overview The TPS7A19 is a low-dropout linear regulator (LDO) combined with enable and power good functions. The power good pin initializes when the output voltage, VOUT, exceeds VT(PG). The power good delay is a function of the value set by an external capacitor on the DELAY pin before releasing the PG pin high. 7.2 Functional Block Diagram IN OUT UVLO Pass Device Thermal Shutdown Current Limit Enable Error Amp FB EN PG Power Good Control DELAY Copyright © 2016, Texas Instruments Incorporated 7.3 Feature Description 7.3.1 Enable Pin (EN) The enable pin is a high-voltage-tolerant pin. A logic-high input on EN actives the device and turns on the LDO. For self-bias applications, connect this input to the IN pin. 7.3.2 Regulated Output Pin (OUT) The OUT pin is the regulated output based on the required voltage. The output is protected by internal current limiting. During initial power up, the LDO has a soft start feature incorporated to control the initial current through the pass element. In the event that the LDO drops out of regulation, the output tracks the input minus a voltage drop based on the load current. When the input voltage drops below the UVLO threshold, the LDO shuts down until the input voltage exceeds the minimum start-up level. 7.3.3 Power-Good Pin (PG) The power good pin is an output with an external pullup resistor to the regulated supply. The output remains low until the regulated VOUT exceeds approximately 91.6% of the set value, and the power good delay has expired. The regulated output falling below the 89.6% level asserts this output low after a short deglitch time of approximately 180 µs (typical). 8 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS7A19 TPS7A19 www.ti.com SBVS256A – MAY 2016 – REVISED SEPTEMBER 2016 Feature Description (continued) 7.3.4 Delay Timer Pin (DELAY) An external capacitor on the DELAY pin sets the timer delay before the PG pin is asserted high. The constant output current charges an external capacitor until the voltage exceeds a threshold that trips an internal comparator. If this pin is open, the default delay time is 325 µs (typical). The pulse delay time, tPG_DLY, is defined with the charge time of an external capacitor DELAY, as shown in Equation 1. § CDELAY u 1 V · ¨ ¸ 9.5 $ © ¹ tPG _DLY 325 V (1) The PG pin initializes when VOUT exceeds 91.6% of the programmed value. The delay is a function of the value set by an external capacitor on the DELAY pin before the PG pin is released high. VIN t < tPG(HL) VT(PG) VT(PG) ±Vhys VOUT VT(PG_DLY) VT(PG_DLY) VDELAY tPG_DLY tPG_DLY tPG(HL) tPG(HL) VPG Figure 12. Conditions to Activate PG 7.3.5 Adjustable Output Voltage (ADJ for TPS7A1901) An output voltage between 1.5 V and 18 V can be selected by using the external resistor dividers. Use Equation 2 to calculate the output voltage, where VFB = 1.233 V. In order to avoid a large leakage current and to prevent a divider error, the value of (R1 + R2) must between 10 kΩ and 100 kΩ. R1 · § VOUT VFB u ¨ 1 ¸ R2 © ¹ (2) 7.3.6 Undervoltage Shutdown The TPS7A19 family of devices has an internally-fixed, undervoltage-shutdown threshold. Undervoltage shutdown activates when the input voltage on VIN drops below VIN_UVLO. This activation makes sure that the regulator is not latched in an unknown state when there is a low-input supply voltage. If the input voltage has a negative transient that drops below the UVLO threshold and recovers, the regulator shuts down and powers up, similar to a typical power-up sequence when the input voltage exceeds the required levels. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS7A19 9 TPS7A19 SBVS256A – MAY 2016 – REVISED SEPTEMBER 2016 www.ti.com Feature Description (continued) 7.3.7 Thermal Shutdown The TPS7A19 incorporates a thermal shutdown (TSD) circuit as protection from overheating. For continuous standard operation, the junction temperature must not exceed the TSD trip point. If the junction temperature exceeds the TSD trip point, the output turns off. When the junction temperature falls below the TSD trip point minus the TSD hysteresis value, the output turns on again. Thermal protection disables the output when the junction temperature rises to approximately 175°C, and allows the device to cool. When the junction temperature cools to approximately 150°C, the output circuitry enables. Based on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may cycle on and off. This cycling limits the temperature of the regulator, and protects the device from damage as a result of overheating. Although the internal protection circuitry of the TPS7A19 device is designed to protect against overload conditions, the circuitry is not intended to replace proper heat-sink methods. Continuously running the TPS7A19 device into thermal shutdown degrades device reliability. 7.4 Device Functional Modes 7.4.1 Operation With VIN < 4 V The devices operate with input voltages above 4 V. The devices do not operate at input voltages below the actual UVLO voltage. 7.4.2 Operation With EN Control The enable rising edge threshold voltage is 1.7 V, maximum. When the EN pin is held above 1.7 V, and the input voltage is greater than the UVLO rising voltage, the device enables. The enable falling edge is 0.4 V, minimum. When the EN pin is held below 0.4 V, the device is disabled. The quiescent current is reduced in this state. 10 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS7A19 TPS7A19 www.ti.com SBVS256A – MAY 2016 – REVISED SEPTEMBER 2016 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information Figure 13 shows a typical application circuit for the TPS7A1901. Based on the end-application, different values of external components can be used. Some applications may require a larger output capacitor during fast load steps in order to prevent a PG low from occurring. Use a low-ESR ceramic capacitor with a dielectric of type X5R or X7R for better load transient response. 8.2 Typical Application VPG PG IN VIN VOUT OUT EN TPS7A19 R1 CIN FB DELAY GND COUT R2 CDELAY Copyright © 2016, Texas Instruments Incorporated Figure 13. Adjustable Operation 8.2.1 Design Requirements For this design example, use the parameters listed in Table 1. Table 1. Design Parameters DESIGN PARAMETER EXAMPLE VALUE Input voltage 12 V, ±10% Output voltage 3.3 V Output current 50 mA (max) PG delay time 1 ms 8.2.2 Detailed Design Procedure To begin the design process: 1. First, make sure that the combination of maximum current, maximum ambient temperature, maximum input voltage, and minimum output voltage does not exceed the maximum operating condition of TJ = 125°C. The Power Dissipation and Thermal Considerations section describes how to calculate the maximum ambient temperature and power dissipation. 2. Next, set the feedback resistors to give the desired output voltage. See Equation 2 for the VOUT relationship to R1 and R2. A good nominal value for R2 is 10 kΩ. 3. Then, calculate the required CDELAY capacitor to achieve the desired PG delay time using Equation 1. For 1 ms of delay, the nearest standard value capacitor is 10 nF. 4. Finally, select an output capacitor with a total effective capacitance between 22 µF and 500 µF, a sufficient voltage rating, and an ESR below 20 Ω. Higher capacitance gives improved transient response, but results in higher inrush current at startup. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS7A19 11 TPS7A19 SBVS256A – MAY 2016 – REVISED SEPTEMBER 2016 www.ti.com 8.2.2.1 Power Dissipation and Thermal Considerations Device power dissipation is calculated with Equation 3. PD IOUT u VIN VOUT IQ u VIN where • • • • PD = continuous power dissipation IOUT = output current VIN = input voltage VOUT = output voltage (3) As IQ « IOUT, the term IQ × VIN in Equation 3 can be ignored. For a device under operation at a given ambient air temperature (TA), calculate the junction temperature (TJ) with Equation 4. TJ = TA + (qJA ´ PD ) where • θJA = junction-to-ambient air thermal impedance (4) A rise in junction temperature because of power dissipation can be calculated with Equation 5. DT = TJ - TA = (qJA ´ PD ) (5) For a given maximum junction temperature (TJM), the maximum ambient air temperature (TAM) at which the device can operate is calculated with Equation 6. TAM = TJM - (qJA ´ PD ) (6) 8.2.3 Application Curves VIN (10 V/div) VIN (5 V/div) VEN (10 V/div) VOUT (1 V/div) VEN (5 V/div) VPG (2 V/div) VOUT (1 V/div) VPG (2 V/div) Time (1ms/div) Time (1ms/div) VIN = 12 V, VEN step from 0 V to 12 V, CIN = 10 µF, COUT = 22 µF, RLOAD = 66 Ω VIN = 12 V, VEN step from 12 V to 0 V, CIN = 10 µF, COUT = 22 µF, RLOAD = 66 Ω Figure 14. Enable Startup 12 Figure 15. Enable Shutdown Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS7A19 TPS7A19 www.ti.com SBVS256A – MAY 2016 – REVISED SEPTEMBER 2016 9 Power Supply Recommendations The device operates from an input voltage supply range between 4 V and 40 V. This input supply must be well regulated. If the input supply is located more than a few inches from the TPS7A19 device, add an electrolytic capacitor with a value of 47 µF and a ceramic bypass capacitor at the input. 10 Layout 10.1 Layout Guidelines • • • • To improve ac performance such as PSRR, output noise, and transient response, design the board with separate ground planes for VIN and VOUT, with each ground plane connected only at the GND pin of the device. In addition, connect the ground connection for the output capacitor directly to the GND pin of the device. Minimize equivalent series inductance (ESL) and equivalent series resistance (ESR) in order to maximize performance and stability. Place every capacitor as close to the device as possible, and on the same side of the PCB as the regulator. Do not place any of the capacitors on the opposite side of the PCB from where the regulator is installed. The use of vias and long traces are strongly discouraged because of the negative impact on system performance. Vias and long traces can also cause instability. If possible, and to maximize the performance listed in this data sheet, use the same layout pattern used for the TPS7A19 evaluation module, TPS7A1901EVM-760 (SBVU031). 10.2 Layout Example Input Ground Plane VOUT CDELAY CIN COUT DELAY 1 OUT 2 FB 3 GND 4 8 PG Thermal 7 IN Pad 6 EN 5 GND R1 Sense Line R2 VIN Output Ground Plane Notes: CIN and COUT are 1208 packages CDELAY, R1, and R2 are 0402 packages Denotes a via to a connection made on another layer Figure 16. TPS7A19 Layout Example Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS7A19 13 TPS7A19 SBVS256A – MAY 2016 – REVISED SEPTEMBER 2016 www.ti.com 11 Device and Documentation Support 11.1 Device Support 11.1.1 Development Support 11.1.1.1 Evaluation Modules An evaluation module (EVM) is available to assist in the initial circuit performance evaluation using the TPS7A19. The summary information for this fixture is shown in Table 2. Table 2. Evaluation Modules NAME EVM FOLDER TPS7A19 40-V, 450-mA, High-Voltage, Ultra-Low IQ Low-Dropout Regulator Evaluation Module TPS7A1901EVM-760 11.1.1.2 Spice Models Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of analog circuits and systems. A SPICE model for the TPS7A19 is available through the TPS7A19 product folder under the tools and software tab. 11.1.2 Device Nomenclature Table 3. Ordering Information (1) PRODUCT TPS7A19XXYYYZ (1) DESCRIPTION XX is the nominal output voltage option; 01 for adjustable. YYY is the package designator. Z is the package quantity. For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the device product folder at www.ti.com. 11.2 Documentation Support 11.2.1 Related Documentation TPS7A1901EVM-760 Evaluation Module User's Guide (SBVU031) 11.3 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 11.4 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.5 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 14 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS7A19 TPS7A19 www.ti.com SBVS256A – MAY 2016 – REVISED SEPTEMBER 2016 11.6 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 11.7 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS7A19 15 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TPS7A1901DRBR ACTIVE SON DRB 8 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 A1901 TPS7A1901DRBT ACTIVE SON DRB 8 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 A1901 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of