TPS7A21
SBVS398A – DECEMBER 2021 – REVISED SEPTEMBER 2022
TPS7A21 500-mA, Low-Noise, Low-IQ, High-PSRR LDO
1 Features
3 Description
•
•
•
•
•
•
The TPS7A21 is an ultra-small, low-dropout (LDO)
linear voltage regulator that can source 500 mA
of output current. The device provides low noise,
high PSRR, and excellent load and line transient
performance to meet the requirements of RF and
other sensitive analog circuits. Innovative design
techniques result in low-noise performance without
the addition of an external noise bypass capacitor.
With the device low quiescent current, the TPS7A21
is a good choice for battery-powered systems. The
2.0-V to 6.0-V input voltage range and 0.8-V to
5.5-V output voltage range support a variety of
system requirements. The internal precision reference
circuit enables excellent accuracy; the maximum
output voltage tolerance is 1.5% over load, line, and
temperature variations.
•
•
•
•
•
Very low IQ: 6.5 μA
Input voltage range: 2.0 V to 6.0 V
Output voltage range: 0.8 V to 5.5 V (50-mV steps)
High PSRR: 91 dB at 1 kHz
Low output voltage noise: 7.7 μVRMS
Low dropout:
– 175 mV (maximum) at 500 mA (2.5-V VOUT)
Smart EN pulldown
Output voltage tolerance:
– ±1.5% (line, load, and temperature)
Supports wide range of ceramic capacitors:
– 1 µF to 200 µF
Operating junction temperature: –40°C to +125°C
Package:
– 0.602-mm × 0.602-mm power DSBGA
2 Applications
•
•
•
•
•
•
•
Mobile phones and tablets
Wearables
IP cameras
Portable medical equipment
Smart meters and field transmitters
RF, PLL, VCO, and clock power supplies
Motor drives
An internal soft-start circuit helps control the inrush
current, thus minimizing the input voltage drop during
start up. The LDO is stable with small ceramic
capacitors, allowing for a small overall solution size.
A smart enable input circuit with an internally
controlled pulldown resistor keeps the LDO disabled
even when the EN pin is unconnected and helps
eliminate external components that are otherwise
required to pull down the EN input.
Package Information(1)
PART NUMBER
TPS7A21
(1)
PACKAGE
BODY SIZE (NOM)
YWD (DSBGA, 4)
0.602 mm × 0.602 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS7A21
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SBVS398A – DECEMBER 2021 – REVISED SEPTEMBER 2022
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................5
6.6 Typical Characteristics................................................ 7
7 Detailed Description......................................................14
7.1 Overview................................................................... 14
7.2 Functional Block Diagram......................................... 14
7.3 Feature Description...................................................15
7.4 Device Functional Modes..........................................17
8 Applications and Implementation................................ 18
8.1 Application Information............................................. 18
8.2 Typical Application.................................................... 21
8.3 Power Supply Recommendations.............................23
8.4 Layout....................................................................... 23
9 Device and Documentation Support............................25
9.1 Device Support......................................................... 25
9.2 Documentation Support............................................ 25
9.3 Receiving Notification of Documentation Updates....25
9.4 Support Resources................................................... 25
9.5 Trademarks............................................................... 25
9.6 Electrostatic Discharge Caution................................25
9.7 Glossary....................................................................25
10 Mechanical, Packaging, and Orderable
Information.................................................................... 25
10.1 Mechanical Data..................................................... 26
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (December 2021) to Revision A (September 2022)
Page
• Added line, load, and temperature to Output voltage tolerance bullet in Features section................................ 1
• Changed Supports wide range of ceramic capacitors bullet in Features section............................................... 1
• Changed Applications section............................................................................................................................ 1
• Changed description of OUT pin in Pin Functions: DSBGA table...................................................................... 3
• Changed typical short-circuit current limit from 300 mA to 325 mA....................................................................5
• Changed typical value of smart enable pulldown resistor from 450 kΩ to 440 kΩ............................................. 5
• Changed Output Voltage Accuracy vs IOUT and IQ vs VIN figures in Typical Characteristics section..................7
• Deleted second IGND vs IOUT figure from Typical Characteristics section........................................................... 7
• Added discussion regarding sources with limited current drive capability to Smart Enable (EN) section........ 15
• Added discussion that input voltage must be high enough to enable the active discharge to Active Discharge
section.............................................................................................................................................................. 15
• Added last sentence to Dropout Operation section.......................................................................................... 17
• Changed Input voltage and Output current parameters in Design Parameters table....................................... 21
• Changed Detailed Design Procedure section...................................................................................................22
• Added Device Nomenclature section................................................................................................................25
2
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5 Pin Configuration and Functions
1
2
A
IN
OUT
B
EN
GND
TOP VIEW
1
2
B
EN
GND
A
IN
OUT
BOTTOM VIEW
Figure 5-1. YWD Package, 4-Pin DSBGA
Table 5-1. Pin Functions: DSBGA
PIN
DSBGA
NAME
I/O
DESCRIPTION
A1
IN
I
Input voltage supply. For best transient response and to minimize input impedance, use the
recommended value or larger capacitor from IN to GND, as listed in the Recommended
Operating Conditions table. Place the input capacitor as close to the IN and GND pins of the
device as possible.
A2
OUT
O
Regulated output voltage. Connect a low-equivalent series resistance (ESR) capacitor
to this pin. For best transient response, use the nominal recommended value or larger
capacitor from OUT to GND. An internal 150-Ω (typical) pulldown resistor prevents a charge
from remaining on OUT when the regulator is in shutdown mode (VEN< VEN(LOW)).
Enable input. A low voltage (VEN < VEN(LOW)) on this pin turns the regulator off and
discharges the output pin to GND through an internal 150-Ω pulldown resistor. A high
voltage (VEN > VEN(HI)) on this pin enables the regulator output. This pin has an internal
450-kΩ pulldown resistor to hold the regulator off by default. When VEN > VEN(HI), the
450-kΩ pulldown resistor is disconnected to reduce input current.
B1
EN
I
B2
GND
—
Common ground.
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6 Specifications
6.1 Absolute Maximum Ratings
ratings apply over operating free-air temperature range (unless otherwise noted)(1) (3)
VIN
Input voltage
MIN
MAX
–0.3
6.5
UNIT
V
V
VOUT
Output voltage
–0.3
See(2)
VEN
Enable input voltage
–0.3
6.5
V
Maximum output current(4)
Internally limited
A
TJ
Operating junction temperature
-40
150
°C
Tstg
Storage temperature
–65
150
°C
(1)
(2)
(3)
(4)
Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute maximum ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If briefly operating outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not
sustain damage, but it may not be fully functional. Operating the device in this manner may affect device reliability, functionality,
performance, and shorten the device lifetime.
Absolute maximum VOUT is the lesser of VIN + 0.3 V, or 6.5 V.
All voltages are with respect to the GND pin.
Internal thermal shutdown circuitry helps protect the device from permanent damage.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
±750
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
conditions apply over the operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
Input supply voltage
2.0
6.0
V
VEN
Enable input voltage
0
6.0
V
VOUT
Nominal output voltage range
0.8
5.5
V
IOUT
Output current
500
mA
CIN
Input capacitor(2)
COUT
Output capacitor(3)
ESR
Output capacitor effective series resistance
TJ
Operating junction temperature
(1)
(2)
(3)
4
NOM
VIN
0
1
1
–40
µF
200
µF
100
mΩ
125
°C
All voltages are with respect to the GND pin.
An input capacitor is not required for LDO stability. However, an input capacitor with an effective value of 0.47 μF minimum
is recommended to counteract the effect of source resistance and inductance, which may in some cases cause symptoms of
system-level instability such as ringing or oscillation, especially in the presence of load transients.
Effective output capacitance of 0.4 μF minimum and 200 μF maximum over all temperature and voltage conditions is required for
stability with ESR values as high as 100 mΩ. If the ESR is reduced to 20 mΩ or lower, stable operation can be achieved with effective
output capacitance as low as 0.3 μF.
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6.4 Thermal Information
TPS7A21
YWD
(DSBGA)
THERMAL METRIC(1)
UNIT
4 PINS
RθJA
Junction-to-ambient thermal resistance
197.1
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
2.9
°C/W
RθJB
Junction-to-board thermal resistance
52.4
°C/W
ψJT
Junction-to-top characterization parameter
1.5
°C/W
ψJB
Junction-to-board characterization parameter
52.4
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and ICPackage Thermal Metrics and An
empirical analysis of the impact of board layout on LDO thermal performance application notes.
6.5 Electrical Characteristics
specified over operating temperature range (TJ = –40℃ to +125℃), VIN = VOUT(NOM) + 0.3 V or 2 V, whichever is greater, VEN
= 1.0 V, IOUT = 1 mA, CIN = 1 µF, COUT = 1 µF (unless otherwise noted); all typical values are at TJ = 25℃
PARAMETER
ΔVOUT
Output voltage tolerance
TEST CONDITIONS
MIN
%
VIN = (VOUT(NOM) + 0.3 V) to 6.0 V,
IOUT = 1 mA to 500 mA,
VOUT < 1.85 V
–30
30
mV
VIN = (VOUT(NOM) + 0.3 V) to 6.0 V,
IOUT = 1 mA
ΔVOUT
Load regulation
IOUT = 1 mA to 500 mA
0.03
Shutdown current
IQ(DO)
Quiescent current in dropout
VDO
Dropout voltage
6.5
VEN = VIN, VIN = 6.0 V,
TJ = –40°C to 85°C
IOUT = 0 mA
TJ = –40°C to 125°C
%/mA
9
11
15
VEN = VIN, VIN = 6.0 V, IOUT = 500 mA
2900
3500
VEN = 0 V (disabled), VIN = 6.0 V, TJ = 25°C
0.15
1
VEN = 0 V (disabled), VIN = 6.0 V, TJ = –40°C to 125°C
4
VIN ≤ VOUT(NOM), IOUT = 0 mA
IOUT = 500 mA,
VOUT = 95% ×
VOUT(NOM)
7
Output current limit
VOUT = 0.9 × VOUT(NOM)
ISC
Short-circuit current limit
VOUT = 0V
IOUT = 20 mA,
VIN = VOUT + 1.0 V
Power-supply rejection ratio
IOUT = 500 mA,
VIN = VOUT + 1.0 V
15
0.8 V ≤ VOUT < 1.0 V (1)
750
1.0 V ≤ VOUT < 1.2 V (1)
530
(1)
395
1.2 V ≤ VOUT < 1.5 V
1.5 V ≤ VOUT < 2.5 V
µA
µA
µA
mV
260
2.5 V ≤ VOUT ≤ 5.5 V
ICL
PSRR
%/V
0.001
TJ = 25°C
ISHTDWN
UNIT
1.5
Line regulation
Quiescent current
MAX
–1.5
ΔVOUT
IGND
TYP
VIN = (VOUT(NOM) + 0.3 V) to 6.0 V,
IOUT = 1 mA to 500 mA,
VOUT ≥ 1.85 V
175
740
1060
325
f = 100 Hz
90
f = 1 kHz
91
f = 10 kHz
71
f = 100 kHz
61
f = 1 MHz
50
f = 100 Hz
65
f = 1 kHz
85
f = 10 kHz
79
f = 100 kHz
44
f = 1 MHz
50
1500
mA
mA
dB
dB
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6.5 Electrical Characteristics (continued)
specified over operating temperature range (TJ = –40℃ to +125℃), VIN = VOUT(NOM) + 0.3 V or 2 V, whichever is greater, VEN
= 1.0 V, IOUT = 1 mA, CIN = 1 µF, COUT = 1 µF (unless otherwise noted); all typical values are at TJ = 25℃
PARAMETER
MIN
TYP
VN
Output noise voltage
BW = 10 Hz to
100 kHz,
VOUT = 2.8 V
RPULLDOWN
Output automatic discharge
pulldown resistance
VIN = 2 V, VEN < VIL (output disabled)
150
Thermal shutdown rising
TJ rising
165
Thermal shutdown falling
TJ falling
140
VEN(LOW)
Low input threshold
VIN = 2.0 V to 6.0 V,
VEN falling until the output is disabled
VEN(HI)
High input threshold
VIN = 2.0 V to 6.0 V,
VEN rising until the output is enabled
VUVLO
UVLO threshold
VUVLO(HYST)
UVLO hysteresis
IEN
EN pin leakage current
REN(PULL-
Smart enable pulldown resistor
TSD
DOWN)
tON
(1)
6
TEST CONDITIONS
Turnon time
IOUT = 500 mA
7.7
IOUT = 1 mA
10
MAX
µVRMS
Ω
°C
0.3
0.9
1.11
1.32
1.63
VIN falling
1.05
1.27
1.57
50
100
120
200
V
mV
250
440
From VEN > VIH to VOUT = 95% of VOUT(NOM)
V
V
VIN rising
VEN = 6.0 V and VIN = 6.0 V
UNIT
nA
kΩ
280
µs
Dropout voltages for VOUT values below or very near the UVLO threshold cannot be measured directly. Values shown are verified by
simulation.
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6.6 Typical Characteristics
VIN = 3.6 V, VOUT = 3.3 V, IOUT = 1 mA, CIN = 1 µF, COUT = 1 µF, and TA = 25°C (unless otherwise noted)
VEN = 1 V
VEN = 1 V
Figure 6-2. Output Voltage Accuracy vs IOUT
Figure 6-1. Output Voltage Accuracy vs IOUT
VEN = 1 V
VEN = 1 V
Figure 6-3. Output Voltage Accuracy vs VIN
Figure 6-4. Line Regulation vs VIN
160
TJ
-55 °C
-40 °C
0 °C
25 °C
10
8
150
85 °C
125 °C
150 °C
-55°C
-40°C
140
Dropout Voltage (mV)
Change in Output Voltage (mV)
12
6
4
0°C
25°C
TJ
85°C
125°C
150°C
130
120
110
100
90
80
70
2
60
50
0
0
50
100
150
200 250 300 350
Output Current (mA)
400
450
500
0
50
Load
100
150
200 250 300 350
Output Current (mA)
400
450
500
VEN = 1 V
VEN = 1 V
Figure 6-5. Load Regulation vs IOUT
Figure 6-6. Dropout Voltage vs IOUT
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6.6 Typical Characteristics (continued)
VIN = 3.6 V, VOUT = 3.3 V, IOUT = 1 mA, CIN = 1 µF, COUT = 1 µF, and TA = 25°C (unless otherwise noted)
85
-55°C
-40°C
Dropout Voltage (mV)
80
0°C
25°C
TJ
85°C
125°C
150°C
75
70
65
60
55
0
0.2
0.4
0.6
0.8
1
1.2 1.4
Output Current (mA)
1.6
1.8
2
VEN = 1 V
VEN = VIN
Figure 6-7. Dropout Voltage vs IOUT
Figure 6-8. IQ vs VIN
VEN = 1 V
VEN = 1 V
Figure 6-10. IGND vs IOUT
Figure 6-9. IQ vs VIN
Quiescent Current in Shutdown (nA)
70
Figure 6-11. IGND vs IOUT
8
0°C
25°C
50
40
30
20
10
0
-10
1.8
VEN = 1 V
TJ
-40°C
-55°C
60
2.4
3
3.6
4.2
Input Voltage (V)
4.8
5.4
6
VEN = 0 V, IOUT = 0 mA
Figure 6-12. Shutdown Current vs VIN
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6.6 Typical Characteristics (continued)
VIN = 3.6 V, VOUT = 3.3 V, IOUT = 1 mA, CIN = 1 µF, COUT = 1 µF, and TA = 25°C (unless otherwise noted)
5
TJ
125°C
85°C
4.5
150°C
2500
-55°C
-40°C
4
Output Voltage (V)
Quiescent Current in Shutdown (nA)
3000
2000
1500
1000
0°C
25°C
TJ
85°C
125°C
150°C
3.5
3
2.5
2
1.5
500
1
0.5
0
1.8
2.4
3
3.6
4.2
Input Voltage (V)
4.8
5.4
0
6
0
200
400
VEN = 0 V, IOUT = 0 mA
600
800
1000
Output Current (mA)
1200
1400
VEN = 1 V
Figure 6-13. Shutdown Current vs VIN
Figure 6-14. Foldback Current Limit
Enable Pin Leakage Current (nA)
5000
4500
4000
3500
3000
2500
2000
1500
1000
-55°C
-40°C
0°C
500
TJ
25°C
85°C
125°C
150°C
0
0
0.5
1
1.5
2
2.5 3 3.5
VEN - VIN (V)
4
4.5
5
5.5
6
VEN = 6 V, IOUT = 0 mA
Figure 6-15. Enable Logic Threshold vs Temperature
Figure 6-16. Enable Pin Leakage Current vs VEN – VIN
VEN = 0.3 V
VEN = 0.3 V
Figure 6-17. Smart Enable Pulldown Resistor vs Temperature
and VIN
Figure 6-18. Output Pulldown Resistance vs
Temperature and VIN
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6.6 Typical Characteristics (continued)
VIN = 3.6 V, VOUT = 3.3 V, IOUT = 1 mA, CIN = 1 µF, COUT = 1 µF, and TA = 25°C (unless otherwise noted)
VEN = 1 V
VIN = 0 V to 4.3 V, slew rate = 1 V/μs, IOUT = 500 mA
Figure 6-19. VIN UVLO Threshold vs Temperature
VIN = 0 V to 4.3 V, slew rate = 1 V/μs, IOUT = 0 mA
Figure 6-21. Start-Up With VEN After VIN
VIN = 0 V to 4.3 V, slew rate = 1 V/μs, IOUT = 500 mA
Figure 6-20. Start-Up With VEN Before VIN
VIN = 0 V to 4.3 V, slew rate = 1 V/μs, IOUT = 500 mA
Figure 6-22. Start-Up With VEN After VIN
VIN = 4.3 V, VEN = 0 V to 4.3 V, slew rate = 1 V/μs,
IOUT = 0 mA, COUT = 1 μF
Figure 6-24. Start-Up Inrush Current
Figure 6-23. Start-Up With VEN = VIN
10
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6.6 Typical Characteristics (continued)
VIN = 3.6 V, VOUT = 3.3 V, IOUT = 1 mA, CIN = 1 µF, COUT = 1 µF, and TA = 25°C (unless otherwise noted)
VIN = 4.3 V, VEN = 0 V to 4.3 V, slew rate = 1 V/μs,
IOUT = 0 mA, COUT = 10 μF
VEN = VEN(HI) to VOUT = 95% of VOUT(NOM), IOUT = 0 mA
Figure 6-26. Start-Up Turn-On Time vs Temperature
5
6
4
5
4
5
3
4
3
4
2
3
2
3
1
2
1
2
0
1
0
1
-1
0
-1
0
-2
-1
VOUT
VIN
-3
0
10
20
30
40
50
60
Time (µs)
70
80
90
AC-Coupled Output Voltage (mV)
6
-2
100
-2
-3
10
VEN = VIN, tr = tf = 5 μs, IOUT = 500 mA
20
30
40
50
60
Time (µs)
70
80
90
-2
100
VEN = VIN, tr = tf = 5 μs, IOUT = 1 mA
Figure 6-27. Line Transient From 3.6 V to 4.6 V
Figure 6-28. Line Transient From 3.6 V to 4.6 V
750
320
500
90
500
240
250
60
250
160
0
30
-250
0
-500
-30
-750
-60
-1000
-1250
0
20
40
IOUT -90
VOUT
-120
58
Output Current (mA)
120
0
80
-250
0
-500
-80
-750
-160
-1000
IOUT -240
VOUT
-320
75 90 105 120 135 150 165 180
Time (µs)
-1250
0
15
Time (µs)
VEN = VIN, tr = tf = 1 μs
30
45
60
AC-Coupled Output Voltage (mV)
750
AC-Coupled Output Voltage (mV)
Output Current (mA)
-1
VOUT
VIN
0
Input Voltage (V)
5
Input Voltage (V)
AC-Coupled Output Voltage (mV)
Figure 6-25. Start-Up Inrush Current
VEN = VIN, tr = tf = 200 ns
Figure 6-29. Load Transient From 1 mA to 500 mA
Figure 6-30. Load Transient From 1 mA to 500 mA
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6.6 Typical Characteristics (continued)
750
320
500
90
500
240
250
60
250
160
0
30
-250
0
-500
-30
-750
-60
-1000
-1250
0
20
40
IOUT -90
VOUT
-120
58
Output Current (mA)
120
0
80
-250
0
-500
-80
-750
-160
-1000
IOUT -240
VOUT
-320
80 100 120 140 160 180 200
Time (µs)
-1250
0
20
Time (µs)
VEN = VIN, tr = tf = 1 μs
60
VEN = VIN, tr = tf = 200 ns
Figure 6-31. Load Transient From 0 mA to 500 mA
Figure 6-32. Load Transient From 0 mA to 500 mA
VEN = VIN
VEN = VIN, IOUT = 20 mA
Figure 6-33. PSRR vs Frequency and IOUT
Figure 6-34. PSRR vs Frequency and VIN
VEN = VIN, IOUT = 500 mA
VEN = VIN, IOUT = 20 mA
Figure 6-35. PSRR vs Frequency and VIN
12
40
AC-Coupled Output Voltage (mV)
750
AC-Coupled Output Voltage (mV)
Output Current (mA)
VIN = 3.6 V, VOUT = 3.3 V, IOUT = 1 mA, CIN = 1 µF, COUT = 1 µF, and TA = 25°C (unless otherwise noted)
Figure 6-36. PSRR vs Frequency and COUT
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6.6 Typical Characteristics (continued)
VIN = 3.6 V, VOUT = 3.3 V, IOUT = 1 mA, CIN = 1 µF, COUT = 1 µF, and TA = 25°C (unless otherwise noted)
2
VIN
3.6 V, RMS Noise = 6.73 V RMS
4.75 V, RMS Noise = 6.70 V RMS
6.0 V, RMS Noise = 6.65 V RMS
Output Voltage Noise ( V Hz)
1
0.5
0.2
0.1
0.05
0.02
0.01
0.005
0.002
0.001
10
100
1k
10k
100k
Frequency (Hz)
1M
10M
VEN = VIN, IOUT = 20 mA
VEN = VIN, IOUT = 500 mA
Figure 6-38. Noise vs Frequency and VIN
Figure 6-37. PSRR vs Frequency and COUT
5
VIN
3.6 V, RMS Noise = 6.90 V RMS
4.75 V, RMS Noise = 7.32 V RMS
6.0 V, RMS Noise = 11.54 V RMS
Output Voltage Noise ( V Hz)
2
1
0.5
0.2
0.1
0.05
0.02
0.01
0.005
0.002
0.001
10
100
1k
10k
100k
Frequency (Hz)
1M
10M
VEN = VIN, IOUT = 500 mA
VEN = VIN
Figure 6-39. Noise vs Frequency and VIN
Figure 6-40. Noise vs Frequency and IOUT
1
COUT
0.47 µF, RMS Noise = 6.63 V RMS
1.0 µF, RMS Noise = 6.71 V RMS
10 µF, RMS Noise = 7.20 V RMS
200 uF, RMS Noise = 7.69 V RMS
0.1
0.05
0.03
0.02
0.01
0.005
0.003
0.002
0.001
10
100
1k
10k
100k
Frequency (Hz)
1M
10M
Output voltage Noise ( V Hz)
Output voltage Noise ( V Hz)
1
0.5
0.3
0.2
COUT
0.47 µF, RMS Noise = 6.84 V RMS
1.0 µF, RMS Noise = 6.96 V RMS
10 µF, RMS Noise = 7.16 V RMS
200 uF, RMS Noise = 8.74 V RMS
0.5
0.3
0.2
0.1
0.05
0.03
0.02
0.01
0.005
0.003
0.002
0.001
10
VEN = VIN, IOUT = 20 mA
100
1k
10k
100k
Frequency (Hz)
1M
10M
VEN = VIN, IOUT = 500 mA
Figure 6-41. Noise vs Frequency and COUT
Figure 6-42. Noise vs Frequency and COUT
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7 Detailed Description
7.1 Overview
Designed to meet the needs of sensitive RF and analog circuits, the TPS7A21 provides low noise, high PSRR,
and low quiescent current, as well as excellent line and load transient response. The TPS7A21 achieves
excellent noise performance without the need for a separate noise filter capacitor.
The TPS7A21 is designed to operate properly with a single 1-µF input capacitor and a single 1-µF ceramic
output capacitor. The effective output capacitance must be at least 0.4 µF across all operating voltage and
temperature conditions.
7.2 Functional Block Diagram
14
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7.3 Feature Description
7.3.1 Smart Enable (EN)
The enable pin (EN) is active high. The output is enabled when the voltage applied to EN is greater than VEN(HI)
and disabled when the applied voltage is less than VEN(LOW). If external control of the output voltage is not
needed, connect EN to IN. This device has a smart enable circuit to reduce quiescent current. When the voltage
on the enable pin is driven above VEN(HI), the output is enabled and the smart enable internal pulldown resistor
(REN(PULLDOWN)) is disconnected. When the enable pin is floating, the REN(PULLDOWN) is connected and pulls the
enable pin low to disable the output. In addition to reducing quiescent current, the smart pulldown helps ensure
that the logic level is correct even when EN is driven from a source that has limited current drive capability. The
REN(PULLDOWN) value is listed in the Electrical Characteristics table.
7.3.2 Low Output Noise
Any internal noise at the TPS7A21 reference voltage is reduced by a first-order, low-pass RC filter before being
passed to the output buffer stage. The low-pass RC filter has a –3-dB cutoff frequency of approximately 0.1 Hz.
During start-up, the filter resistor is bypassed to reduce output rise time. The filter begins normal operation after
the output voltage reaches the nominal value.
7.3.3 Active Discharge
The regulator has an internal metal-oxide-semiconductor field-effect transistor (MOSFET) that connects a
pulldown resistor between the output and ground pins when the device is disabled to actively discharge the
output voltage. The voltage on IN must be high enough to turn on the pulldown MOSFET; when VIN is too low to
provide sufficient VGS on the pulldown MOSFET, the pulldown circuit is not active. The active discharge circuit is
activated by the enable pin, or by the voltage on IN falling below the undervoltage lockout (UVLO) threshold.
Do not rely on the active discharge circuit for discharging a large amount of output capacitance after the input
supply has collapsed because reverse current can possibly flow from the output to the input. This reverse current
flow can cause damage to the device. Limit reverse current to no more than 5% of the device rated current for
only a short period of time.
7.3.4 Dropout Voltage
Dropout voltage (VDO) is defined as the input voltage minus the output voltage (VIN – VOUT) at the rated output
current (IRATED), when the pass transistor is fully on. IRATED is the maximum IOUT listed in the Recommended
Operating Conditions table. The pass transistor is in the ohmic or triode region of operation, and acts as a
switch. The dropout voltage indirectly specifies a minimum input voltage greater than the nominal programmed
output voltage at which the output voltage is expected to stay in regulation. If the input voltage falls to less than
the value required to support output regulation, then the output voltage falls as well.
For a CMOS regulator, the dropout voltage is determined by the drain-source, on-state resistance (RDS(ON)) of
the pass transistor. Therefore, if the linear regulator operates at less than the rated current, the dropout voltage
for that current scales accordingly. Equation 1 calculates the RDS(ON) of the device.
RDS(ON) =
VDO
IRATED
(1)
7.3.5 Foldback Current Limit
The TPS7A21 has an internal current limit circuit that protects the regulator during transient high-load current
faults or shorting events. The current limit is a hybrid brick-wall foldback scheme. The current limit transitions
from a brick-wall scheme to a foldback scheme at the foldback voltage (VFOLDBACK).
In a high-load current fault with the output voltage above VFOLDBACK, the brick-wall scheme limits the output
current to the current limit (ICL). When the output voltage drops below VFOLDBACK, a foldback current limit
activates that scales back the current when the output voltage approaches GND. When the output is shorted, the
device supplies a typical current called the short-circuit current limit (ISC). ICL and ISC are listed in the Electrical
Characteristics table.
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The output voltage is not regulated when the device is in current limit. When a current limit event occurs, the
regulator begins to heat up because of the increase in power dissipation. When the device is in brick-wall
current limit, the pass transistor dissipates power [(VIN – VOUT) × ICL]. When the output is shorted and the output
voltage is less than VFOLDBACK, the pass transistor dissipates power [(VIN – VOUT) × ISC]. If thermal shutdown
is triggered, the device turns off. After the device cools down, the internal thermal shutdown circuit turns the
device back on. If the output current fault condition persists, the device cycles between current limit and thermal
shutdown. For more information on current limits, see the Know Your Limits application note.
Figure 7-1 shows a diagram of the foldback current limit.
VOUT
Brickwall
VOUT(NOM)
VFOLDBACK
Foldback
IOUT
0V
0 mA
IRATED
ISC
ICL
Figure 7-1. Foldback Current Limit
7.3.6 Undervoltage Lockout
An independent undervoltage lockout (UVLO) circuit monitors the input voltage, allowing a controlled and
consistent turn on and turn off of the output voltage. If the input voltage drops during load transients (when
the device output is enabled), the UVLO has built-in hysteresis to prevent unwanted turn off.
7.3.7 Thermal Overload Protection (TSD)
Thermal shutdown disables the output when the junction temperature TJ rises to the shutdown temperature
threshold TSD. The thermal shutdown circuit hysteresis requires the temperature to fall to a lower temperature
before turning on again. The thermal time constant of the semiconductor die is fairly short; thus, the device may
cycle on and off when thermal shutdown is reached until power dissipation is reduced.
Power dissipation during start up can be high from large VIN – VOUT voltage drops across the device or from
high inrush currents charging large output capacitors. Under some conditions, the thermal shutdown protection
disables the device before start up completes.
For reliable operation, limit the junction temperature to the maximum listed in the Recommended Operating
Conditions table. Operation above this maximum temperature causes the regulator to exceed operational
specifications.
Although the thermal shutdown circuitry is designed to protect against temporary thermal overload conditions,
this circuitry is not intended to replace proper thermal design. Continuously running the regulator into thermal
shutdown or above the maximum recommended junction temperature reduces long-term reliability.
16
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7.4 Device Functional Modes
7.4.1 Device Functional Mode Comparison
Table 7-1 shows the conditions that lead to the different modes of operation. See the Electrical Characteristics
table for parameter values.
Table 7-1. Device Functional Mode Comparison
PARAMETER
OPERATING MODE
VIN
VEN
IOUT
TJ
Normal operation
VIN > VOUT(nom) + VDO and VIN > VIN(min)
VEN ≥ VEN(HI)
IOUT < IOUT(max)
TJ < TSD(shutdown)
Dropout operation
VIN(min) < VIN < VOUT(nom) + VDO
VEN ≥ VEN(HI)
IOUT < IOUT(max)
TJ < TSD(shutdown)
VIN < VUVLO
VEN ≤ VEN(LOW)
Not applicable
TJ ≥ TSD(shutdown)
Disabled
(any true condition
disables the device)
7.4.2 Normal Operation
The device regulates to the nominal output voltage when the following conditions are met:
•
•
•
•
The input voltage is greater than the nominal output voltage plus the dropout voltage (VOUT(nom) + VDO)
The output current is less than the current limit (IOUT < ICL)
The device junction temperature is less than the thermal shutdown temperature (TJ < TSD)
The enable voltage has previously exceeded the enable rising threshold voltage and has not yet decreased
to less than the enable falling threshold
7.4.3 Dropout Operation
If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other
conditions are met for normal operation, the device operates in dropout mode. In this mode, the output voltage
tracks the input voltage. During this mode, the transient performance of the device becomes significantly
degraded because the pass transistor is in the ohmic or triode region, and acts as a switch. Line or load
transients in dropout can result in large output-voltage deviations.
When the device is in a steady dropout state (defined as when the device is in dropout, VIN < VOUT(NOM) + VDO,
directly after being in a normal regulation state, but not during start up), the pass transistor is driven into the
ohmic or triode region. When the input voltage returns to a value greater than or equal to the nominal output
voltage plus the dropout voltage (VOUT(NOM) + VDO), the output voltage can overshoot for a short period of time
while the device pulls the pass transistor back into the linear region.
For output currents less than about 200 mA, the slope of the dropout voltage curve is lower than for higher
currents. This slope helps maintain better performance when the LDO is in dropout.
7.4.4 Disabled
The output of the device can be shut down by forcing the voltage of the enable pin to less than VEN(LOW)).
When disabled, the pass transistor is turned off, internal circuits are shut down, and the output voltage is actively
discharged to ground by an internal discharge circuit from the output to ground.
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8 Applications and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
8.1.1 Recommended Capacitor Types
The device is designed to be stable using low equivalent series resistance (ESR) ceramic capacitors at the input
and output. Multilayer ceramic capacitors have become the industry standard for many types of applications
and are recommended, but must be used with good judgment. Ceramic capacitors that employ X7R-, X5R-,
and C0G-rated dielectric materials provide good capacitive stability across temperature, whereas the use of
Y5V-rated capacitors is discouraged because of large variations in capacitance.
Regardless of the ceramic capacitor type selected, the effective capacitance varies with operating voltage
and temperature. Consult the manufacturer data sheet to verify performance. Generally, expect the effective
capacitance to decrease by as much as 50%. The input and output capacitors recommended in the
Recommended Operating Conditions table account for an effective capacitance of approximately 50% of the
nominal value.
8.1.2 Input and Output Capacitor Requirements
Although the LDO is stable without an input capacitor, good design practice is to connect a capacitor from IN
to GND, with a value at least equal to the nominal value specified in the Recommended Operating Conditions
table. The input capacitor counteracts reactive input sources and improves transient response, input ripple,
and PSRR, and is recommended if the source impedance is greater than 0.5 Ω. When the source resistance
and inductance are sufficiently high, the overall system can be susceptible to instability (including ringing and
sustained oscillation) and other performance degradation if there is insufficient capacitance between IN and
GND. A capacitor with a value greater than the minimum may be necessary if there are large fast-rise-time load
or line transients or if the LDO is located more than a few centimeters from the input power source.
An output capacitor of an appropriate value helps ensure stability and improve dynamic performance. Use an
output capacitor within the range specified in the Recommended Operating Conditions table.
8.1.3 Load Transient Response
The load-step transient response is the output voltage response by the LDO to a step in load current, whereby
output voltage regulation is maintained. There are two key transitions during a load transient response: the
transition from a light to a heavy load and the transition from a heavy to a light load. The regions shown in Figure
8-1 are broken down as follows. Regions A, E, and H are where the output voltage is in a steady state.
tAt
tCt
B
tDt
tEt
tGt
tHt
F
Figure 8-1. Load Transient Waveform
18
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During transitions from a light load to a heavy load, the:
•
•
Initial voltage dip is a result of the depletion of the output capacitor charge and parasitic impedance to the
output capacitor (region B)
Recovery from the dip results from the LDO increasing the sourcing current, and leads to output voltage
regulation (region C)
During transitions from a heavy load to a light load, the:
•
•
Initial voltage rise results from the LDO sourcing a large current, and leads to the output capacitor charge to
increase (region F)
Recovery from the rise results from the LDO decreasing the sourcing current in combination with the load
discharging the output capacitor (region G)
A larger output capacitance reduces the peaks during a load transient but slows down the response time of the
device. A larger DC load also reduces the peaks because the amplitude of the transition is lowered and a higher
current discharge path is provided for the output capacitor.
8.1.4 Undervoltage Lockout (UVLO) Operation
The UVLO circuit verifies that the device stays disabled before the input supply reaches the minimum
operational voltage range, and makes sure that the device shuts down when the input supply collapses. Figure
8-2 shows the UVLO circuit response to various input voltage events. The diagram can be separated into the
following parts:
•
•
•
•
•
•
•
Region A: The device does not start until the input reaches the UVLO rising threshold.
Region B: Normal operation, regulating device.
Region C: Brownout event above the UVLO falling threshold (UVLO rising threshold – UVLO hysteresis). The
device remains enabled even if the output falls out of regulation.
Region D: Normal operation, regulating device.
Region E: Brownout event below the UVLO falling threshold. The device is disabled in most cases and the
output falls because of the load and active discharge circuit. The device is re-enabled when the UVLO rising
threshold is reached by the input voltage and a normal start-up follows.
Region F: Normal operation followed by the input falling to the UVLO falling threshold.
Region G: The device is disabled when the input voltage falls below the UVLO falling threshold to 0 V. The
output falls because of the load and active discharge circuit.
UVLO Rising Threshold
UVLO Hysteresis
VIN
C
VOUT
tAt
tBt
tDt
tEt
tFt
tGt
Figure 8-2. Typical UVLO Operation
8.1.5 Power Dissipation (PD)
Circuit reliability demands that proper consideration be given to device power dissipation, location of the circuit
on the printed circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator
must be as free as possible of other heat-generating devices that cause added thermal stresses.
As a first-order approximation, power dissipation in the regulator depends on the input-to-output voltage
difference and load conditions. Use Equation 2 to approximate PD:
PD = (VIN – VOUT) × IOUT
(2)
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Power dissipation can be minimized, and thus greater efficiency achieved, by proper selection of the system
voltage rails. Proper selection allows the minimum input-to-output voltage differential to be obtained. The low
dropout of the TPS7A21 allows for maximum efficiency across a wide range of output voltages.
The main heat conduction path for the device is through the thermal pad on the package. As such, the thermal
pad must be soldered to a copper pad area under the device. This pad area contains an array of plated vias that
conduct heat to any inner plane areas or to a bottom-side copper plane.
The maximum allowable junction temperature (TJ) determines the maximum power dissipation for the device.
According to Equation 3, power dissipation and junction temperature are most often related by the junction-toambient thermal resistance (RθJA) of the combined PCB and device package and the temperature of the ambient
air (TA).
TJ = TA + (RθJA × PD)
(3)
Equation 4 rearranges Equation 3 for output current.
IOUT = (TJ – TA) / [RθJA × (VIN – VOUT)]
(4)
Unfortunately, this thermal resistance (RθJA) is highly dependent on the heat-spreading capability built into the
particular PCB design, and therefore varies according to the total copper area, copper weight, and location
of the planes. The RθJA recorded in the Thermal Information table is determined by the JEDEC standard,
PCB, and copper-spreading area, and is only used as a relative measure of package thermal performance.
For a well-designed thermal layout, RθJA is actually the sum of the package junction-to-case (bottom) thermal
resistance (RθJC(bot)) plus the thermal resistance contribution by the PCB copper.
8.1.6 Estimating Junction Temperature
The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures
of the LDO when in-circuit on a typical PCB board application. These metrics are not strictly speaking thermal
resistances, but rather offer practical and relative means of estimating junction temperatures. These psi metrics
are determined to be significantly independent of the copper-spreading area. The key thermal metrics (ΨJT and
ΨJB) are used in accordance with Equation 5 and are given in the Thermal Information table.
ΨJT : TJ = TT + ΨJT × PD and ΨJB : TJ = TB + ΨJB × PD
(5)
where:
•
•
•
PD is the power dissipated as explained in the Power Dissipation (PD) section
TT is the temperature at the center-top of the device package
TB is the PCB surface temperature measured 1 mm from the device package and centered on the package
edge
8.1.7 Recommended Area For Continuous Operation
The operational area of an LDO is limited by the dropout voltage, output current, junction temperature, and input
voltage. The recommended area for continuous operation for a linear regulator is given in Figure 8-3 and can be
separated into the following parts:
•
•
•
•
20
Dropout voltage limits the minimum differential voltage between the input and the output (VIN – VOUT) at a
given output current level. See the Dropout Operation section for more details.
The rated output currents limits the maximum recommended output current level. Exceeding this rating
causes the device to fall out of specification.
The rated junction temperature limits the maximum junction temperature of the device. Exceeding this rating
causes the device to fall out of specification and reduces long-term reliability.
– The shape of the slope is depicted in the third region of Figure 8-3. The slope is nonlinear because the
maximum-rated junction temperature of the LDO is controlled by the power dissipation across the LDO.
Thus, when VIN – VOUT increases the output current must decrease.
The rated input voltage range governs both the minimum and maximum of VIN – VOUT.
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Output Current (A)
Figure 8-3 shows the recommended area of operation for this device on a JEDEC-standard high-K board with a
RθJA, as given in the Thermal Information table.
Output current limited by
dropout
Rated output
current
Output current limited by thermals
Limited by
maximum VIN
Limited by
minimum VIN
VIN ± VOUT (V)
Figure 8-3. Region Description of Continuous Operation Regime
8.2 Typical Application
Figure 8-4 shows the typical application circuit for the TPS7A21. Input and output capacitances may need to be
increased above the 1 µF minimum value for some applications.
VOUT
VIN
INPUT
OUTPUT
1 µF
1 µF
TPS7A21
VEN
ENABLE
GND
Figure 8-4. TPS7A21 Typical Application
8.2.1 Design Requirements
Table 8-1 summarizes the design requirements for the typical application circuit.
Table 8-1. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage
3.6 V
Output voltage
3.3 V
Output current
400 mA
Maximum ambient temperature
85°C
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8.2.2 Detailed Design Procedure
For this design example, the 3.3-V output version (TPS7A2133) is selected. A nominal 3.6-V input supply is
assumed. Use a minimum 1.0-μF input capacitor to minimize the effect of resistance and inductance between
the 3.6-V source and the LDO input. A minimum 1.0-μF output capacitor is also used for stability and good load
transient response. The dropout voltage (VDO) is less than 150 mV maximum at a 3.3-V output voltage and
500-mA output current, so there are no dropout issues with a minimum input voltage of 3.5 V and a maximum
output current of 400 mA.
With an ambient temperature of 85°C, an input voltage of 3.6 V and an output current of 400 mA, the die
temperature is 0.3 V × 0.4 A × 197.1°C/W + 85°C = 108.7°C.
8.2.2.1 Power Dissipation and Device Operation
The permissible power dissipation for any package is a measure of the capability of the device to pass heat from
the power source (the junctions of the device) to the ultimate heat sink of the ambient environment. Thus, power
dissipation is dependent on the ambient temperature and the thermal resistance across the various interfaces
between the die junction and ambient air.
Equation 6 calculates the maximum allowable power dissipation for the device in a given package:
PD-MAX = ((TJ-MAX – TA) / RθJA)
(6)
Equation 7 represents the actual power being dissipated in the device:
PD = (VIN – VOUT) × IOUT
(7)
These two equations establish the relationship between the maximum power dissipation allowed resulting from
thermal consideration, the voltage drop across the device, and the continuous current capability of the device.
Use these two equations to determine the optimum operating conditions for the device in the application.
In applications where lower power dissipation (PD) or excellent package thermal resistance (RθJA) is present, the
maximum ambient temperature (TA-MAX) can be increased.
In applications where high power dissipation or poor package thermal resistance is present, the maximum
ambient temperature (TA-MAX) may have to be derated. As given by Equation 8, TA-MAX is dependent on the
maximum operating junction temperature (TJ-MAX-OP = 125°C), the maximum allowable power dissipation in the
device package in the application (PD-MAX), and the junction-to ambient thermal resistance of the device or
package in the application (RθJA):
TA-MAX = (TJ-MAX-OP – (RθJA × PD-MAX))
(8)
Alternately, if TA-MAX can not be derated, the PD value must be reduced. This reduction can be accomplished by
reducing VIN in the VIN–VOUT term as long as the minimum VIN is met, or by reducing the IOUT term, or by some
combination of the two.
22
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8.2.3 Application Curves
VEN = VIN, IOUT = 500 mA
VIN = 0 V to 4.3 V, slew rate = 1 V/μs, IOUT = 1 mA
Figure 8-5. Start-Up With VEN After VIN
Figure 8-6. PSRR vs Frequency and VIN
8.3 Power Supply Recommendations
This LDO is designed to operate from an input supply voltage range of 2.0 V to 5.5 V. The input supply must
be well regulated and free of spurious noise. To ensure that the TPS7A21 output voltage is well regulated and
dynamic performance is optimum, the input supply must be at least VOUT + 0.3 V. A minimum capacitor value of
1 µF is required to be within 1 cm of the IN pin.
8.4 Layout
8.4.1 Layout Guidelines
The dynamic performance of the TPS7A21 is dependent on the layout of the PCB. PCB layout practices that are
adequate for typical LDOs may degrade the PSRR, noise, or transient performance of the TPS7A21.
Best performance is achieved by placing CIN and COUT on the same side of the PCB as the TPS7A21, and
as close to the package as practical. The ground connections for CIN and COUT must be back to the TPS7A21
ground pin using as wide and short a copper trace as practical.
Connections using long trace lengths, narrow trace widths, or connections through vias must be avoided. These
connections add parasitic inductances and resistance that results in inferior performance, especially during
transient conditions.
8.4.1.1 DSBGA Mounting
The DSBGA package requires specific mounting techniques, which are detailed in the AN-1112 DSBGA Wafer
Level Chip Scale Package application note. For best results during assembly, alignment ordinals on the PCB can
be used to facilitate placement of the DSBGA device.
8.4.1.2 DSBGA Light Sensitivity
Exposing the DSBGA device to direct light may cause incorrect operation of the device. Light sources such
as halogen lamps can affect electrical performance if they are situated in proximity to the device. Light with
wavelengths in the red and infrared part of the spectrum have the most detrimental effect; thus, the fluorescent
lighting used inside most buildings has very little effect on performance.
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8.4.2 Layout Example
VIN
VOUT
A1
A2
COUT
CIN
B1
B2
Power Ground
VEN
Figure 8-7. Typical DSBGA Layout
24
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TPS7A21
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SBVS398A – DECEMBER 2021 – REVISED SEPTEMBER 2022
9 Device and Documentation Support
9.1 Device Support
9.1.1 Device Nomenclature
Table 9-1. Device Nomenclature(1)(2)
(1)
(2)
PRODUCT
VOUT
TPS7A21xx(x)Pyyyz
xx(x) is the nominal output voltage. For output voltages with a resolution of 100 mV, two digits are
used in the ordering number; otherwise, three digits are used (for example, 28 = 2.8 V; 125 = 1.25
V).
P indicates an active output discharge feature. All members of the TPS7A21 family actively
discharge the output when the device is disabled.
yyy is the package designator.
z is the package quantity. J is for 12000-piece reel.
For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
Output voltages from 0.8 V to 5.5 V in 50-mV increments are available. Contact the factory for details and availability.
9.2 Documentation Support
9.2.1 Related Documentation
For related documentation see the following:
• Texas Instruments, AN-1112 DSBGA Wafer Level Chip Scale Package application report
• Texas Instruments, QFN/SON PCB Attachment application report
• Texas Instruments, TPS7A21EVM-059 Evaluation Module user guide
9.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
9.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
9.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
9.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
9.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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25
TPS7A21
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SBVS398A – DECEMBER 2021 – REVISED SEPTEMBER 2022
10.1 Mechanical Data
PACKAGE OUTLINE
YWD0004A-C01
PowerWCSP - 0.3 mm max height
SCALE 20.000
POWER CHIP SCALE PACKAGE
0.622
0.582
B
A
PIN A1 INDEX
AREA
0.622
0.582
0.3 MAX
C
SEATING PLANE
0.10
0.07
0.05 C
0.35
B
SYMM
0.35
A
1
2
SYMM
4X
0.175
0.155
0.015
C A B
4228730/A 05/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
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TPS7A21
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SBVS398A – DECEMBER 2021 – REVISED SEPTEMBER 2022
EXAMPLE BOARD LAYOUT
YWD0004A-C01
PowerWCSP - 0.3 mm max height
POWER CHIP SCALE PACKAGE
(0.35)
4X ( 0.165)
2
1
A
SYMM
(0.35)
B
SYMM
(R0.05) TYP
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 80X
0.0375 MAX
ALL AROUND
0.0375 MIN
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED
METAL
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4228730/A 05/2022
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
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TPS7A21
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SBVS398A – DECEMBER 2021 – REVISED SEPTEMBER 2022
EXAMPLE STENCIL DESIGN
YWD0004A-C01
PowerWCSP - 0.3 mm max height
POWER CHIP SCALE PACKAGE
(0.385)
4X (
0.2)
1
2
A
SYMM
(0.385)
B
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.075 mm THICK STENCIL
SCALE: 80X
4228730/A 05/2022
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
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PACKAGE OPTION ADDENDUM
www.ti.com
17-Mar-2023
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TPS7A2128PYWDJ
ACTIVE
DSBGA
YWD
4
12000
RoHS & Green
Call TI
Level-1-260C-UNLIM
-40 to 125
Y
Samples
TPS7A2133BPYWDJ
ACTIVE
DSBGA
YWD
4
12000
RoHS & Green
Call TI
Level-1-260C-UNLIM
-40 to 125
Z
Samples
TPS7A2133PYWDJ
ACTIVE
DSBGA
YWD
4
12000
RoHS & Green
Call TI
Level-1-260C-UNLIM
-40 to 125
Z
Samples
TPS7A21345PYWDJ
ACTIVE
DSBGA
YWD
4
12000
RoHS & Green
Call TI
Level-1-260C-UNLIM
-40 to 125
1
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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