0
登录后你可以
  • 下载海量资料
  • 学习在线课程
  • 观看技术视频
  • 写文章/发帖/加入社区
会员中心
创作中心
发布
  • 发文章

  • 发资料

  • 发帖

  • 提问

  • 发视频

创作活动
TPS7A3501EVM-547

TPS7A3501EVM-547

  • 厂商:

    BURR-BROWN(德州仪器)

  • 封装:

    Module

  • 描述:

    EVAL KIT FOR TPS7A3501

  • 数据手册
  • 价格&库存
TPS7A3501EVM-547 数据手册
Sample & Buy Product Folder Technical Documents Support & Community Tools & Software TPS7A3501 SBVS228B – JULY 2013 – REVISED MARCH 2015 TPS7A3501 High PSRR, Low-Noise, 1-A Power Filter 1 Features 2 Applications • • • • • • • • 1 • • • • • • • • • Regulates Input-to-Output Voltage: – User-Programmable Input-to-Output Voltage Regulation Range: 200 mV to 500 mV Power-Supply Rejection Ratio: – 42 dB at 1 MHz – ≥ 32 dB (360 kHz to 3.9 MHz) Low-Noise Output: – 3.8 µVRMS (10 Hz to 100 kHz) Output Current: Up to 1 A Output Voltage Range: 1.21 V to 4.5 V Excellent Load Transient Response Stable With Ceramic Capacitors as Low as 10 µF Current Limit and Thermal Shutdown for Fault Protection Available in a Low Thermal Resistance Package: 2-mm × 2-mm WSON-6 Operating Temperature Range: –40°C to 125°C Post DC-DC Converter Ripple Filtering Base Stations and Telecom Infrastructure Professional Audio Communications Imaging Test and Measurement Passive Filter Replacement 3 Description The TPS7A3501 is a positive voltage, low-noise (3.8-µVRMS) power filter capable of sourcing a 1-A load suitable for quiet supply solutions. Power filters, such as the TPS7A3501, provide voltage regulation across the input and output terminals with high efficiency (low insertion loss), and power-supply rejection. The device is ideally suited as a noise filter for 3.3-V, 2.5-V, and 1.8-V supplies at up to 1 A. The input-to-output voltage regulation is also userprogrammable, from 200 mV to 500 mV, with a single external resistor. If no resistor is used, the TPS7A3501 provides 330 mV of input-to-output voltage regulation. The device is stable with 10-µF input and output ceramic capacitors and a 10-nF noise-reduction ceramic capacitor. The TPS7A3501 is fully specified over a wide temperature of –40°C to 125°C. The device is offered in a low thermal resistance, 2-mm × 2-mm, WSON-6 package. Unlike passive filters, the TPS7A3501 provides thermal and current protection for itself and surrounding circuitry. Device Information(1) PART NUMBER TPS7A3501 PACKAGE WSON (6) BODY SIZE (NOM) 2.00 mm × 2.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Typical Application Circuit (VIN – VOUT) = 300 mV VIN = 3.6 V + IN (Optional) VOUT = 3.3 V COUT = 10 µF CIN = 10 µF RNR OUT – TPS7A3501 EN SENSE NR GND Load CNR = 1 µF 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPS7A3501 SBVS228B – JULY 2013 – REVISED MARCH 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 4 5 6.1 6.2 6.3 6.4 6.5 6.6 5 5 5 5 6 7 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Typical Characteristics .............................................. Detailed Description ............................................ 11 7.1 7.2 7.3 7.4 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ 11 11 12 13 8 Application and Implementation ........................ 15 8.1 Application Information............................................ 15 8.2 Typical Application ................................................. 15 8.3 Do's and Don'ts ....................................................... 18 9 Power Supply Recommendations...................... 18 10 Layout................................................................... 19 10.1 10.2 10.3 10.4 Layout Guidelines ................................................. Layout Example .................................................... Power Dissipation ................................................. Estimating Junction Temperature ......................... 19 19 19 20 11 Device and Documentation Support ................. 21 11.1 11.2 11.3 11.4 11.5 Device Support...................................................... Documentation Support ....................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 21 21 21 21 21 12 Mechanical, Packaging, and Orderable Information ........................................................... 21 4 Revision History Changes from Revision A (October 2013) to Revision B Page • Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ................................................................................................. 1 • Changed "free-air temperature" to "junction temperature" in Absolute Maximum Ratings condition statement ................... 5 • Changed Figure 14 to Figure 18: collected new data ............................................................................................................ 8 Changes from Original (July 2013) to Revision A Page • Changed document status to Production Data....................................................................................................................... 1 • Changed document title.......................................................................................................................................................... 1 • Deleted second sub-bullet from first Features bullet .............................................................................................................. 1 • Changed sub-bullets in Power-Supply Rejection Ratio and Low-Noise Output Features bullets .......................................... 1 • Changed Output Current, Transient Response, Ceramic Capacitors, and Package Features bullets .................................. 1 • Deleted Input Voltage Range Features bullet ........................................................................................................................ 1 • Added Output Voltage Range Features bullet........................................................................................................................ 1 • Added 4th to 7th Applications bullets ..................................................................................................................................... 1 • Changed 1st and 3rd paragraphs of Description section ....................................................................................................... 1 • Changed voltage regulation value in second Description paragraph ..................................................................................... 1 • Added changes to Typical Application Circuit ........................................................................................................................ 1 • Changed descriptions of IN, NR, OUT, and PowerPAD pins in Pin Functions table ............................................................. 4 • Added PowerPAD row to Pin Functions table ........................................................................................................................ 4 • Changed associated pins of Voltage parameter in Absolute Maximum Ratings table........................................................... 5 • Changed TJ Temperature range parameter minimum specification in Absolute Maximum Ratings table ............................. 5 • Changed conditions of Electrical Characteristics table .......................................................................................................... 6 • Changed VIN and VOUT parameter maximum specifications in Electrical Characteristics table.............................................. 6 • Added VUVLO(in) parameter to Electrical Characteristics table ................................................................................................. 6 • Changed VIN – VOUT voltage range, Vn, and Tsd parameters in Electrical Characteristics table............................................. 6 2 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: TPS7A3501 TPS7A3501 www.ti.com SBVS228B – JULY 2013 – REVISED MARCH 2015 • Changed ICL and IEN parameter specifications in Electrical Characteristics table .................................................................. 6 • Changed IGND parameter typical specification in Electrical Characteristics table ................................................................... 6 • Changed ISHDN test conditions and parameter specifications in Electrical Characteristics table............................................ 6 • Changed VEN(HI) parameter minimum specification in Electrical Characteristics table ........................................................... 6 • Changed Typical Characteristics section ............................................................................................................................... 7 • Added Functional Block Diagram ......................................................................................................................................... 11 • Changed Application Information section ............................................................................................................................. 15 • Changed Board Layout Recommendations section ............................................................................................................. 19 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: TPS7A3501 3 TPS7A3501 SBVS228B – JULY 2013 – REVISED MARCH 2015 www.ti.com 5 Pin Configuration and Functions DRV Package 6-Pin WSON Top View IN 1 6 OUT EN 2 5 SENSE GND 3 4 NR Pin Functions PIN NAME NO. I/O DESCRIPTION Enable pin. Driving EN high turns on the device (if driven low, EN turns off the device). EN must not be left floating and can be connected to IN if not used. EN 2 I GND 3 — IN 1 I Input supply. A capacitor greater than or equal to 10 µF must be tied from this pin to ground to assure stability. This configuration is especially important when long input traces or high source impedances are encountered. TI recommends using X5R- or X7R-type dielectrics to minimize the temperature variations inherent to capacitors. Ground NR 4 O Noise-reduction pin. When a capacitor is connected from this pin to GND, RMS noise can be reduced to very low levels. A capacitor greater than or equal to 10 nF must be tied from this pin to ground to assure stability. TI recommends connecting a 1-µF capacitor from NR to GND (as close to the device as possible) to maximize AC performance and minimize noise. TI recommends using X5R- or X7R-type dielectrics to minimize the temperature variations inherent to capacitors. In addition, when a resistor is connected from this pin to GND or IN, the device input-to-output voltage can be programmed; see Feature Description for details. OUT 6 O Regulator output. A capacitor greater than or equal to 10 µF must be tied from this pin to ground to assure stability. TI recommends using a X5R- or X7R-type dielectrics to minimize the temperature variations inherent to capacitors. PowerPAD™ — — Connect the PowerPAD to the ground plane for improved thermal performance. SENSE 5 I 4 Control-loop error amplifier input. This pin must be connected to OUT. TI recommends connecting SENSE at the point of load to maximize accuracy. Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: TPS7A3501 TPS7A3501 www.ti.com SBVS228B – JULY 2013 – REVISED MARCH 2015 6 Specifications 6.1 Absolute Maximum Ratings over operating junction temperature range (unless otherwise noted). (1) Voltage Current (2) MAX –0.3 7 OUT, SENSE –0.3 VIN + 0.3 (2) OUT Temperature (1) MIN IN, NR, EN UNIT V Internally limited Operating junction, TJ –40 125 Storage, Tstg –55 150 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Absolute maximum rating is VIN + 0.3 V or + 7 V, whichever is smaller. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) ±1000 Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2) ±250 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating junction temperature range (unless otherwise noted). MIN VIN Input voltage IOUT Output current TJ Operating junction temperature NOM MAX UNIT 1.71 5 0 1 V A –40 125 °C 6.4 Thermal Information THERMAL METRIC (1) DRV (WSON) 6 PINS RθJA Junction-to-ambient thermal resistance 66.9 RθJC(top) Junction-to-case (top) thermal resistance 86.5 RθJB Junction-to-board thermal resistance 36.4 ψJT Junction-to-top characterization parameter 1.8 ψJB Junction-to-board characterization parameter 36.6 RθJC(bot) Junction-to-case (bottom) thermal resistance 7.3 (1) UNIT °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: TPS7A3501 5 TPS7A3501 SBVS228B – JULY 2013 – REVISED MARCH 2015 www.ti.com 6.5 Electrical Characteristics At TJ = –40°C to 125°C, VIN = 3.6 V, RNR = ∞ (not connected), IOUT = 10 mA, VEN = VIN, and CIN = COUT = 10 µF, unless otherwise noted. PARAMETER VIN Input voltage range VUVLO(in) Input supply UVLO VOUT Output voltage range VIN – VOUT voltage range TEST CONDITIONS VIN increasing kΩ 1.4 1.8 2.4 EN pin input current VEN = VIN ISHUTDOWN Shutdown current (IGND) VEN ≤ 0.3 V (1) (2) 6 mV 210 GND pin current Thermal shutdown junction temperature V 500 170 IEN Tsd 4.5 200 110 (2) IGND EN pin input high (enable) 1.21 RNR_INTERNAL (1) VOUT = 0.85 × VOUT(nom) VEN(HI) V mV mV Output current limit EN pin input low (disable) V 363 ICL VEN(LO) 1.7 200 UNIT 330 10 mA ≤ IOUT ≤ 1 A Output noise voltage 5 297 INR_INTERNAL Vn MAX VOUT(nom) = VIN – 330 mV, IOUT ≤ 1 A, 1.71 V ≤ VIN ≤ 4.83 V Load regulation Power-supply rejection ratio TYP 1.5 VIN hysteresis ∆VOUT(∆IOUT) PSRR MIN 1.71 10 µA µV/mA 1.1 A 2.25 5 1 50 nA 0.01 3 µA f = 10 kHz, CNR = 1 µF, IOUT = 0.5 A 55 f = 100 kHz, CNR = 1 µF, IOUT = 0.5 A 40 f = 1 MHz, CNR = 1 µF, IOUT = 0.5 A 42 BW = 10 Hz to 100 kHz, CNR = 1 µF, IOUT = 1 A 3.8 BW = 100 Hz to 100 kHz, CNR = 1 µF, IOUT = 1 A 3.62 BW = 10 Hz to 1 MHz, CNR = 1 µF, IOUT = 1 A 12.1 dB µVRMS 0.4 1.1 mA V V Shutdown, temperature increasing 165 Shutdown, temperature hysteresis 20 °C RNR_INTERNAL refers to the internal resistor used to set (VIN – VOUT) for the device when no external RNR is used. See Adjustable Voltage Drop and Typical Application Circuit for details. INR_INTERNAL refers to the internal current source used to set (VIN – VOUT) for the device when no external RNR is used. See Adjustable Voltage Drop and Typical Application Circuit for details. Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: TPS7A3501 TPS7A3501 www.ti.com SBVS228B – JULY 2013 – REVISED MARCH 2015 6.6 Typical Characteristics At VIN = 3.6 V, RNR = ∞ (not connected), IOUT = 10 mA, VEN = VIN, COUT = 10 µF, CIN = 10 µF, and CNR = 0.1 µF, unless otherwise noted. 0.345 -40ƒC +105ƒC 0ƒC +125ƒC 0.322 +25ƒC 0ƒC +125ƒC +25ƒC 0.321 VIN - VOUT (V) 0.34 VIN - VOUT (V) -40ƒC +105ƒC 0.335 0.33 0.325 0.32 0.319 0.318 0.317 IOUT = 1 A 0.32 0.316 1.8 2.2 2.6 3 3.4 3.8 4.2 4.6 Input Voltage (V) 5 1.8 2.2 -40ƒC +105ƒC 3.4 3.8 4.2 4.6 5 C002 Figure 2. Line Regulation 0ƒC +125ƒC 0.6 +25ƒC 0.34 0.5 ¨9 P9 0.335 VIN - VOUT (V) VIN - VOUT (V) 3 Input Voltage (V) Figure 1. Line Regulation 0.345 2.6 C001 0.33 0.325 ¨9 P9 0.4 ¨9 P9 0.3 0.32 0.2 0.315 0.1 IOUT = 100 mA 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 Output Current (A) 1 ±40 ±25 ±10 -40ƒC +105ƒC 3 0ƒC +125ƒC 35 50 65 80 95 110 125 C004 Figure 4. VDELTA vs Temperature 4.5 +25ƒC -40ƒC +105ƒC 0ƒC +125ƒC +25ƒC 4 2.75 3.5 IGND (mA) IGND (mA) 20 Temperature (ƒC) Figure 3. Load Regulation 3.25 5 C003 2.5 2.25 3 2.5 2 2 1.75 1.5 1.5 1.8 2.2 2.6 3 3.4 3.8 4.2 4.6 Input Voltage (V) 5 0 0.1 Figure 5. Ground Current vs Input Voltage 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 Output Current (A) C005 1 C006 Figure 6. Ground Current vs Output Current Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: TPS7A3501 7 TPS7A3501 SBVS228B – JULY 2013 – REVISED MARCH 2015 www.ti.com Typical Characteristics (continued) At VIN = 3.6 V, RNR = ∞ (not connected), IOUT = 10 mA, VEN = VIN, COUT = 10 µF, CIN = 10 µF, and CNR = 0.1 µF, unless otherwise noted. 1000 -40ƒC +105ƒC 900 0ƒC +125ƒC 800 2 +25ƒC -40ƒC +105ƒC 0ƒC +125ƒC +25ƒC 1.9 VEN = 0 V 600 ICL (A) ISHDN (nA) 700 500 1.8 1.7 400 300 1.6 200 VOUT = 90% x VOUT(NOM) 100 1.5 0 1.8 2.1 2.4 2.7 3 3.3 1.8 3.6 Input Voltage (V) 2.1 2.4 2.7 3 3.3 3.6 Input Voltage (V) C007 C008 Figure 8. Current Limit vs Input Voltage Figure 7. Shutdown Current vs Input Voltage 100 3.5 Iout OUT = 100 mA 90 3 Iout OUT = 500 mA Iout OUT = 1 A 70 PSRR (dB) Output Voltage (V) 80 2.5 2 1.5 60 50 40 30 1 20 0.5 10 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 Iout (A) 1.8 10 2 ¨9 P9 ¨9 P9 100 ¨9 P9 90 80 80 70 70 60 50 40 20 10k Frequency (Hz) 100k Cnr NR = 10 nF 10 CIN = 1 F, Iout = 500 mA 1k C010 10M 10 100 1k 10k Frequency (Hz) C010 Figure 11. Power-Supply Rejection Ratio vs Frequency Cnr NR = 100 nF Cnr NR = 1 uF CIN = 1 F, Iout = 500 mA 0 1M 10M 40 30 100 1M 50 20 10 100k 60 30 0 10k Figure 10. Power-Supply Rejection Ratio vs Frequency 90 10 1k Frequency (Hz) PSRR (dB) PSRR (dB) 100 100 C009 Figure 9. Foldback Current Limit 8 CIN = 1 F, CNR = 1 µF 0 100k 1M 10M C010 Figure 12. Power-Supply Rejection Ratio vs Frequency Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: TPS7A3501 TPS7A3501 www.ti.com SBVS228B – JULY 2013 – REVISED MARCH 2015 Typical Characteristics (continued) At VIN = 3.6 V, RNR = ∞ (not connected), IOUT = 10 mA, VEN = VIN, COUT = 10 µF, CIN = 10 µF, and CNR = 0.1 µF, unless otherwise noted. 10 RMS Noise (BW 100Hz-100kHz) Cnr …Vrms 1 uF 3.6 100 nF 4.2 10 nF 20.7 1RLVH —9¥+] 1 VIN = 3.6 V, IOUT = 10 mA → 1 A → 10 mA CIN = COUT = 10 mF, CNR = 10 nF Slew Rate = 1 A/ms I OUT (1 A/div) 0.1 0.01 VOUT (50 mV/div) Cnr NR = 10 nF Cnr NR = 100 nF Cnr NR = 1 uF 0.001 10 100 1k IOUT = 1 A 10k 100k 1M Time (50 ms/div) 10M Frequency (Hz) C010 Figure 14. Load Transient Response Figure 13. Spectral Noise Density vs Frequency VIN = 1.7 V → 4.8 V → 1.7 V, IOUT = 500 mA CIN = COUT = 10 mF, CNR = 10 mF, Slew Rate = 1 A/ms VIN = 3.6 V, IOUT = 10 mA → 1 A → 10 mA CIN = COUT = 10 mF, CNR = 1 mF Slew Rate = 1 A/ms VIN (2 V/div) I OUT (1 A/div) VOUT (50 mV/div) VOUT (2 V/div) Time (50 ms/div) Time (10 ms/div) Figure 15. Load Transient Response Figure 16. Line Transient Response VIN = 1.7 V → 4.8 V → 1.7 V, IOUT = 500 mA CIN = COUT = 10 mF, CNR = 1 mF, Slew Rate = 1 A/ms VIN (2 V/div) VIN (2 V/div) VOUT (2 V/div) VOUT (2 V/div) Time (10 ms/div) VIN = VEN = 0 V → 3.6 V IOUT = 1 A CIN = COUT = 10 mF CNR = 10 nF Time (1 ms/div) Figure 17. Line Transient Response Figure 18. Start-up Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: TPS7A3501 9 TPS7A3501 SBVS228B – JULY 2013 – REVISED MARCH 2015 www.ti.com Typical Characteristics (continued) At VIN = 3.6 V, RNR = ∞ (not connected), IOUT = 10 mA, VEN = VIN, COUT = 10 µF, CIN = 10 µF, and CNR = 0.1 µF, unless otherwise noted. VIN (2 V/div) VIN = VEN = 0 V → 3.6 V IOUT = 1 A CIN = COUT = 10 mF CNR = 1 mF VOUT (2 V/div) Time (1 ms/div) Figure 19. Start-up 10 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: TPS7A3501 TPS7A3501 www.ti.com SBVS228B – JULY 2013 – REVISED MARCH 2015 7 Detailed Description 7.1 Overview The TPS7A3501 is a positive-voltage, low-noise (3.8-µVRMS) power filter capable of sourcing a 1-A load. Power filters such as the TPS7A3501 provide voltage regulation across the input and output terminals with high accuracy and power-supply rejection ratio. The device is ideally suited as a noise filter for 4.5-V, 3.3-V, and 1.8-V supplies up to 1-A loads. The input-to-output voltage drop is also user-programmable, from 200 mV up to 500 mV, with an external resistor. If no resistor is used, the TPS7A3501 provides 330 mV of input-to-output voltage regulation. The TPS7A3501 is stable with 10-µF ceramic input and output capacitors and a 10-nF ceramic noise-reduction capacitor. The device is fully specified over a wide temperature range of –40°C to 125°C and is offered in a low thermal resistance, 2-mm × 2-mm, 6-pin WSON package. 7.2 Functional Block Diagram VIN = 3.6 V IN CIN = 10 µF VEN = 3.6 V Charge Pump EN NR + OUT (Optional) RNR VOUT = VIN – 300 mV = 3.3 V – CNR 1 mF SENSE COUT = 10 µF GND Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: TPS7A3501 11 TPS7A3501 SBVS228B – JULY 2013 – REVISED MARCH 2015 www.ti.com 7.3 Feature Description 7.3.1 Power Filter Operation A power filter is very similar to a low-dropout (LDO) regulator, except that instead of regulating output voltage relative to ground, the power filter regulates output voltage relative to VIN. In other words, a power filter maintains a fixed ΔV from input to output. The device is optimized for high PSRR with a low VIN-to-VOUT delta, leading to a lower power dissipation than standard LDOs. Unlike a standard LDO, the bandgap and noise associated with the device are never gained up, resulting in low output noise regardless of VOUT. The external noise capacitor on the power filter lets the user set the frequency at which the power filter starts to reject noise from the input. Table 1 summarizes the differences between a power filter and a high-performance LDO. Table 1. Power Filter vs LDO Characteristics PARAMETER POWER FILTER Voltage regulation Regulates input-to-output delta. Voltage delta can be set from 0.2 V to 0.5 V. Relies on the upstream power rail to set the output voltage. Regulates the output voltage referenced to ground. Outputs any output voltage within the output voltage range (limited by power dissipation). PSRR High PSRR at typical switching frequencies of DC-DC converters with lower power dissipation. Lower PSRR at low frequencies. High PSRR over broad bandwidth. Effective rejection of low-frequency noise and switching noise from DCDC. Noise Lower noise, 3.8 µV. Noise is not gained up when VOUT increases. Low noise (typically in the range of 5 µVRMS to 20 µVRMS). Noise is gained up when VOUT increases. High PSRR can be achieved with only 330 mV from VIN to VOUT. Typically requires 750 mV to 1 V of VIN-to-VOUT delta to achieve high PSRR. Power dissipation LDO 7.3.2 Minimum Load The device is stable without an output load. 7.3.3 Shutdown The enable pin (EN) is active high and compatible with standard and low-voltage TTL-CMOS levels. The enable pin voltage level is independent of input voltage and can be biased to a higher value than VIN as long as EN is within the maximum specification. When shutdown capability is not required, EN can be connected to IN. 7.3.4 Internal Current Limit The device has an internal foldback current limit that helps protect the power filter during fault conditions. The current supplied by the device is gradually reduced when the output voltage decreases. When the output is shorted to GND, the LDO supplies a typical current of 550 mA. When in current limit, the output voltage is not regulated and VOUT = IOUT × RLOAD. For reliable operation, do not operate the device in current limit for extended periods of time. Because of the nature of the foldback current limit circuitry, if OUT is forced below 0 V before EN goes high, the device may not start up. To ensure proper start-up in applications that have both a positive and negative voltage rail, extra care must be taken to ensure that OUT is greater than or equal to 0 V. There are several ways to help ensure proper start-up for dual-rail applications: • Enable the device before the negative rail and disable the device after the negative rail. • Delaying the EN voltage with respect to IN voltage allows the internal pulldown resistor to discharge any residual voltage at OUT. • If a faster discharge rate is required, or if EN is tied directly to IN, an external resistor from OUT to GND can be used. 7.3.5 Reverse Current The TPS7A3501 has a built-in body diode that conducts current when the voltage at OUT exceeds the voltage at IN. This current is not internally limited, so if reverse voltage conditions are anticipated, external limiting is required. If there are potential situations where reverse current is expected, place a diode from OUT to IN, as shown in Figure 20. 12 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: TPS7A3501 TPS7A3501 www.ti.com SBVS228B – JULY 2013 – REVISED MARCH 2015 VIN VOUT IN OUT Device EN NR Load SENSE GND Figure 20. Reverse Current Protection Schematic 7.3.6 Undervoltage Lockout (UVLO) The device uses an undervoltage lockout circuit to keep the output shut off until the internal circuitry is operating properly, ensuring a well-controlled start-up. 7.3.7 Thermal Protection Thermal protection disables the output when the junction temperature rises to approximately 160°C, allowing the device to cool. When the junction temperature cools to approximately 140°C, the output circuitry is again enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may cycle on and off. This cycling limits device power dissipation, thus protecting the device from damage resulting from overheating. Any activation of the thermal protection circuit indicates excessive power dissipation or inadequate thermal dissipation on the PCB. For reliable operation, limit junction temperature to 125°C (maximum). To estimate the margin of safety in a complete design, increase the ambient temperature until the thermal protection is triggered using worst-case loads and signal conditions. For good reliability, thermal protection should trigger at least 35°C above the maximum expected ambient condition of the application. This configuration produces a worst-case junction temperature of 125°C at the highest-expected ambient temperature and worst-case load. The device internal protection circuitry is designed to protect against overload conditions. This circuitry is not intended to replace proper heat-sinking or thermal dissipation on the PCB. Continuously running the device into thermal shutdown degrades device reliability. 7.4 Device Functional Modes Table 2 provides a quick comparison between the normal, dropout, and disabled modes of operation. Table 2. Device Functional Mode Comparison PARAMETER OPERATING MODE VIN EN IOUT TJ Normal 1.71 ≤ VIN ≤ 5 VEN > VEN(HI) IOUT < ICL TJ < Tsd Disabled — VEN < VEN(LO) — TJ > Tsd 7.4.1 Normal Operation The device functions as a fixed voltage drop filter under the following conditions: • The input voltage is within the specified operating range of 1.71 V to 5 V. • The enable voltage has previously exceeded the enable rising threshold voltage and not yet decreased below the enable falling threshold. • The output current is less than the current limit (IOUT < ICL). • The device junction temperature is less than the thermal shutdown temperature (TJ < Tsd). Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: TPS7A3501 13 TPS7A3501 SBVS228B – JULY 2013 – REVISED MARCH 2015 www.ti.com 7.4.2 Disabled The device is disabled under the following conditions: • The enable voltage is less than the enable falling threshold voltage or has not yet exceeded the enable rising threshold. • The device junction temperature is greater than the thermal shutdown temperature (TJ > Tsd). 14 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: TPS7A3501 TPS7A3501 www.ti.com SBVS228B – JULY 2013 – REVISED MARCH 2015 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The TPS7A3501 is well-suited for use as a filter for switching power supplies. The high PSRR of the device significantly reduces the ripple caused by the switching frequency as well as the subsequent harmonic frequencies. Figure 21 shows the basic circuit connections for the TPS7A3501. The IN pin should be connected to a well-regulated power source, typically a switching power supply. + VIN IN OUT ± VOUT Optional(1) Device (1) Decreases 'V EN Load SENSE NR GND Increases 'V Refer to Table 4. Figure 21. Basic Circuit Connections 8.2 Typical Application Figure 22 shows a schematic for filtering the output of a switching regulator using the TPS7A3501 to power an analog-to-digital converter (ADC). PVIN VIN TPS54620 BOOT EN IN PH OUT CIN PWRGD COUT Device SS/TR RT/CLK COMP VSENSE GND EN ADC SENSE NR GND CNR Exposed Thermal Pad Figure 22. Typical Application Schematic Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: TPS7A3501 15 TPS7A3501 SBVS228B – JULY 2013 – REVISED MARCH 2015 www.ti.com Typical Application (continued) 8.2.1 Design Requirements Table 3 shows the design requirements. Table 3. Design Requirements PARAMETER DESIGN REQUIREMENT Input voltage 3.63 V Output voltage 3.3 V 100-Hz to 100-kHz RMS noise < 4 µVRMS Maximum output current 700 mA 8.2.2 Detailed Design Procedure Select the input and output capacitors to be at least 10 µF for stability. Select a value for RNR to give the desired voltage drop. For this example of a 330-mV voltage drop, no external resistor on the NR pin is required. Pick a value for CNR greater than 10 nF, but large enough to provide the required noise performance. Refer to Table 5 for guidelines on selecting CNR for a desired RMS noise target. For this example, to achieve an RMS noise (100 Hz to 100 kHz) less than 4 µVRMS, the noise reduction capacitor must be at least 1 µF. 8.2.2.1 Adjustable Voltage Drop In the TPS7A3501, the nominal voltage drop (ΔV) from IN to OUT is 330 mV. ΔV can be adjusted from this nominal setting with an external resistor. By connecting a resistor from the NR pin to IN, ΔV can be decreased to as low as 200 mV. By connecting a resistor from the NR pin to GND, ΔV can be increased to as high as 500 mV. The ability to change ΔV allows for the creation of standard voltage rails from higher voltage rails (for example, 2.5 V from 3 V, 1.5 V from 1.8 V, and so forth). By connecting a resistor from the NR pin to IN, ΔV can be decreased to as low as 200 mV. Use Equation 1 to determine the size of the resistor required to set ΔV. R = ΔV / (0.33 – ΔV) × 150,000 Ω (1) By connecting a resistor from the NR pin to GND, ΔV can be increased to as high as 500 mV. Use Equation 2 to determine the size of the resistor required to set ΔV. R = VOUT / (ΔV – 0.33) × 150,000 Ω (2) Table 4 lists the standard external resistor values required for different input-to-output voltage drops. Table 4. Common Input-to-Output Voltage Drops ΔV (mV) VOUT 200 330 400 500 R TO VIN R TO GND Any 240 kΩ Do not install Any Do not install Do not install 3.3 V Do not install 6.8 MΩ 2.5 V Do not install 5.1 MΩ 1.8 V Do not install 3.9 MΩ 3.3 V Do not install 3 MΩ 2.5 V Do not install 2.2 MΩ 1.8 V Do not install 1.6 MΩ 8.2.2.2 Input and Output Capacitor Requirements Ceramic 10-µF or larger input and output capacitors are required to assure proper device operation. This capacitor counteracts reactive source impedances, improving supply transient response and decreasing input ripple. Higher-value capacitors may be used if large, fast slew rate load transients are anticipated, or if the device is located several inches away from the power source. To assure correct device operation, there should be no more than 100 µF of capacitance on the output of the device, including capacitance from downstream bypass capacitors. 16 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: TPS7A3501 TPS7A3501 www.ti.com SBVS228B – JULY 2013 – REVISED MARCH 2015 TI recommends X5R- and X7R-type ceramic capacitors because these types of capacitors have minimal variation in value and equivalent series resistance (ESR) overtemperature. Other types of capacitors, such as electrolytic or tantalum, can make the device unstable. 8.2.2.3 Output Noise A 10-nF, or higher, noise-reduction capacitor is required to assure stability. Using a 1-μF ceramic capacitor minimizes output noise (see Figure 13). To assure correct device operation, a maximum capacitor of 2.2 µF can be connected to NR. 8.2.2.4 Power-Supply Rejection Ratio (PSRR) Unlike standard LDOs, the TPS7A3501 PSRR is significantly affected by the noise-reduction capacitor. The larger the noise-reduction capacitor, the higher the PSRR is for frequencies below 10 kHz. Using a 1-μF ceramic capacitor maximizes PSRR. One of the most compelling features of the TPS7A3501 is its high PSRR capabilities. The rejection ratio for this device is lower than standard LDOs at frequencies below 1 kHz but becomes higher at higher frequencies. For better low-frequency PSRR performance, a larger noise-reduction capacitor can be used. TI recommends connecting a 1-µF ceramic capacitor to NR to maximize PSRR (see Figure 12). A higher input-to-output voltage difference also increases the device rejection ratio. Although the device maximizes rejection ratio at 500 mV, high rejection ratio can still be achieved with as little as a 330-mV input-to-output voltage differential, unlike most standard LDOs. 8.2.2.5 Start-up Because adding a noise-reduction capacitor leads to the formation of an RC filter, start-up time and the rate at which the device tracks VIN are increased. Thus, consider the tradeoff between start-up time, noise, and PSRR when selecting a noise-reduction capacitor to use with the TPS7A3501. Use Equation 3 to calculate the typical start-up time. T_startup = 250,000 × CNR (s) (3) Table 5 shows the effect of various noise-reduction capacitors on RMS noise (with a 100-Hz to 100-kHz bandwidth), PSRR (at 1 kHz), and start-up time. Table 5. Effect of Various Filter Capacitors FILTER CAPACITOR RMS NOISE (BW 100 Hz to 100 kHz) PSRR (at 1 kHz) START-UP TIME (EN to 90% of VOUT) 1 µF 3.62 µV 60 dB 250 ms 100 nF 4.21 µV 40 dB 25 ms 10 nF 20.70 µV 20 dB 3 ms 8.2.2.6 Transient Response Increasing the size of the output capacitor reduces overshoot and undershoot magnitude during transients; however this size increase also slows the recovery from these transients. Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: TPS7A3501 17 TPS7A3501 SBVS228B – JULY 2013 – REVISED MARCH 2015 www.ti.com 8.2.3 Application Curves 10 100 ¨9 P9 ¨9 P9 RMS Noise (BW 100Hz-100kHz) Cnr …Vrms 1 uF 3.6 100 nF 4.2 10 nF 20.7 ¨9 P9 90 80 1 1RLVH —9¥+] PSRR (dB) 70 60 50 40 30 0.1 0.01 Cnr NR = 10 nF 20 Cnr NR = 100 nF 10 CIN = 1 F, Iout = 500 mA 0 10 100 1k 10k 100k Cnr NR = 1 uF 0.001 1M Frequency (Hz) 10M 10 1k 10k 100k 1M 10M Frequency (Hz) C010 Figure 23. Power-Supply Rejection Ratio vs Frequency 100 IOUT = 1 A C010 Figure 24. Spectral Noise Density vs Frequency 8.3 Do's and Don'ts Place at least 10-μF ceramic capacitors on both the IN and OUT pins of the device, as close as possible to the pins of the regulator. Do not place the input or output capacitor more than 10 mm away from the regulator. Connect a 10-nF or greater, low-equivalent series resistance (ESR) capacitor across the NR pin and GND of the regulator. Larger capacitors provide lower noise performance. Do not use a capacitor larger than 2.2 µF on the NR pin. Do not exceed the absolute maximum ratings. 9 Power Supply Recommendations For best performance, connect a low-output impedance power supply directly to the IN pin of the device. Inductive impedances between the input supply and the IN pin create significant voltage excursions at the IN pin. 18 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: TPS7A3501 TPS7A3501 www.ti.com SBVS228B – JULY 2013 – REVISED MARCH 2015 10 Layout 10.1 Layout Guidelines Input and output capacitors should be placed as close to the device pins as possible. TI recommends that all components be on the same side of the printed-circuit-board (PCB) as the device. Using long, thin traces or vias to connect the device to external components is highly discouraged because this practice leads to parasitic inductances, which in turn degrade noise, PSRR, and transient response. For an example layout, refer to the TPS7A3501EVM-547 Evaluation Module User Guide ( SLVU921). 10.2 Layout Example GND PLANE COUT CIN TPS7A3501 VIN IN 1 6 OUT EN 2 5 SENSE GND 3 4 NR VOUT GND PLANE CNR Figure 25. PCB Layout Example (DRV Package) 10.3 Power Dissipation Knowing the device power dissipation and proper sizing of the thermal plane connected to the tab or pad is critical to avoiding thermal shutdown and ensuring reliable operation. Device power dissipation depends on input voltage and load conditions and can be calculated with Equation 4: PD = (VIN – VOUT) × IOUT (4) Power dissipation can be minimized and greater efficiency can be achieved by using the lowest available voltage drop option of 200 mV. However, keep in mind that higher voltage drops result in better PSRR performance. On the WSON (DRV) package, the primary conduction path for heat is through the exposed power pad to the PCB. To ensure the device does not overheat, connect the pad to ground with an appropriate amount of copper PCB area through vias. The maximum power dissipation determines the maximum allowable junction temperature (TJ) for the device. Power dissipation and junction temperature are most often related by the junction-to-ambient thermal resistance (θJA) of the combined PCB and device package and the temperature of the ambient air (TA), according to Equation 5: TJ = TA + (θJA × PD) (5) Unfortunately, this thermal resistance (θJA) is highly dependent on the heat-spreading capability of the particular PCB design, and therefore varies according to the total copper area, copper weight, and location of the planes. The θJA recorded in the table is determined by the JEDEC standard for PCB and copper-spreading area and is to be used only as a relative measure of package thermal performance. For a well-designed thermal layout, θJA is actually the sum of the package junction-to-case (bottom) thermal resistance (θJCbot) plus the thermal resistance contribution by the PCB copper. Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: TPS7A3501 19 TPS7A3501 SBVS228B – JULY 2013 – REVISED MARCH 2015 www.ti.com 10.4 Estimating Junction Temperature The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures of the power filter on a typical PCB board application. These metrics are not strictly speaking thermal resistances, but rather offer practical and relative means of estimating junction temperatures. These psi metrics are determined to be significantly independent of copper-spreading area. The key thermal metrics (ΨJT and ΨJB) are given in the table and are used in accordance with Equation 6. YJT: TJ = TT + YJT ´ PD YJB: TJ = TB + YJB ´ PD where: • • • 20 PD is the power dissipated as explained in Equation 4, TT is the temperature at the center-top of the device package, and TB is the PCB surface temperature measured 1 mm from the device package and centered on the package edge. (6) Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: TPS7A3501 TPS7A3501 www.ti.com SBVS228B – JULY 2013 – REVISED MARCH 2015 11 Device and Documentation Support 11.1 Device Support 11.1.1 Development Support 11.1.1.1 Evaluation Modules An evaluation module (EVM) is available to assist in the initial circuit performance evaluation using the TPS7A3501. The TPS7A3501EVM-547 evaluation module (and related user guide) can be requested at the Texas Instruments website through the product folder or purchased directly from the TI eStore. 11.1.1.2 Spice Models Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of analog circuits and systems. A SPICE model for the TPS7A3501 is available through the product folder under Tools & Software. 11.2 Documentation Support 11.2.1 Related Documentation • TPS7A3501EVM-547 User's Guide, SLVU921. 11.3 Trademarks PowerPAD is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 11.4 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 11.5 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: TPS7A3501 21 PACKAGE OPTION ADDENDUM www.ti.com 11-Aug-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) TPS7A3501DRVR ACTIVE WSON DRV 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 SIQ Samples TPS7A3501DRVT ACTIVE WSON DRV 6 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 SIQ Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
TPS7A3501EVM-547 价格&库存

很抱歉,暂时无法提供与“TPS7A3501EVM-547”相匹配的价格&库存,您可以联系我们找货

免费人工找货