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TPS7A37
SBVS220B – MARCH 2013 – REVISED AUGUST 2015
TPS7A37 1% High-Accuracy, 1-A, Low-Dropout Regulator With Reverse Current
Protection
1 Features
3 Description
•
The TPS7A37 family of linear low-dropout (LDO)
voltage regulators uses an NMOS pass element in a
voltage-follower configuration. This topology is
relatively insensitive to output capacitor value and
ESR, allowing a wide variety of load configurations.
Load transient response is excellent, even with a
small 1-μF ceramic output capacitor. The NMOS
topology also allows very low dropout.
1
•
•
•
•
•
•
•
Stable with 1-μF or Larger Ceramic Output
Capacitor
Input Voltage Range: 2.2 V to 5.5 V
Ultralow Dropout Voltage:
– 200-mV Maximum at 1 A
Excellent Load Transient Response—Even With
Only 1-μF Output Capacitor
NMOS Topology Delivers Low Reverse Leakage
Current
Excellent Accuracy:
– 0.23% Nominal Accuracy
– 1% Overall Accuracy Over Line, Over Load,
and Over Temperature
Less Than 20-nA typical IQ in Shutdown Mode
Thermal Shutdown and Current Limit for Fault
Protection
The TPS7A37 family uses an advanced BiCMOS
process to yield high precision while delivering very
low dropout voltages and low ground pin current.
Current consumption, when not enabled, is under 20
nA and ideal for portable applications. These devices
are protected by thermal shutdown and foldback
current limit.
Device Information(1)
PART NUMBER
TPS7A37
PACKAGE
BODY SIZE (NOM)
WSON (6)
2.00 mm × 2.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
•
Point of Load Regulation for DSPs, FPGAs,
ASICs, and Microprocessors
• Post-Regulation for Switching Supplies
• Portable and Battery-Powered Equipment
SPACE
Typical Application Circuit (Adjustable Version)
Optional
VIN
IN
OUT
VOUT
Typical Application Circuit (Fixed Version)
VIN
IN
EN
OFF
GND
VOUT
1.0 mF
TPS7A3701
EN
OUT
TPS7A37xx
GND
FB
ON
ON
OFF
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS7A37
SBVS220B – MARCH 2013 – REVISED AUGUST 2015
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
6.1
6.2
6.3
6.4
6.5
6.6
3
3
4
4
5
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 11
7.1
7.2
7.3
7.4
Overview .................................................................
Functional Block Diagrams .....................................
Feature Description.................................................
Device Functional Modes........................................
11
11
12
13
8
Application and Implementation ........................ 14
8.1 Application Information............................................ 14
8.2 Typical Applications ................................................ 16
9 Power Supply Recommendations...................... 19
10 Layout................................................................... 19
10.1
10.2
10.3
10.4
10.5
Layout Guidelines .................................................
Layout Example ....................................................
Thermal Considerations ........................................
Power Dissipation .................................................
Estimating Junction Temperature ........................
19
19
20
20
21
11 Device and Documentation Support ................. 23
11.1
11.2
11.3
11.4
Documentation Support ........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
23
23
23
23
12 Mechanical, Packaging, and Orderable
Information ........................................................... 23
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (July 2013) to Revision B
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................ 1
•
Changed Internal Reference (VFB) parameter typ value ....................................................................................................... 5
Changes from Original (March 2013) to Revision A
•
2
Page
Changed device status to Production Data ............................................................................................................................ 1
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SBVS220B – MARCH 2013 – REVISED AUGUST 2015
5 Pin Configuration and Functions
DRV Package
6-Pin WSON
Top View
OUT
1
6
IN
NR/FB
2
5
N/C
GND
3
4
EN
Power dissipation may limit operating range. Check Thermal Information table.
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
EN
4
I
Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts the regulator
into shutdown mode. Refer to the Shutdown section under Applications Information for more
details. EN must not be left floating and can be connected to IN if not used.
FB
2
I
Adjustable voltage version only—this pin is the input to the control loop error amplifier, and is
used to set the output voltage of the device.
GND
3, Pad
—
IN
6
I
N/C
5
—
Not connected
NR/FB
2
—
Fixed voltage versions only—connecting an external capacitor to this pin bypasses noise
generated by the internal bandgap, reducing output noise to very low levels.
Regulator output. A 1.0-μF or larger capacitor of any type is required for stability.
OUT
1
O
PowerPAD
—
—
Ground
Unregulated input supply
6 Specifications
6.1 Absolute Maximum Ratings
Over operating temperature range (unless otherwise noted). (1)
Voltage
MAX
UNIT
–0.3
6
V
EN
–0.3
6
V
OUT
–0.3
5.5
V
NR, FB
–0.3
6
V
Peak output current
Current
Internally limited
Output short-circuit duration
Temperature
(1)
MIN
IN
A
Indefinite
A
Operating junction, TJ
–55
150
°C
Storage, Tstg
–65
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VIN
2.2
5.5
V
VOUT
VFB
5.5 – VDO
V
VEN
0
VIN
IOUT
0
1
CIN
1
COUT
(1)
R1
(2)
CFF
(1)
(2)
µF
1
CNR
A
µF
10
nF
VOUT(nom) ×
15.833
kΩ
10
100
nF
If the product of COUT × ESR < 50 nΩ-F, the part may ring after a transient.
This nominal value is for the best accuracy.
6.4 Thermal Information
TPS7A37
THERMAL METRIC (1)
DRV (WSON)
UNIT
6 PINS
RθJA
Junction-to-ambient thermal resistance
67.2
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
87.6
°C/W
RθJB
Junction-to-board thermal resistance
36.8
°C/W
ψJT
Junction-to-top characterization parameter
1.8
°C/W
ψJB
Junction-to-board characterization parameter
37.2
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
7.7
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.5 Electrical Characteristics
Over operating temperature range (TJ = –40°C to 125°C), VIN = VOUT(nom) + 1 V (1), IOUT = 10 mA, VEN = 2.2 V, and COUT = 2.2
μF, unless otherwise noted. Typical values are at TJ = 25°C.
PARAMETER
TEST CONDITIONS
VIN
Input voltage range (1) (2)
VFB
Internal reference
TJ = 25°C
Output voltage range
TPS7A3701 (3)
VOUT
Accuracy (1) ,
(4)
ΔVO(ΔVI)
Line regulation (1)
ΔVO(ΔIO)
Load regulation
MIN
TYP
2.2
Nominal
TJ = 25°C
over VIN, IOUT,
and TJ= –40°C to
125°C
VOUT + 0.5 V ≤ VIN ≤ 5.5 V;
10 mA ≤ IOUT ≤ 1 A
1.192
1.204
VFB
MAX
UNIT
5.5
V
1.216
V
5.5 – VDO
V
0.23%
–1%
VOUT(nom) + 0.5 V ≤ VIN ≤ 5.5 V
0.1 mA ≤ IOUT ≤ 300 mA
10 mA ≤ IOUT ≤ 1 A
+1.0%
0.01
0.03
%/V
0.25%
0.35%
3
5
mV
200
mV
0.5%
VDO
Dropout voltage (5)
(VIN = VOUT(nom) – 0.1 V)
IOUT = 1 A
ZO(DO)
Output impedance in dropout
2.2 V ≤ VIN ≤ VOUT + VDO
ICL
Output current limit
VOUT = 0.9 × VOUT(nom)
ISC
Short-circuit current
VOUT = 0 V
450
mA
IREV
Reverse leakage current (6) (–IIN)
VEN ≤ 0.5 V, 0 V ≤ VIN ≤ VOUT
0.1
μA
IOUT = 10 mA (IQ)
400
130
1.6
IGND
GND pin current
ISHDN
Shutdown current (IGND)
VEN ≤ 0.5 V, VOUT ≤ VIN ≤ 5.5 V
20
IFB
FB pin current
TPS7A3701
0.1
PSRR
Power-supply rejection ratio (ripple
rejection)
f = 100 Hz, IOUT = 1 A
58
f = 10 kHz, IOUT = 1 A
37
VN
Output noise voltage
BW = 10 Hz to 100 kHz
COUT = 10 μF
tSTR
Startup time
VOUT = 3 V, RL = 30 Ω, COUT = 1 μF
VEN(HI)
EN pin high (enabled)
VEN(LO)
EN pin low (shutdown)
IEN(HI)
EN pin current (enabled)
TSD
Thermal shutdown temperature
TJ
Operating junction temperature
(1)
(2)
(3)
(4)
(5)
(6)
Ω
0.25
1.05
IOUT = 1 A
2.2
A
μA
1300
nA
μA
0.6
dB
μVRMS
27 × VOUT
μs
600
1.7
VIN
0
0.5
VEN = 5.5 V
20
Shutdown, temperature increasing
160
Reset, temperature decreasing
140
–40
V
V
nA
°C
125
°C
Minimum VIN = VOUT + VDO or 2.2 V, whichever is greater.
For VOUT(nom) < 1.6 V, when VIN ≤ 1.6 V, the output will lock to VIN and may result in an over-voltage condition on the output. To avoid
this situation, disable the device before powering down VIN.
TPS7A3701 is tested at VOUT = 1.2 V.
Tolerance of external resistors not included in this specification.
VDO is not measured for fixed output versions with VOUT(nom) < 2.3 V since minimum VIN = 2.2 V.
Fixed-voltage versions only; refer to the Application Information section for more information.
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6.6 Typical Characteristics
For all voltage versions at TJ = 25°C, VIN = VOUT(nom) + 1 V, IOUT = 10 mA, VEN = 2.2 V, and COUT = 2.2 μF, unless otherwise
noted.
0.5
Referred to VIN = VOUT + 1.0V at IOUT = 10mA
-40°C
+25°C
+125°C
0.2
0.1
0
-0.1
-0.2
Change in VOUT (%)
0.15
0.3
Change in VOUT (%)
0.20
Referred to IOUT = 10mA
0.4
-0.3
0.10
0
-0.05
-40°C
-0.10
-0.15
-0.4
-0.5
-0.20
0
100 200
300 400
500 600 700
800 900 1000
0
0.5
1.0
IOUT (mA)
200
2.0
2.5
3.0
3.5
4.0
4.5
Figure 2. Line Regulation
200
VOUT = 2.5V
180
1.5
VIN - VOUT (V)
Figure 1. Load Regulation
180
160
160
+125°C
+25°C
140
120
140
VDO (mV)
VDO (mV)
+25°C
+125°C
0.05
100
80
120
100
80
60
60
-40°C
40
40
20
20
0
0
0
100 200 300
400 500
600 700
800 900 1000
-50
-25
IOUT (mA)
0
25
50
75
100
125
150
Temperature (°C)
IOUT = 1-A
Figure 3. Dropout Voltage vs Output Current
VOUT = 2.5-V
Figure 4. Dropout Voltage vs Temperature
30
18
IOUT = 10mA
16
IOUT = 10mA
25
Percent of Units (%)
Percent of Units (%)
14
20
15
10
12
10
8
6
4
5
2
6
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
100
0
-1.0
-0.9
-0.8
-0.7
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0
VOUT Error (%)
Worst Case dVOUT/dT (ppm/°C)
Figure 5. Output Voltage Histogram
Figure 6. Output Voltage Drift Histogram
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Typical Characteristics (continued)
For all voltage versions at TJ = 25°C, VIN = VOUT(nom) + 1 V, IOUT = 10 mA, VEN = 2.2 V, and COUT = 2.2 μF, unless otherwise
noted.
3000
2500
IOUT = 1A
VIN = 5.0V
2500
2000
IGND (mA)
VIN = 5.0V
IGND (mA)
1500
VIN = 3.3V
2000
VIN = 3.3V
1500
1000
1000
VIN = 2.2V
VIN = 2.2V
500
500
0
0
0
200
400
600
800
-50
1000
0
-25
50
75
100
125
Figure 8. Ground Pin Current vs Temperature
Figure 7. Ground Pin Current vs Output Current
1
2.00
VENABLE = 0.5V
VIN = VOUT + 0.5V
1.80
ICL
1.60
Output Current (A)
IGND (mA)
25
Temperature (°C)
IOUT (mA)
0.1
1.40
1.20
1.00
0.80
0.60
ISC
0.40
0.20
0.01
-50
-25
0
25
50
75
100
VOUT = 3.3V
0
-0.5
125
0
0.5
Figure 9. Ground Pin Current in Shutdown vs Temperature
1.5
2.0
2.5
3.0
3.5
Figure 10. Current Limit vs VOUT (Foldback)
2.0
2.0
1.9
1.9
1.8
1.8
1.7
1.7
Current Limit (A)
Current Limit (A)
1.0
Output Voltage (V)
Temperature (°C)
1.6
1.5
1.4
1.3
1.6
1.5
1.4
1.3
1.2
1.2
1.1
1.1
1.0
VOUT = 1.2V
1.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
-50
-25
0
25
50
75
100
VIN (V)
Temperature (°C)
Figure 11. Current Limit vs VIN
Figure 12. Current Limit vs Temperature
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Typical Characteristics (continued)
For all voltage versions at TJ = 25°C, VIN = VOUT(nom) + 1 V, IOUT = 10 mA, VEN = 2.2 V, and COUT = 2.2 μF, unless otherwise
noted.
90
40
IOUT = 100mA
COUT = Any
70
IOUT = 1mA
COUT = 1mF
35
30
IOUT = 1mA
COUT = 10mF
60
50
IO = 100mA
CO = 1mF
IOUT = 1mA
COUT = Any
40
PSRR (dB)
Ripple Rejection (dB)
80
30
20
20
15
Frequency = 10kHz
COUT = 10mF
VOUT = 2.5V
IOUT = 100mA
10
IOUT = 100mA
COUT = 10mF
10
25
5
0
0
10
100
1k
10k
100k
1M
0
10M
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
VIN - VOUT (V)
Frequency (Hz)
Figure 13. PSRR (Ripple Rejection) vs Frequency
Figure 14. PSRR (Ripple Rejection) vs VIN – VOUT
1
60
COUT = 1mF
55
0.1
VN (uVrms)
eN (mV/ÖHz)
50
COUT = 10mF
45
40
35
VOUT = 2.5V
COUT = 0μF
R1 = 39.2kΩ
10Hz < Frequency < 100kHz
30
25
IOUT = 150mA
0.01
10
100
1k
10k
20
10p
100k
100p
Frequency (Hz)
1n
10n
CFF (F)
Figure 15. Noise Spectral Density
Figure 16. TPS7A3701: RMS Noise Voltage vs CFF
60
140
50
120
VOUT = 5.0V
100
40
30
VN (uVrms)
VN (uVrms)
VOUT = 5.0V
VOUT = 3.3V
20
10
0.1
8
20
CNR = 0.01μF
10Hz < Frequency < 100kHz
0
1
10
VOUT = 3.3V
60
40
VOUT = 1. 5V
0
80
VOUT = 1.5V
COUT = 0μF
10Hz < Frequency < 100kHz
1p
10p
100p
1n
COUT (mF)
CNR (F)
Figure 17. RMS Noise Voltage vs COUT
Figure 18. RMS Noise Voltage vs CNR
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Typical Characteristics (continued)
For all voltage versions at TJ = 25°C, VIN = VOUT(nom) + 1 V, IOUT = 10 mA, VEN = 2.2 V, and COUT = 2.2 μF, unless otherwise
noted.
CNR = 10nF
CNR = 10nF
COUT = 10mF
VOUT
200mV/div
COUT = 10mF
100mV/div
VOUT
1A
5.3V
10mA
4.3V
IOUT
VIN
10ms/div
10ms/div
VOUT = 3.3V
VOUT = 3.3V
Figure 19. TPS7A3701: Load Transient Response
Figure 20. TPS7A3701: Line Transient Response
RL = 20W
COUT = 10mF
VOUT
1V/div
RL = 20W
COUT = 1mF
RL = 20W
COUT = 1mF
1V/div
RL = 20W
COUT = 10mF
VOUT
2V
2V
VEN
1V/div
1V/div
0V
0V
VEN
100ms/div
100ms/div
Figure 21. TPS7A3701: Turn-on Response
Figure 22. TPS7A3701: Turn-off Response
6
4
VIN
VOUT
IENABLE (nA)
5
10
Volts
3
2
1
1
0.1
0
-1
0.01
-50
-2
-25
0
25
50
75
100
50ms/div
Temperature (°C)
Figure 23. TPS7A3701: Power-up/Power-down (VOUT = 3.3 V)
Figure 24. IENABLE vs Temperature
125
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Typical Characteristics (continued)
60
160
55
140
50
120
45
100
IFB (nA)
VN (VRMS)
For all voltage versions at TJ = 25°C, VIN = VOUT(nom) + 1 V, IOUT = 10 mA, VEN = 2.2 V, and COUT = 2.2 μF, unless otherwise
noted.
40
60
35
30
25
80
VOUT = 2.5V
COUT = 0mF
R1 = 39.2kW
10Hz < Frequency < 100kHz
20
10p
100p
40
20
1n
10n
0
-50
-25
0
25
50
75
100
CFB (F)
Temperature (°C)
Figure 25. TPS7A3701: RMS Noise Voltage vs CFB
Figure 26. TPS7A3701: IFB vs Temperature
CFB = 10nF
R1 = 39.2kW
COUT = 10mF
100mV/div
VOUT
COUT = 10mF
100mV/div
125
VOUT = 2.5V
CFB = 10nF
VOUT
4.5V
250mA
3.5V
10mA
10
IOUT
VIN
10ms/div
5ms/div
Figure 27. TPS7A3701: Load Transient, Adjustable Version
Figure 28. TPS7A3701: Line Transient, Adjustable Version
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7 Detailed Description
7.1 Overview
The TPS7A37 belongs to a family of LDO regulators that use an NMOS pass transistor to achieve ultra-lowdropout performance and reverse current protection. These features combined with an enable input make the
TPS7A37 ideal for portable applications. This regulator family offers a wide selection of fixed output voltage
versions and an adjustable output version. All versions have thermal and over-current protection, including
foldback current limit.
7.2 Functional Block Diagrams
IN
4-MHZ
Charge Pump
EN
Thermal
Protection
Ref
Servo
27 kW
Bandgap
Error
Amp
Current
Limit
OUT
8 kW
GND
R1
R1 + R2 = 80 kW
R2
NR
Figure 29. Fixed Voltage Version
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Functional Block Diagrams (continued)
IN
Standard 1% Resistor Values
for Common Output Voltages
4-MHZ
Charge Pump
EN
Thermal
Protection
Ref
Servo
27 kW
Bandgap
Error
Amp
GND
8 kW
80 kW
R1
R2
1.2 V
Short
Open
1.5 V
23.2 kW
95.3 kW
1.8 V
28.0 kW
56.2 kW
2.5 V
39.2 kW
36.5 kW
2.8 V
44.2 kW
33.2 kW
3.0 V
46.4 kW
30.9 kW
3.3 V
52.3 kW
30.1 kW
NOTE: VOUT = (R1 + R2)/R2 ´ 1.204;
R1 || R2 @ 19 kW for best
accuracy.
OUT
Current
Limit
VO
R1
FB
R2
Figure 30. Adjustable Voltage Version
7.3 Feature Description
7.3.1 Internal Current Limit
The TPS7A37 internal current limit helps protect the regulator during fault conditions. Foldback current limit helps
to protect the regulator from damage during output short-circuit conditions by reducing current limit when VOUT
drops below 0.5 V. See Figure 10 in the Typical Characteristics section.
Note from Figure 10 that approximately –0.2 V of VOUT results in a current limit of 0 mA. Therefore, if OUT is
forced below –0.2 V before EN goes high, the device may not start up. In applications that work with both a
positive and negative voltage supply, the TPS7A37 should be enabled first.
7.3.2 Enable Pin and Shutdown
The enable pin (EN) is active high and is compatible with standard TTL-CMOS levels. A VEN below 0.5 V (max)
turns the regulator off and drops the GND pin current to approximately 10 nA. When EN is used to shutdown the
regulator, all charge is removed from the pass transistor gate, and the output ramps back up to a regulated VOUT
(see Figure 21).
When shutdown capability is not required, EN can be connected to VIN. However, the pass gate may not be
discharged using this configuration, and the pass transistor may be left on (enhanced) for a significant time after
VIN has been removed. This scenario can result in reverse current flow (if the IN pin is low impedance) and faster
ramp times upon power-up. In addition, for VIN ramp times slower than a few milliseconds, the output may
overshoot upon power-up.
Note that current limit foldback can prevent device start-up under some conditions. See the Internal Current Limit
section for more information.
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Feature Description (continued)
7.3.3 Reverse Current
The NMOS pass element of the TPS7A37 provides inherent protection against current flow from the output of the
regulator to the input when the gate of the pass device is pulled low. To ensure that all charge is removed from
the gate of the pass element, the EN pin must be driven low before the input voltage is removed. If this is not
done, the pass element may be left on because of stored charge on the gate.
After the EN pin is driven low, no bias voltage is needed on any pin for reverse current blocking. Note that
reverse current is specified as the current flowing out of the IN pin because of voltage applied on the OUT pin.
There will be additional current flowing into the OUT pin as a result of the 80-kΩ internal resistor divider to
ground (see Figure 29 and Figure 30).
For the TPS7A3701, reverse current may flow when VFB is more than 1.0 V above VIN.
7.4 Device Functional Modes
Driving the EN pin over 1.7 V turns on the regulator. Driving the EN pin below 0.5 V causes the regulator to enter
shutdown mode. In shutdown, the current consumption of the device is reduced to 20 nA, typically.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 Input and Output Capacitor Requirements
Although an input capacitor is not required for stability if input impedance is very low, it is good analog design
practice to connect a 0.1-μF to 1-μF low equivalent series resistance (ESR) capacitor across the input supply
near the regulator. This capacitor counteracts reactive input sources and improves transient response, noise
rejection, and ripple rejection. A higher-value capacitor may be necessary if large, fast rise-time load transients
are anticipated or the device is located several inches from the power source.
The TPS7A37 requires a 1-µF output capacitor for stability. It is designed to be stable for all available types and
values of capacitors. In applications where multiple low ESR capacitors are in parallel, ringing may occur when
COUT × ESR < 50 nΩ-F. Total ESR includes all parasitic resistances, including capacitor ESR and board, socket,
and solder joint resistance. In most applications, the sum of capacitor ESR and trace resistance will meet this
requirement.
8.1.2 Output Noise
A precision bandgap reference is used to generate the internal reference voltage, VREF. This reference is
dominant noise source within the TPS7A37 and it generates approximately 32 μVRMS (10 Hz to 100 kHz) at
reference output (NR). The regulator control loop gains up the reference noise with the same gain as
reference voltage, so that the noise voltage of the regulator is approximately given by:
V
(R + R2 )
= 32mVRMS ´ OUT
VN = 32mVRMS ´ 1
R2
VREF
Since the value of VREF is 1.2V, this relationship reduces to:
æ mV
ö
VN (mVRMS ) = 27 ç RMS ÷ ´ VOUT (V)
V
è
ø
the
the
the
(1)
(2)
for the case of no CNR.
An internal 27-kΩ resistor in series with the noise reduction pin (NR) forms a low-pass filter for the voltage
reference when an external noise reduction capacitor, CNR, is connected from NR to ground. For CNR = 10 nF,
the total noise in the 10-Hz to 100-kHz bandwidth is reduced by a factor of ~3.2, giving the approximate
relationship:
mVRMS
VN(mVRMS) = 8.5
x VOUT(V)
V
(3)
(
)
for CNR = 10 nF.
This noise reduction effect is shown as RMS Noise Voltage vs CNR in the Typical Characteristics section.
The TPS7A3701 adjustable version does not have the NR pin available. However, connecting a feedback
capacitor, CFB, from the output to the feedback pin (FB) reduces output noise and improve load transient
performance. This capacitor should be limited to 0.1 µF.
The TPS7A37 uses an internal charge pump to develop an internal supply voltage sufficient to drive the gate of
the NMOS pass element above VOUT. The charge pump generates ~250 μV of switching noise at ~4 MHz;
however, charge-pump noise contribution is negligible at the output of the regulator for most values of IOUT and
COUT.
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Application Information (continued)
8.1.3 Dropout Voltage
The TPS7A37 uses an NMOS pass transistor to achieve extremely low dropout. When (VIN – VOUT) is less than
the dropout voltage (VDO), the NMOS pass device is in its linear region of operation and the input-to-output
resistance is the RDS, ON of the NMOS pass element.
For large step changes in load current, the TPS7A37 requires a larger voltage drop from VIN to VOUT to avoid
degraded transient response. The boundary of this transient dropout region is approximately twice the dc
dropout. Values of VIN – VOUT above this line ensure normal transient response.
Operating in the transient dropout region can cause an increase in recovery time. The time required to recover
from a load transient is a function of the magnitude of the change in load current rate, the rate of change in load
current, and the available headroom (VIN to VOUT voltage drop). Under worst-case conditions [full-scale
instantaneous load change with (VIN – VOUT) close to dc dropout levels], the TPS7A37 can take a couple of
hundred microseconds to return to the specified regulation accuracy.
8.1.4 Transient Response
The low open-loop output impedance provided by the NMOS pass element in a voltage follower configuration
allows operation without a 1.0-µF output capacitor. As with any regulator, the addition of additional capacitance
from the OUT pin to ground reduces undershoot magnitude but increases its duration. In the adjustable version,
the addition of a capacitor, CFB, from the OUT pin to the FB pin will also improve the transient response.
The TPS7A37 does not have active pull-down when the output is over-voltage. This architecture allows
applications that connect higher voltage sources, such as alternate power supplies, to the output. This
architecture also results in an output overshoot of several percent if the load current quickly drops to zero when a
capacitor is connected to the output. The duration of overshoot can be reduced by adding a load resistor. The
overshoot decays at a rate determined by output capacitor COUT and the internal/external load resistance. The
rate of decay is given by:
(Fixed voltage version)
VOUT
dV
=
dT COUT ´ 80kW P RLOAD
(4)
(Adjustable voltage version)
VOUT
dV
=
dT COUT ´ 80kW P (R1 + R2 ) P RLOAD
(5)
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8.2 Typical Applications
8.2.1 Typical Application Schematic
VIN
VOUT
OUT
IN
CIN
COUT
CFF
TPS7A3701
R1
FB
R1
EN
GND
Figure 31. Typical Application Schematic
8.2.1.1 Design Requirements
Table 1 lists the design parameters.
Table 1. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage
3.6 V
Output voltage
3.3 V
DC output current
100 mA
Peak output current
1A
8.2.1.2 Detailed Design Procedure
Due to the transients in this application input and output capacitors should be used. A CIN = COUT = 10-uF
capacitor has been selected.
The ESR of the chosen capacitor can be checked by looking the magnitude of the complex impedance over
frequency. When |Zc| reaches a minimum the DC ESR is the value of |Zc| at that frequency. The ESR of the
chosen capacitor is 10 mΩ, which gives us a product of 10 mΩ * 10 uF = 100 nΩ-F > 50 nΩ-F, minimizing the
ringing during transients.
As the VIN - VOUT change is only 300 mV with a 100-mA DC current, the expected junction temperature rise over
the ambient, on a JEDEC standard board, is 67.2 C/W × 0.3V × 0.1 A = 2 C.
To ensure best accuracy, R1 = 52.3 kΩ and R2 = 30.1 kΩ, and a 10-nF CFF is used to reduce output noise.
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8.2.1.3 Application Curves
RL = 20W
COUT = 10mF
VOUT
1V/div
RL = 20W
COUT = 1mF
RL = 20W
COUT = 1mF
1V/div
RL = 20W
COUT = 10mF
VOUT
2V
2V
VEN
1V/div
1V/div
0V
0V
100ms/div
100ms/div
Figure 32. TPS7A3701: Turn-on Response
CFB = 10nF
R1 = 39.2kW
VEN
COUT = 10mF
100mV/div
Figure 33. TPS7A3701: Turn-off Response
VOUT
COUT = 10mF
VOUT = 2.5V
CFB = 10nF
100mV/div
VOUT
4.5V
250mA
3.5V
10mA
IOUT
VIN
10ms/div
5ms/div
Figure 34. TPS7A3701: Load Transient, Adjustable Version
Figure 35. TPS7A3701: Line Transient, Adjustable Version
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8.2.2 Fixed-Voltage Version
Figure 36 shows the basic circuit connections for the fixed voltage models.
VIN
IN
VOUT
OUT
TPS7A37xx
EN
GND
ON
OFF
Figure 36. Typical Application Circuit for Fixed-Voltage Version
8.2.3 Adjustable Operation
Figure 37 gives the connections for the adjustable output version, TPS7A3701 .
R1 and R2 can be calculated for any output voltage using the formula shown in Figure 37. Sample resistor values
for common output voltages are shown in Figure 30.
For best accuracy, make the parallel combination of R1 and R2 approximately equal to 19 kΩ. This 19 kΩ, in
addition to the internal 8-kΩ resistor, presents the same impedance to the error amp as the 27-kΩ bandgap
reference output. This impedance helps compensate for leakages into the error amp terminals.
Optional input capacitor.
May improve source
impedance, noise, or PSRR.
VIN
IN
Output capacitor
must be ³ 1.0 mF.
TPS7A3701
EN
OFF
VOUT
OUT
GND
R1
CFF
FB
ON
R2
VOUT =
(R1 + R2)
x 1.204
R2
Optional capacitor
reduces output noise
and improves
transient response.
Figure 37. Typical Application Circuit for Adjustable-Voltage Version(1)
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9 Power Supply Recommendations
The input supply for the LDO must be within its recommended operating conditions (that is, between 2.2 V to 5.5
V). The input voltage must provide adequate headroom in order for the device to have a regulated output. If the
input supply is noisy, additional input capacitors with low ESR can help improve the output transient
performance.
10 Layout
10.1 Layout Guidelines
Layout is a critical part of good power-supply design. There are several signal paths that conduct fast-changing
currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade
the power-supply performance. To help eliminate these problems, the IN pin should be bypassed to ground with
a low ESR ceramic bypass capacitor with an X5R or X7R dielectric.
The GND pin should be tied directly to the PowerPAD under the IC. The PowerPAD should be connected to any
internal PCB ground planes using multiple vias directly under the IC.
Do not place any of the capacitors on the opposite side of the PCB from where the regulator is installed. The use
of vias and long traces is strongly discouraged because these circuits may impact system performance
negatively, and even cause instability.
10.1.1 Board Layout Recommendations to Improve PSRR and Noise Performance
To improve AC performance (such as PSRR, output noise, and transient response), TI recommends designing
the board with separate ground planes for VIN and VOUT, with each ground plane star connected only at the GND
pin of the device.
To EN I/O or
VIN if not used
To Input Power
Supply
4
EN
5
NC
6
IN
Thermal Pad
10.2 Layout Example
GND
3
NR
2
OUT
1
To Load
Ground Plane
for thermals
*Denotes thermal vias for heat dissipation
Figure 38. Fixed Voltage Layout
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To EN I/O or
VIN if not used
4
EN
5
NC
6
IN
To Input
Power Supply
Thermal Pad
Layout Example (continued)
Ground Plane
for thermals
GND
3
FB
2
Sense
Line to
Load
OUT
1
To Load
Ground Plane
for thermals
*Denotes thermal vias for heat dissipation
Figure 39. Adjustable Voltage Layout
10.3 Thermal Considerations
Thermal protection disables the output when the junction temperature rises to approximately +160°C, allowing
the device to cool. When the junction temperature cools to approximately +140°C, the output circuitry is again
enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection
circuit may cycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage due to
overheating.
Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate
heatsink. For reliable operation, junction temperature should be limited to +125°C maximum. To estimate the
margin of safety in a complete design (including heatsink), increase the ambient temperature until the thermal
protection is triggered; use worst-case loads and signal conditions. For good reliability, thermal protection should
trigger at least +35°C above the maximum expected ambient condition of your application. This produces a
worst-case junction temperature of +125°C at the highest expected ambient temperature and worst-case load.
The internal protection circuitry of the TPS7A37 has been designed to protect against overload conditions. It was
not intended to replace proper heatsinking. Continuously running the TPS7A37 into thermal shutdown degrades
device reliability.
10.4 Power Dissipation
Knowing the device power dissipation and proper sizing of the thermal plane that is connected to the tab or pad
is critical to avoiding thermal shutdown and ensuring reliable operation.
Power dissipation of the device depends on input voltage and load conditions and can be calculated using
Equation 6:
PD VIN VOUT u IOUT
(6)
Power dissipation can be minimized and greater efficiency can be achieved by using the lowest possible input
voltage necessary to achieve the required output voltage regulation.
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Power Dissipation (continued)
On the WSON (DRV) package, the primary conduction path for heat is through the exposed pad to the printed
circuit board (PCB). The pad can be connected to ground or be left floating; however, it should be attached to an
appropriate amount of copper PCB area to ensure the device does not overheat. That tab should be connected
to ground. The maximum junction-to-ambient thermal resistance depends on the maximum ambient temperature,
maximum device junction temperature, and power dissipation of the device and can be calculated using
Equation 7:
125qC TA
RTJA
PD
(7)
Knowing the maximum RθJA, the minimum amount of PCB copper area needed for appropriate heatsinking can
be estimated using Figure 40.
160
140
qJA (°C/W)
120
100
80
60
40
20
0
0
Note:
1
2
4
5
7
3
6
Board Copper Area (in2)
8
9
10
θJA value at board size of 9in2 (that is, 3in × 3in) is a JEDEC standard.
Figure 40. DRV (WSON) Package θJA vs Board Size
Figure 40 shows the variation of θJA as a function of ground plane copper area in the board. It is intended only as
a guideline to demonstrate the effects of heat spreading in the ground plane and should not be used to estimate
actual thermal performance in real application environments.
NOTE
When the device is mounted on an application PCB, it is strongly recommended to use
ΨJT and ΨJB, as explained in the Estimating Junction Temperature section.
10.5 Estimating Junction Temperature
Using the thermal metrics ΨJT and ΨJB, as shown in the Thermal Information table, the junction temperature can
be estimated with corresponding formulas (given in Equation 8). For backwards compatibility, an older θJC,Top
parameter is listed as well.
YJT: TJ = TT + YJT · PD
YJB: TJ = TB + YJB · PD
(8)
Where PD is the power dissipation shown by Equation 6, TT is the temperature at the center-top of the IC
package, and TB is the PCB temperature measured 1mm away from the IC package on the PCB surface (as
Figure 42 shows).
NOTE
Both TT and TB can be measured on actual application boards using a thermo-gun (an
infrared thermometer).
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Estimating Junction Temperature (continued)
For more information about measuring TT and TB, see the application note SBVA025, Using New Thermal
Metrics, available for download at www.ti.com.
By looking at Figure 41, the new thermal metrics (ΨJT and ΨJB) have very little dependency on board size. That
is, using ΨJT or ΨJB with Equation 8 is a good way to estimate TJ by simply measuring TT or TB, regardless of the
application board size.
35
YJT and YJB (°C/W)
30
25
DRV YJB
20
DRV YJT
15
10
5
0
0
1
2
3
4
5
6
7
8
9
10
Board Copper Area (in2)
Figure 41. DRV (WSON) Package ΨJT and ΨJB vs Board Size
For a more detailed discussion of why TI does not recommend using θJC(top) to determine thermal characteristics,
refer to application report SBVA025, Using New Thermal Metrics, available for download at www.ti.com. For
further information, refer to application report SPRA953, Semiconductor and IC Package Thermal Metrics, also
available on the TI website.
TT on top
of IC
TB on PCB
surface
1mm
See note (1)
(1)
Power dissipation may limit operating range. Check Thermal Information table.
(2)
Example DRV (SON) Package Measurement
Figure 42. Measuring Points for TT and TB
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
•
•
Using New Thermal Metrics, SBVA025
TPS7A37xxEVM-529 Evaluation Module, SLVU850
11.1.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.2 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS7A3701DRVR
ACTIVE
WSON
DRV
6
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
SJI
TPS7A3701DRVT
ACTIVE
WSON
DRV
6
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
SJI
TPS7A3721DRVR
ACTIVE
WSON
DRV
6
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
SIX
TPS7A3721DRVT
ACTIVE
WSON
DRV
6
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
SIX
TPS7A3725DRVR
ACTIVE
WSON
DRV
6
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
SJH
TPS7A3725DRVT
ACTIVE
WSON
DRV
6
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
SJH
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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