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TPS7A4001
SBVS162B – MARCH 2011 – REVISED JULY 2015
TPS7A4001 100-V Input Voltage, 50-mA, Very High Voltage Linear Regulator
1 Features
3 Description
•
•
•
The TPS7A4001 device is a very high voltagetolerant linear regulator that offers the benefits of a
thermally-enhanced package (HVSSOP), and is able
to withstand continuous DC or transient input
voltages of up to 100 V.
1
•
•
•
•
•
•
•
•
•
•
Very High Maximum Input Voltage: 100 V
Wide Input Voltage Range: 7 to 100 V
Accuracy:
– Nominal: 1%
– Over Line, Load, and Temperature: 2.5%
Low Quiescent Current: 25 µA
Quiescent Current at Shutdown: 4.1 µA
Maximum Output Current: 50 mA
CMOS Logic-Level-Compatible Enable Pin
Adjustable Output Voltage from about 1.175 to
90 V
Stable With Ceramic Capacitors:
– Input Capacitance: ≥1 µF
– Output Capacitance: ≥4.7 µF
Dropout Voltage: 290 mV
Built-In Current Limit and Thermal Shutdown
Protection
Package: High Thermal Performance HVSSOP
PowerPAD™
Operating Temperature Range: –40°C to 125°C
2 Applications
•
•
•
•
•
•
•
Microprocessors, Microcontrollers Powered by
Industrial Busses With High Voltage Transients
Industrial Automation
Telecom Infrastructure
Automotive
Power over Ethernet (PoE)
LED Lighting
Bias Power Supplies
The TPS7A4001 device is stable with any output
capacitance greater than 4.7 µF and any input
capacitance greater than 1 µF (over temperature and
tolerance). Therefore, implementations of this device
require minimal board space because of its
miniaturized packaging (HVSSOP) and a potentially
small output capacitor. In addition, the TPS7A4001
device offers an enable pin (EN) compatible with
standard CMOS logic to enable a low-current
shutdown mode.
The TPS7A4001 device has an internal thermal
shutdown and current limiting to protect the system
during fault conditions. The HVSSOP packages has
an operating temperature range of TJ = –40°C to
125°C.
In addition, the TPS7A4001 device is ideal for
generating a low-voltage supply from intermediate
voltage rails in telecom and industrial applications;
not only can it supply a well-regulated voltage rail, but
it can also withstand and maintain regulation during
very high and fast voltage transients. These features
translate to simpler and more cost-effective electrical
surge-protection circuitry for a wide range of
applications, including PoE, bias supply, and LED
lighting.
Device Information(1)
PART NUMBER
TPS7A4001
PACKAGE
HVSSOP (8)
BODY SIZE (NOM)
3.00 mm × 5.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Schematic
100 V
VIN
VIN
VOUT
OUT
IN
CIN
CBYP
TPS7A4001
VEN
R1
COUT
EN
GND
FB
R2
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS7A4001
SBVS162B – MARCH 2011 – REVISED JULY 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
4
5
6
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 8
7.1 Overview ................................................................... 8
7.2 Functional Block Diagram ......................................... 8
7.3 Feature Description................................................... 8
7.4 Device Functional Modes.......................................... 9
8
Application and Implementation ........................ 10
8.1 Application Information............................................ 10
8.2 Typical Application ................................................. 11
9 Power Supply Recommendations...................... 12
10 Layout................................................................... 13
10.1
10.2
10.3
10.4
Layout Guidelines .................................................
Layout Example ....................................................
Thermal Considerations ........................................
Power Dissipation .................................................
13
13
13
14
11 Device and Documentation Support ................. 15
11.1
11.2
11.3
11.4
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
15
15
15
15
12 Mechanical, Packaging, and Orderable
Information ........................................................... 15
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (March 2011) to Revision B
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................ 1
•
Changed Package from MSOP-8 to HVSSOP. ..................................................................................................................... 1
•
Changed TJ value for disabled mode operating mode from 165 to 170°C............................................................................. 9
•
Changed value from 35 to 45°C ........................................................................................................................................... 14
Changes from Original (March 2011) to Revision A
•
2
Page
Changed all 105 V to 100 V on page 1 .................................................................................................................................. 1
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5 Pin Configuration and Functions
DGN Package
8-Pin HVSSOP
Top View
OUT
FB
NC
GND
1
2
3
4
8
7
6
5
IN
NC
NC
EN
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
OUT
1
O
Regulator output. A capacitor > 4.7 µF must be tied from this pin to ground to assure stability.
FB
2
O
This pin is the input to the control-loop error amplifier. It is used to set the output voltage of the device.
—
Not internally connected. This pin must either be left open or tied to GND.
—
Ground
3
NC
6
7
GND
4
EN
5
I
This pin turns the regulator on or off.
If VEN ≥ VEN_HI the regulator is enabled.
If VEN ≤ VEN_LO, the regulator is disabled.
If not used, the EN pin can be connected to IN. Make sure that VEN ≤ VIN at all times.
IN
8
I
Input supply
PowerPAD
—
—
Solder to printed-circuit-board (PCB) to enhance thermal performance.
NOTE: The PowerPAD is internally connected to GND.
Although it can be left floating, TI highly recommends connecting the PowerPAD to the GND plane.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating junction temperature range (unless otherwise noted) (1)
MIN
MAX
–0.3
105
OUT pin to GND pin
–0.3
105
OUT pin to IN pin
–105
0.3
FB pin to GND pin
–0.3
2
FB pin to IN pin
–105
0.3
EN pin to IN pin
–105
0.3
EN pin to GND pin
–0.3
105
IN pin to GND pin
Voltage
Current
Peak output
Temperature
(1)
UNIT
V
Internally limited
Operating virtual junction, TJ
–40
125
Storage, Tstg
–65
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2500
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating junction temperature range (unless otherwise noted)
MIN
MAX
UNIT
7
100
V
1.161
90
V
VEN
0
100
V
IOUT
0
50
mA
VIN
VOUT
NOM
6.4 Thermal Information
TPS7A4001
THERMAL METRIC (1)
DGN (HVVSOP)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
66.7
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
54.1
°C/W
RθJB
Junction-to-board thermal resistance
38.1
°C/W
ψJT
Junction-to-top characterization parameter
2
°C/W
ψJB
Junction-to-board characterization parameter
37.8
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
15.5
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.5 Electrical Characteristics
At TJ = –40°C to 125°C, VIN = VOUT(NOM) + 2 V or VIN = 7 V (whichever is greater), VEN = VIN, IOUT = 100 µA, CIN = 1 μF, COUT = 4.7 μF, and
FB tied to OUT, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
100
V
1.173
1.185
V
VREF
90
V
–1
1
%VOUT
–2.5
2.5
%VOUT
VIN
Input voltage
VREF
Internal reference
TJ = 25°C, VFB = VREF, VIN = 9 V, IOUT = 25 mA
Output voltage range (1)
VIN ≥ VOUT(NOM) + 2 V
Nominal accuracy
TJ = 25°C, VIN = 9 V, IOUT = 25 mA
Overall accuracy
VOUT(NOM) + 2 V ≤ VIN ≤ 24 V (2)
100 µA ≤ IOUT ≤ 50 mA
D%VOUT
DVIN
Line regulation
7 V ≤ VIN ≤ 100 V
0.03
%VOUT
D%VOUT
DIOUT
Load regulation
100 µA ≤ IOUT ≤ 50 mA
0.31
%VOUT
VOUT
VDO
7
Dropout voltage
ILIM
Current limit
IGND
Ground current
ISHDN
Shutdown supply current
Feedback current
IEN
Enable current
VEN_HI
Enable high-level voltage
VEN_LO
Enable low- level voltage
VNOISE
Output noise voltage
PSRR
Power-supply rejection ratio
TSD
Thermal shutdown temperature
TJ
Operating junction temperature
(1)
(2)
(3)
(4)
VIN = 17 V, VOUT(NOM) = 18 V, IOUT = 20 mA
290
VIN = 17 V, VOUT(NOM) = 18 V, IOUT = 50mA
0.78
1.3
mV
V
VOUT = 90% VOUT(NOM), VIN = 7 V, TJ ≤ 85°C
51
117
200
mA
VOUT = 90% VOUT(NOM), VIN = 9 V
51
128
200
mA
7 V ≤ VIN ≤ 100 V, IOUT = 0 mA
25
65
μA
IOUT = 50 mA
25
VEN = 0.4 V
4.1
20
μA
0.01
0.1
µA
0.02
1
μA
1.5
VIN
V
0
0.4
V
(3)
IFB
1.161
–0.1
7 V ≤ VIN ≤ 100 V, VIN = VEN
μA
VIN = 12 V, VOUT(NOM) = VREF, COUT = 10 μF,
BW = 10 Hz to 100 kHz
58
μVRMS
VIN = 12 V, VOUT(NOM) = 5 V, COUT = 10 μF,
CBYP (4) = 10 nF, BW = 10 Hz to 100 kHz
73
μVRMS
VIN = 12 V, VOUT(NOM) = 5 V, COUT = 10 μF,
CBYP (4) = 10 nF, ƒ = 100 Hz
65
dB
Shutdown, temperature increasing
170
°C
Reset, temperature decreasing
150
–40
°C
125
°C
To ensure stability at no-load conditions, a current from the feedback resistive network greater than or equal to 10μA is required.
Maximum input voltage is limited to 24 V because of the package power dissipation limitations at full load (P ≈ (VIN – VOUT) × IOUT = (24
V – VREF) × 50 mA ≈ 1.14 W). The device is capable of sourcing a maximum current of 50 mA at higher input voltages as long as the
power dissipated is within the thermal limits of the package plus any external heatsinking.
IFB > 0 flows out of the device.
CBYP refers to a bypass capacitor connected to the FB and OUT pins.
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6.6 Typical Characteristics
At TJ = –40°C to 125°C, VIN = VOUT(NOM) + 2 V or VIN = 9 V (whichever is greater), VEN = VIN, IOUT = 100 µA, CIN = 1 μF, COUT =
4.7 μF, and FB tied to OUT, unless otherwise noted.
VIN = 12V, VOUT = 5V
DIOUT = 1mA®29mA®1mA
COUT = 10mF, CBYP = 10nF
VOUT = 5V, IOUT = 28mA, COUT = 10mF
VIN Slew Rate = 220V/ms
DVIN = 12V®55V
CBYP = 0nF
100mV/div
VOUT
VOUT
CBYP = 10nF
100mV/div
VOUT
50mV/div
VIN
IOUT
10mA/div
50V/div
Time (100ms/div)
Time (1ms/div)
Figure 1. Line Transient Response vs CBYP
Figure 2. Load Transient Response
10
1.275
− 40°C
+ 25°C
+ 85°C
7.5
+ 105°C
+ 125°C
− 40°C
+ 25°C
+ 85°C
1.225
2.5
VFB (V)
VOUT(NOM) (%)
5
+ 105°C
+ 125°C
0
1.175
−2.5
−5
1.125
−7.5
−10
5
15
25
35
45
55
65
Input Voltage (V)
75
85
95
105
1.075
5
Figure 3. Line Regulation
25
35
45
55
65
Input Voltage (V)
75
85
95
105
Figure 4. Feedback Voltage
100
100
− 40°C
+ 25°C
+ 85°C
+ 105°C
+ 125°C
80
60
90
80
70
IFB (nA)
Isub (GND)
15
40
60
50
40
30
20
20
10
IOUT = 0mA
0
5
15
25
35
45
55
65
Input Voltage (V)
75
85
95
105
0
−40 −25 −10
Figure 5. Ground Current vs Input Voltage
6
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5
20 35 50 65
Temperature (°C)
80
95
110 125
Figure 6. Feedback Current
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Typical Characteristics (continued)
At TJ = –40°C to 125°C, VIN = VOUT(NOM) + 2 V or VIN = 9 V (whichever is greater), VEN = VIN, IOUT = 100 µA, CIN = 1 μF, COUT =
4.7 μF, and FB tied to OUT, unless otherwise noted.
100
2
− 40°C
+ 25°C
+ 85°C
+ 105°C
+ 125°C
90
80
60
50
40
+ 105°C
+ 125°C
1.5
1.25
VDROP (V)
IGND (µA)
70
− 40°C
+ 25°C
+ 85°C
1.75
1
0.75
30
0.5
20
0.25
10
0
0
10
20
30
Output Current (mA)
40
0
50
0
10
Figure 7. Ground Current vs Output Voltage
20
30
Output Current (mA)
40
50
Figure 8. Dropout Voltage
2.5
10
2
Noise (µV/ Hz)
VEN (V)
1
1.5
Vsub (EN_HI)
1
0.1
VIN = 12V
VOUT = VREF
COUT = 10µF
CBYP = 10nF
0.01
0.5
Vsub (EN_LO)
0
−40 −25 −10
5
20 35 50 65
Temperature (°C)
80
95
110 125
0.001
10
Figure 9. Enable Threshold Voltage
100
IOUT = 100µA,VNOISE = 60µVRMS
IOUT = 50mA,VNOISE = 100µVRMS
1k
10k
100k
Frequency (Hz)
1M
10M
Figure 10. Output Spectral Noise Density
200
100
90
160
80
PSRR (dB)
ICL (mA)
70
120
80
− 40°C
+ 25°C
+ 85°C
+ 105°C
+ 125°C
40
0
6
9
12
15
18
Input Voltage (V)
Figure 11. Current Limit
21
24
60
50
40
30
VIN = 12V
VOUT = 5V
COUT = 10µF
CBYP = 10nF
20
10
0
10
100
IOUT = 50mA
IOUT = 100µA
1k
10k
100k
Frequency (Hz)
1M
10M
Figure 12. Power-Supply Rejection Ratio
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7 Detailed Description
7.1 Overview
The TPS7A4001 device belongs to a new generation of linear regulators that use an innovative BiCMOS process
technology to achieve very high maximum input and output voltages.
This process not only allows the TPS7A4001 device to maintain regulation during very fast high-voltage
transients up to 105 V, but it also allows the TPS7A4001 device to regulate from a continuous high-voltage input
rail. Unlike other regulators created using bipolar technology, the ground current of the TPS7A4001 device is
also constant over its output current range, resulting in increased efficiency and lower power consumption.
These features, combined with a high thermal performance HVSSOP PowerPAD package, make this device
ideal for industrial and telecom applications.
7.2 Functional Block Diagram
IN
OUT
UVLO
Pass
Device
Thermal
Shutdown
Current
Limit
Enable
Error
Amp
EN
FB
7.3 Feature Description
7.3.1 Internal Current Limit
The fixed internal current limit of the TPS7A4001 device helps protect the regulator during fault conditions. The
maximum amount of current the device can source is the current limit (309 mA, typical), and is largely
independent of output voltage. For reliable operation, the device does not operate in current limit for extended
periods of time.
7.3.2 Enable Pin Operation
The TPS7A4001 device provides an enable pin (EN) feature that turns on the regulator when VEN > VEN_HI, and
disables the regulator when VEN < VEN_LO.
7.3.3 Thermal Protection
Thermal protection disables the output when the junction temperature rises to approximately 170°C, allowing the
device to cool. When the junction temperature cools to approximately 150°C, the output circuitry is enabled.
Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may
cycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage as a result of
overheating.
Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate
heatsink. For reliable operation, limit junction temperature to a maximum of 125°C. To estimate the margin of
safety in a complete design (including heatsink), increase the ambient temperature until the thermal protection is
triggered; use worst-case loads and signal conditions. For good reliability, trigger thermal protection at least 35°C
above the maximum expected ambient condition of your particular application. This configuration produces a
worst-case junction temperature of 125°C at the highest expected ambient temperature and worst-case load.
8
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Feature Description (continued)
The internal protection circuitry of the TPS7A4001 device has been designed to protect against overload
conditions. The protection circuitry was not intended to replace proper heatsinking. Continuously running the
TPS7A4001 device into thermal shutdown degrades device reliability.
7.3.4 Undervoltage Lockout (UVLO)
The TPS7A4001 contains an Undervoltage Lockout comparator that ensures the error amplifier is disabled when
the input voltage is below the required minimum operational voltage. The minimum recommended operational
voltage is 7 V.
7.4 Device Functional Modes
7.4.1 Normal Operation
The device regulates to the nominal output voltage under the following conditions:
• The input voltage is at least as high as VIN(min).
• The input voltage is greater than the nominal output voltage added to the dropout voltage.
• The enable voltage has previously exceeded the enable rising threshold voltage and has not decreased
below the enable falling threshold.
• The output current is less than the current limit.
• The device junction temperature is less than the maximum specified junction temperature.
7.4.2 Dropout Operation
If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other
conditions are met for normal operation, the device operates in dropout mode. In this mode of operation, the
output voltage is the same as the input voltage minus the dropout voltage. The transient performance of the
device is significantly degraded because the pass device (as a bipolar junction transistor, or BJT) is in saturation
and no longer controls the current through the LDO. Line or load transients in dropout can result in large output
voltage deviations.
7.4.3 Disabled
The device is disabled under the following conditions:
• The enable voltage is less than the enable falling threshold voltage or has not yet exceeded the enable rising
threshold.
• The device junction temperature is greater than the thermal shutdown temperature.
Table 1 lists the conditions that lead to the different modes of operation.
Table 1. Device Functional Mode Comparison
PARAMETER
OPERATING MODE
VIN
VEN
IOUT
TJ
Normal mode
VIN > VOUT(nom) + VDO and
VIN > VIN(min)
VEN > VEN_HI
IOUT < ILIM
T J < 125°C
Dropout mode
VIN(min) < VIN < VOUT(nom) + VDO
VEN > VEN_HI
—
TJ < 125°C
—
VEN < VEN_LO
—
TJ > 170°C
Disabled mode
(any true condition disables the device)
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
One of the primary applications of the TPS7A4001 device is to provide transient voltage protection to sensitive
circuitry that may be damaged in the presence of high-voltage spikes.
This transient voltage protection can be more cost-effective and compact compared to topologies that use a
transient voltage suppression (TVS) block.
8.1.1 Adjustable Operation
The TPS7A4001 device has an output voltage range of about 1.175 to 90 V. The nominal output voltage of the
device is set by two external resistors, as shown in Figure 13.
VOUT
VIN
CIN
10 µF
OUT
IN
CBYP
10 nF
TPS7A4001
EN
GND
R1
FB
COUT
10 µF
R2
Figure 13. Adjustable Operation for Maximum AC Performance
Calculate R1 and R2 for any output voltage range using the formula shown in Equation 1. To ensure stability
under no-load conditions, this resistive network must provide a current ≥ 10 μA.
VOUT
VOUT
³ 10mA
R1 = R2
- 1 , where
R1 + R2
VREF
(1)
If greater voltage accuracy is required, consider the output voltage offset contributions because of the feedback
pin current and use 0.1% tolerance resistors.
10
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8.2 Typical Application
VIN
CIN
10 µF
VEN
CBYP
10 nF
TPS7A4001
EN
VOUT
OUT
IN
R1
FB
GND
Where:
COUT
10 µF
VOUT
≥10 µA, and
R1 + R2
R1 = R2
R2
VOUT
–1
VREF
Figure 14. Example Circuit to Maximize Transient Performance
8.2.1 Design Requirements
For this design example, use the following parameters listed in Table 2.
Table 2. Design Parameters
PARAMETER
VALUE
VIN
12 V, with 55 V surge tolerance
VOUT
5 V (ideal), 4.981 (actual)
IOUT
28 mA
Accuracy
5%
R1, R2
162 kΩ, 49.9 kΩ
8.2.2 Detailed Design Procedure
The maximum value of total feedback resistance can be calculated to be 500 kΩ. Equation 1 was used to
calculate R1 and R2, and standard 1% resistors were selected to keep the accuracy within the 5% allocation. 10uF ceramic input and output capacitors were selected, along with a 10-nF bypass capacitor for optimal AC
performance.
8.2.2.1 Capacitor Recommendations
Low equivalent series resistance (ESR) capacitors should be used for the input, output, and bypass capacitors.
Ceramic capacitors with X7R and X5R dielectrics are required. Ceramic X7R capacitors offer improved voltage
and temperature coefficients, while ceramic X5R capacitors are the most cost-effective and are available in
higher values.
NOTE
High ESR capacitors may degrade PSRR.
8.2.2.2 Input and Output Capacitor Requirements
The TPS7A4001 device high voltage linear regulator achieves stability with a minimum output capacitance of 4.7
µF and input capacitance of 1 µF; however, TI highly recommends to use 10-μF output and input capacitors to
maximize AC performance.
8.2.2.3 Bypass Capacitor Requirements
Although a bypass capacitor (CBYP) is not needed to achieve stability, TI highly recommends using a 10-nF
bypass capacitor to maximize AC performance (including line transient, noise, and PSRR). For additional
information regarding the performance improvements of using a bypass capacitor, see .
8.2.2.4 Transient Response
As with any regulator, increasing the size of the output capacitor reduces overshoot and undershoot magnitude
but increases the duration of the transient response.
The presence of the CBYP capacitor may greatly improve the line transient response of the TPS7A4001 device,
as shown in Figure 1.
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8.2.3 Application Curves
VIN = 12V, VOUT = 5V
DIOUT = 1mA®29mA®1mA
COUT = 10mF, CBYP = 10nF
VOUT = 5V, IOUT = 28mA, COUT = 10mF
VIN Slew Rate = 220V/ms
DVIN = 12V®55V
CBYP = 0nF
100mV/div
CBYP = 10nF
100mV/div
VOUT
VOUT
50mV/div
VOUT
VIN
IOUT
10mA/div
50V/div
Time (100ms/div)
Time (1ms/div)
Figure 15. Line Transient Response vs CBYP
Figure 16. Load Transient Response
9 Power Supply Recommendations
The input supply for the LDO should not exceed its recommended operating conditions (7 V to 100 V). The input
voltage should provide adequate headroom for the device to have a regulated output. If the input supply is noisy,
additional input capacitors with low ESR can help improve the output noise performance. The input and output
supplies should also be bypassed with 10-µF capacitors located near the input and output pins. There should be
no other components located between these capacitors and the pins.
12
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10 Layout
10.1 Layout Guidelines
10.1.1 Board Layout Recommendations to Improve PSRR and Noise Performance
To improve AC performance such as PSRR, output noise, and transient response, TI recommends designing the
board with separate ground planes for IN and OUT, with each ground plane connected only at the GND pin of
the device. In addition, the ground connection for the output capacitor should connect directly to the GND pin of
the device.
Equivalent series inductance (ESL) and ESR must be minimized to maximize performance and ensure stability.
Every capacitor (CIN, COUT, CBYP) must be placed as close as possible to the device and on the same side of the
PCB as the regulator itself.
Do not place any of the capacitors on the opposite side of the PCB from where the regulator is installed. The use
of vias and long traces is strongly discouraged because they may impact system performance negatively and
even cause instability.
If possible, and to ensure the maximum performance denoted in this product data sheet, use the same layout
pattern used for the TPS7A40 evaluation board, available at www.ti.com.
10.2 Layout Example
Input GND Plane
Vout
Cin
Sense Line
OUT
1
FB
2
NC
3
GND
4
8
IN
7
NC
6
NC
5
EN
R1
Cout
R2
Thermal
Pad
Vin
Output GND Plane
Figure 17. Recommended Layout Example
10.3 Thermal Considerations
Thermal protection disables the output when the junction temperature rises to approximately 170°C, allowing the
device to cool. When the junction temperature cools to approximately 150°C, the output circuitry is enabled.
Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may
cycle ON and OFF. This cycling limits the dissipation of the regulator, protecting it from damage as a result of
overheating.
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Thermal Considerations (continued)
Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate
heatsink. For reliable operation, junction temperature should be limited to a maximum of 125°C. To estimate the
margin of safety in a complete design (including heatsink), increase the ambient temperature until the thermal
protection is triggered; use worst-case loads and signal conditions. For good reliability, thermal protection should
trigger at least 45°C above the maximum expected ambient condition of the particular application. This
configuration produces a worst-case junction temperature of 125°C at the highest expected ambient temperature
and worst-case load.
The internal protection circuitry of the TPS7A4001 has been designed to protect against overload conditions. It
was not intended to replace proper heatsinking. Continuously running the TPS7A4001 device into thermal
shutdown degrades device reliability.
10.4 Power Dissipation
The ability to remove heat from the die is different for each package type, presenting different considerations in
the PCB layout. The PCB area around the device that is free of other components moves the heat from the
device to the ambient air. Using heavier copper increases the effectiveness in removing heat from the device.
The addition of plated through-holes to heat dissipating layers also improves the heatsink effectiveness.
Power dissipation depends on input voltage and load conditions. Power dissipation (PD) is equal to the product of
the output current times the voltage drop across the output pass element, as shown in Equation 2:
PD = (VIN - VOUT) IOUT
(2)
14
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11 Device and Documentation Support
11.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.2 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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6-Feb-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPS7A4001DGNR
ACTIVE
HVSSOP
DGN
8
2500
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
QVQ
TPS7A4001DGNT
ACTIVE
HVSSOP
DGN
8
250
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
QVQ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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