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TPS7A8018DRBT

TPS7A8018DRBT

  • 厂商:

    BURR-BROWN(德州仪器)

  • 封装:

    VSON-8_3X3MM-EP

  • 描述:

    TPS7A80 LOW-NOISE, HIGH-BANDWIDT

  • 数据手册
  • 价格&库存
TPS7A8018DRBT 数据手册
Product Folder Order Now Support & Community Tools & Software Technical Documents Reference Design TPS7A80 SBVS135J – JUNE 2010 – REVISED JANUARY 2018 TPS7A80 Low-Noise, Wide-Bandwidth, High PSRR, Low-Dropout 1-A Linear Regulator 1 Features 3 Description • • • • The TPS7A80 family of low-dropout linear regulators (LDOs) offer very high power-supply ripple rejection (PSRR) at the output. This LDO family uses an advanced BiCMOS process and a PMOSFET pass device to achieve very low noise, excellent transient response, and excellent PSRR performance. 1 • • • • • • • Low-Dropout 1-A Regulator With Enable Adjustable Output Voltages: 0.8 V to 6 V Fixed Output Voltages: 0.8 V to 6 V Wide-Bandwidth High PSRR: – 63 dB at 1 kHz – 57 dB at 100 kHz – 38 dB at 1 MHz Low Noise: (14 × VOUT ) μVRMS Typical (100 Hz to 100 kHz) Stable with a 4.7-μF Ceramic Capacitor Excellent Load/Line Transient Response 3% Overall Accuracy (Over Load/Line/Temp) Overcurrent and Overtemperature Protection Very Low Dropout: 170 mV Typical at 1 A 3-mm × 3-mm VSON-8 DRB Package The TPS7A80 family is stable with a 4.7-μF ceramic output capacitor, and uses a precision voltage reference and feedback loop to achieve a worst-case accuracy of 3% over all load, line, process, and temperature variations. This family is fully specified over the temperature range of TJ = –40°C to +125°C, and is offered in a 3mm × 3-mm, VSON-8 package with a thermal pad. Device Information(1) PART NUMBER TPS7A80 BODY SIZE (NOM) 3.00 mm × 3.00 mm (1) For all available packages, see the package option addendum at the end of the data sheet. 2 Applications • • • PACKAGE VSON (8) Telecom Infrastructure Audio High-Speed I/F (PLL/VCO) Typical Application Diagram Optional 1.0mF input capacitor. May improve source impedance, noise, or PSRR. VIN IN R1 TPS7A8001 EN FB GND VEN VOUT OUT NR 4.7mF Ceramic R2 To avoid inrush current, it is recommended to always connect a 1nF to 10nF capacitor 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPS7A80 SBVS135J – JUNE 2010 – REVISED JANUARY 2018 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 4 5 6.1 6.2 6.3 6.4 6.5 6.6 5 5 5 5 6 7 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Typical Characteristics .............................................. Detailed Description ............................................ 12 7.1 Overview ................................................................. 12 7.2 Functional Block Diagram ....................................... 12 7.3 Feature Description................................................. 13 7.4 Device Functional Modes........................................ 14 8 Application and Implementation ........................ 15 8.1 Application Information............................................ 15 8.2 Typical Application .................................................. 15 9 Power Supply Recommendations...................... 18 10 Layout................................................................... 18 10.1 Layout Guidelines ................................................. 18 10.2 Layout Example .................................................... 21 11 Device and Documentation Support ................. 22 11.1 11.2 11.3 11.4 11.5 11.6 Documentation Support ........................................ Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 22 22 22 22 22 22 12 Mechanical, Packaging, and Orderable Information ........................................................... 22 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision I (August 2015) to Revision J Page • Added new fixed voltage devices and associated content to data sheet .............................................................................. 1 • Changed device name to generic part number to show new fixed voltage device options ................................................... 1 • Added SNS pin and description to Pin Functions table ......................................................................................................... 4 • Changed TA to TJ in Recommended Operating Conditions table .......................................................................................... 5 • Added fixed-voltage-version values to Electrical Characteristics table ................................................................................. 6 • Added test conditions to VNR parameter in Electrical Characteristics table ........................................................................... 6 • Added new note (3) to output accuracy parameter in Electrical Characteristics table........................................................... 6 • Deleted typical value for ISHDN in Electrical Characteristics table .......................................................................................... 6 Changes from Revision H (January 2013) to Revision I Page • Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ................................................................................................. 1 • Deleted "Fixed Output Voltages: 0.8 V to 5 V Using Innovating Facatory EEPROM Programming" bullet from Features ... 1 • Changed "12.6" to "14" in Low Noise bullet ........................................................................................................................... 1 • Deleted SNS row from Pin Functions table ........................................................................................................................... 4 • Deleted fixed version from VOUT row in Electrical Characteristics ......................................................................................... 6 • Deleted ISNS row from Electrical Characteristics ................................................................................................................. 6 Changes from Revision G (April 2012) to Revision H • 2 Page Updated Figure 8.................................................................................................................................................................... 7 Submit Documentation Feedback Copyright © 2010–2018, Texas Instruments Incorporated Product Folder Links: TPS7A80 TPS7A80 www.ti.com SBVS135J – JUNE 2010 – REVISED JANUARY 2018 Changes from Revision F (March 2012) to Revision G • Page Changed Thermal Information table values, added new footnote 2, changed footnote 3...................................................... 5 Changes from Revision E (February 2012) to Revision F Page • Changed Low Noise Features bullet ...................................................................................................................................... 1 • Updated Equation 3.............................................................................................................................................................. 17 Changes from Revision D (December 2010) to Revision E Page • Changed Low Noise Features bullet ...................................................................................................................................... 1 • Changed caption of front-page application circuit .................................................................................................................. 1 • Updated Figure 12.................................................................................................................................................................. 7 • Updated Figure 26................................................................................................................................................................ 10 • Added Equation 1 note in Start-up section........................................................................................................................... 14 • Updated Equation 3.............................................................................................................................................................. 17 Changes from Revision C (September, 2010) to Revision D Page • Updated front-page figure with new characteristic graph ....................................................................................................... 1 • Revised Figure 17 .................................................................................................................................................................. 8 • Changed Figure 18................................................................................................................................................................. 8 Changes from Revision B (August, 2010) to Revision C Page • Changed data sheet title......................................................................................................................................................... 1 • Changed ultra-high PSRR to wide-bandwidth lhgh PSRR in Features list ............................................................................ 1 • Corrected typos in Figure 21 through Figure 23 .................................................................................................................... 9 • Revised first paragraph of Application Information to remove phrase ultra-wide bandwidth ............................................... 15 Submit Documentation Feedback Copyright © 2010–2018, Texas Instruments Incorporated Product Folder Links: TPS7A80 3 TPS7A80 SBVS135J – JUNE 2010 – REVISED JANUARY 2018 www.ti.com 5 Pin Configuration and Functions DRB Package 8-Pin VSON Top View OUT 1 8 IN OUT 2 7 IN FB/SNS 3 6 NR GND 4 5 EN Pin Functions PIN NAME NO. I/O DESCRIPTION EN 5 I Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts the regulator into shutdown mode. Refer to Shutdown in the Application and Implementation section for more details. EN must not be left floating and can be connected to IN if not used. FB/SNS 3 I FB (adjustable version only): This pin is the input to the control loop error amplifier and is used to set the output voltage of the device. SNS (fixed versions only): Output voltage sense pin. (1) GND 4, pad — IN 7, 8 I Unregulated input supply. OUT 1, 2 O Regulator output. A 4.7-μF or larger capacitor of any type is required for stability. 6 — Connect an external capacitor between this pin and ground to reduce output noise to very low levels. Also, the capacitor slows down the VOUT ramp (RC softstart). NR (1) 4 Ground. In order to minimize the trace resistive drop, connect the SNS pin close to the load, and make sure that the trace inductance to the load is also minimized. Submit Documentation Feedback Copyright © 2010–2018, Texas Instruments Incorporated Product Folder Links: TPS7A80 TPS7A80 www.ti.com SBVS135J – JUNE 2010 – REVISED JANUARY 2018 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) Voltage Current (2) MAX –0.3 7 FB, NR –0.3 3.6 EN –0.3 VIN + 0.3 (2) OUT –0.3 7 OUT Temperature (1) MIN IN UNIT V Internally Limited Operating virtual junction, TJ –55 150 Operating free air temperature, TA –40 125 Storage, Tstg –55 150 A °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. VEN absolute maximum rating is VIN + 0.3 V or 7 V, whichever is smaller. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) ±2000 Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2) ±500 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN MAX 2.2 6.5 UNIT VIN Input voltage (1) IOUT Output current 0 1 A TJ Operating junction temperature –40 125 °C TA Operating free air temperature –40 125 °C (1) V Minimum VIN = VOUT + VDO or 2.2 V, whichever is greater. 6.4 Thermal Information TPS7A80 THERMAL METRIC (1) (2) DRB (VSON) (3) UNIT 8 PINS RθJA Junction-to-ambient thermal resistance 47.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 53.9 °C/W RθJB Junction-to-board thermal resistance 23.4 °C/W ψJT Junction-to-top characterization parameter 1 °C/W ψJB Junction-to-board characterization parameter 23.5 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 7.4 °C/W (1) (2) (3) For information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator. Thermal data for the DRB package are derived by thermal simulations based on JEDEC-standard methodology as specified in the JESD51 series. The following assumptions are used in the simulations: (a) The exposed pad is connected to the PCB ground layer through a 2 × 2 thermal via array. (b) The top and bottom copper layers are assumed to have a 5% thermal conductivity of copper representing a 20% copper coverage. (c) This data were generated with only a single device at the center of a JEDEC high-K (2s2p) board with 3 inches × 3 inches copper area. To understand the effects of the copper area on thermal performance, refer to the Power Dissipation and Estimating Junction Temperature sections. Submit Documentation Feedback Copyright © 2010–2018, Texas Instruments Incorporated Product Folder Links: TPS7A80 5 TPS7A80 SBVS135J – JUNE 2010 – REVISED JANUARY 2018 www.ti.com 6.5 Electrical Characteristics At TJ = –40°C to +125°C, VIN = VOUT(TYP) + 0.5 V or 2.2 V (whichever is greater), IOUT = 1 mA, VEN = 2.2 V, COUT = 4.7 μF, and CNR = 0.01 μF (unless otherwise noted). TPS7A8001 tested at VOUT = 0.8 V and VOUT = 6 V. Typical values are at TJ = 25°C. PARAMETER VNR Internal reference VOUT Output voltage Output accuracy (1) (2) MIN TYP MAX UNIT Adjustable and Fixed VOUT = 1.2 V TEST CONDITIONS 0.79 0.8 0.81 V Fixed VOUT ≥ 1.8 V 1.23 1.243 1.26 V Adjustable version only (TPS7A8001) 0.8 6 V Fixed versions only 1.2 5 V VOUT + 0.5 V ≤ VIN ≤ 6 V, VIN ≥ 2.5 V, 100 mA ≤ IOUT ≤ 500 mA, 0°C ≤ TJ ≤ 85°C –2% 2% VOUT + 0.5 V ≤ VIN ≤ 6.5 V, VIN ≥ 2.2 V, 100 mA ≤ IOUT ≤ 1 A –3% ΔVOUT/ΔVIN Line regulation VOUT(NOM) + 0.5 V ≤ VIN ≤ 6.5 V, VIN ≥ 2.2 V, IOUT = 100 mA ΔVOUT/ΔIOUT Load regulation 100 mA ≤ IOUT ≤ 1 A Dropout voltage (3) VDO ICL Output current limit IGND Ground pin current 2 mV VOUT + 0.5 V ≤ VIN ≤ 6.5 V, VIN ≥ 2.5 V, IOUT = 750 mA, VFB = GND or VSNS = GND 350 mV VOUT + 0.5 V ≤ VIN ≤ 6.5 V, VIN ≥ 2.5 V, IOUT = 1 A, VFB = GND or VSNS = GND 500 mV VOUT = 0.85 × VOUT(NOM), VIN ≥ 3.3 V Adjustable 1100 Fixed 1100 μA 120 μA IOUT = 1 A 350 μA 2 μA 1 μA VIN = 6.5 V, VFB = 0.8 V VIN = 4.3 V, VOUT = 3.3 V, IOUT = 750 mA BW = 100 Hz to 100 kHz, VIN = 4.3 V, VOUT = 3.3 V, IOUT = 100 mA 48 dB f = 1 kHz 63 dB f = 10 kHz 63 dB f = 100 kHz 57 dB f = 1 MHz 38 dB CNR = 0.001 μF 14.6 × VOUT μVRMS CNR = 0.01 μF 14.3 × VOUT μVRMS 13.9 × VOUT μVRMS CNR = 0.1μF V 3.6 V < VIN ≤ 6.5 V, RL = 1 kΩ 1.35 V VEN(LO) Enable low (shutdown) IEN(HI) Enable pin current, enabled VIN = VEN = 6.5 V tSTR Start-up time VOUT(NOM) = 3.3 V, VOUT = 0%–90% VOUT(NOM), RL = 3.3 kΩ, COUT = 4.7 μF UVLO Undervoltage lockout VIN rising, RL = 1 kΩ UVLO hysteresis VIN falling, RL = 1 kΩ Thermal shutdown temperature 6 f = 100 Hz 1.2 Enable high (enabled) (3) 0.02 2.2 V ≤ VIN ≤ 3.6 V, RL = 1 kΩ VEN(HI) (2) mA 100 Feedback pin current (TPS7A8001) (1) 2000 2000 60 IFB TSD 1400 IOUT = 1 mA, fixed versions only VEN ≤ 0.4 V, VIN ≥ 2.2 V, RL = 1 kΩ, 0°C ≤ TJ ≤ 85°C Output noise voltage μV/mA 250 Shutdown current (IGND) VN μV/V VOUT + 0.5 V ≤ VIN ≤ 6.5 V, VIN ≥ 2.2 V, IOUT = 500 mA, VFB = GND or VSNS = GND ISHDN Power-supply rejection ratio 3% 150 IOUT = 1 mA, adjustable version only PSRR ±0.3% RL = 1 kΩ 0 0.02 0.4 V 1 μA CNR = 1 nF 0.1 ms CNR = 10 nF 1.6 ms 1.86 2 2.10 V 75 mV Shutdown, temperature increasing 160 °C Reset, temperature decreasing 140 °C The TPS7A8001 (adjustable) does not include external resistor tolerances and is not tested at these conditions: VOUT = 0.8 V, 4.5 V ≤ VIN ≤ 6.5 V, and 750 mA ≤ IOUT ≤ 1 A because power dissipation is higher than maximum rating of the package. The TPS7A8012, TPS7A8018, and TPS7A8033 are not tested at these conditions: 4.5 V ≤ VIN ≤ 6.5 V, and 750 mA ≤ IOUT ≤ 1 A because power dissipation is higher than maximum rating of the package. VDO is not measured for fixed output voltage devices with VOUT < 1.7 V because minimum VIN = 2.2 V. Submit Documentation Feedback Copyright © 2010–2018, Texas Instruments Incorporated Product Folder Links: TPS7A80 TPS7A80 www.ti.com SBVS135J – JUNE 2010 – REVISED JANUARY 2018 6.6 Typical Characteristics At VOUT(TYP) = 3.3 V, VIN = VOUT(TYP) + 0.5 V or 2.2 V (whichever is greater), IOUT = 100 mA, VEN = VIN, CIN = 1 μF, COUT = 4.7 μF, and CNR = 0.01 μF, all temperature values refer to TJ (unless otherwise noted). 3.399 3.399 +125°C +85°C +25°C 0°C -40°C 3.366 3.366 3.333 VOUT (V) VOUT (V) 3.333 +125°C +85°C +25°C 0°C -40°C 3.3 3.267 3.3 3.267 3.234 3.234 NOTE: Y axis shows 1% VOUT per division NOTE: Y axis shows 1% VOUT per division 3.201 3.201 0 100 200 300 400 500 600 700 800 900 1000 IOUT (mA) 0 0.824 +125°C +85°C +25°C 0°C -40°C 20 25 VOUT = 0.8V IOUT = 5mA 0.816 +125°C +85°C +25°C 0°C -40°C 0.808 VOUT (V) VOUT (V) 0.818 0.8 0.792 0.8 0.792 0.784 0.784 NOTE: Y axis shows 1% VOUT per division NOTE: Y axis shows 1% VOUT per division 0.776 0.776 2.2 2.6 3 3.4 3.8 4.2 4.6 VIN (V) 5 5.4 5.8 6.2 2.2 6.6 Figure 3. Line Regulation 500 2.6 3 3.4 3.8 4.2 4.6 VIN (V) 5 5.4 5.8 6.2 6.6 Figure 4. Line Regulation Under Light Loads 500 IOUT = 1A 450 +125°C +85°C +25°C 0°C -40°C 400 350 300 250 200 IOUT = 750mA 450 +125°C +85°C +25°C 0°C -40°C 400 350 VDO (V) VDO (V) 15 Figure 2. Load Regulation Under Light Loads VOUT = 0.8V IOUT = 750mA 0.816 10 IOUT (mA) Figure 1. Load Regulation 0.824 5 300 250 200 150 150 100 100 50 50 0 0 2 2.5 3 3.5 4 4.5 VIN (V) 5 5.5 6 Figure 5. Dropout Voltage vs Input Voltage 6.5 2 2.5 3 3.5 4 4.5 VIN (V) 5 5.5 6 6.5 Figure 6. Dropout Voltage vs Input Voltage Submit Documentation Feedback Copyright © 2010–2018, Texas Instruments Incorporated Product Folder Links: TPS7A80 7 TPS7A80 SBVS135J – JUNE 2010 – REVISED JANUARY 2018 www.ti.com Typical Characteristics (continued) At VOUT(TYP) = 3.3 V, VIN = VOUT(TYP) + 0.5 V or 2.2 V (whichever is greater), IOUT = 100 mA, VEN = VIN, CIN = 1 μF, COUT = 4.7 μF, and CNR = 0.01 μF, all temperature values refer to TJ (unless otherwise noted). 500 500 IOUT = 500mA 450 +125°C +85°C +25°C 0°C -40°C 400 300 250 200 350 300 250 200 150 150 100 100 50 50 0 0 2 2.5 3 3.5 4 4.5 VIN (V) 5 5.5 6 6.5 0 100 200 300 400 500 600 700 800 900 1000 IOUT (mA) Figure 8. Dropout Voltage vs Load Current Figure 7. Dropout Voltage vs Input Voltage 500 300 VIN = 3.6V 450 IOUT = 1000mA IOUT = 750mA IOUT = 5mA 400 250 200 300 IGND (mA) VDO (V) 350 250 200 150 100 50 50 0 0 -40 -25 -10 5 20 35 50 65 Temperature (°C) 80 95 VOUT = 0.8V IOUT = 750mA 2.2 110 125 Figure 9. Dropout Voltage vs Temperature 2.6 3 3.4 3.8 4.2 4.6 VIN (V) 5 5.4 5.8 6.2 6.6 Figure 10. Ground Pin Current vs Input Voltage 2 300 VIN = 2.2V VIN = 2.5V VIN = 3V VIN = 3.3V 1.8 250 1.6 1.4 ISHDN (mA) 200 IGND (mA) +125°C +85°C +25°C 0°C -40°C 100 150 150 +125°C +85°C +25°C 0°C -40°C 100 50 VIN = 5V VIN = 5.5V VIN = 6V VIN = 6.6V 1.2 1 0.8 0.6 0.4 0.2 VEN = 0.4V 0 0 0 100 200 300 400 500 600 700 800 900 1000 IOUT (mA) Figure 11. Ground Pin Current vs Load Current 8 +125°C +85°C +25°C 0°C -40°C 400 VDO (V) VDO (V) 350 VIN = 3.6V 450 -40 -25 -10 5 20 35 50 65 Temperature (°C) 80 95 110 125 Figure 12. Shutdown Current vs Temperature Submit Documentation Feedback Copyright © 2010–2018, Texas Instruments Incorporated Product Folder Links: TPS7A80 TPS7A80 www.ti.com SBVS135J – JUNE 2010 – REVISED JANUARY 2018 Typical Characteristics (continued) At VOUT(TYP) = 3.3 V, VIN = VOUT(TYP) + 0.5 V or 2.2 V (whichever is greater), IOUT = 100 mA, VEN = VIN, CIN = 1 μF, COUT = 4.7 μF, and CNR = 0.01 μF, all temperature values refer to TJ (unless otherwise noted). 1800 90 1600 80 1400 70 PSRR (dB) ICL (mA) 1200 1000 800 600 VIN = 2.2V VIN = 3.8V VIN = 5.5V VIN = 6.5V 400 200 VOUT = VIN - 0.5V 0 50 40 30 IOUT = 100mA No CIN 20 5 20 35 50 65 Temperature (°C) 80 95 110 125 10 Figure 13. Current Limit vs Temperature 90 80 80 70 70 60 60 50 40 IOUT = 10mA IOUT = 100mA IOUT = 750mA IOUT = 1A 30 20 10 100 VDO = 1.0V No CIN 1k 10k 100k Frequency (Hz) 1M 1k 10k 100k Frequency (Hz) 1M 10M VDO = 0.5V No CIN 50 40 IOUT = 10mA IOUT = 100mA IOUT = 750mA IOUT = 1A 30 10 100 Figure 14. Power-Supply Ripple Rejection vs Frequency 90 PSRR (dB) PSRR (dB) 60 10 -40 -25 -10 20 10 10M 10 100 1k 10k 100k Frequency (Hz) 1M 10M Figure 15. Power-Supply Ripple Rejection vs Frequency Figure 16. Power-Supply Ripple Rejection vs Frequency 90 90 80 80 70 70 60 60 PSRR (dB) PSRR (dB) VDO = 1.0V VDO = 0.5V VDO = 0.3V 50 40 IOUT = 10mA IOUT = 100mA IOUT = 750mA IOUT = 1A 30 20 VDO = 1.0V COUT = 100mF No CIN 10 10 100 1k 10k 100k Frequency (Hz) 1M 10M Figure 17. Power-Supply Ripple Rejection vs Frequency 50 40 IOUT = 10mA IOUT = 100mA IOUT = 750mA IOUT = 1A 30 20 VDO = 0.5V COUT = 100mF No CIN 10 10 100 1k 10k 100k Frequency (Hz) 1M 10M Figure 18. Power-Supply Ripple Rejection vs Frequency Submit Documentation Feedback Copyright © 2010–2018, Texas Instruments Incorporated Product Folder Links: TPS7A80 9 TPS7A80 SBVS135J – JUNE 2010 – REVISED JANUARY 2018 www.ti.com Typical Characteristics (continued) At VOUT(TYP) = 3.3 V, VIN = VOUT(TYP) + 0.5 V or 2.2 V (whichever is greater), IOUT = 100 mA, VEN = VIN, CIN = 1 μF, COUT = 4.7 μF, and CNR = 0.01 μF, all temperature values refer to TJ (unless otherwise noted). 90 80 70 70 60 60 50 40 f = 1kHz f = 10kHz f = 100kHz f = 1MHz 30 20 IOUT = 750mA No CIN 80 PSRR (dB) PSRR (dB) 90 IOUT = 100mA No CIN 50 40 f = 1kHz f = 10kHz f = 100kHz f = 1MHz 30 20 10 10 0 0.5 1 1.5 2 VDO (V) 2.5 3 0 3.5 0.5 100 RMS Noise (100Hz to 100kHz) 47.95mVRMS (COUT = 4.7mF) 47.33mVRMS (COUT = 22mF) 47.42mVRMS (COUT = 47mF) VDO = 0.5V IOUT = 100mA 10 1 0.1 COUT = 4.7mF COUT = 22mF COUT = 47mF 0.01 10 100 1k Frequency (Hz) 10k 100k 100 10 IOUT = 10mA IOUT = 100mA IOUT = 750mA 0.1 CNR = 1nF CNR = 10nF CNR = 100nF 0.01 100 1k Frequency (Hz) 10k 100k 1000 RLOAD = 1kW 100 10 1 0.1 0.01 10 100 1k Frequency (Hz) 10k 100k 1 10 100 1000 CNR (nF) Figure 23. Output Spectral Noise Density vs Frequency 10 3.5 1 10 EN to 90% VOUT (ms) Output Spectral Noise Density (mV/ÖHz) 1 0.1 3 Figure 22. Output Spectral Noise Density vs Frequency RMS Noise (100Hz to 100kHz) 92.07mVRMS (IOUT = 10mA) 47.95mVRMS (IOUT = 100mA) 46.87mVRMS (IOUT = 750mA) VDO = 0.5V 10 2.5 RMS Noise (100Hz to 100kHz) 48.14mVRMS (CNR = 1nF) 47.33mVRMS (CNR = 10nF) 45.90mVRMS (CNR = 100nF) VDO = 0.5V IOUT = 100mA Figure 21. Output Spectral Noise Density vs Frequency 100 1.5 2 VDO (V) Figure 20. Power-Supply Ripple Rejection vs Dropout Voltage Output Spectral Noise Density (mV/ÖHz) Output Spectral Noise Density (mV/ÖHz) Figure 19. Power-Supply Ripple Rejection vs Dropout Voltage 1 Submit Documentation Feedback Figure 24. Start-Up Time vs Noise Reduction Capacitance Copyright © 2010–2018, Texas Instruments Incorporated Product Folder Links: TPS7A80 TPS7A80 www.ti.com SBVS135J – JUNE 2010 – REVISED JANUARY 2018 Typical Characteristics (continued) At VOUT(TYP) = 3.3 V, VIN = VOUT(TYP) + 0.5 V or 2.2 V (whichever is greater), IOUT = 100 mA, VEN = VIN, CIN = 1 μF, COUT = 4.7 μF, and CNR = 0.01 μF, all temperature values refer to TJ (unless otherwise noted). 7 5.5 3.30825 VIN = 3.8V ® 4.8V ® 3.8V (1V/div) 3.3 3.29175 4.5 3.27525 3.5 IOUT = 500mA VOUT 3.35 50ms/div 2 IOUT = 100mA ® 1A ® 100mA (1A/ms) 3.25 0.5 3.15 0 50ms/div 3.5 5 EN VIN, VOUT (V) VEN, VOUT (V) RLOAD = 33W 6 3 2.5 Figure 26. Load Transient Response 7 RLOAD = 33W 4 1.5 1 3.2 Figure 25. Line Transient Response 4.5 2.5 3.3 3.15 3.267 3 3.7 IOUT (A) 3.2835 4 VIN (for reference) 3.75 VIN, VOUT (V) 3.3165 VOUT (V), 0.25% of 3.3V/div VOUT 5 3.8 3.32475 6 VIN (V), 0.5V/div 3.85 3.333 6.5 OUT 2 1.5 1 VIN = VEN 4 VOUT 3 2 1 0.5 0 0 -1 -0.5 1ms/div 1ms/div The internal reference requires approximately 2 ms of rampup time (see Start-Up); therefore, VOUT fully reaches the target output voltage of 3.3 V in 2 ms from start-up. Figure 27. Enable Pulse Response Figure 28. Power-Up and Power-Down Response Submit Documentation Feedback Copyright © 2010–2018, Texas Instruments Incorporated Product Folder Links: TPS7A80 11 TPS7A80 SBVS135J – JUNE 2010 – REVISED JANUARY 2018 www.ti.com 7 Detailed Description 7.1 Overview The TPS7A80 devices belong to a family of new-generation LDO regulators that uses innovative circuitry to achieve wide bandwidth and high loop gain, resulting in extremely high PSRR (over a 1-MHz range), even with very low headroom (VIN – VOUT). A noise-reduction capacitor (CNR) at the NR pin and a bypass capacitor (CBYPASS) decrease noise generated by the band-gap reference to improve PSRR, while a quick-start circuit fastcharges the noise-reduction capacitor. This family of regulators offers sub-band-gap output voltages, current limit, and thermal protection, and is fully specified from –40°C to +125°C. 7.2 Functional Block Diagram OUT IN Current Limit EN Thermal Shutdown UVLO 1.20V Bandgap 33kW FB Quick-Start NR 33kW 225kW 0.8V 15pF Adjustable 58.7kW TPS7A8001 GND Figure 29. Adjustable Voltage Version 12 Submit Documentation Feedback Copyright © 2010–2018, Texas Instruments Incorporated Product Folder Links: TPS7A80 TPS7A80 www.ti.com SBVS135J – JUNE 2010 – REVISED JANUARY 2018 Functional Block Diagram (continued) OUT IN SNS Current Limit EN Thermal Shutdown 2.5mA UVLO 1.20V Bandgap VOUT > 1.6V Quick-Start 33kW NR 33kW 225kW 0.8V 15pF VOUT £ 1.6V 58.7kW TPS7A80xx GND Figure 30. Fixed Voltage Versions 7.3 Feature Description 7.3.1 Internal Current Limit The TPS7A80 internal current limit helps protect the regulator during fault conditions. During current limit, the output sources a fixed amount of current that is largely independent of output voltage. For reliable operation, do not operate these devices in a current limit state for extended periods of time. The PMOS pass element in the TPS7A80 has a built-in body diode that conducts current when the voltage at OUT exceeds the voltage at IN. This current is not limited, so if extended reverse voltage operation is anticipated, external limiting is required. 7.3.2 Shutdown The enable pin (EN) is active high and is compatible with standard and low voltage, TTL-CMOS levels. When shutdown capability is not required, EN can be connected to IN. Submit Documentation Feedback Copyright © 2010–2018, Texas Instruments Incorporated Product Folder Links: TPS7A80 13 TPS7A80 SBVS135J – JUNE 2010 – REVISED JANUARY 2018 www.ti.com Feature Description (continued) 7.3.3 Start-Up Through a lower resistance, the band-gap reference can quickly charge the noise reduction capacitor (CNR). The TPS7A80 have a quick-start circuit to quickly charge CNR, if present; see the Functional Block Diagram. At startup, this quick-start switch is closed, with only 33 kΩ of resistance between the band-gap reference and the NR pin. The quick-start switch opens approximately 2ms after any device enabling event, and the resistance between the band-gap reference and the NR pin becomes higher in value (approximately 250 kΩ) to form a very good low-pass (RC) filter. This low-pass filter achieves very good noise reduction for the reference voltage. Inrush current can be a problem in many applications. The 33-kΩ resistance during the start-up period is intentionally put there to slow down the reference voltage ramp up, thus reducing the inrush current. For example, the capacitance of connecting the recommended CNR value of 0.01 μF along with the 33-kΩ resistance causes approximately 1-ms RC delay. Start-up time with the other CNR values can be calculated as Equation 1: tSTR (s) = 76,000 x CNR (F) (1) Equation 1 is valid up to tSTR = 2 ms or CNR = 26 nF, whichever is smaller. Although the noise reduction effect is nearly saturated at 0.01 μF, connecting a CNR value greater than 0.01 μF can help reduce noise slightly more; however, start-up time will be extremely long because the quick-start switch opens after approximately 2 ms. That is, if CNR is not fully charged during this 2 ms period, CNR finishes charging through a higher resistance of 250 kΩ, and takes much longer to fully charge. A low leakage CNR should be used; most ceramic capacitors are suitable. 7.3.4 Undervoltage Lockout (UVLO) The TPS7A80 use an undervoltage lockout circuit to keep the output shut off until the internal circuitry is operating properly. The UVLO circuit has a deglitch feature so that it typically ignores undershoot transients on the input if they are less than 50-μs duration. 7.4 Device Functional Modes Driving the EN pin over 1.2 V for VIN from 2.2 V to 3.6 V or 1.35 V for VIN from 3.6 V to 6.5 V turns on the regulator. Driving the EN pin below 0.4 V causes the regulator to enter shutdown mode. In shutdown, the current consumption of the device is reduced to 0.02 µA, typically. 14 Submit Documentation Feedback Copyright © 2010–2018, Texas Instruments Incorporated Product Folder Links: TPS7A80 TPS7A80 www.ti.com SBVS135J – JUNE 2010 – REVISED JANUARY 2018 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The TPS7A80 devices belong to a family of new generation LDO regulators that use innovative circuitry to achieve wide bandwidth and high loop gain, resulting in extremely high PSRR (over a 1-MHz range) at very low headroom (VIN – VOUT). A noise reduction capacitor (CNR) at the NR pin bypasses noise generated by the bandgap reference to improve PSRR, while a quick-start circuit fast-charges this capacitor. This family of regulators offers sub-band-gap output voltages, current limit, and thermal protection, and is fully specified from –40°C to 125°C. Figure 31 gives the connections for the adjustable-output version (TPS7A8001). Figure 32 shows the connections for the fixed-voltage versions. 8.2 Typical Application Optional 1.0mF input capacitor. May improve source impedance, noise, or PSRR. VIN IN VOUT OUT R1 TPS7A8001 EN 4.7mF Ceramic FB GND NR R2 VEN To avoid inrush current, it is recommended to always connect a 1nF to 10nF capacitor Figure 31. Typical Application Circuit: Adjustable-Voltage Version Optional 1.0mF input capacitor. May improve source impedance, noise, or PSRR. VIN IN VOUT OUT TPS7A80xx SNS EN VEN GND NR 4.7mF Ceramic To avoid inrush current, it is recommended to always connect a 1nF to 10nF capacitor Figure 32. Typical Application Circuit: Fixed-Voltage Versions Submit Documentation Feedback Copyright © 2010–2018, Texas Instruments Incorporated Product Folder Links: TPS7A80 15 TPS7A80 SBVS135J – JUNE 2010 – REVISED JANUARY 2018 www.ti.com Typical Application (continued) 8.2.1 Design Requirements 8.2.1.1 Dropout Voltage The TPS7A80 use a PMOS pass transistor to achieve low dropout. When (VIN – VOUT) is less than the dropout voltage (VDO), the PMOS pass device is in its linear region of operation and the input-to-output resistance is the RDS(ON) of the PMOS pass element. VDO scales approximately with output current because the PMOS device in dropout behaves the same way as a resistor. As with any linear regulator, PSRR and transient response are degraded as (VIN – VOUT) approaches dropout. This effect is shown in Figure 19 and Figure 20 in the Typical Characteristics section. 8.2.1.2 Minimum Load The TPS7A80 are stable and well-behaved with no output load. Traditional PMOS LDO regulators suffer from lower loop gain at very light output loads. The TPS7A80 employ an innovative low-current mode circuit to increase loop gain under very light or no-load conditions, resulting in improved output voltage regulation performance down to zero output current. 8.2.1.3 Input and Output Capacitor Requirements Although an input capacitor is not required for stability, it is good analog design practice to connect a 0.1-μF to 1μF low equivalent series resistance (ESR) capacitor across the input supply near the regulator. This capacitor counteracts reactive input sources and improves transient response, noise rejection, and ripple rejection. A higher-value capacitor may be necessary if large, fast rise-time load transients are anticipated or if the device is located several inches from the power source. If source impedance is not sufficiently low, a 0.1-μF input capacitor may be necessary to provide stability. The TPS7A80 are designed to be stable with standard ceramic capacitors of capacitance values 4.7 μF or larger. These devices is evaluated using a 4.7-μF ceramic capacitor of 10-V rating, 10% tolerance, X5R type, and 0805 size (2 mm × 1.25 mm). X5R- and X7R-type capacitors are highly recommended because they have minimal variation in value and ESR over temperature. Maximum ESR should be < 1 Ω. The TPS7A80 implement an innovative internal compensation circuit that does not require a feedback capacitor across R2 for stability. Do not use a feedback capacitor for this device. 8.2.1.4 Transient Response As with any regulator, increasing the size of the output capacitor reduces over- and undershoot magnitude, but increases duration of the transient response. 16 Submit Documentation Feedback Copyright © 2010–2018, Texas Instruments Incorporated Product Folder Links: TPS7A80 TPS7A80 www.ti.com SBVS135J – JUNE 2010 – REVISED JANUARY 2018 Typical Application (continued) 8.2.2 Detailed Design Procedure The voltage on the FB pin sets the output voltage and is determined by the values of R1 and R2. The values of R1 and R2 can be calculated for any voltage using the formula given in Equation 2: (R + R2 ) VOUT = 1 x 0.800 R2 (2) Sample resistor values for common output voltages are shown in Table 1. In Table 1, E96 series resistors are used, and all values meet 1% of the target VOUT, assuming resistors with zero error. For the actual design, pay attention to any resistor error factors. Using lower values for R1 and R2 reduces the noise injected from the FB pin. Table 1. Sample 1% Resistor Values for Common Output Voltages VOUT R1 R2 0.8 V 0 Ω (Short) Do not populate 1V 2.49 kΩ 10 kΩ 1.2 V 4.99 kΩ 10 kΩ 1.5 V 8.87 kΩ 10 kΩ 1.8 V 12.5 kΩ 10 kΩ 2.5 V 21 kΩ 10 kΩ 3.3 V 30.9 kΩ 10 kΩ 5V 52.3 kΩ 10 kΩ 8.2.2.1 Output Noise In most LDOs, the band gap is the dominant noise source. If a noise reduction capacitor (CNR) is used with the TPS7A80, the band gap does not contribute significantly to noise. Instead, noise is dominated by the output resistor divider and the error amplifier input. To minimize noise in a given application, use a 0.01-μF (minimum) noise-reduction capacitor. Equation 3 approximates the total noise when CNR = 0.01 μF: VN = 14.6 × VOUT + (µVRMS) (3) 8.2.3 Application Curve 7 RLOAD = 33W 6 VIN, VOUT (V) 5 4 VIN = VEN VOUT 3 2 1 0 -1 1ms/div Figure 33. Power-Up and Power-Down Response Submit Documentation Feedback Copyright © 2010–2018, Texas Instruments Incorporated Product Folder Links: TPS7A80 17 TPS7A80 SBVS135J – JUNE 2010 – REVISED JANUARY 2018 www.ti.com 9 Power Supply Recommendations These devices are designed to operate with an input voltage supply range from 2.2 V to 6.5 V. The input voltage range should provide adequate headroom for the device to have a regulated output. Use a well-regulated input supply. If the input supply is noisy, additional input capacitors with low ESR can help improve the output noise performance. 10 Layout 10.1 Layout Guidelines 10.1.1 Board Layout Recommendations to Improve PSRR and Noise Performance To improve ac performance such as PSRR, output noise, and transient response, TI recommends designing the board with separate ground planes for VIN and VOUT, with each ground plane connected only at the GND pin of the device. In addition, the ground connection for the bypass capacitor should connect directly to the GND pin of the device. 10.1.2 Thermal Considerations Thermal protection disables the output when the junction temperature rises to approximately 160°C, allowing the device to cool. When the junction temperature cools to approximately 140°C the output circuitry is again enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may cycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage because of overheating. Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate heatsink. For reliable operation, junction temperature should be limited to 125°C maximum. To estimate the margin of safety in a complete design (including heatsink), increase the ambient temperature until the thermal protection is triggered; use worst-case loads and signal conditions. For good reliability, thermal protection should trigger at least 35°C above the maximum expected ambient condition of your particular application. This configuration produces a worst-case junction temperature of 125°C at the highest expected ambient temperature and worst-case load. The internal protection circuitry of the TPS7A80 has been designed to protect against overload conditions. It was not intended to replace proper heatsinking. Continuously running the TPS7A80 into thermal shutdown degrades device reliability. 10.1.3 Power Dissipation Knowing the device power dissipation and proper sizing of the thermal plane that is connected to the tab or pad is critical to avoiding thermal shutdown and ensuring reliable operation. Power dissipation of the device depends on input voltage and load conditions and can be calculated using Equation 4: PD VIN VOUT u IOUT (4) Power dissipation can be minimized and greater efficiency can be achieved by using the lowest possible input voltage necessary to achieve the required output voltage regulation. On the VSON (DRB) package, the primary conduction path for heat is through the exposed pad to the printedcircuit-board (PCB). The pad can be connected to ground or be left floating; however, it should be attached to an appropriate amount of copper PCB area to make sure the device does not overheat. The maximum junction-toambient thermal resistance depends on the maximum ambient temperature, maximum device junction temperature, and power dissipation of the device and is calculated using Equation 5: 125qC TA RTJA PD (5) Knowing the maximum RθJA, the minimum amount of PCB copper area needed for appropriate heatsinking is estimated using Figure 34. 18 Submit Documentation Feedback Copyright © 2010–2018, Texas Instruments Incorporated Product Folder Links: TPS7A80 TPS7A80 www.ti.com SBVS135J – JUNE 2010 – REVISED JANUARY 2018 Layout Guidelines (continued) 160 140 qJA (°C/W) 120 100 80 60 40 20 0 0 1 2 4 5 7 3 6 Board Copper Area (in2) 8 9 10 NOTE: θJA value at board size of 9 in2 (that is, 3 inches × 3 inches) is a JEDEC standard. Figure 34. RθJA vs Board Size Figure 34 shows the variation of θJA as a function of ground plane copper area in the board. It is intended only as a guideline to demonstrate the effects of heat spreading in the ground plane and should not be used to estimate actual thermal performance in real application environments. NOTE When the device is mounted on an application PCB, it is strongly recommended to use ΨJT and ΨJB, as explained in the section. 10.1.4 Estimating Junction Temperature Using the thermal metrics ΨJT and ΨJB, as shown in the Thermal Information table, the junction temperature can be estimated with corresponding formulas (given in Equation 6). For backwards compatibility, an older θJC,Top parameter is listed as well. YJT: TJ = TT + YJT · PD YJB: TJ = TB + YJB · PD (6) Where PD is the power dissipation shown by Equation 5, TT is the temperature at the center-top of the IC package, and TB is the PCB temperature measured 1 mm away from the IC package on the PCB surface (as Figure 36 shows). NOTE Both TT and TB can be measured on actual application boards using a thermo gun (an infrared thermometer). For more information about measuring TT and TB, see Using New Thermal Metrics. By looking at Figure 35, the new thermal metrics (ΨJT and ΨJB) have very little dependency onboard size. That is, using ΨJT or ΨJB with Equation 6 is a good way to estimate TJ by simply measuring TT or TB, regardless of the application board size. Submit Documentation Feedback Copyright © 2010–2018, Texas Instruments Incorporated Product Folder Links: TPS7A80 19 TPS7A80 SBVS135J – JUNE 2010 – REVISED JANUARY 2018 www.ti.com Layout Guidelines (continued) 20 18 YJB YJT and YJB (°C/W) 16 14 12 10 8 6 YJT 4 2 0 0 1 2 3 4 5 6 7 8 9 10 Board Copper Area (in2) Figure 35. ΨJT and ΨJB vs Board Size For a more detailed discussion of why TI does not recommend using θJC(top) to determine thermal characteristics, see Using New Thermal Metrics. For further information, see Semiconductor and IC Package Thermal Metrics. TT on top of IC surface TB TB on PCB TT 1mm 1mm Figure 36. Measuring Points for TT and TB 20 Submit Documentation Feedback Copyright © 2010–2018, Texas Instruments Incorporated Product Folder Links: TPS7A80 TPS7A80 www.ti.com SBVS135J – JUNE 2010 – REVISED JANUARY 2018 10.2 Layout Example GND R2 C(NR) R1 C(IN) VI C(OUT) GND C(BYPASS) VO Figure 37. Layout Example Submit Documentation Feedback Copyright © 2010–2018, Texas Instruments Incorporated Product Folder Links: TPS7A80 21 TPS7A80 SBVS135J – JUNE 2010 – REVISED JANUARY 2018 www.ti.com 11 Device and Documentation Support 11.1 Documentation Support 11.1.1 Related Documentation For related documentation see the following: TPS7A80xxDRBEVM User's Guide 11.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 11.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.4 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 11.5 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 11.6 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 22 Submit Documentation Feedback Copyright © 2010–2018, Texas Instruments Incorporated Product Folder Links: TPS7A80 PACKAGE OPTION ADDENDUM www.ti.com 28-Sep-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TPS7A8001DRBR ACTIVE SON DRB 8 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 OFU TPS7A8001DRBT ACTIVE SON DRB 8 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 OFU TPS7A8012DRBR ACTIVE SON DRB 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 1G1H TPS7A8012DRBT ACTIVE SON DRB 8 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 1G1H TPS7A8018DRBR ACTIVE SON DRB 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 1G2H TPS7A8018DRBT ACTIVE SON DRB 8 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 1G2H TPS7A8033DRBR ACTIVE SON DRB 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 1G3H TPS7A8033DRBT ACTIVE SON DRB 8 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 1G3H TPS7A8050DRBR ACTIVE SON DRB 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 1G4H TPS7A8050DRBT ACTIVE SON DRB 8 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 1G4H (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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TPS7A8018DRBT
  •  国内价格 香港价格
  • 250+11.30205250+1.35737
  • 500+10.89857500+1.30892
  • 750+10.69649750+1.28465
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库存:465

TPS7A8018DRBT
  •  国内价格 香港价格
  • 1+19.788381+2.37658
  • 10+14.6550810+1.76007
  • 25+13.3747325+1.60630
  • 100+11.97129100+1.43775

库存:465

TPS7A8018DRBT
  •  国内价格 香港价格
  • 1+17.212501+2.06800
  • 10+12.7578010+1.53280
  • 100+11.83650100+1.42210
  • 250+11.17180250+1.34220
  • 500+10.07560500+1.21050
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库存:283

TPS7A8018DRBT
    •  国内价格
    • 20+4.86972
    • 200+4.63752
    • 1000+4.54464

    库存:220