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TPS7B6701-Q1
TPS7B6733-Q1, TPS7B6750-Q1
ZHCSBU8D – OCTOBER 2013 – REVISED APRIL 2018
TPS7B67xx-Q1 450mA 高压超低 IQ 低压降稳压器
1 特性
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1
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•
•
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•
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•
2 应用
符合汽车类 标准
符合 AEC-Q100 标准的下列结果
– 器件温度等级 1：环境运行温度范围为 -40°C
至 125°C
– 人体放电模型 (HBM) 静电放电 (ESD) 分类等级
H2
– 器件 CDM ESD 分类等级 C3B
4V 至 40V 宽 VIN 输入电压范围，瞬态电压高达
45V
最大输出电流，450mA
低静态电流 (IQ)
– < 4µA，EN = 低电平（关断模式）
– 轻负载时典型值为 15µA
低 ESR（0.001 至 20Ω）陶瓷输出稳定电容器
（VO ≥ 2.5V 时为 10µF 至 500µF，VO = 1.5V 至
2.5V 时为 22µF 至 500µF）
400mA 时的最大压降为 450mV
1.5V 至 18V 可调节输出电压
低输入电压跟踪至欠压闭锁 (UVLO)
集成型加电复位
– 可编程复位脉冲延迟
– 漏极开路复位输出
集成故障保护
– 热关断
– 短路保护功能
20 引脚散热薄型小外形尺寸 (HTSSOP) 封装
•
•
•
•
汽车
信息娱乐系统调谐器电源
车身控制模块
常开电池 应用
– 网关 应用
– 遥控免钥匙进入系统
– 发动机防盗系统
3 说明
TPS7B6701-Q1、TPS7B6733-Q1 和 TPS7B6750-Q1
器件 (TPS7B67xx-Q1) 为低压降线性稳压器，设计用
于输入电压 VIN 高达 40V 的操作。这些器件在轻负载
时的静态电流仅为 15µA，显著延长了汽车电池的续航
时间，可驱动高达 450mA 的负载。
TPS7B67xx-Q1 系列器件 集成有 短路和过流保护。在
加电时执行复位延迟和电源正常信号，以表示输出电压
稳定并且在稳压范围内。一个外部电容器设定此延迟。
此使能功能使用一个 MCU 的输入输出 (I/O) 端口来激
活此器件，以及使器件无效。
此器件的运行温度范围介于 -40°C 至 125°C 之间。
器件信息(1)
器件型号
封装
封装尺寸（标称值）
TPS7B6701-Q1
TPS7B6733-Q1
HTSSOP (20)
6.50mm x 4.40mm
TPS7B6750-Q1
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
可调输出选项
VI
TPS7B6701-Q1
固定输出选项
VO
Vbat
EN
RESET
Vreg
Vbat
VI
EN
TPS7B6733-Q1
TPS7B6750-Q1
VO
Vreg
RESET
ADJ
DELAY
GND
DELAY
GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLVSCB2
TPS7B6701-Q1
TPS7B6733-Q1, TPS7B6750-Q1
ZHCSBU8D – OCTOBER 2013 – REVISED APRIL 2018
www.ti.com.cn
目录
1
2
3
4
5
6
7
8
特性 ..........................................................................
应用 ..........................................................................
说明 ..........................................................................
修订历史记录 ...........................................................
Device Comparison ...............................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
4
4
5
7.1
7.2
7.3
7.4
7.5
7.6
7.7
5
5
5
5
6
7
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Typical Characteristics ..............................................
Detailed Description ............................................ 11
8.1 Overview ................................................................. 11
8.2 Functional Block Diagrams ..................................... 11
8.3 Feature Description................................................. 12
8.4 Device Functional Modes........................................ 14
9
Application and Implementation ........................ 15
9.1 Application Information............................................ 15
9.2 Typical Application .................................................. 15
10 Power Supply Recommendations ..................... 17
10.1 Dropout Recovery ................................................. 17
11 Layout................................................................... 19
11.1 Layout Guidelines ................................................. 19
11.2 Layout Example .................................................... 21
12 器件和文档支持 ..................................................... 22
12.1
12.2
12.3
12.4
12.5
12.6
相关链接................................................................
接收文档更新通知 .................................................
社区资源................................................................
商标 .......................................................................
静电放电警告.........................................................
术语表 ...................................................................
22
22
22
22
22
22
13 机械、封装和可订购信息 ....................................... 22
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision C (December 2014) to Revision D
•
Page
Added Dropout Recovery section explaining LDO behavior when exiting dropout ............................................................. 17
Changes from Revision B (March 2014) to Revision C
Page
•
已删除 数据表中的 TPS7B6750A-Q1 和 TPS7B6750B-Q1 器件以及 DDPAK 封装 .............................................................. 1
•
Changed the word terminal to pin throughout the data sheet ................................................................................................ 4
•
Changed the Handling Ratings table to ESD Ratings and moved the storage temperature into the Absolute
Maximum Ratings table. Added corner pin values for CDM ratings. .................................................................................... 5
Changes from Revision A (November 2013) to Revision B
Page
•
更新了首页内容，包括以下新增内容：器件信息表，器件系列名称更新为文档标题，增加了导航按钮.................................. 1
•
已更改 EN = 低电平时的 IQ 值从 < 2 改为 < 4（特性 列表..................................................................................................... 1
•
已添加 内容表 并且已将 修订历史记录 移至第二页 ................................................................................................................ 1
•
Replaced the ORDERING INFORMATION table with the Device Comparison Table and deleted the Device and
Package columns ................................................................................................................................................................... 4
•
Added Moved all electrical specifications tables and the Typical Characteristics section into the Specifications section..... 5
•
Changed the max value for DELAY from VI to 45 V in the Absolute Maximum Ratings table. Also added new table
note for DELAY....................................................................................................................................................................... 5
•
Changed the max value for ADJ, RESET from VO to 22 V in the Absolute Maximum Ratings table .................................... 5
•
Changed the value of IO from 1 mA to 450 mA for the Input voltage test conditions in the Electrical Characteristics table . 6
•
Added the value for VI in the test conditions of the Regulated output and the Line regulator parameters in the
Electrical Characteristics table .............................................................................................................................................. 6
•
Moved the timing parameters (TIMING FOR RESET) out of the Electrical Characteristics table and into the new
Timing Requirements table .................................................................................................................................................... 7
•
Added the Overview section title to the first paragraph of the Detailed Description section ............................................... 11
2
版权 © 2013–2018, Texas Instruments Incorporated
TPS7B6701-Q1
TPS7B6733-Q1, TPS7B6750-Q1
www.ti.com.cn
ZHCSBU8D – OCTOBER 2013 – REVISED APRIL 2018
•
Updated the Power-On_Reset (RESET) section by making the following changes: changed the percentage that VO
exceeds for the reset output to change from 90% to 91.6% (also changed this value in the Reset Delay Timer
(DELAY) section), removed The on-chip oscillator presets the delay, and changed the percentage level to assert the
output from 90% to 89.6% .................................................................................................................................................... 12
•
Changed the junction temperature value that disables thermal protection from 170°C to 175°C in the Thermal
Protection section ................................................................................................................................................................. 14
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Added the Device Functional Modes section ...................................................................................................................... 14
•
Added the Typical Application section in the new Applications and Implementation section ............................................. 15
•
Added the Power Supply Recommendations section ......................................................................................................... 17
•
Changed the LAYOUT INFORMATION section to the Layout section and added the Layout Example section................. 19
•
已添加 机械封装和可订购信息 部分。还添加了器件和文档支持部分，目前此部分包含商标部分和 静电放电警告。这
个部分还包括对 TI 术语表的全新引用................................................................................................................................... 22
Changes from Original (October 2013) to Revision A
Page
•
已更改 将特性 列表的电压监控项目中添加了“独立”................................................................................................................ 1
•
已添加 车身控制模块到应用分类等级 ..................................................................................................................................... 1
•
已更改 低压跟踪特性至使能功能（说明部分） ....................................................................................................................... 1
•
已更改 文档状态从 产品预览 改为 生产数据 ........................................................................................................................... 1
•
已更改 典型应用电路原理图以显示可调输出和固定输出选项之间的差异 ............................................................................... 1
•
Changed the MIN value for RESET and ADJ in the RECOMMENDED OPERATING CONDITIONS table from 0 to
1.5 and removed low voltage parameter for those pins ......................................................................................................... 5
•
Added Added board dimensions to the high K profile THERMAL INFORMATION table note............................................... 5
•
Changed test condition for the input voltage to fixed 3.3-V output and added 5-V and two adjustable output conditions .... 6
•
Changed max value for the line regulation parameter from 2 to 10....................................................................................... 6
•
Changed TYP value for dropout voltage where IO = 400 mA from 240 to 260 ...................................................................... 6
•
Changed TYP value for dropout voltage where IO = 200 mA from 160 to 150 ...................................................................... 6
•
Changed Output current-limit typ value to max value for VOUT short to ground ..................................................................... 6
•
Deleted VIN condition from test condition for PSRR ............................................................................................................... 6
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Added TYPICAL CHARACTERISTICS section...................................................................................................................... 8
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Added the DETAILED DESCRIPTION section..................................................................................................................... 11
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Added block diagram fro the TPS7B6733-Q1 and TPS7B6750-Q1..................................................................................... 11
•
Added the APPLICATION INFORMATION section.............................................................................................................. 15
•
Added the LAYOUT INFORMATION section ....................................................................................................................... 19
Copyright © 2013–2018, Texas Instruments Incorporated
3
TPS7B6701-Q1
TPS7B6733-Q1, TPS7B6750-Q1
ZHCSBU8D – OCTOBER 2013 – REVISED APRIL 2018
www.ti.com.cn
5 Device Comparison
ORDERABLE PART NUMBER
VOLTAGE OPTION (VOUT)
TPS7B6701QPWPRQ1
Adjustable 1.5 V to 18 V
TPS7B6733QPWPRQ1
Fixed 3.3 V
TPS7B6750QPWPRQ1
Fixed 5 V
6 Pin Configuration and Functions
PWP Package
20-Pin HTSSOP With PowerPAD™
Top View
180
RESET
1
20
NC
NC
2
19
VIN
DELAY
3
18
NC
VOUT
4
17
NC
ADJ/NC
5
16
NC
NC
6
15
EN
NC
7
14
NC
GND
8
13
GND
NC
9
12
NC
NC
10
11
NC
Pin Functions
PIN
NAME
PWP
TYPE
DESCRIPTION
ADJ
5
I
Feedback pin. This pin is used with an external resistor divider or the NC pin when in a fixed version.
DELAY
3
O
Reset pulse delay adjustment. Connect this pin through a capacitor to GND.
EN
15
I
Enable pin. When the EN pin becomes lower than threshold, the device enters the stand-by state.
8, 13
G
Ground reference
2, 6, 7, 9,
10, 11, 12,
14, 16, 17,
18, 20
—
Not connected
RESET
1
O
Output ready. This open-drain pin must be connected to VOUT through an external resistor. RESET is
pulled down when the output voltage goes below threshold.
VIN
19
P
Input power-supply voltage
VOUT
4
P
Output voltage
—
Thermal pad
GND
NC
PowerPAD™
4
Copyright © 2013–2018, Texas Instruments Incorporated
TPS7B6701-Q1
TPS7B6733-Q1, TPS7B6750-Q1
www.ti.com.cn
ZHCSBU8D – OCTOBER 2013 – REVISED APRIL 2018
7 Specifications
7.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
Unregulated input range (2) (3) (4)
Output range
MIN
MAX
VIN, EN
–0.3
45
VOUT
–0.3
22
DELAY (2) (3) (5)
45
ADJ, RESET
22
UNIT
V
V
Operating junction temperature (TJ)
–40
150
°C
Storage temperature (Tstg)
–65
150
°C
(1)
(2)
(3)
(4)
(5)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability
All voltage values are with respect to GND.
Absolute negative voltage on these pins does not go below –0.3 V.
Absolute maximum voltage.
The voltage at the DELAY pin must be lower than the VIN voltage.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002 (1) (2)
±2000
All pins
±500
Corner pins (1, 10, 11,
and 20)
±750
Charged-device model (CDM), per AEC
Q100-011
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
The human body model is a 107-pF capacitor discharged through a 1.5-kΩ resistor into each pin.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
Unregulated input range
Output range
TJ
MIN
MAX
VIN
4
40
EN, DELAY
0
40
1.5
18
–40
150
VOUT, RESET, ADJ
Operating junction temperature range
UNIT
V
V
°C
7.4 Thermal Information
TPS7B67xx-Q1
THERMAL METRIC (1) (2)
PWP (HTSSOP)
UNIT
20 PINS
RθJA
Junction-to-ambient thermal resistance
44.9
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
27.4
°C/W
RθJB
Junction-to-board thermal resistance
23.6
°C/W
ψJT
Junction-to-top characterization parameter
1.1
°C/W
ψJB
Junction-to-board characterization parameter
23.4
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
3.1
°C/W
(1)
(2)
The thermal data is based on JEDEC standard high K profile — JESD 51-7. Two signal, two plane, four-layer board with 2-oz copper.
The copper pad is soldered to the thermal land pattern. Also correct attachment procedure must be incorporated.
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Copyright © 2013–2018, Texas Instruments Incorporated
5
TPS7B6701-Q1
TPS7B6733-Q1, TPS7B6750-Q1
ZHCSBU8D – OCTOBER 2013 – REVISED APRIL 2018
www.ti.com.cn
7.5 Electrical Characteristics
VI = 14 V, 1 mΩ < ESR < 20 Ω, TJ = –40°C to 150°C unless otherwise stated
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY VOLTAGE AND CURRENT (VIN)
Fixed 3.3-V output, IO = 0 mA to 450 mA
VI
Input voltage
IQ
Quiescent current
4
40
5.5
40
Adjustable output, VO ≤ 3.5 V, IO = 0 mA to 450 mA
4
40
Adjustable output, VO ≥ 3.5 V, IO = 0 mA to 450 mA
VO + 0.5
40
Fixed 5-V output, IO = 0 mA to 450 mA
VI = 5.5 V to 40 V (fixed 5 V), 4 V to 40 V (fixed 3.3 V),
EN = ON, IO = 0.2 mA
15
25
VI = 4 V to 40 V (adjustable version, VO = 1.5 V),
EN = ON, IO = 0.2 mA
15
25
VI = 18.5 V to 40 V (adjustable version, VO = 18 V),
EN = ON, IO = 0.2 mA
25
35
V
µA
ISleep
Input sleep current
NO load current and EN = OFF
4
µA
IEN
EN pin current
EN = 40 V
1
µA
Vbg
Band gap
Reference voltage for ADJ
2%
V
VINUVLO
Undervoltage detection
Ramp VI down until output is turned OFF
2.6
V
UVLOHys
Undervoltage detection
hysteresis
–2%
1.233
1
V
ENABLE INPUT (EN)
VIL
Logic input low level
VIH
Logic input high level
0
0.4
1.7
V
V
REGULATED OUTPUT (VOUT)
VO
Regulated output (1)
VI = VO + 0.5 V to 40 V and VI ≥ 4 V, IO = 0 mA to 450 mA
ΔVO(ΔVI)
Line regulation
VI = VO + 1 V to 40 V and VI ≥ 4 V, IO = 100 mA, ∆VO
10
mV
ΔVO(ΔIL)
Load regulation
IO = 1 mA to 450 mA, ∆VO
10
mV
Vdropout
Dropout voltage
IO
Output current
–2%
2%
VI – VO, IO = 400 mA
240
450
VI – VO, IO = 200 mA
160
300
VO in regulation
0
450
VO short to ground
140
360
VO = VO typical × 0.9
470
850
Ilreg-CL
Output current-limit
PSRR
Power-supply ripple rejection (2) IL = 100 mA, CO = 22 µF
Freq = 100 Hz
60
Freq = 100 kHz
40
mV
mA
mA
dB
RESET
VOL
Reset pulled low
IOL = 0.5 mA
IOH
Reset pulled VOUT through
10-kΩ resistor
Leakage current
VTH-(POR)
Power-on-reset threshold
VO power-up set tolerance
Vhys
Hysteresis
VO power-down set tolerance
89.6
0.4
V
1
µA
91.6
93.6 % of VOUT
2
% of VOUT
RESET DELAY
IChg
Delay capacitor charging
current
Vth
Threshold to release RESET
high
Rdelay = 0 V
6
9.5
14
1
µA
V
OPERATING TEMPERATURE RANGE
TJ
Junction temperature
Tsd
Junction shutdown
temperature
Thys
Hysteresis of thermal
shutdown
(1)
(2)
6
–40
150
°C
175
°C
24
°C
External resistor divider variation is not considered.
Design information — not tested, ensured by characterization.
Copyright © 2013–2018, Texas Instruments Incorporated
TPS7B6701-Q1
TPS7B6733-Q1, TPS7B6750-Q1
www.ti.com.cn
ZHCSBU8D – OCTOBER 2013 – REVISED APRIL 2018
7.6 Timing Requirements
MIN
TYP
MAX
UNIT
TIMING FOR RESET
tPOR
Power-on reset delay
Where C = delay-capacitor value
capacitance, C = 100 nF (1)
tPOR-fixed
Power-on reset delay
No capacitor on pin
tDeglitch
Reset deglitch time
(1)
10.5
ms
100
325
550
µs
55
180
420
µs
This information only will NOT be tested in production. The equation is based on:
(C × 1) / (9.5 × 10–6) = tDelay (delay time)
Where
tab● C = delay capacitor value capacitance
tab● C range = 100 pf to 500 nF
Copyright © 2013–2018, Texas Instruments Incorporated
7
TPS7B6701-Q1
TPS7B6733-Q1, TPS7B6750-Q1
ZHCSBU8D – OCTOBER 2013 – REVISED APRIL 2018
www.ti.com.cn
7.7 Typical Characteristics
1.60
160
1.58
140
120
1.54
1.52
IGND (µA)
VO Nominal (%)
1.56
1.50
1.48
1.46
VO
VO (±40ƒC)
(t40ƒC)
1.44
VO (25ƒC)
(25°C)
VO
1.42
100
80
60
40
IGND
(±40ƒC)
IGND (t40°C)
20
IGND (25°C)
IGND
(25ƒC)
VO (125ƒC)
(125°C)
VO
IGND (125°C)
IGND
(125ƒC)
0
1.40
0
5
10
15
20
25
30
35
VI (V)
0
40
50
100
150
200
250
300
350
400
450
IO (mA)
C001
Figure 1. Line Regulation
(VO = 1.5 V, IL = 100 mA)
C002
Figure 2. Ground Current vs Output Current
(VI = 14 V, VO = 1.5 V)
160
25
140
120
15
IGND (µA)
IQ (µA)
20
10
5
100
80
60
IO (t40°C)
IO
(±40ƒC)
40
IO (25°C)
IO
(25ƒC)
20
IGND
(±40ƒC)
IGND (t40°C)
IGND (25°C)
IGND
(25ƒC)
IGND (125°C)
IGND
(125ƒC)
IO (125°C)
IO
(125ƒC)
0
0
0
10
20
30
0
40
VI (V)
30
350
Dropout Voltage (mV)
400
IQ (µA)
25
20
15
10
IGND
(±40ƒC)
IO (t40°C)
5
IO (25°C)
IGND
(25ƒC)
IO (125°C)
IGND
(125ƒC)
30
35
40
VI (V)
Figure 5. Quiescent Current vs Input Voltage
(VO = 18 V)
8
200
250
300
350
400
450
C004
300
250
200
150
100
Vdrop
(±40ƒC)
Vdrop (t40°C)
50
Vdrop (25°C)
Vdrop
(25ƒC)
Vdrop (125°C)
Vdrop
(125ƒC)
0
0
25
150
Figure 4. Ground Current vs Output Current
(VI = 24 V, VO = 18 V)
35
20
100
IO (mA)
Figure 3. Quiescent Current vs Input Voltage
(VO = 1.5 V)
15
50
C003
45
C005
0
50
100
150
200
250
300
350
400
IO (mA)
450
C006
Figure 6. Dropout Voltage vs Output Current
Copyright © 2013–2018, Texas Instruments Incorporated
TPS7B6701-Q1
TPS7B6733-Q1, TPS7B6750-Q1
www.ti.com.cn
ZHCSBU8D – OCTOBER 2013 – REVISED APRIL 2018
Typical Characteristics (continued)
1.60
100
500
1.58
1.56
80
400
1.52
CL (µF)
VO (V)
1.54
1.50
1.48
1.46
VO
VO (±40ƒC)
(t40ƒC)
1.44
VO (125ƒC)
(125°C)
VO
1.40
0
50
100
150
200
250
300
350
400
IO (mA)
Stable Region
40
200
20
100
VO
VO (25ƒC)
(25°C)
1.42
60
300
220
0.001
0.0
450
5
0.5
10
1.0
15
1.5
20
ESR of CO (
C007
Figure 7. Load Regulation
(VI = 14 V, VO = 1.5 V)
C008
Figure 8. ESR Stability vs Load Capacitance
(VO ≤ 2.5 V)
100
500
6
5
80
400
VO (V)
CL (µF)
4
60
300
Stable Region
40
200
3
2
20
100
1
100
0
0.001
0.0
5
0.5
10
1.0
15
1.5
20
ESR of CO (
0
Figure 9. ESR Stability vs Load Capacitance
(VO ≥ 2.5 V)
10
15
20
25
30
35
40
C010
Figure 10. Output Voltage vs Supply Voltage
(Fixed 5-V Version, IL = 0)
3.5
120
3.0
100
2.5
80
PSRR (dB)
VO (V)
5
VS (V)
C009
2.0
1.5
60
40
1.0
20
0.5
0.0
0
0
5
10
15
20
25
30
35
VS (V)
Figure 11. Output Voltage vs Supply Voltage
(Fixed 3.3-V Version, IL = 0)
Copyright © 2013–2018, Texas Instruments Incorporated
40
C011
1010
100
100000010000000
10000000
100 1000
1000 10000
10000100000
100000 1000000
100000000
Frequency (Hz)
C012
Figure 12. Power-Supply Rejection Ratio vs Frequency
(VI = 14 V, CO = 47 µF, IL = 25 mA)
9
TPS7B6701-Q1
TPS7B6733-Q1, TPS7B6750-Q1
ZHCSBU8D – OCTOBER 2013 – REVISED APRIL 2018
www.ti.com.cn
Typical Characteristics (continued)
220
630
620
610
Current Limit (mA)
Current Limit (mA)
215
210
205
200
600
590
580
570
560
550
540
195
530
190
520
±40 ±25 ±10
5
20
35
50
65
Temperature (ƒC)
80
95
110 125
±40 ±25 ±10
Figure 13. Short to GND Current-Limit vs Temperature
5
20
35
50
65
80
95
110 125
Temperature (ƒC)
C013
C014
Figure 14. Current-Limit vs Temperature
Figure 15. Load Transient
10-µF Ceramic Output Capacitor
10
Copyright © 2013–2018, Texas Instruments Incorporated
TPS7B6701-Q1
TPS7B6733-Q1, TPS7B6750-Q1
www.ti.com.cn
ZHCSBU8D – OCTOBER 2013 – REVISED APRIL 2018
8 Detailed Description
8.1 Overview
The TPS7B67xx-Q1 family of devices is an low-dropout linear regulator combined with an enable and reset
function. The power-on-reset initializes when the output voltage, VO, exceeds 91.6% of the target value. The
power-on reset delay is a function of the value set by an external capacitor on the DELAY pin before releasing
the RST pin high.
8.2 Functional Block Diagrams
UVLO
±
Comp
Band Gap
Vref
+
VIN
Vbat
47 µF
Vref
EN
Logic
Control
0.1 µF
Overcurrent
Detection
Thermal
Shutdown
Regulator
Control
VOUT
Vreg
GND
+
±
22 µF
Vref
ADJ
10 k
DELAY
RESET
Reset Control
Figure 16. TPS7B6701-Q1 Functional Block Diagram
UVLO
±
Comp
+
Vref
VIN
Vbat
Band Gap
47 µF
Vref
EN
Logic
Control
0.1 µF
Overcurrent
Detection
Thermal
Shutdown
Regulator
Control
VOUT
Vreg
GND
+
±
DELAY
Reset Control
22 µF
Vref
RESET
10k
Figure 17. TPS7B6733-Q1 and TPS7B6750-Q1 Functional Block Diagram
Copyright © 2013–2018, Texas Instruments Incorporated
11
TPS7B6701-Q1
TPS7B6733-Q1, TPS7B6750-Q1
ZHCSBU8D – OCTOBER 2013 – REVISED APRIL 2018
www.ti.com.cn
8.3 Feature Description
8.3.1 Enable (EN)
The enable pin is a high-voltage-tolerant pin. A high input on EN actives the device and turns on the regulator.
For self-bias applications, connect this input to the VIN pin.
8.3.2 Regulated Output (VOUT)
The VOUT pin is the regulated output based on the required voltage. The output has current limitation. During
initial power up, the regulator has a soft start incorporated to control the initial current through the pass element.
In the event that the regulator drops out of regulation, the output tracks the input minus a drop based on the load
current. When the input voltage drops below the UVLO threshold, the regulator shuts down until the input voltage
recovers above the minimum start-up level.
8.3.3 Power-On-Reset (RESET)
The power-on-reset is an output with an external pullup resistor to the regulated supply. The reset output remains
low until the regulated VO exceeds approximately 91.6% of the set value and the power-on-reset delay has
expired. The regulated output falling below the 89.6% level asserts this output low after a short de-glitch time of
approximately 180 µs (typical).
8.3.4 Reset Delay Timer (DELAY)
An external capacitor on this pin sets the timer delay before the reset pin is asserted high. The constant output
current charges an external capacitor until the voltage exceeds a threshold to trip an internal comparator. If this
pin is open, the default delay time is 325 µs (typical).
The reset pulse delay time td, is defined with the charge time of an external capacitor DELAY (see Equation 1).
´1V
C
t d = DELAY
9.5 µA
(1)
The power-on-reset initializes when VO exceeds 91.6% of the programmed value. The power-on-reset delay is a
function of the value set by an external capacitor on the DELAY pin before the RESET pin is released high.
V IN
t
