TPS7B87-Q1
TPS7B87-Q1
SBVS363A – DECEMBER 2020 – REVISED
APRIL 2021
SBVS363A – DECEMBER 2020 – REVISED APRIL 2021
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TPS7B87-Q1 500-mA, 40-V, Low-Dropout Regulator
With Power-Good
1 Features
3 Description
•
The TPS7B87-Q1 is a low-dropout linear regulator
designed to connect to the battery in automotive
applications. The device has an input voltage range
extending to 40 V, which allows the device to
withstand transients (such as load dumps) that are
anticipated in automotive systems. With only a 17µA quiescent current at light loads, the device is an
optimal solution for powering always-on components
such as microcontrollers (MCUs) and controller area
network (CAN) transceivers in standby systems.
AEC-Q100 qualified for automotive applications:
– Temperature grade 1: –40°C to +125°C, TA
– Junction temperature: –40°C to +150°C, TJ
Input voltage range: 3 V to 40 V (42 V max)
Output voltage range: 3.3 V and 5 V (fixed)
Maximum output current: 500 mA
Output voltage accuracy: ±0.85% (max)
Low dropout voltage:
– 475 mV (max) at 450 mA
Low quiescent current:
– 17 µA (typ) at light loads
Excellent line transient response:
– ±2% VOUT deviation during cold-crank
– ±2% VOUT deviation (1-V/µs VIN slew rate)
Power-good with programmable delay period
Stable with a 2.2-µF or larger capacitor
Functional Safety-Capable
– Documentation available to aid functional safety
system design
Package options:
– 5-pin TO-252 package: 29.7°C/W RθJA
– 8-pin HSOIC-8 package with thermal pad:
41.8°C/W RθJA
•
•
•
•
•
•
•
•
•
•
•
2 Applications
Reconfigurable instrument clusters
Body control modules (BCM)
Always-on battery-connected applications:
– Automotive gateways
– Remote keyless entries (RKE)
Input Voltage (V)
45
PART NUMBER
TPS7B87-Q1
40
35
0.15
30
0.1
25
0.05
20
0
15
-0.05
10
-0.1
5
-0.15
0
500
1000
1500
Time (Ps)
2000
2500
The device is available in thermally conductive
packaging to allow the device to efficiently transfer
heat to the circuit board.
Device Information (1)
0.25
VIN
VOUT 0.2
0
The power-good delay can be adjusted by external
components, allowing the delay time to be configured
to fit application-specific systems.
(1)
PACKAGE
BODY SIZE (NOM)
HSOIC (8)
4.89 mm × 3.90 mm
TO-252 (5)
6.60 mm × 6.10 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
Output Voltage (V)
•
•
•
The device has state-of-the-art transient response
that allows the output to quickly react to changes
in load or line (for example, during cold-crank
conditions). Additionally, the device has a novel
architecture that minimizes output overshoot when
recovering from dropout. During normal operation, the
device has a tight DC accuracy of ±0.85% over line,
load, and temperature.
IN
OUT
TPS7B87-Q1
DELAY
PG
I/O
GND
-0.2
3000
Output Equal to Reference Voltage
Line Transient Response (3-V/µs VIN Slew Rate)
An©IMPORTANT
NOTICEIncorporated
at the end of this data sheet addresses availability, warranty, changes, use in
safety-critical
applications,
Copyright
2021 Texas Instruments
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SBVS363A – DECEMBER 2020 – REVISED APRIL 2021
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings ....................................... 4
6.2 ESD Ratings .............................................................. 4
6.3 Recommended Operating Conditions ........................4
6.4 Thermal Information ...................................................5
6.5 Electrical Characteristics ............................................6
6.6 Switching Characteristics ...........................................7
6.7 Typical Characteristics................................................ 8
7 Detailed Description......................................................14
7.1 Overview................................................................... 14
7.2 Functional Block Diagram......................................... 14
7.3 Feature Description...................................................15
7.4 Device Functional Modes..........................................17
8 Application and Implementation.................................. 18
8.1 Application Information............................................. 18
8.2 Typical Application.................................................... 23
9 Power Supply Recommendations................................24
10 Layout...........................................................................25
10.1 Layout Guidelines................................................... 25
10.2 Layout Examples ................................................... 26
11 Device and Documentation Support..........................27
11.1 Device Support........................................................27
11.2 Documentation Support.......................................... 27
11.3 Receiving Notification of Documentation Updates.. 27
11.4 Support Resources................................................. 27
11.5 Trademarks............................................................. 27
11.6 Electrostatic Discharge Caution.............................. 27
11.7 Glossary.................................................................. 27
12 Mechanical, Packaging, and Orderable
Information.................................................................... 27
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (December 2020) to Revision A (April 2021)
Page
• Added Functional Safety-Capable bullet to Features list....................................................................................1
• Updated pin functions table to reflect pin 4 of the HSOIC (DDA) package as an NC pin...................................3
2
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5 Pin Configuration and Functions
Thermal
OUT
1
NC
2
8
IN
7
NC
Thermal
Pad
Pad
DELAY
3
6
PG
NC
4
5
GND
2
3
4
5
PG
GND
DELAY
VO
1
Figure 5-2. DDA Package, 8-Pin HSOIC, Top View
VI
Not to scale
Figure 5-1. KVU Package, 5-Pin TO-252, Top View
Table 5-1. Pin Functions
PIN
NAME
KVU
DDA
TYPE(1)
DESCRIPTION
DELAY
4
3
I
Power-good delay adjustment pin. Connect a capacitor from this pin to GND
to set the PG reset delay. Leave this pin floating for a default (t(DLY_FIX)) delay.
See the Power-Good (PG) section for more information. If this functionality is
not desired, leave this pin floating because connecting this pin to GND causes
a permanent increase in the GND current.
GND
3
5
G
Ground reference
NC
—
2, 4, 7
—
No internal connection. This pin can be left floating or tied to GND for best
thermal performance.
PG
2
IN
1
OUT
Thermal
pad
(1)
I
Power-good pin. This pin has an internal pullup resistor. Do not connect this pin
to VOUT or any other biased voltage rail. VPG is logic level high when VOUT is
above the power-good threshold. See the Power-Good (PG) section for more
information.
P
Input power-supply voltage pin. For best transient response and to minimize
input impedance, use the recommended value or larger ceramic capacitor from
IN to GND as listed in the Recommended Operating Conditions table and the
Input Capacitor section. Place the input capacitor as close to the input of the
device as possible.
6
8
5
1
O
Regulated output voltage pin. A capacitor is required from OUT to GND for
stability. For best transient response, use the nominal recommended value or
larger ceramic capacitor from OUT to GND; see the Recommended Operating
Conditions table and the Output Capacitor section. Place the output capacitor
as close to output of the device as possible. If using a high equivalent
series resistance (ESR) capacitor, decouple the output with a 100-nF ceramic
capacitor.
Pad
Pad
—
Connect the thermal pad to a large area GND plane for improved thermal
performance.
I = input; O = output; P = power; G = ground.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX UNIT
VIN
Unregulated input
–0.3
42
V
VOUT
Regulated output
–0.3 VIN + 0.3 V(2)
V
Delay
Reset delay input, power-good adjustable threshold
–0.3
6
V
PG
Power-good outupt
–0.3
20
V
TJ
Operating junction temperature
–40
150
°C
Tstg
Storage temperature
–65
150
°C
(1)
(2)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. Theseare stress ratings
only and functional operation of the device at these or any other conditionsbeyond those indicated under recommended operating
conditions isnot implied. Exposure to absolute-maximum-rated conditions for extended periods may affect devicereliability.
The absolute maximum rating is VIN + 0.3 V or 20 V, whichever is smaller
6.2 ESD Ratings
VALUE
Human-body model (HBM), per AEC
V(ESD)
(1)
Electrostatic discharge
Q100-002(1)
Charged-device model (CDM), per AEC
Q100-011
UNIT
±2000
All pins
±500
Corner pins
±750
V
AEC Q100-002 indicates that HBM stressing shall be in accordancewith the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VIN
TYP
3
MAX
40
UNIT
V
VOUT
Output voltage
1.2
18
V
IOUT
Output current
0
500
mA
V
VDelay
Delay pin voltage, power-good adjustable threshold
0
5.5
VPG
Power-good outupt pin
0
18
V
COUT
Output capacitor(2)
2.2
220
µF
ESR
Output capacitor ESR requirements
CIN
Input capacitor(1)
CDelay
Power-good delay capacitor
TJ
Operating junction temperature
(1)
(2)
4
Input voltage
0.001
0.1
–40
2
1
Ω
µF
1
µF
150
°C
For robust EMI performance the minimum input capacitance is 500 nF.
Effective output capacitance of 1 µF minimum required for stability.
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6.4 Thermal Information
TPS7B87-Q1
THERMAL
RθJA
METRIC(1) (2)
DDA
8 PINS
UNIT
29.7
41.8
°C/W
RθJC(top) Junction-to-case (top) thermal resistance
40.2
55
°C/W
RθJB
Junction-to-board thermal resistance
8.6
17.3
°C/W
ψJT
Junction-to-top characterization parameter
2.9
4.5
°C/W
ψJB
Junction-to-board characterization parameter
8.5
17.3
°C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance
1.5
5.7
°C/W
(1)
(2)
Junction-to-ambient thermal resistance
KVU
5 PINS
The thermal data is based on the JEDEC standard high K profile,JESD 51-7. Two-signal, two-plane, four-layer board with 2-oz. copper.
The copper pad is soldered tothe thermal land pattern. Also, correct attachment procedure must be incorporated.
For more information about traditional and new thermal metrics,see the Semiconductor and IC PackageThermal Metrics application
report.
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6.5 Electrical Characteristics
specified at TJ = –40°C to +150°C, VIN = 13.5 V, IOUT = 0 mA, COUT = 2.2 µF, 1 mΩ < COUT ESR < 2 Ω, CIN = 1 µF typical
values are at TJ = 25°C
PARAMETER
VOUT
Regulated output
Test Conditions
Load regulation
TYP
0.85
VIN = VOUT + 1 V to 40 V, IOUT = 100 µA to 500 mA, TJ =
25ºC(1)
–0.85
0.85
mA(1)
–1.15
1.15
VIN = VOUT + 1 V to 40 V, IOUT = 100 µA to 500 mA(1)
–1.15
1.15
VIN = VOUT + 1 V, IOUT = 100 µA to 450 mA , VOUT ≥ 3.3
V
0.425
VIN = VOUT + 1 V, IOUT = 100 µA to 500 mA , VOUT ≥ 3.3
V
0.45
UNIT
%
%
ΔVOUT(ΔVIN)
Line regulation
VIN = VOUT + 1 V to 40 V, IOUT = 100 µA
0.2
%
ΔVOUT
Load transient response
settling time
tR = tF = 1 µs; COUT = 10 µF, VOUT ≥ 3.3V
100
µs
ΔVOUT
Load transient response
overshoot, undershoot(2)
tR = tF = 1 µs; COUT =
10 µF
10%
%VOUT
IOUT = 150 mA to 350 mA
–2%
IOUT = 350 mA to 150 mA
IOUT = 0 mA to 500 mA
–10%
VIN = VOUT + 1 V to 40V, IOUT = 0 mA, TJ = 25ºC(3)
IQ
Quiescent current
VIN = VOUT + 1 V to 40 V, IOUT = 0
17
mA(3)
Dropout voltage fixed output
voltages (DDA Package)
43
IOUT = 315 mA, VOUT ≥ 3.3 V, VIN = VOUT(NOM)
260
360
IOUT = 450 mA, VOUT ≥ 3.3 V, VIN = VOUT(NOM)
335
475
IOUT = 500 mA, VOUT ≥ 3.3 V, VIN = VOUT(NOM)
360
535
IOUT = 315 mA, VOUT ≥ 3.3 V, VIN = VOUT(NOM)
275
400
IOUT = 450 mA, VOUT ≥ 3.3 V, VIN = VOUT(NOM)
360
525
IOUT = 500 mA, VOUT ≥ 3.3 V, VIN = VOUT(NOM)
390
575
IOUT ≤ 1 mA, VOUT ≥ 3.3 V, VIN = VOUT(NOM) x 0.95
Dropout voltage fixed output
voltages (KVU Package)
VDO
µA
35
IOUT ≤ 1 mA, VOUT ≥ 3.3 V, VIN = VOUT(NOM) x 0.95
VDO
21
26
IOUT = 500 µA
6
MAX
–0.85
VIN = VOUT + 1 V to 40 V, IOUT = 100 µA to 450
ΔVOUT(ΔIOUT)
MIN
VIN = VOUT + 1 V to 40 V, IOUT = 100 µA to 450 mA, TJ =
25ºC(1)
mV
46
mV
VUVLO(RISING)
Rising input supply UVLO
VIN rising
2.6
2.7
2.82
V
VUVLO(FALLING)
Falling input supply UVLO
VIN falling
2.38
2.5
2.6
V
540
VUVLO(HYST)
V UVLO(IN) hysteresis
ICL
Output current limit
VIN = VOUT + 1 V, VOUT short to 90% x VOUT(NOM)
230
mV
PSRR
Power supply rejection ratio
VIN - VOUT = 1 V, frequency = 1 kHz, IOUT = 450 mA
RPG
Power-good internal pull up
resistor
VPG(OL)
PG pin low level output voltage VOUT ≤ 0.83 x VOUT
VPG(TH,RISING)
Default power-good threshold
VOUT rising
85
95
VPG(TH,FALLING)
Default power-good threshold
VOUT falling
83
93
VPG(HYST)
Power-good hysteresis
VDLY(TH)
Threshold to release powergood high
Voltage at DELAY pin rising
1.17
1.21
1.25
V
IDLY(CHARGE)
Delay capacitor charging
current
Voltage at DELAY pin = 1 V
1
1.5
2
µA
TJ
Junction temperature
150
°C
TSD(SHUTDOWN)
Junction shutdown
temperature
780
70
10
30
mA
dB
50
kΩ
0.4
V
%VOUT
2
–40
175
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6.5 Electrical Characteristics (continued)
specified at TJ = –40°C to +150°C, VIN = 13.5 V, IOUT = 0 mA, COUT = 2.2 µF, 1 mΩ < COUT ESR < 2 Ω, CIN = 1 µF typical
values are at TJ = 25°C
PARAMETER
TSD(HYST)
(1)
(2)
(3)
Test Conditions
MIN
Hysteresis of thermal
shutdown
TYP
MAX
20
UNIT
°C
Power dissipation is limited to 2 W for device production testing purposes. The power dissipation can be higher during normal
operation. See the thermal dissipation section for more information on how much power the device can dissipate while maintaining a
junction temperature below 150℃.
Specified by design.
For the adjustable output this is tested in unity gain and resistor current is not included.
6.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TIMING POWER-GOOD
t(DLY_FIX)
Power-good propagation delay
No capacitor connect at DELAY pin
100
µs
t(Deglitch)
Power-good deglitch time
No capacitor connect at DELAY pin
90
µs
Power-good propagation delay
Delay capacitor value:
C(DELAY) = 100 nF
80
ms
t(DLY)
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6.7 Typical Characteristics
specified at TJ = –40°C to +150°C, VIN = 13.5 V, IOUT = 100 µA, COUT = 2.2 µF, 1 mΩ < COUT ESR < 2 Ω, and CIN = 1 µF
(unless otherwise noted)
5.015
0.3
500 mA
100 PA
0.25
0.2
0.15
0qC
25qC
85qC
125qC
150qC
5.005
Output Voltage (V)
Accuracy (%)
-55qC
-40qC
5.01
0.1
0.05
0
-0.05
-0.1
-0.15
5
4.995
4.99
4.985
-0.2
4.98
-0.25
-0.3
-60
-40
-20
0
20
40
60
80
Temperature qC
4.975
100 120 140 160
5
10
15
20
25
Input Voltage (V)
30
35
40
VOUT = 5 V, IOUT = 150 mA
Figure 6-1. Accuracy vs Temperature
Figure 6-2. Line Regulation vs VIN
5.015
5.015
-55qC
-40qC
5.01
0qC
25qC
85qC
125qC
150qC
5
4.995
4.99
150qC
4.995
4.99
4.985
4.98
4.98
4.975
5
10
15
20
25
Input Voltage (V)
30
35
40
5
10
VOUT = 5 V, IOUT = 5 mA
15
20
25
Input Voltage (V)
30
35
40
VOUT = 5 V, IOUT = 1 mA
Figure 6-3. Line Regulation vs VIN
Figure 6-4. Line Regulation vs VIN
5.015
5.01
-55qC
-40qC
5.01
0qC
25qC
85qC
125qC
150qC
-40 qC
25 qC
85 qC
5.0075
5.005
5.005
Output Voltage (V)
Output Voltage (V)
85qC
125qC
5
4.985
4.975
5
4.995
4.99
5.0025
5
4.9975
4.985
4.995
4.98
4.9925
4.975
0
25
50
75
100
Output Current (mA)
125
150
4.99
0
5
VOUT = 5 V
10
15
20
25
Input Voltage (V)
30
35
40
COUT = 10 µF, VOUT = 5 V
Figure 6-5. Load Regulation vs IOUT
8
0qC
25qC
5.005
Output Voltage (V)
5.005
Output Voltage (V)
-55qC
-40qC
5.01
Figure 6-6. Line Regulation at 50 mA
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6.7 Typical Characteristics (continued)
specified at TJ = –40°C to +150°C, VIN = 13.5 V, IOUT = 100 µA, COUT = 2.2 µF, 1 mΩ < COUT ESR < 2 Ω, and CIN = 1 µF
(unless otherwise noted)
5.01
550
-40 qC
25 qC
85 qC
5.0075
450
Dropout Voltage (mV)
5.005
Output Voltage (V)
-55 qC
-40 qC
0 qC
500
5.0025
5
4.9975
4.995
25 qC
85 qC
125 qC
150 qC
400
350
300
250
200
150
100
4.9925
50
0
4.99
0
5
10
15
20
25
Input Voltage (V)
30
35
0
40
50
100
400
450
500
Figure 6-8. Dropout Voltage (VDO) vs IOUT
Figure 6-7. Line Regulation at 100 mA
90
10
5
80
2
1
0.5
70
60
Noise (PV/—Hz)
Power Supply Rejection Ratio (dB)
200 250 300 350
Output Current (mA)
VIN = 3 V
COUT = 10 µF, VOUT = 5 V
50
40
30
20
1 mA
10 mA
10
0
10
100
50 mA
150 mA
1k
350 mA
500 mA
10k
100k
Frequency (Hz)
1M
10M
0.2
0.1
0.05
0.02
0.01
0.005
IOUT
10 mA, 364.8 PVRMS
150 mA, 391.4 PVRMS
500 mA, 437.2 PVRMS
0.002
0.001
10
COUT = 10 µF (X7R 50 V), VOUT = 5 V
100
1k
10k
100k
Frequency (Hz)
1M
10M
COUT = 10 µF (X7R 50 V), VOUT = 5 V
Figure 6-9. PSRR vs Frequency and IOUT
Figure 6-10. Noise vs Frequency
80
Power Supply Rejection Ratio (dB)
10
5
Noise (PV/—Hz)
150
2
1
0.5
0.2
0.1
0.05
0.02
0.01
0.005
0.002
0.001
10
IOUT
10 mA, 252.5 PVRMS
150 mA, 267.6 PVRMS
500 mA, 293.8 PVRMS
100
1k
10k
100k
Frequency (Hz)
COUT = 10 µF (X7R 50 V), VOUT = 3.3 V
Figure 6-11. Noise vs Frequency
70
60
50
40
30
20
10
6 V VIN
1M
10M
0
10
100
7 V VIN
1k
10 VIN
10k
100k
Frequency (Hz)
13.5 V VIN
1M
10M
COUT = 10 µF (X7R 50 V), IOUT = 500 mA, VOUT = 5 V
Figure 6-12. PSRR vs Frequency and VIN
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6.7 Typical Characteristics (continued)
0.25
VIN
VOUT 0.2
35
0.15
30
0.1
25
0.05
20
0
15
-0.05
10
5
0
1000
1500
Time (Ps)
2000
6
180
4
120
2
60
0
0
-2
-60
-4
-120
-0.1
-6
-180
-0.15
-8
-240
-10
-300
500
-0.2
3000
2500
300
VIN
VOUT 240
0
50
100
300
-40qC
25qC
150qC
IOUT
0
0
-50
-100
-100
-200
-150
-300
2.5
3
Time (ms)
3.5
4
4.5
25qC
150qC
IOUT
60
0
-60
-20
-120
-30
-180
-40
-240
-50
-300
120
160
Time (Ps)
200
240
-100
-100
-200
280
VOUT = 5 V, IOUT = 45 mA to 105 mA, slew rate = 0.1 A/µs,
COUT = 10 µF
Figure 6-17. Load Transient, 45 mA to 105 mA
20
40
60
80
100 120
Time (Ps)
140
160
180
-300
200
Figure 6-16. Load Transient, No Load to 100-mA Rising Edge
40
10
-10
0
-50
50
120
80
0
240
20
40
100
300
180
0
50
VOUT = 5 V, IOUT = 0 mA to 100 mA, slew rate = 1 A/µs,
COUT = 10 µF
30
0
IOUT
200
0
200
-40qC
Output Current (mA)
AC Coupled Output Voltage (mV)
-40qC
40
150qC
-150
Figure 6-15. Load Transient, No Load to 100 mA
50
25qC
100
5
AC Coupled Output Voltage (mV)
2
VOUT = 5 V, IOUT = 0 mA to 100 mA, slew rate = 1 A/µs,
COUT = 10 µF
10
AC Coupled Output Voltage (mV)
200
100
1.5
450
300
-40qC
50
1
400
150
Output Current (mA)
AC Coupled Output Voltage (mV)
150
0.5
350
Figure 6-14. Line Transients
Figure 6-13. Line Transients
0
200 250 300
Time (Ps)
VOUT = 5 V, IOUT = 100 mA, VIN = 5.5 V to 6.5 V,
rise time = 1 µs
VOUT = 5 V, IOUT = 1 mA, VIN = 13.5 V to 45 V,
slew rate = 2.7 V/µs
100
150
Output Current (mA)
500
8
25qC
150qC
IOUT
150
30
100
20
50
10
0
0
-50
-10
-100
-20
-150
-30
-200
-40
0
20
40
60
80
100 120
Time (Ps)
140
160
180
Output Current (mA)
0
10
Input Voltage (V)
40
Output Voltage (V)
Input Voltage (V)
45
AC Coupled Output Voltage (mV)
specified at TJ = –40°C to +150°C, VIN = 13.5 V, IOUT = 100 µA, COUT = 2.2 µF, 1 mΩ < COUT ESR < 2 Ω, and CIN = 1 µF
(unless otherwise noted)
-250
200
VOUT = 5 V, IOUT = 45 mA to 105 mA, slew rate = 0.1 A/µs,
COUT = 10 µF
Figure 6-18. Load Transient, 45-mA to 105-mA Rising Edge
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6.7 Typical Characteristics (continued)
specified at TJ = –40°C to +150°C, VIN = 13.5 V, IOUT = 100 µA, COUT = 2.2 µF, 1 mΩ < COUT ESR < 2 Ω, and CIN = 1 µF
(unless otherwise noted)
200
100
0
0
-50
-100
-100
-200
-150
-300
0.5
0.75
1
1.25
Time (ms)
1.5
1.75
400
0
300
-50
200
-100
-150
75
100 125 150
Time (Ps)
175
200
225
-50
-100
-100
-200
80
100 120
Time (Ps)
140
160
180
-300
200
600
-40qC
25qC
150qC
IOUT
500
400
300
100
200
50
100
0
0
-50
-100
-100
-200
-150
-300
-200
-400
-250
-500
-600
0.5
1
1.5
2
2.5
3
Time (ms)
3.5
4
4.5
5
VOUT = 5 V, IOUT = 0 mA to 500 mA, slew rate = 1 A/µs,
COUT = 10 µF
Figure 6-22. Load Transient, No Load to 500 mA
660
750
659
50
600
658
0
450
-50
300
-100
150
-150
0
-200
-150
IOUT
657
IOUT (mA)
Output Current (mA)
150qC
60
150
100
25qC
40
200
900
-40qC
20
250
0
Figure 6-21. Load Transient, 150-mA to 350-mA
150
0
-300
0
250
VOUT = 5 V, IOUT = 150 mA to 350 mA, slew rate = 0.1 A/µs,
COUT = 10 µF
AC Coupled Output Voltage (mV)
0
300
100
50
100
Figure 6-20. Load Transient, No Load to 150-mA Rising Edge
Output Current (mA)
AC Coupled Output Voltage (mV)
50
25
50
VOUT = 5 V, IOUT = 0 mA to 150 mA, slew rate = 1 A/µs,
COUT = 10 µF
600
-40qC
25qC
150qC 500
IOUT
0
200
0
Figure 6-19. Load Transient, No Load to 150-mA
100
IOUT
-150
VOUT = 5 V, IOUT = 0 mA to 150 mA, slew rate = 1 A/µs,
COUT = 10 µF
150
150qC
100
2
AC Coupled Output Voltage (mV)
0.25
25qC
Output Current (mA)
50
0
300
-40qC
AC Coupled Output Voltage (mV)
100
150
Output Current (mA)
300
-40qC
25qC
150qC
IOUT
Output Current (mA)
AC Coupled Output Voltage (mV)
150
656
655
654
653
652
-250
0
20
40
60
80
100 120
Time (Ps)
140
160
180
-300
200
VOUT = 5 V, IOUT = 0 mA to 500 mA, slew rate = 1 A/µs,
COUT = 10 µF
Figure 6-23. Load Transient, No Load to 500-mA Rising Edge
651
Current Limit
650
-75
-45
-15
15
45
75
Temperature (qC)
105
135
VIN = VOUT + 1 V, VOUT = 90% × VOUT(NOM)
Figure 6-24. Output Current Limit vs Temperature
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6.7 Typical Characteristics (continued)
specified at TJ = –40°C to +150°C, VIN = 13.5 V, IOUT = 100 µA, COUT = 2.2 µF, 1 mΩ < COUT ESR < 2 Ω, and CIN = 1 µF
(unless otherwise noted)
175
40
-55qC
-40qC
35
0qC
25qC
85qC
125qC
150qC
125
Iq (PA)
30
Iq (PA)
-55qC
-40qC
0qC
25qC
85qC
150
25
20
125qC
150qC
100
75
50
15
25
10
0
5
10
15
20
25
Input Voltage (V)
30
35
40
0
5
10
15
20
25
Input Voltage (V)
30
35
40
VOUT = 5 V
Figure 6-26. Quiescent Current (IQ) vs VIN
281
1300
1200
1100
1000
900
800
700
600
500
400
300
200
100
0
-55 qC
-40 qC
0 qC
25 qC
85 qC
125 qC
150 qC
280
279
Ground Current (PA)
Ground Current (PA)
Figure 6-25. Quiescent Current (IQ) vs VIN
278
277
276
275
274
273
272
0
50
100
150
200 250 300 350
Output Current (mA)
400
450
271
-75
500
Figure 6-27. Ground Current (IGND) vs IOUT
-50
-25
0
25
50
75
Temperature (qC)
100
125
150
Figure 6-28. Ground Current at 100 mA
92
26
Falling Threshold
Rising Threshold
91
PG Threshold (%)
Ground Current (PA)
25
24
23
90
89
22
88
21
-75
-50
-25
0
25
50
75
Ambient Temperature (qC)
100
Figure 6-29. Ground Current at 500 µA
12
125
150
87
-60
-40
-20
0
20 40 60 80
Temperature (qC)
100 120 140 160
Figure 6-30. PG Threshold vs Temperature
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6.7 Typical Characteristics (continued)
specified at TJ = –40°C to +150°C, VIN = 13.5 V, IOUT = 100 µA, COUT = 2.2 µF, 1 mΩ < COUT ESR < 2 Ω, and CIN = 1 µF
(unless otherwise noted)
20
800
700
600
10
500
7.5
400
5
300
2.5
200
0
100
-2.5
2.7
UVLO Threshold (V)
12.5
2.65
2.6
2.55
2.5
0
-5
0
250
500
2.45
-100
750 1000 1250 1500 1750 2000 2250 2500
Time (Ps)
2.4
-60
VIN = 13.5 V, VOUT = 5 V, IOUT = 150 mA, COUT = 10 µF
-40
-20
0
20 40 60 80
Temperature (qC)
100 120 140 160
Figure 6-32. Undervoltage Lockout (UVLO) Threshold vs
Temperature
Figure 6-31. Startup Plot Inrush Current
1.58
20
18
1.57
16
Output voltage (V)
Delay Pin Current (PA)
Falling Threshold
Rising Threshold
2.75
Output Current (mA)
15
Voltage (V)
2.8
900
Input Voltage
Output Voltage
Output Current
17.5
1.56
1.55
1.54
14
12
10
8
1.53
6
1.52
-60
-40
-20
0
20 40 60 80
Temperature qC
4
0.2
100 120 140 160
0.4
VDELAY = 1 V
Figure 6-33. Delay Pin Current vs Temperature
ESR (:)
0
25
50
75 100 125
Temperature (qC)
150
175
200
1.6
1.8
x
0.2
0.1
0.05
x
Stable region
0.02
0.01
0.005
0.002
0.001
0.0005
-25
1.4
xx
xxx
xxxx
xxx
xxxx
xx
xxx
xxxx
xxx
xxxx
xxx
xx
xxx
xxxx
xxx
xxxx
xxx
xx
xxx
xxxx
xxx
xxxx
xxx
xx
2
1
0.5
OFF
-50
0.8
1
1.2
Injected current (mA)
Figure 6-34. Output Voltage vs Injected Current
10
5
ON
0.6
x
0.0002
0.0001
1
2
3 4 5 6 78 10
20 30 50 70 100
COUT (PF)
200 300 500
Figure 6-35. Thermal Shutdown
Figure 6-36. Stability, ESR vs COUT
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7 Detailed Description
7.1 Overview
The TPS7B87-Q1 is a low-dropout linear regulator (LDO) with improved transient performance that allows
for quick response to changes in line or load conditions. The device aslo features a novel output overshoot
reduction feature that minimizes output overshoot during cold-crank conditions.
The integrated power-good and delay features allow for the system to notify down-stream components when the
power is good and assist in sequencing requirements.
During normal operation, the device has a tight DC accuracy of ±0.85% over line, load, and temperature. The
increased accuracy allows for the powering of sensitive analog loads or sensors.
7.2 Functional Block Diagram
IN
OUT
Current
Limit
R1
±
+
Thermal
Shutdown
UVLO
R2
Bandgap
±
VREF
+
VOUT
30k
VSUBREG
PG
DELAY
±
VREF
+
Cap
Control
GND
14
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7.3 Feature Description
7.3.1 Power-Good (PG)
The PG signal provides an easy solution to meet demanding sequencing requirements because PG alerts when
the output nears its nominal value. PG can be used to signal other devices in a system when the output voltage
is near, at, or above the set output voltage (VOUT(nom)). Figure 7-1 shows a simplified schematic. The PG signal
is an internal pullup resistor to the nominal output voltage and is active high. The PG circuit sets the PG pin into
a high-impedance state to indicate that the power is good.
OUT
PG
+
+
±
VREF
Figure 7-1. Simplified Power-Good Schematic
7.3.2 Adjustable Power-Good Delay Timer (DELAY)
The power-good delay period is a function of the external capacitor on the DELAY pin. The adjustable delay
configures the amount of time required before the PG pin becomes high. This delay is configured by connecting
an external capacitor from this pin to GND. Figure 7-2 shows the typical timing diagram for the power-good delay
pin. If the DELAY pin is left floating, the power-good delay is t(DLY_FIX). For more information on how to program
the PG delay, see the Setting the Adjustable Power-Good Delay section.
VIN
V(UVLO)
t < t(DEGLITCH)
VOUT
DELAY
V(PG_HYST)
V(PG_TH) rising
V(PG_ADJ) rising
V(PG_TH) falling
V(PG_ADJ) falling
V(DLY _TH)
t(DEGLITCH)
t(DLY )
t(DEGLITCH)
t(DLY )
PG
Power Up
Input Voltage Drop
Undervoltage
Power Down
V(PG_TH) falling = V(PG_TH) rising – V(PG_HYST)..
Figure 7-2. Typical Power-Good Timing Diagram
7.3.3 Undervoltage Lockout
The device has an independent undervoltage lockout (UVLO) circuit that monitors the input voltage, allowing a
controlled and consistent turn on and off of the output voltage. To prevent the device from turning off if the input
drops during turn on, the UVLO has hysteresis as specified in the Electrical Characteristics table.
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7.3.4 Thermal Shutdown
The device contains a thermal shutdown protection circuit to disable the device when the junction temperature
(TJ) of the pass transistor rises to TSD(shutdown) (typical). Thermal shutdown hysteresis assures that the device
resets (turns on) when the temperature falls to TSD(reset) (typical).
The thermal time-constant of the semiconductor die is fairly short, thus the device may cycle on and off
when thermal shutdown is reached until power dissipation is reduced. Power dissipation during startup can
be high from large VIN – VOUT voltage drops across the device or from high inrush currents charging large
output capacitors. Under some conditions, the thermal shutdown protection disables the device before startup
completes.
For reliable operation, limit the junction temperature to the maximum listed in the Recommended Operating
Conditions table. Operation above this maximum temperature causes the device to exceed its operational
specifications. Although the internal protection circuitry of the device is designed to protect against thermal
overall conditions, this circuitry is not intended to replace proper heat sinking. Continuously running the device
into thermal shutdown or above the maximum recommended junction temperature reduces long-term reliability.
7.3.5 Current Limit
The device has an internal current limit circuit that protects the regulator during transient high-load current faults
or shorting events. The current limit is a brickwall scheme. In a high-load current fault, the brickwall scheme
limits the output current to the current limit (ICL). ICL is listed in the Electrical Characteristics table.
The output voltage is not regulated when the device is in current limit. When a current limit event occurs, the
device begins to heat up because of the increase in power dissipation. When the device is in brickwall current
limit, the pass transistor dissipates power [(VIN – VOUT) × ICL]. If thermal shutdown is triggered, the device
turns off. After the device cools down, the internal thermal shutdown circuit turns the device back on. If the
output current fault condition continues, the device cycles between current limit and thermal shutdown. For more
information on current limits, see the Know Your Limits application report.
Figure 7-3 shows a diagram of the current limit.
VOUT
Brickwall
VOUT(NOM)
IOUT
0V
0 mA
IRATED
ICL
Figure 7-3. Current Limit
16
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7.4 Device Functional Modes
7.4.1 Device Functional Mode Comparison
The Device Functional Mode Comparison table shows the conditions that lead to the different modes of
operation. See the Electrical Characteristics table for parameter values.
Table 7-1. Device Functional Mode Comparison
PARAMETER
OPERATING MODE
VIN
IOUT
TJ
Normal operation
VIN > VOUT(nom) + VDO and VIN > VIN(min)
IOUT < IOUT(max)
TJ < TSD(shutdown)
Dropout operation
VIN(min) < VIN < VOUT(nom) + VDO
IOUT < IOUT(max)
TJ < TSD(shutdown)
VIN < VUVLO
Not applicable
TJ > TSD(shutdown)
Disabled
(any true condition
disables the device)
7.4.2 Normal Operation
The device regulates to the nominal output voltage when the following conditions are met:
•
•
•
The input voltage is greater than the nominal output voltage plus the dropout voltage (VOUT(nom) + VDO)
The output current is less than the current limit (IOUT < ICL)
The device junction temperature is less than the thermal shutdown temperature (TJ < TSD)
7.4.3 Dropout Operation
If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other
conditions are met for normal operation, the device operates in dropout mode. In this mode, the output voltage
tracks the input voltage. During this mode, the transient performance of the device becomes significantly
degraded because the pass transistor is in the ohmic or triode region, and acts as a switch. Line or load
transients in dropout can result in large output-voltage deviations.
When the device is in a steady dropout state (defined as when the device is in dropout, VIN < VOUT(NOM) + VDO,
directly after being in a normal regulation state, but not during startup), the pass transistor is driven into the
ohmic or triode region. When the input voltage returns to a value greater than or equal to the nominal output
voltage plus the dropout voltage (VOUT(NOM) + VDO), the output voltage can overshoot for a short period of time
while the device pulls the pass transistor back into the linear region.
7.4.4 Disabled
The output of the device can be shutdown by forcing the input voltage below the UVLO falling threshold (see
the Electrical Characteristics table). When disabled, the pass transistor is turned off and internal circuits are
shutdown.
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
8.1.1 Input and Output Capacitor Selection
The TPS7B87-Q1 requires an output capacitor of 2.2 µF or larger (1 µF or larger capacitance) for stability
and an equivalent series resistance (ESR) between 0.001 Ω and 2 Ω. For best transient performance, use
X5R- and X7R-type ceramic capacitors because these capacitors have minimal variation in value and ESR over
temperature. When choosing a capacitor for a specific application, be mindful of the DC bias characteristics for
the capacitor. Higher output voltages cause a significant derating of the capacitor. For best performance, the
maximum recommended output capacitance is 220 µF.
Although an input capacitor is not required for stability, good analog design practice is to connect a capacitor
from IN to GND. Some input supplies have a high impedance, thus placing the input capacitor on the input
supply helps reduce the input impedance. This capacitor counteracts reactive input sources and improves
transient response, input ripple, and PSRR. If the input supply has a high impedance over a large range of
frequencies, several input capacitors can be used in parallel to lower the impedance over frequency. Use a
higher-value capacitor if large, fast, rise-time load transients are anticipated, or if the device is located several
inches from the input power source.
8.1.2 Dropout Voltage
Dropout voltage (VDO) is defined as the input voltage minus the output voltage (VIN – VOUT) at the rated output
current (IRATED), where the pass transistor is fully on. IRATED is the maximum IOUT listed in the Recommended
Operating Conditions table. The pass transistor is in the ohmic or triode region of operation, and acts as a
switch. The dropout voltage indirectly specifies a minimum input voltage greater than the nominal programmed
output voltage at which the output voltage is expected to stay in regulation. If the input voltage falls to less than
the nominal output regulation, then the output voltage falls as well.
For a CMOS regulator, the dropout voltage is determined by the drain-source on-state resistance (RDS(ON)) of the
pass transistor. Therefore, if the linear regulator operates at less than the rated current, the dropout voltage for
that current scales accordingly. The following equation calculates the RDS(ON) of the device.
RDS(ON) =
VDO
IRATED
(1)
8.1.3 Reverse Current
Excessive reverse current can damage this device. Reverse current flows through the intrinsic body diode of the
pass transistor instead of the normal conducting channel. At high magnitudes, this current flow degrades the
long-term reliability of the device.
Conditions where reverse current can occur are outlined in this section, all of which can exceed the absolute
maximum rating of VOUT ≤ VIN + 0.3 V.
•
•
•
If the device has a large COUT and the input supply collapses with little or no load current
The output is biased when the input supply is not established
The output is biased above the input supply
If reverse current flow is expected in the application, external protection is recommended to protect the device.
Reverse current is not limited in the device, so external limiting is required if extended reverse voltage operation
is anticipated.
18
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8.1.4 Power Dissipation (PD)
Circuit reliability requires consideration of the device power dissipation, location of the circuit on the printed
circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator must have few
or no other heat-generating devices that cause added thermal stress.
To first-order approximation, power dissipation in the regulator depends on the input-to-output voltage difference
and load conditions. The following equation calculates power dissipation (PD).
PD = (VIN – VOUT) × IOUT
(2)
Note
Power dissipation can be minimized, and therefore greater efficiency can be achieved, by correct
selection of the system voltage rails. For the lowest power dissipation use the minimum input voltage
required for correct output regulation.
For devices with a thermal pad, the primary heat conduction path for the device package is through the thermal
pad to the PCB. Solder the thermal pad to a copper pad area under the device. This pad area must contain an
array of plated vias that conduct heat to additional copper planes for increased heat dissipation.
The maximum power dissipation determines the maximum allowable ambient temperature (TA) for the device.
According to the following equation, power dissipation and junction temperature are most often related by the
junction-to-ambient thermal resistance (RθJA) of the combined PCB and device package and the temperature of
the ambient air (TA).
TJ = TA + (RθJA × PD)
(3)
Thermal resistance (RθJA) is highly dependent on the heat-spreading capability built into the particular PCB
design, and therefore varies according to the total copper area, copper weight, and location of the planes.
The junction-to-ambient thermal resistance listed in the Thermal Information table is determined by the JEDEC
standard PCB and copper-spreading area, and is used as a relative measure of package thermal performance.
8.1.4.1 Thermal Performance Versus Copper Area
The most used thermal resistance parameter RθJA is highly dependent on the heat-spreading capability built into
the particular PCB design, and therefore varies according to the total copper area, copper weight, and location
of the planes. The RθJA recorded in the Thermal Information table in the Specifications section is determined
by the JEDEC standard (see Figure 8-1), PCB, and copper-spreading area, and is only used as a relative
measure of package thermal performance. For a well-designed thermal layout, RθJA is actually the sum of the
package junction-to-case (bottom) thermal resistance (RθJCbot) plus the thermal resistance contribution by the
PCB copper.
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Mold
Compound
Die
Wire
Die
Attach
2oz
Signal
Trace
Internal Signal
or power plane
1oz copper
Lead
Frame
Internal
GND plane
1oz copper
Thermal
Pad or Tab
of the LDO
Bottom
Relief
2oz copper
Thermal
Vias
Figure 8-1. JEDEC Standard 2s2p PCB
22
105
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
25
4
4
2
2
0
10
20
Layer
Layer
Layer
Layer
PCB,
PCB,
PCB,
PCB,
30
40
50
60
70
Cu Area Per Layer (cm 2)
1
2
1
2
80
oz
oz
oz
oz
copper
copper
copper
copper
90
100
Figure 8-2. RθJA vs Copper Area (DDA Package)
20
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