TPS7B88-Q1
SBVS377 –TPS7B88-Q1
JANUARY 2021
SBVS377 – JANUARY 2021
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TPS7B88-Q1 500-mA, 40-V, Low-Dropout Regulator
1 Features
3 Description
•
The TPS7B88-Q1 is a low-dropout linear regulator
designed to connect to the battery in automotive
applications. The device has an input voltage range
extending to 40 V, which allows the device to
withstand transients (such as load dump) that are
anticipated in automotive systems. With only a 17-µA
quiescent current at light loads, the device is an
optimal solution for powering always-on components
such as microcontrollers (MCUs) and controller area
network (CAN) transceivers in standby systems.
•
•
•
•
•
•
•
•
•
AEC-Q100 qualified for automotive applications:
– Temperature grade 1: –40°C to +125°C, TA
– Junction temperature: –40°C to +150°C, TJ
Input voltage range: 3 V to 40 V (42 V max)
Output voltage range: 3.3 V and 5 V (fixed)
Maximum output current: 500 mA
Output voltage accuracy: ±1.15% (max)
Low dropout voltage:
– 525 mV (max) at 450 mA
Low quiescent current:
– 17 µA (typ) at light loads
Excellent line transient response:
– ±2% VOUT deviation during cold-crank
– ±2% VOUT deviation (1-V/µs VIN slew rate)
Stable with a 2.2-µF or larger capacitor
Package 3-pin TO-252: (RθJA): 30°C/W
The device has state-of-the-art transient response
that allows the output to quickly react to changes in
load or line (for example, during cold-crank
conditions). Additionally, the device has a novel
architecture that minimizes output overshoot when
recovering from dropout. During normal operation, the
device has a tight DC accuracy of ±1.15% over line,
load, and temperature.
2 Applications
•
•
•
The device is available in thermally conductive
packaging to allow the parts to efficiently transfer heat
to the circuit board.
Reconfigurable instrument clusters
Body control modules (BCM)
Always-on battery-connected applications:
– Automotive gateways
– Remote keyless entries (RKE)
Device Information (1)
PART NUMBER
TPS7B88-Q1
(1)
40
0.25
VIN
VOUT 0.2
35
0.15
30
0.1
25
0.05
20
0
15
-0.05
10
-0.1
5
BODY SIZE (NOM)
6.60 mm × 6.10 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
IN
OUT
TPS7B88-Q1
GND
Output Voltage (V)
Input Voltage (V)
45
PACKAGE
TO-252 (3)
Output Equal to Reference Voltage
-0.15
0
0
500
1000
1500
Time (Ps)
2000
2500
-0.2
3000
Line Transient Response (3-V/µs VIN Slew Rate)
An©IMPORTANT
NOTICEIncorporated
at the end of this data sheet addresses availability, warranty, changes, use in
safety-critical
applications,
Copyright
2021 Texas Instruments
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intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings ....................................... 4
6.2 ESD Ratings .............................................................. 4
6.3 Recommended Operating Conditions ........................4
6.4 Thermal Information ...................................................4
6.5 Electrical Characteristics ............................................5
6.6 Typical Characteristics................................................ 6
7 Detailed Description......................................................12
7.1 Overview................................................................... 12
7.2 Functional Block Diagram......................................... 12
7.3 Feature Description...................................................12
7.4 Device Functional Modes..........................................14
8 Application and Implementation.................................. 15
8.1 Application Information............................................. 15
8.2 Typical Application.................................................... 17
9 Power Supply Recommendations................................19
10 Layout...........................................................................20
10.1 Layout Guidelines................................................... 20
10.2 Layout Example...................................................... 21
11 Device and Documentation Support..........................22
11.1 Device Support........................................................22
11.2 Documentation Support.......................................... 22
11.3 Receiving Notification of Documentation Updates.. 22
11.4 Support Resources................................................. 22
11.5 Trademarks............................................................. 22
11.6 Electrostatic Discharge Caution.............................. 22
11.7 Glossary.................................................................. 22
12 Mechanical, Packaging, and Orderable
Information.................................................................... 22
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
DATE
January 2021
2
REVISION
*
NOTES
Initial Release
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5 Pin Configuration and Functions
1
2
3
IN
GND
OUT
Thermal pad
Not to scale
Figure 5-1. KVU Package, 3-Pin TO-252, Top View
Table 5-1. Pin Functions
PIN
NAME
KVU
TYPE(1)
DESCRIPTION
GND
2
G
Ground pin. Connect this pin to the thermal pad with a low-impedance connection.
IN
1
P
Input power-supply voltage pin. For best transient response and to minimize input
impedance, use the recommended value or larger ceramic capacitor from IN to ground as
listed in the Recommended Operating Conditions table and the Input Capacitor section.
Place the input capacitor as close to the input of the device as possible
3
O
Regulated output voltage pin. A capacitor is required from OUT to ground for stability. For
best transient response, use the nominal recommended value or larger ceramic capacitor
from OUT to ground; see the Recommended Operating Conditions table and the Output
Capacitor section. Place the output capacitor as close to output of the device as possible.
If using a high ESR capacitor, decouple the output with a 100-nF ceramic capacitor.
Pad
—
Connect the thermal pad to a large area GND plane for improved thermal performance.
OUT
Thermal pad
(1)
I = input; O = output; P = power; G = ground.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX UNIT
VIN
Unregulated input
–0.3
42
V
VOUT
Regulated output
–0.3 VIN + 0.3 V(2)
V
TJ
Operating junction temperature
–40
150
°C
Tstg
Storage temperature
–65
150
°C
(1)
(2)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. Theseare stress ratings
only and functional operation of the device at these or any other conditionsbeyond those indicated under recommended operating
conditions isnot implied. Exposure to absolute-maximum-rated conditions for extended periods may affect devicereliability.
The absolute maximum rating is VIN + 0.3 V or 20 V, whichever is smaller
6.2 ESD Ratings
VALUE
Human-body model (HBM), per AEC Q100-002(1)
V(ESD)
(1)
Electrostatic discharge
Charged-device model (CDM), per AEC
Q100-011
UNIT
±2000
All pins
±500
Corner pins
±750
V
AEC Q100-002 indicates that HBM stressing shall be in accordancewith the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VIN
Input voltage
TYP
3
MAX
40
UNIT
V
VOUT
Output voltage
1.2
18
V
IOUT
Output current
0
500
mA
COUT
Output capacitor(2)
2.2
220
µF
ESR
Output capacitor ESR requirements
0.001
2
Ω
capacitor(1)
CIN
Input
TJ
Operating junction temperature
(1)
(2)
0.1
–40
1
µF
150
°C
For robust EMI performance the minimum input capacitance is 500 nF.
Effective output capacitance of 1 µF minimum required for stability.
6.4 Thermal Information
TPS7B88-Q1
THERMAL
METRIC(1) (2)
KVU
3 PINS
RθJA
Junction-to-ambient thermal resistance
30
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
39.5
°C/W
RθJB
Junction-to-board thermal resistance
8.6
°C/W
ψJT
Junction-to-top characterization parameter
2.6
°C/W
ψJB
Junction-to-board characterization parameter
8.6
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
1.3
°C/W
(1)
(2)
4
UNIT
The thermal data is based on the JEDEC standard high K profile,JESD 51-7. Two-signal, two-plane, four-layer board with 2-oz. copper.
The copper pad is soldered tothe thermal land pattern. Also, correct attachment procedure must be incorporated.
For more information about traditional and new thermal metrics,see the Semiconductor and IC PackageThermal Metrics application
report.
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6.5 Electrical Characteristics
specified at TJ = –40°C to +150°C, VIN = 13.5 V, IOUT = 0 mA, COUT = 2.2 µF, 1 mΩ < COUT ESR < 2 Ω, CIN = 1 µF typical
values are at TJ = 25°C
PARAMETER
VOUT
Regulated output
Test Conditions
Load regulation
TYP
MAX
–0.85
0.85
VIN = VOUT + 1 V to 40 V, IOUT = 100 µA to 500 mA, TJ =
25ºC(1)
–0.85
0.85
mA(1)
–1.15
1.15
VIN = VOUT + 1 V to 40 V, IOUT = 100 µA to 500 mA(1)
–1.15
1.15
VIN = VOUT + 1 V to 40 V, IOUT = 100 µA to 450
ΔVOUT(ΔIOUT)
MIN
VIN = VOUT + 1 V to 40 V, IOUT = 100 µA to 450 mA, TJ =
25ºC(1)
VIN = VOUT + 1 V, IOUT = 100 µA to 450 mA , VOUT ≥ 3.3
V
0.425
VIN = VOUT + 1 V, IOUT = 100 µA to 500 mA , VOUT ≥ 3.3
V
0.45
UNIT
%
%
ΔVOUT(ΔVIN)
Line regulation
VIN = VOUT + 1 V to 40 V, IOUT = 100 µA
0.2
%
ΔVOUT
Load transient response
settling time
tR = tF = 1 µs; COUT = 10 µF, VOUT ≥ 3.3V
100
µs
ΔVOUT
Load transient response
overshoot, undershoot(2)
tR = tF = 1 µs; COUT =
10 µF
10%
%VOUT
IOUT = 150 mA to 350 mA
–2%
IOUT = 350 mA to 150 mA
IOUT = 0 mA to 500 mA
–10%
VIN = VOUT + 1 V to 40V, IOUT = 0 mA, TJ = 25ºC(3)
IQ
Quiescent current
VIN = VOUT + 1 V to 40 V, IOUT = 0
17
mA(3)
26
IOUT = 500 µA
Dropout voltage fixed output
voltages (KVU Package)
µA
35
IOUT ≤ 1 mA, VOUT ≥ 3.3 V, VIN = VOUT(NOM) x 0.95
VDO
21
46
IOUT = 315 mA, VOUT ≥ 3.3 V, VIN = VOUT(NOM)
275
400
IOUT = 450 mA, VOUT ≥ 3.3 V, VIN = VOUT(NOM)
360
525
IOUT = 500 mA, VOUT ≥ 3.3 V, VIN = VOUT(NOM)
390
575
mV
VUVLO(RISING)
Rising input supply UVLO
VIN rising
2.6
2.7
2.82
V
VUVLO(FALLING)
Falling input supply UVLO
VIN falling
2.38
2.5
2.6
V
VUVLO(HYST)
V UVLO(IN) hysteresis
ICL
Output current limit
VIN = VOUT + 1 V, VOUT short to 90% x VOUT(NOM)
540
VIN - VOUT = 1 V, frequency = 1 kHz, IOUT = 450 mA
PSRR
Power supply rejection ratio
TJ
Junction temperature
TSD(SHUTDOWN)
Junction shutdown
temperature
TSD(HYST)
Hysteresis of thermal
shutdown
(1)
(2)
(3)
230
mV
780
70
–40
mA
dB
150
°C
175
°C
20
°C
Power dissipation is limited to 2 W for device production testing purposes. The power dissipation can be higher during normal
operation. See the thermal dissipation section for more information on how much power the device can dissipate while maintaining a
junction temperature below 150℃.
Specified by design.
For the adjustable output this is tested in unity gain and resistor current is not included.
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6.6 Typical Characteristics
specified at TJ = –40°C to +150°C, VIN = 13.5 V, IOUT = 100 µA, COUT = 2.2 µF, 1 mΩ < COUT ESR < 2 Ω, CIN = 1 µF (unless
otherwise noted)
5.015
0.3
500 mA
100 PA
0.25
0.2
0.15
0qC
25qC
85qC
125qC
150qC
5.005
Output Voltage (V)
Accuracy (%)
-55qC
-40qC
5.01
0.1
0.05
0
-0.05
-0.1
-0.15
5
4.995
4.99
4.985
-0.2
4.98
-0.25
-0.3
-60
-40
-20
0
20
40
60
80
Temperature qC
4.975
100 120 140 160
5
10
15
20
25
Input Voltage (V)
30
35
40
VOUT = 5 V, IOUT = 150 mA
Figure 6-1. Accuracy vs Temperature
Figure 6-2. Line Regulation vs VIN
5.015
5.015
-55qC
-40qC
5.01
0qC
25qC
85qC
125qC
150qC
5
4.995
4.99
4.985
150qC
5
4.995
4.99
4.98
4.98
4.975
4.975
10
15
20
25
Input Voltage (V)
30
35
40
5
10
VOUT = 5 V, IOUT = 5 mA
15
20
25
Input Voltage (V)
30
35
40
VOUT = 5 V, IOUT = 1 mA
Figure 6-3. Line Regulation vs VIN
Figure 6-4. Line Regulation vs VIN
5.015
5.01
-55qC
-40qC
5.01
0qC
25qC
85qC
125qC
150qC
-40 qC
25 qC
85 qC
5.0075
5.005
5.005
Output Voltage (V)
Output Voltage (V)
85qC
125qC
4.985
5
5
4.995
4.99
5.0025
5
4.9975
4.985
4.995
4.98
4.9925
4.975
0
25
50
75
100
Output Current (mA)
125
150
4.99
0
5
VOUT = 5 V
10
15
20
25
Input Voltage (V)
30
35
40
COUT = 10 µF, VOUT = 5 V
Figure 6-5. Load Regulation vs IOUT
6
0qC
25qC
5.005
Output Voltage (V)
5.005
Output Voltage (V)
-55qC
-40qC
5.01
Figure 6-6. Line Regulation at 50 mA
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6.6 Typical Characteristics (continued)
specified at TJ = –40°C to +150°C, VIN = 13.5 V, IOUT = 100 µA, COUT = 2.2 µF, 1 mΩ < COUT ESR < 2 Ω, CIN = 1 µF (unless
otherwise noted)
5.01
550
-40 qC
25 qC
85 qC
5.0075
450
Dropout Voltage (mV)
5.005
Output Voltage (V)
-55 qC
-40 qC
0 qC
500
5.0025
5
4.9975
4.995
25 qC
85 qC
125 qC
150 qC
400
350
300
250
200
150
100
4.9925
50
0
4.99
0
5
10
15
20
25
Input Voltage (V)
30
35
0
40
50
100
400
450
500
Figure 6-8. Dropout Voltage (VDO) vs IOUT
Figure 6-7. Line Regulation at 100 mA
90
10
5
80
2
1
0.5
70
60
Noise (PV/—Hz)
Power Supply Rejection Ratio (dB)
200 250 300 350
Output Current (mA)
VIN = 3 V
COUT = 10 µF, VOUT = 5 V
50
40
30
20
1 mA
10 mA
10
0
10
100
50 mA
150 mA
1k
350 mA
500 mA
10k
100k
Frequency (Hz)
1M
10M
0.2
0.1
0.05
0.02
0.01
0.005
IOUT
10 mA, 364.8 PVRMS
150 mA, 391.4 PVRMS
500 mA, 437.2 PVRMS
0.002
0.001
10
COUT = 10 µF (X7R 50 V), VOUT = 5 V
100
1k
10k
100k
Frequency (Hz)
1M
10M
COUT = 10 µF (X7R 50 V), VOUT = 5 V
Figure 6-9. PSRR vs Frequency and IOUT
Figure 6-10. Noise vs Frequency
80
Power Supply Rejection Ratio (dB)
10
5
Noise (PV/—Hz)
150
2
1
0.5
0.2
0.1
0.05
0.02
0.01
0.005
0.002
0.001
10
IOUT
10 mA, 252.5 PVRMS
150 mA, 267.6 PVRMS
500 mA, 293.8 PVRMS
100
1k
60
50
40
30
20
10
6 V VIN
10k
100k
Frequency (Hz)
1M
COUT = 10 µF (X7R 50 V), VOUT = 3.3 V
Figure 6-11. Noise vs Frequency
70
10M
0
10
100
7 V VIN
1k
10 VIN
10k
100k
Frequency (Hz)
13.5 V VIN
1M
10M
COUT = 10 µF (X7R 50 V), IOUT = 500 mA, VOUT = 5 V
Figure 6-12. PSRR vs Frequency and VIN
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6.6 Typical Characteristics (continued)
0.25
VIN
VOUT 0.2
35
0.15
30
0.1
25
0.05
20
0
15
-0.05
10
5
0
1000
1500
Time (Ps)
2000
6
180
4
120
2
60
0
0
-2
-60
-4
-120
-0.1
-6
-180
-0.15
-8
-240
-10
-300
500
-0.2
3000
2500
300
VIN
VOUT 240
0
50
100
300
-40qC
25qC
150qC
IOUT
0
0
-50
-100
-100
-200
-150
AC Coupled Output Voltage (mV)
200
100
-300
1.5
2
2.5
3
Time (ms)
3.5
4
4.5
150qC
IOUT
10
60
0
-10
-60
-20
-120
-30
-180
-40
-240
-50
-300
120
160
Time (Ps)
200
240
280
VOUT = 5 V, IOUT = 45 mA to 105 mA, slew rate = 0.1 A/µs,
COUT = 10 µF
Figure 6-17. Load Transient, 45 mA to 105 mA
8
-100
-100
-200
20
40
60
80
100 120
Time (Ps)
140
160
180
-300
200
Figure 6-16. Load Transient, No Load to 100-mA Rising Edge
40
120
0
0
-50
50
20
80
0
240
180
40
100
300
30
0
50
VOUT = 5 V, IOUT = 0 mA to 100 mA, slew rate = 1 A/µs,
COUT = 10 µF
200
-40qC
AC Coupled Output Voltage (mV)
25qC
IOUT
200
0
Output Current (mA)
AC Coupled Output Voltage (mV)
-40qC
150qC
-150
Figure 6-15. Load Transient, No Load to 100 mA
50
25qC
100
5
VOUT = 5 V, IOUT = 0 mA to 100 mA, slew rate = 1 A/µs,
COUT = 10 µF
40
450
300
-40qC
50
1
400
150
Output Current (mA)
AC Coupled Output Voltage (mV)
150
0.5
350
Figure 6-14. Line Transients
Figure 6-13. Line Transients
0
200 250 300
Time (Ps)
VOUT = 5 V, IOUT = 100 mA, VIN = 5.5 V to 6.5 V,
rise time = 1 µs
VOUT = 5 V, IOUT = 1 mA, VIN = 13.5 V to 45 V,
slew rate = 2.7 V/µs
100
150
Output Current (mA)
500
8
25qC
150qC
IOUT
150
30
100
20
50
10
0
0
-50
-10
-100
-20
-150
-30
-200
-40
0
20
40
60
80
100 120
Time (Ps)
140
160
180
Output Current (mA)
0
10
Input Voltage (V)
40
Output Voltage (V)
Input Voltage (V)
45
AC Coupled Output Voltage (mV)
specified at TJ = –40°C to +150°C, VIN = 13.5 V, IOUT = 100 µA, COUT = 2.2 µF, 1 mΩ < COUT ESR < 2 Ω, CIN = 1 µF (unless
otherwise noted)
-250
200
VOUT = 5 V, IOUT = 45 mA to 105 mA, slew rate = 0.1 A/µs,
COUT = 10 µF
Figure 6-18. Load Transient, 45-mA to 105-mA Rising Edge
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6.6 Typical Characteristics (continued)
specified at TJ = –40°C to +150°C, VIN = 13.5 V, IOUT = 100 µA, COUT = 2.2 µF, 1 mΩ < COUT ESR < 2 Ω, CIN = 1 µF (unless
otherwise noted)
200
100
0
0
-50
-100
-100
-200
-150
-300
0.25
0.5
0.75
1
1.25
Time (ms)
1.5
1.75
0
-100
-100
-200
250
100
400
300
200
100
0
25
50
75
100 125 150
Time (Ps)
175
200
AC Coupled Output Voltage (mV)
300
-40qC
25qC
150qC 500
IOUT
-100
140
160
180
-300
200
600
150
500
400
300
100
200
50
100
0
0
-50
-100
-100
-200
-150
-300
-200
-400
-250
-500
-600
0.5
1
1.5
2
2.5
3
Time (ms)
3.5
4
4.5
5
Figure 6-22. Load Transient, No Load to 500 mA
660
100
750
659
50
600
658
0
450
-50
300
-100
150
-150
0
-200
-150
IOUT
657
IOUT (mA)
Output Current (mA)
150qC
100 120
Time (Ps)
200
900
25qC
80
VOUT = 5 V, IOUT = 0 mA to 500 mA, slew rate = 1 A/µs,
COUT = 10 µF
Figure 6-21. Load Transient, 150-mA to 350-mA
-40qC
60
-40qC
25qC
150qC
IOUT
0
VOUT = 5 V, IOUT = 150 mA to 350 mA, slew rate = 0.1 A/µs,
COUT = 10 µF
150
40
-300
0
250
225
20
Figure 6-20. Load Transient, No Load to 150-mA Rising Edge
600
-150
0
-50
150
Output Current (mA)
AC Coupled Output Voltage (mV)
100
VOUT = 5 V, IOUT = 0 mA to 150 mA, slew rate = 1 A/µs,
COUT = 10 µF
Figure 6-19. Load Transient, No Load to 150-mA
AC Coupled Output Voltage (mV)
50
-150
VOUT = 5 V, IOUT = 0 mA to 150 mA, slew rate = 1 A/µs,
COUT = 10 µF
-50
IOUT
200
0
0
150qC
100
2
50
25qC
Output Current (mA)
50
0
300
-40qC
AC Coupled Output Voltage (mV)
100
150
Output Current (mA)
300
-40qC
25qC
150qC
IOUT
Output Current (mA)
AC Coupled Output Voltage (mV)
150
656
655
654
653
652
-250
0
20
40
60
80
100 120
Time (Ps)
140
160
180
-300
200
VOUT = 5 V, IOUT = 0 mA to 500 mA, slew rate = 1 A/µs,
COUT = 10 µF
651
Current Limit
650
-75
-45
-15
15
45
75
Temperature (qC)
105
135
VIN = VOUT + 1 V, VOUT = 90% × VOUT(NOM)
Figure 6-23. Load Transient, No Load to 500-mA Rising Edge
Figure 6-24. Output Current Limit vs Temperature
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6.6 Typical Characteristics (continued)
specified at TJ = –40°C to +150°C, VIN = 13.5 V, IOUT = 100 µA, COUT = 2.2 µF, 1 mΩ < COUT ESR < 2 Ω, CIN = 1 µF (unless
otherwise noted)
175
40
-55qC
-40qC
35
0qC
25qC
85qC
125qC
150qC
125
Iq (PA)
30
Iq (PA)
-55qC
-40qC
0qC
25qC
85qC
150
25
125qC
150qC
100
75
20
50
15
25
10
0
5
10
15
20
25
Input Voltage (V)
30
35
40
0
5
10
15
20
25
Input Voltage (V)
30
35
40
VOUT = 5 V
Figure 6-26. Quiescent Current (IQ) vs VIN
281
1300
1200
1100
1000
900
800
700
600
500
400
300
200
100
0
-55 qC
-40 qC
0 qC
25 qC
85 qC
125 qC
150 qC
280
279
Ground Current (PA)
278
277
276
275
274
273
272
0
50
100
150
200 250 300 350
Output Current (mA)
400
450
271
-75
500
Figure 6-27. Ground Current (IGND) vs IOUT
-25
25
50
75
Temperature (qC)
100
20
125
15
Voltage (V)
25
24
800
700
12.5
600
10
500
7.5
400
5
300
23
2.5
200
0
100
22
-2.5
0
-5
0
21
-75
-50
-25
0
25
50
75
Ambient Temperature (qC)
100
Figure 6-29. Ground Current at 500 µA
150
900
Input Voltage
Output Voltage
Output Current
17.5
10
0
Figure 6-28. Ground Current at 100 mA
26
Ground Current (PA)
-50
125
150
Output Current (mA)
Ground Current (PA)
Figure 6-25. Quiescent Current (IQ) vs VIN
250
500
-100
750 1000 1250 1500 1750 2000 2250 2500
Time (Ps)
VIN = 13.5 V, VOUT = 5 V, IOUT = 150 mA, COUT = 10 µF
Figure 6-30. Startup Plot Inrush Current
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6.6 Typical Characteristics (continued)
specified at TJ = –40°C to +150°C, VIN = 13.5 V, IOUT = 100 µA, COUT = 2.2 µF, 1 mΩ < COUT ESR < 2 Ω, CIN = 1 µF (unless
otherwise noted)
2.8
20
Falling Threshold
Rising Threshold
18
2.7
16
Output voltage (V)
UVLO Threshold (V)
2.75
2.65
2.6
2.55
2.5
12
10
8
2.45
2.4
-60
14
6
-40
-20
0
20 40 60 80
Temperature (qC)
4
0.2
100 120 140 160
Figure 6-31. Undervoltage Lockout (UVLO) Threshold vs
Temperature
0.4
ESR (:)
0
25
50
75 100 125
Temperature (qC)
150
Figure 6-33. Thermal Shutdown
175
200
1.6
1.8
x
0.2
0.1
0.05
x
Stable region
0.02
0.01
0.005
0.002
0.001
0.0005
-25
1.4
xx
xxx
xxxx
xxx
xxxx
xx
xxx
xxxx
xxx
xxxx
xxx
xx
xxx
xxxx
xxx
xxxx
xxx
xx
xxx
xxxx
xxx
xxxx
xxx
xx
2
1
0.5
OFF
-50
0.8
1
1.2
Injected current (mA)
Figure 6-32. Output Voltage vs Injected Current
10
5
ON
0.6
x
0.0002
0.0001
1
2
3 4 5 6 78 10
20 30 50 70 100
COUT (PF)
200 300 500
Figure 6-34. Stability, ESR vs COUT
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7 Detailed Description
7.1 Overview
The TPS7B88-Q1 is a low-dropout linear regulator (LDO) with improved transient performance that allows for
quick response to changes in line or load conditions. The device aslo features a novel output overshoot
reduction feature that minimizes output overshoot during cold-crank conditions.
During normal operation, the device has a tight DC accuracy of ±1.15% over line, load, and temperature. The
increased accuracy allows for the powering of sensitive analog loads or sensors.
7.2 Functional Block Diagram
IN
OUT
Current
Limit
R1
±
+
Thermal
Shutdown
UVLO
R2
Bandgap
GND
7.3 Feature Description
7.3.1 Undervoltage Lockout
The device has an independent undervoltage lockout (UVLO) circuit that monitors the input voltage, allowing a
controlled and consistent turn on and off of the output voltage. To prevent the device from turning off if the input
drops during turn on, the UVLO has hysteresis as specified in the Electrical Characteristics table.
7.3.2 Thermal Shutdown
The device contains a thermal shutdown protection circuit to disable the device when the junction temperature
(TJ) of the pass transistor rises to TSD(shutdown) (typical). Thermal shutdown hysteresis assures that the device
resets (turns on) when the temperature falls to TSD(reset) (typical).
The thermal time-constant of the semiconductor die is fairly short, thus the device may cycle on and off when
thermal shutdown is reached until power dissipation is reduced. Power dissipation during startup can be high
from large VIN – VOUT voltage drops across the device or from high inrush currents charging large output
capacitors. Under some conditions, the thermal shutdown protection disables the device before startup
completes.
For reliable operation, limit the junction temperature to the maximum listed in the Recommended Operating
Conditions table. Operation above this maximum temperature causes the device to exceed its operational
specifications. Although the internal protection circuitry of the device is designed to protect against thermal
overall conditions, this circuitry is not intended to replace proper heat sinking. Continuously running the device
into thermal shutdown or above the maximum recommended junction temperature reduces long-term reliability.
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7.3.3 Current Limit
The device has an internal current limit circuit that protects the regulator during transient high-load current faults
or shorting events. The current limit is a brickwall scheme. In a high-load current fault, the brickwall scheme
limits the output current to the current limit (ICL). ICL is listed in the Electrical Characteristics table.
The output voltage is not regulated when the device is in current limit. When a current limit event occurs, the
device begins to heat up because of the increase in power dissipation. When the device is in brickwall current
limit, the pass transistor dissipates power [(VIN – VOUT) × ICL]. If thermal shutdown is triggered, the device turns
off. After the device cools down, the internal thermal shutdown circuit turns the device back on. If the output
current fault condition continues, the device cycles between current limit and thermal shutdown. For more
information on current limits, see the Know Your Limits application report.
Figure 7-1 shows a diagram of the current limit.
VOUT
Brickwall
VOUT(NOM)
IOUT
0V
0 mA
IRATED
ICL
Figure 7-1. Current Limit
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7.4 Device Functional Modes
7.4.1 Device Functional Mode Comparison
The Device Functional Mode Comparison table shows the conditions that lead to the different modes of
operation. See the Electrical Characteristics table for parameter values.
Table 7-1. Device Functional Mode Comparison
OPERATING MODE
PARAMETER
VIN
IOUT
TJ
Normal operation
VIN > VOUT(nom) + VDO and VIN > VIN(min)
IOUT < IOUT(max)
TJ < TSD(shutdown)
Dropout operation
VIN(min) < VIN < VOUT(nom) + VDO
IOUT < IOUT(max)
TJ < TSD(shutdown)
VIN < VUVLO
Not applicable
TJ > TSD(shutdown)
Disabled
(any true condition
disables the device)
7.4.2 Normal Operation
The device regulates to the nominal output voltage when the following conditions are met:
•
•
•
The input voltage is greater than the nominal output voltage plus the dropout voltage (VOUT(nom) + VDO)
The output current is less than the current limit (IOUT < ICL)
The device junction temperature is less than the thermal shutdown temperature (TJ < TSD)
7.4.3 Dropout Operation
If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other
conditions are met for normal operation, the device operates in dropout mode. In this mode, the output voltage
tracks the input voltage. During this mode, the transient performance of the device becomes significantly
degraded because the pass transistor is in the ohmic or triode region, and acts as a switch. Line or load
transients in dropout can result in large output-voltage deviations.
When the device is in a steady dropout state (defined as when the device is in dropout, VIN < VOUT(NOM) + VDO,
directly after being in a normal regulation state, but not during startup), the pass transistor is driven into the
ohmic or triode region. When the input voltage returns to a value greater than or equal to the nominal output
voltage plus the dropout voltage (VOUT(NOM) + VDO), the output voltage can overshoot for a short period of time
while the device pulls the pass transistor back into the linear region.
7.4.4 Disabled
The output of the device can be shutdown by forcing the input voltage below the UVLO falling threshold (see the
Electrical Characteristics table). When disabled, the pass transistor is turned off and internal circuits are
shutdown.
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
8.1.1 Input and Output Capacitor Selection
The TPS7B88-Q1 requires an output capacitor of 2.2 µF or larger (1 µF or larger capacitance) for stability and an
equivalent series resistance (ESR) between 0.001 Ω and 2 Ω. For best transient performance, use X5R- and
X7R-type ceramic capacitors because these capacitors have minimal variation in value and ESR over
temperature. When choosing a capacitor for a specific application, be mindful of the DC bias characteristics for
the capacitor. Higher output voltages cause a significant derating of the capacitor. For best performance, the
maximum recommended output capacitance is 220 µF.
Although an input capacitor is not required for stability, good analog design practice is to connect a capacitor
from IN to GND. Some input supplies have a high impedance, thus placing the input capacitor on the input
supply helps reduce the input impedance. This capacitor counteracts reactive input sources and improves
transient response, input ripple, and PSRR. If the input supply has a high impedance over a large range of
frequencies, several input capacitors can be used in parallel to lower the impedance over frequency. Use a
higher-value capacitor if large, fast, rise-time load transients are anticipated, or if the device is located several
inches from the input power source.
8.1.2 Dropout Voltage
Dropout voltage (VDO) is defined as the input voltage minus the output voltage (VIN – VOUT) at the rated output
current (IRATED), where the pass transistor is fully on. IRATED is the maximum IOUT listed in the Recommended
Operating Conditions table. The pass transistor is in the ohmic or triode region of operation, and acts as a
switch. The dropout voltage indirectly specifies a minimum input voltage greater than the nominal programmed
output voltage at which the output voltage is expected to stay in regulation. If the input voltage falls to less than
the nominal output regulation, then the output voltage falls as well.
For a CMOS regulator, the dropout voltage is determined by the drain-source on-state resistance (RDS(ON)) of the
pass transistor. Therefore, if the linear regulator operates at less than the rated current, the dropout voltage for
that current scales accordingly. The following equation calculates the RDS(ON) of the device.
RDS(ON) =
VDO
IRATED
(1)
8.1.3 Reverse Current
Excessive reverse current can damage this device. Reverse current flows through the intrinsic body diode of the
pass transistor instead of the normal conducting channel. At high magnitudes, this current flow degrades the
long-term reliability of the device.
Conditions where reverse current can occur are outlined in this section, all of which can exceed the absolute
maximum rating of VOUT ≤ VIN + 0.3 V.
•
•
•
If the device has a large COUT and the input supply collapses with little or no load current
The output is biased when the input supply is not established
The output is biased above the input supply
If reverse current flow is expected in the application, external protection is recommended to protect the device.
Reverse current is not limited in the device, so external limiting is required if extended reverse voltage operation
is anticipated.
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8.1.4 Power Dissipation (PD)
Circuit reliability requires consideration of the device power dissipation, location of the circuit on the printed
circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator must have few
or no other heat-generating devices that cause added thermal stress.
To first-order approximation, power dissipation in the regulator depends on the input-to-output voltage difference
and load conditions. The following equation calculates power dissipation (PD).
PD = (VIN – VOUT) × IOUT
(2)
Note
Power dissipation can be minimized, and therefore greater efficiency can be achieved, by correct
selection of the system voltage rails. For the lowest power dissipation use the minimum input voltage
required for correct output regulation.
For devices with a thermal pad, the primary heat conduction path for the device package is through the thermal
pad to the PCB. Solder the thermal pad to a copper pad area under the device. This pad area must contain an
array of plated vias that conduct heat to additional copper planes for increased heat dissipation.
The maximum power dissipation determines the maximum allowable ambient temperature (TA) for the device.
According to the following equation, power dissipation and junction temperature are most often related by the
junction-to-ambient thermal resistance (RθJA) of the combined PCB and device package and the temperature of
the ambient air (TA).
TJ = TA + (RθJA × PD)
(3)
Thermal resistance (RθJA) is highly dependent on the heat-spreading capability built into the particular PCB
design, and therefore varies according to the total copper area, copper weight, and location of the planes. The
junction-to-ambient thermal resistance listed in the Thermal Information table is determined by the JEDEC
standard PCB and copper-spreading area, and is used as a relative measure of package thermal performance.
8.1.4.1 Power Dissipation Versus Ambient Temperature
Figure 8-1 is based off of a JESD51-7 4-layer, high-K board. The allowable power dissipation was estimated
using the following equation. As disscussed in the An empirical analysis of the impact of board layout on LDO
thermal performance application report, thermal dissipation can be improved in the JEDEC high-K layout by
adding top layer copper and increasing the number of thermal vias. If a good thermal layout is used, the
allowable thermal dissipation can be improved by up to 50%.
6# + 4à,# T 2& Q 150 °%
(4)
6.5
KVU Package
Maximum Power Dissipation (W)
6
5.5
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
-40
-20
0
20
40
60
80
Ambient Temerature (qC)
100
120
140
Figure 8-1. TPS7B88-Q1 Allowable Power Dissipation
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8.1.5 Estimating Junction Temperature
The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures
of the linear regulator when in-circuit on a typical PCB board application. These metrics are not thermal
resistance parameters and instead offer a practical and relative way to estimate junction temperature. These psi
metrics are determined to be significantly independent of the copper area available for heat-spreading. The
Thermal Information table lists the primary thermal metrics, which are the junction-to-top characterization
parameter (ψJT) and junction-to-board characterization parameter (ψJB). These parameters provide two methods
for calculating the junction temperature (TJ), as described in the following equations. Use the junction-to-top
characterization parameter (ψJT) with the temperature at the center-top of device package (TT) to calculate the
junction temperature. Use the junction-to-board characterization parameter (ψJB) with the PCB surface
temperature 1 mm from the device package (TB) to calculate the junction temperature.
TJ = TT + ψJT × PD
(5)
where:
•
•
PD is the dissipated power
TT is the temperature at the center-top of the device package
TJ = TB + ψJB × PD
(6)
where
•
TB is the PCB surface temperature measured 1 mm from the device package and centered on the package
edge
For detailed information on the thermal metrics and how to use them, see the Semiconductor and IC Package
Thermal Metrics application report.
8.2 Typical Application
Figure 8-2 shows a typical application circuit for the TPS7B88-Q1. TI recommends a low-ESR ceramic capacitor
with a dielectric of type X5R or X7R.
IN
OUT
TPS7B88-Q1
GND
Figure 8-2. Typical Application Schematic for the TPS7B88-Q1
8.2.1 Design Requirements
For this design example, use the parameters listed in Table 8-1 as the input parameters.
Table 8-1. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage range
6 V to 40 V
Output voltage
5V
Output current
350 mA
Output capacitor
10 µF
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8.2.2 Detailed Design Procedure
8.2.2.1 Input Capacitor
The device requires an input decoupling capacitor, the value of which depends on the application. The typical
recommended value for the decoupling capacitor is 1 µF. The voltage rating must be greater than the maximum
input voltage.
8.2.2.2 Output Capacitor
The device requires an output capacitor to stabilize the output voltage. The capacitor value must be between
2.2 µF and 200 µF and the ESR range must be between 1 mΩ and 2 Ω. For this design, a low ESR, 10-µF
ceramic capacitor was used to improve transient performance.
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8.2.3 Application Curves
Input Voltage
Output Voltage
Output Current
90
800
80
700
12.5
600
10
500
7.5
400
5
300
2.5
200
0
100
-2.5
0
-5
0
250
500
-100
750 1000 1250 1500 1750 2000 2250 2500
Time (Ps)
Output Current (mA)
Voltage (V)
15
900
Power Supply Rejection Ratio (dB)
20
17.5
70
60
50
40
30
20
10
1 mA
10 mA
0
10
Figure 8-3. Power-Up Waveform
50 mA
150 mA
100
1k
350 mA
500 mA
10k
100k
Frequency (Hz)
1M
10M
AC Coupled Output Voltage (mV)
150
600
-40qC
25qC
150qC 500
IOUT
100
50
400
0
300
-50
200
-100
100
-150
0
25
50
75
100 125 150
Time (Ps)
175
200
225
Output Current (mA)
Figure 8-4. PSRR
0
250
Figure 8-5. Transient Response
9 Power Supply Recommendations
This device is designed for operation from an input voltage supply with a range between 3 V and 40 V. This input
supply must be well regulated. If the input supply is located more than a few inches from the TPS7B88-Q1, add
an electrolytic capacitor with a value of 22 µF and a ceramic bypass capacitor at the input.
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10 Layout
10.1 Layout Guidelines
For best overall performance, place all circuit components on the same side of the circuit board and as near as
practical to the respective LDO pin connections. Place ground return connections to the input and output
capacitor, and to the LDO ground pin as close as possible to each other, connected by a wide, component-side,
copper surface. The use of vias and long traces to the input and output capacitors is strongly discouraged and
negatively affects system performance. TI also recommends a ground reference plane either embedded in the
PCB itself or located on the bottom side of the PCB opposite the components. This reference plane serves to
assure accuracy of the output voltage, shield noise, and behaves similarly to a thermal plane to spread (or sink)
heat from the LDO device when connected to the thermal pad. In most applications, this ground plane is
necessary to meet thermal requirements.
10.1.1 Package Mounting
Solder pad footprint recommendations for the TPS7B88-Q1 are available at the end of this document and at
www.ti.com.
10.1.2 Board Layout Recommendations to Improve PSRR and Noise Performance
As depicted in Figure 10-1 , place the input and output capacitors close to the device for the layout of the
TPS7B88-Q1. In order to enhance the thermal performance, place as many vias as possible around the device.
These vias improve the heat transfer between the different GND planes in the PCB.
To improve AC performance such as PSRR, output noise, and transient response, TI recommends a board
design with separate ground planes for VIN and VOUT, with each ground plane connected only at the GND pin of
the device. In addition, the ground connection for the output capacitor must connect directly to the GND pin of
the device.
Minimize equivalent series inductance (ESL) and ESR in order to maximize performance and ensure stability.
Place each capacitor as close as possible to the device and on the same side of the PCB as the regulator itself.
Do not place any of the capacitors on the opposite side of the PCB from where the regulator is installed. TI
strongly discourages the use of vias and long traces to connect the capacitors because may negatively affect
system performance and even cause instability.
If possible, and to ensure the maximum performance specified in this document, use the same layout pattern
used for the TPS7B88-Q1 evaluation board, available at www.ti.com.
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10.2 Layout Example
GND
VOUT
CIN
VIN
COUT
Denotes a via
Figure 10-1. KVU Package Fixed Output
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Device Nomenclature
Table 11-1. Device Nomenclature (1)
PRODUCT
VOUT
TPS7B88xxQKVURQ1
(1)
xx is the nominal output voltage (for example, 33 = 3.3 V V; 50 = 5.0 V).
Q indicates that this device is a grade-1 device in accordance with the AEC-Q100 standard.
Q1 indicates that this device is an automotive grade (AEC-Q100) device.
For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the
device product folder on www.ti.com.
11.1.2 Development Support
For the PSpice model, see the TPS7B4250 PSpice Transient Model.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
• Texas Instruments, Various Applications for Voltage-Tracking LDO application report
• Texas Instruments, TPS7B4250 Evaluation Module user's guide
• Texas Instruments, TPS7B5250-Q1 Pin FMEA application report
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Product Folder Links: TPS7B88-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
19-Sep-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS7B8833QKVURQ1
ACTIVE
TO-252
KVU
3
2500
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 125
7B8833
TPS7B8833QKVURQ1R2
ACTIVE
TO-252
KVU
3
2500
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 150
7B8833
TPS7B8850QKVURQ1
ACTIVE
TO-252
KVU
3
2500
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 125
7B8850
TPS7B8850QKVURQ1R2
ACTIVE
TO-252
KVU
3
2500
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 150
7B8850
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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