www.ti.com
Table of Contents
User’s Guide
TPS7H3302EVM (LP085)
ABSTRACT
This user’s guide describes operational use of the TPS7H3302EVM evaluation module (EVM) as a reference
design for engineering demonstration and evaluation of the TPS7H3302-SEP, a 3-A sink and source DDR
termination LDO regulator. This user's guide provides details about the EVM, the configuration, schematics, and
bill of materials (BOM).
Table of Contents
1 Introduction.............................................................................................................................................................................2
2 Description.............................................................................................................................................................................. 3
2.1 Related Information............................................................................................................................................................3
2.2 Typical Applications............................................................................................................................................................3
2.3 Features............................................................................................................................................................................. 3
2.4 Performance Specification Summary.................................................................................................................................4
3 Test Setup................................................................................................................................................................................4
3.1 Equipment.......................................................................................................................................................................... 4
3.2 EVM Connectors and Test Points...................................................................................................................................... 5
3.3 Testing Procedure.............................................................................................................................................................. 6
4 Board Layout.........................................................................................................................................................................12
5 Schematic..............................................................................................................................................................................16
6 Bill of Materials..................................................................................................................................................................... 17
7 Related Documentation........................................................................................................................................................18
8 Revision History................................................................................................................................................................... 18
List of Figures
Figure 1-1. TPS7H3302EVM Board (Top View)...........................................................................................................................2
Figure 3-1. DDR3 Bode Plot Iload = 500 mA...............................................................................................................................7
Figure 3-2. DDR3 Bode Plot Iload = 1 A......................................................................................................................................8
Figure 3-3. DDR3 Bode Plot Iload = 3 A......................................................................................................................................8
Figure 3-4. DDR3 Scope Plot Response With Both Sinking and Sourcing Enabled and VDDQSNS Isolated..........................10
Figure 3-5. DDR3 Scope Plot of Response with 1.875 A Sinking Only with Isolated VDDQSNS............................................. 10
Figure 3-6. DDR3 Scope Plot of Response with 1.875 A Sourcing Only with Isolated VDDQSNS........................................... 11
Figure 3-7. DDR3 Scope Plot of Response With 1.875 A Sinking and Sourcing With Non-Isolated VDDQSNS...................... 11
Figure 4-1. Top Overlay............................................................................................................................................................. 12
Figure 4-2. Top Solder............................................................................................................................................................... 12
Figure 4-3. Top Layer.................................................................................................................................................................13
Figure 4-4. Signal and Power Layer 1....................................................................................................................................... 13
Figure 4-5. Signal and Power Layer 2....................................................................................................................................... 14
Figure 4-6. Bottom Layer........................................................................................................................................................... 14
Figure 4-7. Bottom Solder..........................................................................................................................................................15
Figure 5-1. LP085B Schematic..................................................................................................................................................16
List of Tables
Table 2-1. Performance Specification Summary..........................................................................................................................4
Table 3-1. Connectors and Test Points........................................................................................................................................ 5
Table 3-2. I/O Voltage Measurement Test Points.........................................................................................................................6
Table 6-1. Bill of Materials..........................................................................................................................................................17
Trademarks
All trademarks are the property of their respective owners.
SLVUCK2A – JANUARY 2023 – REVISED APRIL 2023
Submit Document Feedback
TPS7H3302EVM (LP085)
Copyright © 2023 Texas Instruments Incorporated
1
Introduction
www.ti.com
1 Introduction
The TPS7H3302EVM-SEP (LP085) evaluation board is designed to evaluate the performance and
characteristics of TI's radiation tolerant DDR/DDR2/DDR3/DDR3L/DDR4 termination regulator, the TPS7H3302SEP.
Figure 1-1. TPS7H3302EVM Board (Top View)
2
TPS7H3302EVM (LP085)
SLVUCK2A – JANUARY 2023 – REVISED APRIL 2023
Submit Document Feedback
Copyright © 2023 Texas Instruments Incorporated
www.ti.com
Description
2 Description
The TPS7H3302-SEP is a radiation-tolerant double data rate (DDR) ±3 A termination regulator with built-in
VTTREF buffer. The regulator is specifically designed to provide a complete, compact, low-noise device for
space DDR termination applications such as single board computers, solid state recorders, and payload
processing.
The TPS7H3302-SEP supports DDR VTT termination applications using DDR, DDR2, DDR3, and DDR4. The
fast transient response of the TPS7H3302-SEP VTT regulator allows for a very stable supply during read and
write conditions. During transients, the fast tracking feature of the VTTREF supply minimizes any voltage offset
between VTT and VTTREF. To enable simple power sequencing, both an enable input and a power-good output
(PGOOD) have been integrated into the TPS7H3302-SEP. The open-drain output of the PGOOD terminal is
compatible with being tied to other open-drain outputs, which facilitates the monitoring of a group supplies; such
that a solitary GPIO pin can detect when all supplies are in regulation. The enable signal also discharges VTT
during suspend to RAM (S3) power down mode.
2.1 Related Information
•
TPS7H3302-SEP data sheet (SLVSGX6)
2.2 Typical Applications
The EVM is used in the following applications:
•
•
Radiation-tolerant DDR power applications
Memory termination regulator for DDR, DDR2, DDR3, and DDR4
2.3 Features
This EVM has the following features:
•
•
•
•
•
•
Input core voltage VDD supports 2.5-V rail and 3.3-V rail
VLDOIN, VDDQ voltage range: 0.9 V–3.5 V
Dynamic performance evaluation features:
– Sink and source integrated load switches for transient load step emulation
– Configurable load step and slew rate control by on-board resistors
CAUTION
The default EVM configuration using the built-in transient test circuit supports testing the
DDR4 at ±1.5 A, DDR3 at ±1.875 A, DDR2 at ±2.25 A. To evaluate the DDR node, or different
currents for DDR2, DDR3, DDR3L, and DDR4 the total resistance of resistors R6-R9, and
R17-R20 needs to be changed to not exceed device maximum ratings.
Jumper J14 (pins 1 and 2) for device enable. (enabled without J14 installed)
Convenient test points for probing PGOOD, CLK_IN, and loop response testing
Optional placeholders for VDDQSNS to VLDOIN filter when not using independent VDDQSNS source
SLVUCK2A – JANUARY 2023 – REVISED APRIL 2023
Submit Document Feedback
TPS7H3302EVM (LP085)
Copyright © 2023 Texas Instruments Incorporated
3
Description
www.ti.com
2.4 Performance Specification Summary
Table 2-1 lists the EVM performance specifications. See data sheet (SLVSGX6) for complete specifications.
Table 2-1. Performance Specification Summary
Specification
Test Conditions
Input voltage range, (VVIN)
MIN
TYP
2.375
VDDQSNS voltage range (VVDDQSNS)
VLDOIN voltage range (VVLDOIN)
MAX
3.3
Unit
3.5
1
3.5
0.9
3.5
V
VTT Termination Voltage
DDR
DDR2
DDR3
DDR4
VTT
1.25
VTTREF
1.25
VTT
0.9
VTTREF
0.9
VTT
0.75
VTTREF
0.75
VTT
0.6
VTTREF
0.6
Termination current (IVTT)
Reference current (IVTTREF)
–3
3
A
–10
10
mA
3 Test Setup
3.1 Equipment
3.1.1 Power Supplies
Power supply #1 (PS#1): a power supply capable of supplying up to 3.5 V at > 3 A is required for VLODIN.
Power supply #2 (PS#2): a power supply capable of supplying up to 2.5 V at 100 mA is required for VDDQSNS.
Only required if not using VLDOIN for VDDQSNS.
Power supply #3 (PS#3): a power supply capable of supplying up to 3.5 V at 100 mA is required for VIN.
Power supply #4 (PS#4): a power supply capable of supplying up to 5 V at 100 mA is required to power transient
circuit.
Power supply #5 (PS#5): a power supply capable of supplying up to 3.5 V at > 3 A is required for V2 source for
transient circuit.
3.1.2 Load #1
Electronic load capable of testing desired DC sink or source load current (up to 3 A).
4
TPS7H3302EVM (LP085)
SLVUCK2A – JANUARY 2023 – REVISED APRIL 2023
Submit Document Feedback
Copyright © 2023 Texas Instruments Incorporated
www.ti.com
Test Setup
3.2 EVM Connectors and Test Points
Section 3.2 lists the EVM connectors and test points.
Table 3-1. Connectors and Test Points
Reference
Designator
Function
J1
Ground (GND)
J2
Input voltage VDD. VIN range is from 2.375 V to 3.5 V
J3
Ground (GND) for VDD
J4
VDDQSNS voltage range 1.2 V – 2.5 V.
J5
Jumper to connect VDDQSNS to VLDOIN
J6
Jumper to disable device. No jumper = enabled.
J7
VLDOIN
J8
SMA VTTREF
J9
Ground (GND)
J10
SMA VTT
J11
VTT
J12
Ground (GND) for VTT
J13
Transient circuit 5 V 2-pin input header
J14
Source load selector: Jumper (pins 1 and 2) part of transient circuit
J15
Sink load selector Jumper (pins 1 and 2) part of transient circuit
J16
V2 voltage for DDR sink – transient test
J17
Ground (GND) for V2
TP1
Test point for the input voltage node. VDD
TP2
Ground (GND)
TP3
Test point for EN signal
TP4
Test point for Bode signal injection
TP5
Test point for Bode signal injection
TP6
Test point for output voltage node VTT
TP7
Test point for input voltage node VLDOIN
TP8
Test point for input voltage node VLDOIN
TP9
Test point for output voltage VTTREF
TP10
Test point for PGOOD signal
TP11
Test point Ground (GND)
TP12
Test point Ground (GND)
TP13
Test point Ground (GND)
TP14
Test point Ground (GND)
TP15
Test point or voltage input for 5 V transient circuit
TP16
Test point Ground (GND)
TP17
Test point Ground (GND)
TP18
Test point Clock
TP19
Test point for voltage source V2
SLVUCK2A – JANUARY 2023 – REVISED APRIL 2023
Submit Document Feedback
TPS7H3302EVM (LP085)
Copyright © 2023 Texas Instruments Incorporated
5
Test Setup
www.ti.com
3.3 Testing Procedure
Use these steps for testing the EVM with a static DC external load:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
Verify all supplies are off prior to connecting the EVM.
Verify proper polarity of power supply and load connections.
Remove jumper on J6 to set device to enable.
Place a jumper on J5 (pins 1 and 2), connecting VDDQSNS to VLDOIN.
a. Alternatively a separate voltage source can be used for VLDOIN and a separate voltage source of
VDDQSNS, thus isolating the two. This method isolates the transients introduced on VLDOIN from
impacting VDDQSNS. Additionally, this method allows for reduced internal power dissipation. VLDOIN
can be reduced to VTT + VDO.
Set the load to sink desired current up to 3 A.
Connect a power supply VDD using J2/J1, or test points TP1 and TP2. Vin current is less than 100 mA.
Connect power supply to J7/J9 - VLDOIN. VLDOIN current can be up to 3 A and possibly higher during
startup.
Connect VTT voltmeter (+) terminal to TP6 and (–) terminal to TP13, or J10.
Connect the load (+) to J11 and (–) to J12. If desired, connect a current meter in series to test VTT sourcing
current. Alternatively, connect isolated load (+) from J7 VLDOIN and (-) to J11 to test VTT sinking.
Set the power supply for VLDOIN to 1.5 V.
Set the power supply for VIN to 3 V.
Enable both VIN and VLDOIN supplies.
Connect a scope or voltmeter monitoring VTTREF to TP9 and GND TP, or using SMA J8.
The voltmeter monitoring VTTREF reads approximately 0.75 V
The voltmeter monitoring VTT reads approximately 0.75 V
Enable the VTT load to observed Sink or Source effect on VTT.
Place jumper on J6 to disable the device.
The voltmeter monitoring VTT reads near zero volts, as VTT is discharged when disabled.
The voltmeter monitoring VTTREF still reads approximately 0.75 V as VTTREF is still active when disabled.
Disable supplies to complete the DC static loading test.
Table 3-2 displays the input voltage and output voltage measurement test points. Using the following connection
points, monitor VTT and VTTREF regulation overline and overload.
Table 3-2. I/O Voltage Measurement Test Points
6
EVM
Input / Output Voltage
TPS7H3302EVM-SEP
VIN
2.375 V ≤ VIN ≤ 3.5 V
Test point
TP15 (+) TP16(–)
VLDOIN
0.9 V ≤ VLDOIN ≤ 3.5 V
TP7(+) TP11(–)
VDDQSNS
1.2 V ≤ VDDQSNS ≤ 3.5 V
J4 or (Pin2 J5)(+) TP12(–)
VTT
½ VDDQSNS
TP6(+) TP13(–)
VTTREF
½ VDDQSNS
TP9(+) TP11(–)
TPS7H3302EVM (LP085)
SLVUCK2A – JANUARY 2023 – REVISED APRIL 2023
Submit Document Feedback
Copyright © 2023 Texas Instruments Incorporated
www.ti.com
Test Setup
3.3.1 EVM Bode Plot Measurement Setup
The setup for EVM bode plot measurement is as follows:
1. Use a Bode 100 loop analyzer or equivalent equipment.
2. Remove jumper on J5 to isolate VDDQSNS from VLDOIN. To test with VLDOIN tied to single VDDQ along
with VDDQSNS, use the optional filter. See note below.
3. Connect the oscillator output across R3 = 51 Ω resistor. Connect the output of oscillator to TP4 (VTTSNS).
4. Connect Channel 2 of the analyzer at TP5 and connect ground to TP2
5. Connect Channel 1 of the analyzer at TP4 and connect ground to TP2.
6. Power EVM with desired conditions for VLDOIN, VIN, VDDQSNS, and VTT load.
7. With the EVM loaded to the required load, run bode plot over desired frequency range.
To verify stability across loads and rated operating temperature, implement a quantity of four 4.7 uF ceramic
output capacitors in the application circuit.
All of the bode measurements presented, VDDQSNS is provided from an independent supply from
VLDOIN. If VDDQSNS and VLDOIN inputs are connected to same supply, then use the isolation
filter on the EVM to isolate the load effects on VLDOIN from VDDQSNS. The filter can be used by
replacing components for R4, and C3.
Figure 3-1 through Figure 3-3 show bode plots for this EVM. All plots generated using default CIN and COUT
capacitances populated on EVM. CIN = 150 µF tantalum // 5-10 µF ceramic, COUT = 3-150 µF tantalum // 4-4.7
µF ceramic.
Bode Plot for DDR3 VDDQSNS = 1.5V
100
90
80
70
60
50
40
30
20
10
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
100
200
180
160
140
120
100
80
60
40
20
0
-20
-40
-60
-80
-100
-120
-140
-160
-180
-200
Gain
Phase
1k
10k
100k
Phase (°)
Gain (dB)
VTT load 500 mA
1M
Frequency
Figure 3-1. DDR3 Bode Plot Iload = 500 mA
SLVUCK2A – JANUARY 2023 – REVISED APRIL 2023
Submit Document Feedback
TPS7H3302EVM (LP085)
Copyright © 2023 Texas Instruments Incorporated
7
Test Setup
www.ti.com
Bode Plot for DDR3 VDDQSNS = 1.5V
1k
10k
100k
200
180
160
140
120
100
80
60
40
20
0
-20
-40
-60
-80
-100
-120
-140
-160
-180
-200
Phase (°)
Gain
Phase
200
180
160
140
120
100
80
60
40
20
0
-20
-40
-60
-80
-100
-120
-140
-160
-180
-200
Phase (°)
Gain (dB)
VTT load 1 A
100
90
80
70
60
50
40
30
20
10
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
100
1M
Frequency
Figure 3-2. DDR3 Bode Plot Iload = 1 A
Bode Plot for DDR3 VDDQSNS = 1.5V
Gain (dB)
VTT load 3 A
100
90
80
70
60
50
40
30
20
10
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
100
Gain
Phase
1k
10k
100k
1M
Frequency
Figure 3-3. DDR3 Bode Plot Iload = 3 A
TI recommends that VLDOIN and VDDQSNS be isolated from each other. If isolating VLDOIN and VDDQSNS
is not possible, then add an external input filter between VLDOIN and VDDQSNS. Adding an RC filter between
VLDOIN and VDDQSNS results in some loss of dynamic tracking of VTT and VTTREF to VDDQSNS.
8
TPS7H3302EVM (LP085)
SLVUCK2A – JANUARY 2023 – REVISED APRIL 2023
Submit Document Feedback
Copyright © 2023 Texas Instruments Incorporated
www.ti.com
Test Setup
3.3.2 EVM Transient Test
A transient test setup circuit is incorporated as part of the EVM.
The built-in transient load switches (with both sinking and sourcing capability) are available to emulate the
sink or source transient behavior to evaluate the dynamic performance. For ease of use, both load step and
transient timing can be modified by on-board resistors. The EVM has two sets of four parallel 1.6 Ω resistors
connected for transient load for both the VTT to GND, and VTT to V2 to accommodate both sourcing and
sinking evaluation. Optionally, resistor R13 can be populated with zero Ω resistor to utilize VLDOIN as source for
sinking transients. This method can cause a poor response due to transients introduced on VLDOIN, especially if
VDDQSNS is tied to VLDOIN.
CAUTION
The default EVM configuration using the built-in transient test circuit supports testing the DDR4 at
±1.5 A, DDR3 at ±1.875 A, and DDR2 at ±2.25 A. To evaluate the DDR node, or different loads for
DDR2, DDR3, DDR3L, and DDR4 the total resistance of resistors R6-R9 and R17-R20 needs to be
changed to not exceed device maximum ratings.
1.
2.
3.
4.
5.
6.
7.
8.
Remove any external loads.
Place jumper J14 (pins 2 and 3) source load selector (labeled "EN").
Place jumper J15 (pins 1 and 2) sink load selector.
Remove jumper J5 to isolate VDDQSNS from VLDOIN.
Apply 2.5 V to VIN.
Apply 1.5 V to J7/J9 VLDOIN.
Apply 1.5 V to J16/J17 V2 (this is the source for the sinking transients).
Apply 1.5 V to J4/J3 VDDQSNS. If testing with VDDQSNS is not isolated from VLDOIN, install J10, and only
apply to VLDOIN (with reduced performance).
9. Monitor VTT to verify VTT voltage is present. VTT is approximately 750 mV.
10. Apply 5 V to J13 (pin 2 [+], pin 1 [–]) (or by TP15, TP16), providing power to the transient load setup.
11. Monitor VTT at J10 using a scope to see transient results.
The following plots show the results of using the transient circuit configured for DDR3 voltages. All the plots have
VTT and VTTREF shown with 750 mV offset applied. In addition to VTT and VTTREF, the plots include the clock
signal (CLK), the math function of the difference of VTTREF - VTT, and the current measurements of V2. Note,
that V2 only represents the current when the device is sinking. Thus, during the sourcing, this current is zero.
During sourcing, a near identical current is present through VLDOIN.
Figure 3-5 shows the response of the circuit with both sinking and sourcing enabled.
Figure 3-5 shows the response of the circuit with only sinking transients applied. This method can be tested by
only having shunt on J15 and no shunt on J14.
Figure 3-6 shows the response of the circuit with only sourcing transients applied. This method can be tested by
only having shunt on EN pins of J14, and no shunt on J15.
Figure 3-7 shows the transient response with VDDQSNS not isolated from VLDOIN with both sinking and
sourcing enabled. Transients on VLDOIN also influences VDDQSNS and cause undesirable disturbances.
Transient response can be improved with implementation of a filter on VDDQSNS from VLDOIN. The filter can
be implemented by replacing components for R4, and C3. Note the large fluctuation on VTTREF due to VLDOIN
and hence VDDQSNS transients.
SLVUCK2A – JANUARY 2023 – REVISED APRIL 2023
Submit Document Feedback
TPS7H3302EVM (LP085)
Copyright © 2023 Texas Instruments Incorporated
9
Test Setup
www.ti.com
Figure 3-4. DDR3 Scope Plot Response With Both Sinking and Sourcing Enabled and VDDQSNS
Isolated.
Figure 3-5. DDR3 Scope Plot of Response with 1.875 A Sinking Only with Isolated VDDQSNS
10
TPS7H3302EVM (LP085)
SLVUCK2A – JANUARY 2023 – REVISED APRIL 2023
Submit Document Feedback
Copyright © 2023 Texas Instruments Incorporated
www.ti.com
Test Setup
Figure 3-6. DDR3 Scope Plot of Response with 1.875 A Sourcing Only with Isolated VDDQSNS
Figure 3-7. DDR3 Scope Plot of Response With 1.875 A Sinking and Sourcing With Non-Isolated
VDDQSNS
SLVUCK2A – JANUARY 2023 – REVISED APRIL 2023
Submit Document Feedback
TPS7H3302EVM (LP085)
Copyright © 2023 Texas Instruments Incorporated
11
Board Layout
www.ti.com
4 Board Layout
Figure 4-1. Top Overlay
Figure 4-2. Top Solder
12
TPS7H3302EVM (LP085)
SLVUCK2A – JANUARY 2023 – REVISED APRIL 2023
Submit Document Feedback
Copyright © 2023 Texas Instruments Incorporated
www.ti.com
Board Layout
Figure 4-3. Top Layer
Figure 4-4. Signal and Power Layer 1
SLVUCK2A – JANUARY 2023 – REVISED APRIL 2023
Submit Document Feedback
TPS7H3302EVM (LP085)
Copyright © 2023 Texas Instruments Incorporated
13
Board Layout
www.ti.com
Figure 4-5. Signal and Power Layer 2
Figure 4-6. Bottom Layer
14
TPS7H3302EVM (LP085)
SLVUCK2A – JANUARY 2023 – REVISED APRIL 2023
Submit Document Feedback
Copyright © 2023 Texas Instruments Incorporated
www.ti.com
Board Layout
Figure 4-7. Bottom Solder
SLVUCK2A – JANUARY 2023 – REVISED APRIL 2023
Submit Document Feedback
TPS7H3302EVM (LP085)
Copyright © 2023 Texas Instruments Incorporated
15
Schematic
www.ti.com
5 Schematic
Figure 5-1 illustrates the TPS7H3302EVM-SEP schematics.
TPS7H3302EVM
J2
J1
GND
VDD
2.375 - 3.5 V
TP1
TP2
VDD
C1
TP3
2
1
EN
J5
R1
20k
10µF
16V
EN
J4
U1
21
J6
2
1
GND
TP8
20
R4
TP7
J7
5
0
VLDOIN IN
0.9-3.5V
VLDOIN
J9
C3
10V
1µF
GND
C4
C5
C6
10µF
16V
10µF
16V
10µF
16V
C12
1nF
100V
C13
C14
10µF
16V
10µF
16V
TP9
J8
1 VTTREF
C15
10V
150uF
TP12
TP11
Optional
Filter
7
8
4
1
2
3
6
12
13
14
15
16
17
18
19
27
30
31
32
2
3
4
5
VDDQSNS
1-3.5V
C16
2.2µF
25V
GND
TP4
VDD
VTTSNS
VTT
VTT
VTT
VTT
EN
VDDQSNS
VLDOIN
VLDOIN
29
C2
23
24
25
26
TP5
R2
R3
392
51.0
TP6
1nF
16V
VTT
1
J3
GND
5
4
3
2
J11
J10
VTTREF
TP10
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
PGOOD
22
VDD
C7
10V
4.7uF
R5
20k
C18
10V
150uF
C17
10V
150uF
AGND
PGND
PGND
PGND
Thermal_Pad
C9
10V
4.7uF
C8
10V
4.7uF
C10
10V
4.7uF
C19
10V
150uF
C20
10V
150uF
VTT
C11
10V
4.7uF
J12
C21
10V
4.7uF
GND
28
9
10
11
TP13
TP14
33
GND
TPS7H3302MDAPTSEP
TPS7H3302EVM Transient circuit
+5VIN
TP15
14
5V VIN
J13
7
U3
+5VIN
6
1
3
2
2
4
U2A
R21
100k
GND
+5VIN
1
8
C24
C25
C26
10µF
16V
10µF
16V
10µF
16V
1.00
5,6,
7,8
R15
10k
VDD
INA
OUTA
INB
OUTB
NC
NC
GND
C23
100nF
50V
GND
5
R22
3
1.00
4
R23
100 ohm
R24
10k
TP17
C27
100nF
50V
R7
1.60
R8
1.60
R17
1.60
R18
1.60
R19
1.60
R9
1.60
V2
7
UCC27325DR
4
J15
4
R11
100 ohm
1,2,3
100k
TP16
5,6,
7,8
GND
R6
1.60
Q1
CSD16408Q5
R20
1.60
R13
0
VLDOIN
R16
VTT
0
Q2
CSD16408Q5
1,2,3
3
2
1
R10
R12
R14
100k
J14
Sink Load
Selection
GND
C22
10V
1µF
GND
Source Load
Selection
VCC
U2E
2
1
5V INPUT
4.5-5.5V
6
2
1
5
U2B
GND
TP18
CLK_IN
+5VIN
U4
8
VCC
OUT
TP19
V2
R25
1.0k
3
+5VIN
V2
0.9-3.5V
9
8
4
6
2
RESET
DISCH
THRES
CONT
TRIG
GND
7
R26
7.5k
5
1
C35
100nF
50V
C36
100nF
50V
C34
2.2µF
25V
GND
U2C
J16
J17
10
V2
C28
C29
10µF
16V
C30
10µF
16V
10µF
16V
C31
C32
10µF
16V
10µF
16V
C33
16V
47uF
12
11
13
U2D
GND
NE555PWR
GND
Figure 5-1. LP085B Schematic
16
TPS7H3302EVM (LP085)
SLVUCK2A – JANUARY 2023 – REVISED APRIL 2023
Submit Document Feedback
Copyright © 2023 Texas Instruments Incorporated
www.ti.com
Bill of Materials
6 Bill of Materials
Table 6-1 lists the EVM BOM.
Table 6-1. Bill of Materials
Designator
Quantity Description
PartNumber
Manufacturer
C1, C4, C5, C6, C13,
C14, C24, C25, C26,
C28, C29, C30, C31,
C32
14
Ceramic capacitor for automotive 10 μF, ±10%,
16VDC, X7R 1206 embossed T/R, 1206
GCM31CR71C106KA64K
Murata
C2
1
Ceramic capacitor, 1000 pF, ±10%, 16 V, X7R, 603
CC0603KRX7R7BB102
YAGEO
C7, C8, C9, C10
4
Ceramic capacitor, 4.7 μF, 10 V, ±10%, X7R, 1210
1210ZC475KAT2A
AVX
C12
1
Ceramic capacitor, 1000 pF, 100 V, ±10%, X7R, 0603
06031C102KAT2A
AVX
C15, C17, C18, C19
4
Capacitor, tantalum polymer, 150 μF, 10 V, ±20%,
0.005 ohm, 7343-31 SMD
T530D157M010ATE005
Kemet
C16, C34
2
Ceramic capacitor, 2.2 μF, 25 V, ±10%, X7R, 0805
08053C225KAT2A
AVX
C22
1
Ceramic capacitor, 1 μF, 10 V, ±10%, X7R, 0603
0603ZC105KAT4A
AVX
C33
1
Capacitor, TA, 47 μF, 16 V, ±20%, 0.15 ohm, SMD
TPSD476M016R0150
AVX
C35, C36
2
Ceramic capacitor, 0.1 µF, 50 V, ±5%, X7R, 0603
06035C104JAT2A
AVX
J1, J2, J3, J4, J7, J9,
J11, J12, J16, J17
10
Standard banana jack, uninsulated, 5.5 mm
575-4
Keystone
J5, J6, J13, J15
4
Header, 100 mil, 2x1, gold, TH
TSW-102-07-G-S
Samtec
J8, J10
2
SMA connector receptacle, female socket 50 Ω,
PTH_RF_CONN
733910060
Molex
J14
1
Header, 100 mil, 3x1, gold, TH
TSW-103-07-G-S
Samtec
Q1, Q2
2
MOSFET, N-channel, 25 V, 113 A, DQH0008A (VSON- CSD16408Q5
CLIP-8)
Texas
Instruments
R1, R5
2
Resistor, 20 kΩ, 5%, 0.1 W, 0603
RC0603JR-0720KL
Yageo
R2
1
Resistor, 392 Ω, 1%, 0.1 W, 0603
RC0603FR-07392RL
Yageo
R3
1
Resistor, 51.0 Ω, 1%, 0.1 W, 0603
RC0603FR-0751RL
Yageo
R4
1
Resistor, 0 Ω, 5%, 0.125 W, 0805
RC0805JR-070RL
Yageo
America
R6, R7, R8, R9, R17,
R18, R19, R20
8
Resistor, 1.60 Ω, 1%, 1 W, 2512
ERJ-1TRQF1R6U
Panasonic
R10, R22
2
Resistor, 1.00 Ω, 1%, 0.125 W, 0805
RC0805FR-071RL
Yageo
America
R11, R23
2
Trimmer, 100 Ω, 0.5W, TH, potentiometer, 953 x 12.36
x 4.95 mm
67WR100LF
TTElectronics-BITechnologies
R12, R14, R21
3
Resistor, 100 kΩ, 5%, 0.1 W, 0603
CRCW0603100KJNEAC
Vishay-Dale
R15, R24
2
Resistor, 10 kΩ, 5%, 0.1 W, 0603
RC0603JR-0710KL
Yageo
R16
1
Resistor, 0 Ω, 5%, 0.75 W, AEC-Q200 grade 0, 2010
CRCW20100000Z0EF
Vishay-Dale
R25
1
Resistor, 1.0 kΩ, 5%, 0.25 W, AEC-Q200 grade 0,
0603
ESR03EZPJ102
Rohm
R26
1
Resistor, 7.5 kΩ, 5%, 0.1 W, 0603
RC0603JR-077K5L
Yageo
SH-J1,SH-J2,SH-J3
3
Shunt, 100 mil, gold plated, black
SNT-100-BK-G
Samtec
SLVUCK2A – JANUARY 2023 – REVISED APRIL 2023
Submit Document Feedback
TPS7H3302EVM (LP085)
Copyright © 2023 Texas Instruments Incorporated
17
Related Documentation
www.ti.com
Table 6-1. Bill of Materials (continued)
Designator
Quantity Description
PartNumber
Manufacturer
TP1, TP5, TP6, TP7,
8
TP8, TP9, TP15, TP19
Test point, multipurpose, red, TH
5010
Keystone
Electronics
TP2, TP11, TP12,
TP13, TP14, TP16,
TP17
Test point, multipurpose, black, TH
5011
Keystone
Electronics
TP3, TP4, TP10, TP18 4
Test point, multipurpose, yellow, TH
5014
Keystone
Electronics
U1
1
Radiation-tolerant 3-A DDR termination regulator,
HTSSOP32
TPS7H3302MDAPTSEP
Texas
Instruments
U2
1
Quadruple 2-input positive-NAND gates, D0014A,
LARGE T&R
U3
1
Dual 4-A Peak High Speed Low-Side Power MOSFET
Drivers, D0008A (SOIC-8)
UCC27325DR
Texas
Instruments
U4
1
Single Precision Timer, PW0008A (TSSOP-8)
NE555PWR
Texas
Instruments
C3
0
Ceramic capacitor, 1 µF, 10 V, ± 10%, X7R, 0603
0603ZC105KAT4A
AVX
C11, C21
0
Ceramic capacitor, 4.7 μF, 10 V, ±10%, X7R, 1210
1210ZC475KAT2A
AVX
C20
0
Capacitor, tantalum polymer, 150 μF, 10 V, ±20%,
0.005 Ω, 7343-31
T530D157M010ATE005
Kemet
C23, C27
0
Ceramic capacitor, 0.1 µF, 50 V,±5%, X7R, 0603
06035C104JAT2A
AVX
R13
0
Resistor, 0 Ω, 5%, 0.75 W, AEC-Q200 Grade 0, 2010
CRCW20100000Z0EF
Vishay-Dale
7
Texas
Instruments
7 Related Documentation
Texas Instruments, Standard Terms for Evaluation Modules
8 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (August 2022) to Revision A (April 2023)
Page
• Deleted notes pertaining to revision A board......................................................................................................7
• Changed board plots to LP085B...................................................................................................................... 12
• Changed schematic to LP085B........................................................................................................................ 16
• Change Bill of Materials to LP085B..................................................................................................................17
18
TPS7H3302EVM (LP085)
SLVUCK2A – JANUARY 2023 – REVISED APRIL 2023
Submit Document Feedback
Copyright © 2023 Texas Instruments Incorporated
STANDARD TERMS FOR EVALUATION MODULES
1.
Delivery: TI delivers TI evaluation boards, kits, or modules, including any accompanying demonstration software, components, and/or
documentation which may be provided together or separately (collectively, an “EVM” or “EVMs”) to the User (“User”) in accordance
with the terms set forth herein. User's acceptance of the EVM is expressly subject to the following terms.
1.1 EVMs are intended solely for product or software developers for use in a research and development setting to facilitate feasibility
evaluation, experimentation, or scientific analysis of TI semiconductors products. EVMs have no direct function and are not
finished products. EVMs shall not be directly or indirectly assembled as a part or subassembly in any finished product. For
clarification, any software or software tools provided with the EVM (“Software”) shall not be subject to the terms and conditions
set forth herein but rather shall be subject to the applicable terms that accompany such Software
1.2 EVMs are not intended for consumer or household use. EVMs may not be sold, sublicensed, leased, rented, loaned, assigned,
or otherwise distributed for commercial purposes by Users, in whole or in part, or used in any finished product or production
system.
2
Limited Warranty and Related Remedies/Disclaimers:
2.1 These terms do not apply to Software. The warranty, if any, for Software is covered in the applicable Software License
Agreement.
2.2 TI warrants that the TI EVM will conform to TI's published specifications for ninety (90) days after the date TI delivers such EVM
to User. Notwithstanding the foregoing, TI shall not be liable for a nonconforming EVM if (a) the nonconformity was caused by
neglect, misuse or mistreatment by an entity other than TI, including improper installation or testing, or for any EVMs that have
been altered or modified in any way by an entity other than TI, (b) the nonconformity resulted from User's design, specifications
or instructions for such EVMs or improper system design, or (c) User has not paid on time. Testing and other quality control
techniques are used to the extent TI deems necessary. TI does not test all parameters of each EVM.
User's claims against TI under this Section 2 are void if User fails to notify TI of any apparent defects in the EVMs within ten (10)
business days after delivery, or of any hidden defects with ten (10) business days after the defect has been detected.
2.3 TI's sole liability shall be at its option to repair or replace EVMs that fail to conform to the warranty set forth above, or credit
User's account for such EVM. TI's liability under this warranty shall be limited to EVMs that are returned during the warranty
period to the address designated by TI and that are determined by TI not to conform to such warranty. If TI elects to repair or
replace such EVM, TI shall have a reasonable time to repair such EVM or provide replacements. Repaired EVMs shall be
warranted for the remainder of the original warranty period. Replaced EVMs shall be warranted for a new full ninety (90) day
warranty period.
WARNING
Evaluation Kits are intended solely for use by technically qualified,
professional electronics experts who are familiar with the dangers
and application risks associated with handling electrical mechanical
components, systems, and subsystems.
User shall operate the Evaluation Kit within TI’s recommended
guidelines and any applicable legal or environmental requirements
as well as reasonable and customary safeguards. Failure to set up
and/or operate the Evaluation Kit within TI’s recommended
guidelines may result in personal injury or death or property
damage. Proper set up entails following TI’s instructions for
electrical ratings of interface circuits such as input, output and
electrical loads.
NOTE:
EXPOSURE TO ELECTROSTATIC DISCHARGE (ESD) MAY CAUSE DEGREDATION OR FAILURE OF THE EVALUATION
KIT; TI RECOMMENDS STORAGE OF THE EVALUATION KIT IN A PROTECTIVE ESD BAG.
www.ti.com
3
Regulatory Notices:
3.1 United States
3.1.1
Notice applicable to EVMs not FCC-Approved:
FCC NOTICE: This kit is designed to allow product developers to evaluate electronic components, circuitry, or software
associated with the kit to determine whether to incorporate such items in a finished product and software developers to write
software applications for use with the end product. This kit is not a finished product and when assembled may not be resold or
otherwise marketed unless all required FCC equipment authorizations are first obtained. Operation is subject to the condition
that this product not cause harmful interference to licensed radio stations and that this product accept harmful interference.
Unless the assembled kit is designed to operate under part 15, part 18 or part 95 of this chapter, the operator of the kit must
operate under the authority of an FCC license holder or must secure an experimental authorization under part 5 of this chapter.
3.1.2
For EVMs annotated as FCC – FEDERAL COMMUNICATIONS COMMISSION Part 15 Compliant:
CAUTION
This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not
cause harmful interference, and (2) this device must accept any interference received, including interference that may cause
undesired operation.
Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to
operate the equipment.
FCC Interference Statement for Class A EVM devices
NOTE: This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to part 15 of
the FCC Rules. These limits are designed to provide reasonable protection against harmful interference when the equipment is
operated in a commercial environment. This equipment generates, uses, and can radiate radio frequency energy and, if not
installed and used in accordance with the instruction manual, may cause harmful interference to radio communications.
Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required to
correct the interference at his own expense.
FCC Interference Statement for Class B EVM devices
NOTE: This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of
the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential
installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance
with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference
will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which
can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more
of the following measures:
•
•
•
•
Reorient or relocate the receiving antenna.
Increase the separation between the equipment and receiver.
Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.
Consult the dealer or an experienced radio/TV technician for help.
3.2 Canada
3.2.1
For EVMs issued with an Industry Canada Certificate of Conformance to RSS-210 or RSS-247
Concerning EVMs Including Radio Transmitters:
This device complies with Industry Canada license-exempt RSSs. Operation is subject to the following two conditions:
(1) this device may not cause interference, and (2) this device must accept any interference, including interference that may
cause undesired operation of the device.
Concernant les EVMs avec appareils radio:
Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitation
est autorisée aux deux conditions suivantes: (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit
accepter tout brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le fonctionnement.
Concerning EVMs Including Detachable Antennas:
Under Industry Canada regulations, this radio transmitter may only operate using an antenna of a type and maximum (or lesser)
gain approved for the transmitter by Industry Canada. To reduce potential radio interference to other users, the antenna type
and its gain should be so chosen that the equivalent isotropically radiated power (e.i.r.p.) is not more than that necessary for
successful communication. This radio transmitter has been approved by Industry Canada to operate with the antenna types
listed in the user guide with the maximum permissible gain and required antenna impedance for each antenna type indicated.
Antenna types not included in this list, having a gain greater than the maximum gain indicated for that type, are strictly prohibited
for use with this device.
2
www.ti.com
Concernant les EVMs avec antennes détachables
Conformément à la réglementation d'Industrie Canada, le présent émetteur radio peut fonctionner avec une antenne d'un type et
d'un gain maximal (ou inférieur) approuvé pour l'émetteur par Industrie Canada. Dans le but de réduire les risques de brouillage
radioélectrique à l'intention des autres utilisateurs, il faut choisir le type d'antenne et son gain de sorte que la puissance isotrope
rayonnée équivalente (p.i.r.e.) ne dépasse pas l'intensité nécessaire à l'établissement d'une communication satisfaisante. Le
présent émetteur radio a été approuvé par Industrie Canada pour fonctionner avec les types d'antenne énumérés dans le
manuel d’usage et ayant un gain admissible maximal et l'impédance requise pour chaque type d'antenne. Les types d'antenne
non inclus dans cette liste, ou dont le gain est supérieur au gain maximal indiqué, sont strictement interdits pour l'exploitation de
l'émetteur
3.3 Japan
3.3.1
3.3.2
Notice for EVMs delivered in Japan: Please see http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_01.page 日本国内に
輸入される評価用キット、ボードについては、次のところをご覧ください。
https://www.ti.com/ja-jp/legal/notice-for-evaluation-kits-delivered-in-japan.html
Notice for Users of EVMs Considered “Radio Frequency Products” in Japan: EVMs entering Japan may not be certified
by TI as conforming to Technical Regulations of Radio Law of Japan.
If User uses EVMs in Japan, not certified to Technical Regulations of Radio Law of Japan, User is required to follow the
instructions set forth by Radio Law of Japan, which includes, but is not limited to, the instructions below with respect to EVMs
(which for the avoidance of doubt are stated strictly for convenience and should be verified by User):
1.
2.
3.
Use EVMs in a shielded room or any other test facility as defined in the notification #173 issued by Ministry of Internal
Affairs and Communications on March 28, 2006, based on Sub-section 1.1 of Article 6 of the Ministry’s Rule for
Enforcement of Radio Law of Japan,
Use EVMs only after User obtains the license of Test Radio Station as provided in Radio Law of Japan with respect to
EVMs, or
Use of EVMs only after User obtains the Technical Regulations Conformity Certification as provided in Radio Law of Japan
with respect to EVMs. Also, do not transfer EVMs, unless User gives the same notice above to the transferee. Please note
that if User does not follow the instructions above, User will be subject to penalties of Radio Law of Japan.
【無線電波を送信する製品の開発キットをお使いになる際の注意事項】 開発キットの中には技術基準適合証明を受けて
いないものがあります。 技術適合証明を受けていないもののご使用に際しては、電波法遵守のため、以下のいずれかの
措置を取っていただく必要がありますのでご注意ください。
1.
2.
3.
電波法施行規則第6条第1項第1号に基づく平成18年3月28日総務省告示第173号で定められた電波暗室等の試験設備でご使用
いただく。
実験局の免許を取得後ご使用いただく。
技術基準適合証明を取得後ご使用いただく。
なお、本製品は、上記の「ご使用にあたっての注意」を譲渡先、移転先に通知しない限り、譲渡、移転できないものとします。
上記を遵守頂けない場合は、電波法の罰則が適用される可能性があることをご留意ください。 日本テキサス・イ
ンスツルメンツ株式会社
東京都新宿区西新宿６丁目２４番１号
西新宿三井ビル
3.3.3
Notice for EVMs for Power Line Communication: Please see http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_02.page
電力線搬送波通信についての開発キットをお使いになる際の注意事項については、次のところをご覧くださ
い。https://www.ti.com/ja-jp/legal/notice-for-evaluation-kits-for-power-line-communication.html
3.4 European Union
3.4.1
For EVMs subject to EU Directive 2014/30/EU (Electromagnetic Compatibility Directive):
This is a class A product intended for use in environments other than domestic environments that are connected to a
low-voltage power-supply network that supplies buildings used for domestic purposes. In a domestic environment this
product may cause radio interference in which case the user may be required to take adequate measures.
3
www.ti.com
4
EVM Use Restrictions and Warnings:
4.1 EVMS ARE NOT FOR USE IN FUNCTIONAL SAFETY AND/OR SAFETY CRITICAL EVALUATIONS, INCLUDING BUT NOT
LIMITED TO EVALUATIONS OF LIFE SUPPORT APPLICATIONS.
4.2 User must read and apply the user guide and other available documentation provided by TI regarding the EVM prior to handling
or using the EVM, including without limitation any warning or restriction notices. The notices contain important safety information
related to, for example, temperatures and voltages.
4.3 Safety-Related Warnings and Restrictions:
4.3.1
User shall operate the EVM within TI’s recommended specifications and environmental considerations stated in the user
guide, other available documentation provided by TI, and any other applicable requirements and employ reasonable and
customary safeguards. Exceeding the specified performance ratings and specifications (including but not limited to input
and output voltage, current, power, and environmental ranges) for the EVM may cause personal injury or death, or
property damage. If there are questions concerning performance ratings and specifications, User should contact a TI
field representative prior to connecting interface electronics including input power and intended loads. Any loads applied
outside of the specified output range may also result in unintended and/or inaccurate operation and/or possible
permanent damage to the EVM and/or interface electronics. Please consult the EVM user guide prior to connecting any
load to the EVM output. If there is uncertainty as to the load specification, please contact a TI field representative.
During normal operation, even with the inputs and outputs kept within the specified allowable ranges, some circuit
components may have elevated case temperatures. These components include but are not limited to linear regulators,
switching transistors, pass transistors, current sense resistors, and heat sinks, which can be identified using the
information in the associated documentation. When working with the EVM, please be aware that the EVM may become
very warm.
4.3.2
EVMs are intended solely for use by technically qualified, professional electronics experts who are familiar with the
dangers and application risks associated with handling electrical mechanical components, systems, and subsystems.
User assumes all responsibility and liability for proper and safe handling and use of the EVM by User or its employees,
affiliates, contractors or designees. User assumes all responsibility and liability to ensure that any interfaces (electronic
and/or mechanical) between the EVM and any human body are designed with suitable isolation and means to safely
limit accessible leakage currents to minimize the risk of electrical shock hazard. User assumes all responsibility and
liability for any improper or unsafe handling or use of the EVM by User or its employees, affiliates, contractors or
designees.
4.4 User assumes all responsibility and liability to determine whether the EVM is subject to any applicable international, federal,
state, or local laws and regulations related to User’s handling and use of the EVM and, if applicable, User assumes all
responsibility and liability for compliance in all respects with such laws and regulations. User assumes all responsibility and
liability for proper disposal and recycling of the EVM consistent with all applicable international, federal, state, and local
requirements.
5.
Accuracy of Information: To the extent TI provides information on the availability and function of EVMs, TI attempts to be as accurate
as possible. However, TI does not warrant the accuracy of EVM descriptions, EVM availability or other information on its websites as
accurate, complete, reliable, current, or error-free.
6.
Disclaimers:
6.1 EXCEPT AS SET FORTH ABOVE, EVMS AND ANY MATERIALS PROVIDED WITH THE EVM (INCLUDING, BUT NOT
LIMITED TO, REFERENCE DESIGNS AND THE DESIGN OF THE EVM ITSELF) ARE PROVIDED "AS IS" AND "WITH ALL
FAULTS." TI DISCLAIMS ALL OTHER WARRANTIES, EXPRESS OR IMPLIED, REGARDING SUCH ITEMS, INCLUDING BUT
NOT LIMITED TO ANY EPIDEMIC FAILURE WARRANTY OR IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS
FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF ANY THIRD PARTY PATENTS, COPYRIGHTS, TRADE
SECRETS OR OTHER INTELLECTUAL PROPERTY RIGHTS.
6.2 EXCEPT FOR THE LIMITED RIGHT TO USE THE EVM SET FORTH HEREIN, NOTHING IN THESE TERMS SHALL BE
CONSTRUED AS GRANTING OR CONFERRING ANY RIGHTS BY LICENSE, PATENT, OR ANY OTHER INDUSTRIAL OR
INTELLECTUAL PROPERTY RIGHT OF TI, ITS SUPPLIERS/LICENSORS OR ANY OTHER THIRD PARTY, TO USE THE
EVM IN ANY FINISHED END-USER OR READY-TO-USE FINAL PRODUCT, OR FOR ANY INVENTION, DISCOVERY OR
IMPROVEMENT, REGARDLESS OF WHEN MADE, CONCEIVED OR ACQUIRED.
7.
4
USER'S INDEMNITY OBLIGATIONS AND REPRESENTATIONS. USER WILL DEFEND, INDEMNIFY AND HOLD TI, ITS
LICENSORS AND THEIR REPRESENTATIVES HARMLESS FROM AND AGAINST ANY AND ALL CLAIMS, DAMAGES, LOSSES,
EXPENSES, COSTS AND LIABILITIES (COLLECTIVELY, "CLAIMS") ARISING OUT OF OR IN CONNECTION WITH ANY
HANDLING OR USE OF THE EVM THAT IS NOT IN ACCORDANCE WITH THESE TERMS. THIS OBLIGATION SHALL APPLY
WHETHER CLAIMS ARISE UNDER STATUTE, REGULATION, OR THE LAW OF TORT, CONTRACT OR ANY OTHER LEGAL
THEORY, AND EVEN IF THE EVM FAILS TO PERFORM AS DESCRIBED OR EXPECTED.
www.ti.com
8.
Limitations on Damages and Liability:
8.1 General Limitations. IN NO EVENT SHALL TI BE LIABLE FOR ANY SPECIAL, COLLATERAL, INDIRECT, PUNITIVE,
INCIDENTAL, CONSEQUENTIAL, OR EXEMPLARY DAMAGES IN CONNECTION WITH OR ARISING OUT OF THESE
TERMS OR THE USE OF THE EVMS , REGARDLESS OF WHETHER TI HAS BEEN ADVISED OF THE POSSIBILITY OF
SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED TO, COST OF REMOVAL OR
REINSTALLATION, ANCILLARY COSTS TO THE PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES, RETESTING,
OUTSIDE COMPUTER TIME, LABOR COSTS, LOSS OF GOODWILL, LOSS OF PROFITS, LOSS OF SAVINGS, LOSS OF
USE, LOSS OF DATA, OR BUSINESS INTERRUPTION. NO CLAIM, SUIT OR ACTION SHALL BE BROUGHT AGAINST TI
MORE THAN TWELVE (12) MONTHS AFTER THE EVENT THAT GAVE RISE TO THE CAUSE OF ACTION HAS
OCCURRED.
8.2 Specific Limitations. IN NO EVENT SHALL TI'S AGGREGATE LIABILITY FROM ANY USE OF AN EVM PROVIDED
HEREUNDER, INCLUDING FROM ANY WARRANTY, INDEMITY OR OTHER OBLIGATION ARISING OUT OF OR IN
CONNECTION WITH THESE TERMS, , EXCEED THE TOTAL AMOUNT PAID TO TI BY USER FOR THE PARTICULAR
EVM(S) AT ISSUE DURING THE PRIOR TWELVE (12) MONTHS WITH RESPECT TO WHICH LOSSES OR DAMAGES ARE
CLAIMED. THE EXISTENCE OF MORE THAN ONE CLAIM SHALL NOT ENLARGE OR EXTEND THIS LIMIT.
9.
Return Policy. Except as otherwise provided, TI does not offer any refunds, returns, or exchanges. Furthermore, no return of EVM(s)
will be accepted if the package has been opened and no return of the EVM(s) will be accepted if they are damaged or otherwise not in
a resalable condition. If User feels it has been incorrectly charged for the EVM(s) it ordered or that delivery violates the applicable
order, User should contact TI. All refunds will be made in full within thirty (30) working days from the return of the components(s),
excluding any postage or packaging costs.
10. Governing Law: These terms and conditions shall be governed by and interpreted in accordance with the laws of the State of Texas,
without reference to conflict-of-laws principles. User agrees that non-exclusive jurisdiction for any dispute arising out of or relating to
these terms and conditions lies within courts located in the State of Texas and consents to venue in Dallas County, Texas.
Notwithstanding the foregoing, any judgment may be enforced in any United States or foreign court, and TI may seek injunctive relief
in any United States or foreign court.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023, Texas Instruments Incorporated
5
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023, Texas Instruments Incorporated
工商网监
湘ICP备2023018690号
