TPS82130SILR

TPS82130 SLVSCY5E – FEBRUARY 2016 – REVISED OCTOBER 2021 TPS82130 17-V Input 3-A Step-Down Converter MicroSiP™ Module with Integrated Inductor 1 Features 3-mm × 2.8-mm × 1.5-mm package 3-V to 17-V input range 3-A continuous output current DCS-Control™ topology Power save mode for light-load efficiency 20-µA operating quiescent current 0.9-V to 6-V adjustable output voltage 100% duty cycle for lowest dropout Power-good output Programmable soft start-up with tracking Thermal shutdown protection –40°C to 125°C operating temperature range Create a custom design using the TPS82130 with the WEBENCH® Power Designer 2 Applications • • • Industrial applications Telecom and networking applications Solid state drives The TPS82130 is a 17-V input 3-A step-down converter MicroSiP power module optimized for small solution size and high efficiency. The module integrates a synchronous step-down converter and an inductor to simplify design, reduce external components, and save PCB area. The low profile and compact solution is suitable for automated assembly by standard surface mount equipment. To maximize efficiency, the converter operates in PWM mode with a nominal switching frequency of 2 MHz and automatically enters power save mode operation at light load currents. In power save mode, the device operates with 20-µA (typical) quiescent current. Using the DCS-Control topology, the device achieves excellent load transient performance and accurate output voltage regulation. Device Information PART NUMBER PACKAGE(1) BODY SIZE (NOM) TPS82130 µSiL (8) 3.00 mm × 2.80 mm (1) VIN C1 10µF C3 3.3nF VOUT EN SS/TR GND R1 124kΩ FB PG For all available packages, see the orderable addendum at the end of the data sheet. 100 TPS82130 VIN 12 V R3 100kΩ C2 22µF VOUT 1.8 V/3 A R2 100kΩ POWER GOOD Copyright © 2016, Texas Instruments Incorporated Simplified Schematic 1.8-V Output Application 90 Efficiency (%) • • • • • • • • • • • • • 3 Description MicroSiP™ 80 70 VOUT = 1.0 V VOUT = 1.8 V VOUT = 2.5 V VOUT = 3.3 V 60 50 1m 10m 100m Load (A) 1 5 D017 12-V Input Voltage Efficiency An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPS82130 www.ti.com SLVSCY5E – FEBRUARY 2016 – REVISED OCTOBER 2021 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Pin Configuration and Functions...................................3 6 Specifications.................................................................. 4 6.1 Absolute Maximum Ratings........................................ 4 6.2 ESD Ratings............................................................... 4 6.3 Recommend Operating Conditions.............................4 6.4 Thermal Information....................................................4 6.5 Electrical Characteristics.............................................5 6.6 Typical Characteristics................................................ 6 7 Detailed Description........................................................7 7.1 Overview..................................................................... 7 7.2 Functional Block Diagram........................................... 7 7.3 Feature Description.....................................................7 7.4 Device Functional Modes............................................9 8 Application and Implementation.................................. 11 8.1 Application Information..............................................11 8.2 Typical Applications...................................................11 9 Power Supply Recommendations................................17 10 Layout...........................................................................18 10.1 Layout Guidelines................................................... 18 10.2 Layout Example...................................................... 18 10.3 Thermal Consideration............................................18 11 Device and Documentation Support..........................19 11.1 Device Support........................................................19 11.2 Receiving Notification of Documentation Updates.. 19 11.3 Support Resources................................................. 19 11.4 Trademarks............................................................. 19 11.5 Glossary.................................................................. 19 11.6 Electrostatic Discharge Caution.............................. 19 12 Mechanical, Packaging, and Orderable Information.................................................................... 20 12.1 Tape and Reel Information......................................24 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision D (November 2018) to Revision E (October 2021) Page • Updated the numbering format for tables, figures, and cross-references throughout the document. ................1 • Corrected grammar throughout document..........................................................................................................1 Changes from Revision C (January 2017) to Revision D (November 2018) Page • Added Tape and Reel Information.................................................................................................................... 24 2 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS82130 TPS82130 www.ti.com SLVSCY5E – FEBRUARY 2016 – REVISED OCTOBER 2021 5 Pin Configuration and Functions EN 1 VIN 2 8 SS/TR 7 PG Thermal Pad GND 3 6 FB VOUT 4 5 VOUT Not to scale Figure 5-1. 8-Pin µSiL Package (SIL0008C Top View) Table 5-1. Pin Functions PIN NAME NO. I/O DESCRIPTION Enable pin. Pull High to enable the device. Pull Low to disable the device. This pin has an internal pulldown resistor of typically 400 kΩ when the device is disabled. EN 1 I VIN 2 PWR Input pin GND 3 VOUT 4, 5 PWR Ground pin FB 6 I Feedback reference pin. An external resistor divider connected to this pin programs the output voltage. PG 7 O Power-good open-drain output pin. A pullup resistor can be connected to any voltage less than 6 V. Leave it open if it is not used. SS/TR 8 I Soft start-up and voltage tracking pin. An external capacitor connected to this pin sets the internal reference voltage rising time. Exposed Thermal Pad Output pin The exposed thermal pad must be connected to the GND pin. Must be soldered to achieve appropriate power dissipation and mechanical reliability. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS82130 3 TPS82130 www.ti.com SLVSCY5E – FEBRUARY 2016 – REVISED OCTOBER 2021 6 Specifications 6.1 Absolute Maximum Ratings Voltage at pins(1) (2) Sink current(1) Module operating MIN MAX VIN –0.3 20 EN, SS/TR –0.3 VIN + 0.3 PG, FB –0.3 7 VOUT 0 Storage temperature(1) (1) (2) V 7 PG temperature(1) UNIT 10 mA –40 125 °C –55 125 °C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground pin. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 Charged device model (CDM), per JEDEC specification JESD22C101(2) ±1000 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommend Operating Conditions Over operating free-air temperature range, unless otherwise noted. VIN Input voltage VPG Power good pull-up resistor voltage VOUT Output voltage IOUT Output current TJ Module operating temperature range for 100,000 hours lifetime(1) (1) MIN MAX UNIT 3 17 V 6 V 6 V 0.9 0 3 A –40 110 °C The module operating temperature range includes module self temperature rise and IC junction temperature rise. In applications where high power dissipation is present, the maximum operating temperature or maximum output current must be derated. For applications where the module operates continuously at 125 °C temperature, the maximum lifetime is reduced to 50,000 hours. 6.4 Thermal Information THERMAL METRIC(1) RθJA TPS82130EVM-720 UNIT 58.2 46.1 °C/W Junction-to-ambient thermal resistance RθJC(top) Junction-to-case (top) thermal resistance 9.4 9.4 °C/W RθJB Junction-to-board thermal resistance 14.4 14.4 °C/W ψJT Junction-to-top characterization parameter 0.9 0.9 °C/W ψJB Junction-to-board characterization parameter 14.2 14.0 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 21.3 21.3 °C/W (1) 4 TPS82130 (JEDEC 51-5) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Theta-JA can be improved with a custom PCB design containing thermal vias where possible. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS82130 TPS82130 www.ti.com SLVSCY5E – FEBRUARY 2016 – REVISED OCTOBER 2021 6.5 Electrical Characteristics TJ = –40°C to 125°C and VIN = 3.0 V to 17 V. Typical values are at TJ = 25°C and VIN = 12 V, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY IQ Quiescent current into VIN No load, device not switching ISD Shutdown current into VIN EN = Low VUVLO Undervoltage lockout threshold TJSD Thermal shutdown threshold VIN falling 2.6 VIN rising 2.8 20 35 µA 1.5 7.4 µA 2.7 2.8 V 2.9 3.0 V TJ rising 160 °C TJ falling 140 °C LOGIC INTERFACE (EN) VIH High-level input voltage VIL Low-level input voltage Ilkg(EN) Input leakage current into the EN pin 0.9 EN = High 0.65 V 0.45 0.3 V 0.01 1 µA 2.5 2.8 µA CONTROL (SS/TR, PG) ISS/TR VPG SS/TR pin source current Power-good threshold 2.1 VOUT rising, referenced to VOUT nominal 92% 95% 99% VOUT falling, referenced to VOUT nominal 87% 90% 94% VPG,OL Power-good low-level voltage Isink = 2 mA 0.1 0.3 V Ilkg(PG) Input leakage current into the PG pin VPG = 1.8 V 1 400 nA 785 800 815 TJ = 0°C to 85°C 788 800 812 COUT = 22 µF 785 800 823 COUT = 2 × 22 µF, TJ = 0°C to 85°C 788 800 815 1 100 OUTPUT PWM mode VFB Feedback regulation voltage PSM Ilkg(FB) Feedback input leakage current VFB = 0.8 V Line regulation IOUT = 1 A, VOUT = 1.8 V Load regulation IOUT = 0.5 A to 3 A, VOUT = 1.8 V mV nA 0.002 %/V 0.12 %/A POWER SWITCH ISW = 500 mA, VIN ≥ 6 V 90 RDS(on ISW = 500 mA, VIN = 3 V 120 ) ISW = 500 mA, VIN ≥ 6 V 40 High-side FET on-resistance Low-side FET on-resistance ISW = 500 mA, VIN = 3 V 125 100% mode, VIN = 3 V 160 Dropout resistance ILIMF High-side FET switch current limit VIN = 6 V, TA = 25°C fSW PWM switching frequency IOUT = 1 A, VOUT = 1.8 V 70 mΩ 50 100% mode, VIN ≥ 6 V RDP 170 3.6 4.2 2.0 mΩ 4.9 A MHz Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS82130 5 TPS82130 www.ti.com SLVSCY5E – FEBRUARY 2016 – REVISED OCTOBER 2021 6.6 Typical Characteristics 50 TJ = -40°C TJ = 25°C TJ = 85°C TJ = 125°C 40 $ 200 4XLHVFHQW &XUUHQW 'URSRXW 5HVLVWDQFH P 250 150 100 30 20 10 VIN = 3.0 V VIN = 6.0 V 50 -40 -20 0 20 40 60 80 Module Temperature (°C) 100 120 0 3 5 7 9 11 Input Voltage (V) D014 Figure 6-1. Dropout Resistance 13 15 17 D025 Figure 6-2. Quiescent Current 6KXWGRZQ &XUUHQW $ 8 TJ = -40°C TJ = 25°C TJ = 85°C TJ = 125°C 6 4 2 0 3 5 7 9 11 Input Voltage (V) 13 15 17 D026 Figure 6-3. Shutdown Current 6 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS82130 TPS82130 www.ti.com SLVSCY5E – FEBRUARY 2016 – REVISED OCTOBER 2021 7 Detailed Description 7.1 Overview The TPS82130 synchronous step-down converter MicroSiP power module is based on DCS-Control (Direct Control with Seamless transition into power save mode). This is an advanced regulation topology that combines the advantages of hysteretic and voltage mode control. The DCS-Control topology operates in PWM (pulse width modulation) mode for medium to heavy load conditions and in PSM (power save mode) at light load currents. In PWM mode, the converter operates with its nominal switching frequency of 2.0 MHz having a controlled frequency variation over the input voltage range. As the load current decreases, the converter enters power save mode, reducing the switching frequency and minimizing the quiescent current of the IC to achieve high efficiency over the entire load current range. DCS-Control supports both operation modes using a single building block and therefore has a seamless transition from PWM to PSM without effects on the output voltage. The TPS82130 offers excellent DC voltage regulation and load transient regulation, combined with low output voltage ripple, minimizing interference with RF circuits. 7.2 Functional Block Diagram PG VIN VFB High Side Current Sense VREF EN 400kΩ(1) Bandgap Undervoltage Lockout Thermal Shutdown L (2) MOSFET Driver Control Logic VIN Ramp Voltage Clamp SS/TR VREF Timer ton Direct Control and Compensation FB Comparator Error Amplifier DCS - Control VOUT 22pF TM VREF GND Note: (1) When the device is enabled, the 400 kΩ resistor is disconnected. (2) The integrated inductor of 1 µH in the module. Copyright © 2016, Texas Instruments Incorporated 7.3 Feature Description 7.3.1 PWM and PSM Operation The TPS82130 includes an on-time (tON) circuitry. tON, in steady-state operation in PWM and PSM modes, is estimated as: t ON = 500ns ´ VOUT VIN (1) In PWM mode, the TPS82130 operates with pulse width modulation in continuous conduction mode (CCM) with a tON shown in Equation 1 at medium and heavy load currents. A PWM switching frequency of typically 2.0 MHz Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS82130 7 TPS82130 www.ti.com SLVSCY5E – FEBRUARY 2016 – REVISED OCTOBER 2021 is achieved by this tON circuitry. The device operates in PWM mode as long as the output current is higher than half of the ripple current of the inductor estimated by Equation 2. DIL = t ON ´ VIN - VOUT L (2) To maintain high efficiency at light loads, the device enters power save mode seamlessly when the load current decreases. This happens when the load current becomes smaller than half of the ripple current of the inductor. In PSM, the converter operates with reduced switching frequency and with a minimum quiescent current to maintain high efficiency. PSM is also based on the tON circuitry. The switching frequency in PSM is estimated as: fPSM = 2 ´ IOUT V - VOUT V t ON2 ´ IN ´ IN VOUT L (3) In PSM, the output voltage rises slightly above the nominal output voltage in PWM mode. This effect is reduced by increasing the output capacitance. The output voltage accuracy in PSM operation is reflected in Section 6.5 and given for a 22-µF output capacitor. For very small output voltages, an absolute minimum on time of approximately 80 ns is kept to limit switching losses. The operating frequency is thereby reduced from its nominal value, which keeps efficiency high. Also, the off time can reach its minimum value at high duty cycles. The output voltage remains regulated in such cases. When VIN decreases to typically 15% above VOUT, the TPS82130 cannot enter power save mode, regardless of the load current. The device maintains output regulation in PWM mode. 7.3.2 Low Dropout Operation (100% Duty Cycle) The TPS82130 offers a low input to output voltage differential by entering 100% duty cycle mode. In this mode, the high-side MOSFET switch is constantly turned on. This is particularly useful in battery powered applications to achieve the longest operation time by taking full advantage of the whole battery voltage range. The minimum input voltage to maintain a minimum output voltage is given by: VIN(min) = VOUT(min) + IOUT ´ RDP (4) where • • RDP = Resistance from VIN to VOUT, including high-side FET on-resistance and DC resistance of the inductor VOUT(min) = Minimum output voltage the load can accept 7.3.3 Switch Current Limit The switch current limit prevents the device from high inductor current and from drawing excessive current from the battery or input voltage rail. Excessive current can occur with a heavy load/shorted output circuit condition. If the inductor peak current reaches the switch current limit after a propagation delay of typically 30 ns, the high-side FET is turned off and the low-side FET is turned on to ramp down the inductor current. 7.3.4 Undervoltage Lockout To avoid mis-operation of the device at low input voltages, an undervoltage lockout is implemented, which shuts down the device at voltages lower than VUVLO with a hysteresis of 200 mV. 7.3.5 Thermal Shutdown The device goes into thermal shutdown and stops switching once the junction temperature exceeds TJSD. Once the device temperature falls below the threshold by 20°C, the device returns to normal operation automatically. 8 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS82130 TPS82130 www.ti.com SLVSCY5E – FEBRUARY 2016 – REVISED OCTOBER 2021 7.4 Device Functional Modes 7.4.1 Enable and Disable (EN) The device is enabled by setting the EN pin to a logic High. Accordingly, shutdown mode is forced if the EN pin is pulled Low with a shutdown current of typically 1.5 μA. An internal 400-kΩ pulldown resistor is connected to the EN pin when the EN pin is Low. The pulldown resistor is disconnected when the EN pin is High. 7.4.2 Soft Start-Up (SS/TR) The internal voltage clamp controls the output voltage slope during start-up. This avoids excessive inrush current and ensures a controlled output voltage rise time. When the EN pin is pulled high, the device starts switching after a delay of typically 55 μs and the output voltage rises with a slope controlled by an external capacitor connected to the SS/TR pin. Using a very small capacitor or leaving the SS/TR pin floating provides the fastest start-up time. The TPS82130 is able to start into a pre-biased output capacitor. During the pre-biased start-up, both the power MOSFETs are not allowed to turn on until the internal voltage clamp sets an output voltage above the pre-bias voltage. When the device is in shutdown, undervoltage lockout, or thermal shutdown, the capacitor connected to the SS/TR pin is discharged by an internal resistor. Returning from those states causes a new start-up sequence. 7.4.3 Voltage Tracking (SS/TR) The SS/TR pin is externally driven by another voltage source to achieve output voltage tracking. The application circuit is shown in Figure 7-1. VOUT1 VOUT2 TPS82130 R3 R1 SS/TR R2 FB R4 Copyright © 2016, Texas Instruments Incorporated Figure 7-1. Output Voltage Tracking When the SS/TR pin voltage is between 50 mV and 1.2 V, the VOUT2 tracks the VOUT1 as described in Equation 5. VOUT 2 R2 R3 + R4 » 0.64 ´ ´ R1 + R2 R4 VOUT1 (5) When the SS/TR pin voltage is above 1.2 V, the voltage tracking is disabled and the FB pin voltage is regulated at 0.8 V. To decrease the SS/TR pin voltage, the device does not sink current from the output, so the resulting decreases of the output voltage can be slower than the SS/TR pin voltage if the load is light. When driving the SS/TR pin with an external voltage, do not exceed the voltage rating of the SS/TR pin which is VIN + 0.3 V. Details about tracking and sequencing circuits are found in the Sequencing and Tracking With the TPS621Family and TPS821-Family Application Report. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS82130 9 TPS82130 www.ti.com SLVSCY5E – FEBRUARY 2016 – REVISED OCTOBER 2021 7.4.4 Power-Good Output (PG) The device has a power-good (PG) output. The PG pin goes high impedance once the output is above 95% of the nominal voltage, and is driven low once the output voltage falls below typically 90% of the nominal voltage. The PG pin is an open-drain output and is specified to sink up to 2 mA. The power good output requires a pullup resistor connecting to any voltage rail less than 6 V. The PG signal can be used for sequencing of multiple rails by connecting it to the EN pin of other converters. Leave the PG pin floating when it is not used. Table 7-1 shows the PG pin logic. Table 7-1. Power Good Pin Logic PG LOGIC STATUS DEVICE STATE Enable (EN=High) HIGH IMPEDANCE VFB ≥ VTH_PG VFB ≤ VTH_PG √ Shutdown (EN = Low) UVLO Thermal Shutdown Power Supply Removal 10 LOW √ √ 0.7 V < VIN < VUVLO √ TJ > TSD √ VIN < 0.7 V Submit Document Feedback √ Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS82130 TPS82130 www.ti.com SLVSCY5E – FEBRUARY 2016 – REVISED OCTOBER 2021 8 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. 8.1 Application Information The output voltage of the TPS82130 is adjusted by component selection. The following section discusses the design of the external components to complete the power supply design for several input and output voltage options by using typical applications as a reference. 8.2 Typical Applications 8.2.1 1.8-V Output Application TPS82130 VIN 12 V VIN C1 10µF VOUT EN SS/TR C3 3.3nF GND R1 124kΩ FB PG R3 100kΩ C2 22µF VOUT 1.8 V/3 A R2 100kΩ POWER GOOD Copyright © 2016, Texas Instruments Incorporated Figure 8-1. 1.8-V Output Application 8.2.1.1 Design Requirements For this design example, use the following as the input parameters. Table 8-1. Design Parameters DESIGN PARAMETER EXAMPLE VALUE Input voltage range 12 V Output voltage 1.8 V Output ripple voltage < 20 mV Output current rating 3A The components used for measurements are given in the following table. Table 8-2. List of Components REFERENCE DESCRIPTION MANUFACTURER C1 10 µF, 25 V, X7R, ±20%, size 1206, C3216X7R1E106M160AE TDK C2 22 µF, 10 V, ±20%, X7S, size 0805, C2012X7S1A226M125AC TDK C3 3300 pF, 50 V, ±5%, C0G/NP0, size 0603, GRM1885C1H332JA01D R1, R2, R3 Standard Murata Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS82130 11 TPS82130 www.ti.com SLVSCY5E – FEBRUARY 2016 – REVISED OCTOBER 2021 8.2.1.2 Detailed Design Procedure 8.2.1.2.1 Custom Design with WEBENCH® Tools Click here to create a custom design using the TPS82130 device with the WEBENCH® Power Designer. 1. Start by entering your VIN, VOUT, and IOUT requirements. 2. Optimize your design for key parameters like efficiency, footprint and cost using the optimizer dial and compare this design with other possible solutions from Texas Instruments. 3. The WEBENCH Power Designer provides you with a customized schematic along with a list of materials with real time pricing and component availability. 4. In most cases, you will also be able to: • Run electrical simulations to see important waveforms and circuit performance • Run thermal simulations to understand the thermal performance of your board • Export your customized schematic and layout into popular CAD formats • Print PDF reports for the design, and share your design with colleagues 5. Get more information about WEBENCH tools at www.ti.com/WEBENCH. 8.2.1.2.2 Setting the Output Voltage The output voltage is set by an external resistor divider according to Equation 6: R1 ö R1 ö æ æ VOUT = VFB ´ ç 1 + = 0.8 V ´ ç 1 + ÷ R2 ø R2 ÷ø è è (6) R2 should not be higher than 100 kΩ to achieve high efficiency at light load while providing acceptable noise sensitivity. Larger currents through R2 improve noise sensitivity and output voltage accuracy. Figure 8-1 shows the external resistor divider value for a 1.8-V output. Choose appropriate resistor values for other outputs. In case the FB pin gets opened, the device clamps the output voltage at the VOUT pin internally to approximately 7 V. 8.2.1.2.3 Input and Output Capacitor Selection For the best output and input voltage filtering, low-ESR ceramic capacitors are required. The input capacitor minimizes input voltage ripple, suppresses input voltage spikes, and provides a stable system rail for the device. A 10-µF or larger input capacitor is required. The output capacitor value can range from 22 μF up to more than 400 μF. Higher values are possible as well and can be evaluated through the transient response. Larger soft start times are recommended for higher output capacitances. High capacitance ceramic capacitors have a DC bias effect, which will have a strong influence on the final effective capacitance. Therefore the right capacitor value has to be chosen carefully. Package size and voltage rating in combination with dielectric material are responsible for differences between the rated capacitor value and the effective capacitance. 8.2.1.2.4 Soft Start-Up Capacitor Selection A capacitance connected between the SS/TR pin and the GND allows programming the start-up slope of the output voltage. A constant current of 2.5 μA charges the external capacitor. The capacitance required for a given soft start-up time for the output voltage is given by: CSS / TR = t SS / TR ´ 12 ISS / TR 1.25 V (7) Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS82130 TPS82130 www.ti.com SLVSCY5E – FEBRUARY 2016 – REVISED OCTOBER 2021 8.2.1.3 Application Performance Curves 100 100 90 90 Efficiency (%) Efficiency (%) TA = 25°C, VIN = 12 V, VOUT = 1.8 V, unless otherwise noted. 80 70 60 10m 100m Load (A) 1 70 60 VIN = 3.3 V VIN = 5.0 V VIN = 12 V 50 1m 80 IOUT = 0.1 A IOUT = 1.0 A IOUT = 3.0 A 50 3 5 100 90 90 Efficiency (%) Efficiency (%) 100 80 70 50 1m 13 15 17 D019 70 60 VIN = 3.3 V VIN = 5.0 V VIN = 12 V IOUT = 0.1 A IOUT = 1.0 A IOUT = 3.0 A 50 10m 100m Load (A) 1 3 5 7 9 11 Input Voltage (V) 13 15 17 D020 Figure 8-5. Efficiency, VOUT = 1.8 V 100 100 90 90 80 70 60 5 D002 Efficiency (%) Efficiency (%) 9 11 Input Voltage (V) 80 Figure 8-4. Efficiency, VOUT = 1.8 V 50 1m 7 Figure 8-3. Efficiency, VOUT = 1.0 V Figure 8-2. Efficiency, VOUT = 1 V 60 5 D001 80 70 60 VIN = 3.3 V VIN = 5.0 V VIN = 12 V IOUT = 0.1 A IOUT = 1.0 A IOUT = 3.0 A 50 10m 100m Load (A) 1 5 3 5 D003 Figure 8-6. Efficiency, VOUT = 2.5 V 7 9 11 Input Voltage (V) 13 15 17 D021 Figure 8-7. Efficiency, VOUT = 2.5 V Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS82130 13 TPS82130 www.ti.com 100 100 90 90 Efficiency (%) Efficiency (%) SLVSCY5E – FEBRUARY 2016 – REVISED OCTOBER 2021 80 70 80 70 60 60 IOUT = 0.1 A IOUT = 1.0 A IOUT = 3.0 A VIN = 5.0 V VIN = 12 V 50 50 1m 10m 100m Load (A) 1 5 5 Figure 8-8. Efficiency, VOUT = 3.3 V 100 100 90 90 80 70 17 D022 IOUT = 0.1 A IOUT = 1.0 A IOUT = 3.0 A 50 10m 100m Load (A) 1 6 5 7 8 9 D023 10 11 12 13 Input Voltage (V) 14 15 16 17 D024 Figure 8-11. Efficiency, VOUT = 5 V Figure 8-10. Efficiency, VOUT = 5.0 V 4 4 3 3 Output Current (A) Output Current (A) 15 70 VIN = 12 V 50 1m 2 1 2 1 VIN = 3.3 V VIN = 5.0 V VIN = 12 V 55 65 VIN = 5.0 V VIN = 12 V 75 85 95 105 Ambient Temperature (°C) VOUT = 1.8 V 115 125 0 45 55 D015 θJA = 46.1°C/W Figure 8-12. Thermal Derating, VOUT = 1.8 V 14 11 13 Input Voltage (V) 80 60 60 0 45 9 Figure 8-9. Efficiency, VOUT = 3.3 V Efficiency (%) Efficiency (%) 7 D004 65 75 85 95 105 Ambient Temperature (°C) VOUT = 3.3 V 115 125 D016 θJA = 46.1°C/W Figure 8-13. Thermal Derating, VOUT = 3.3 V Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS82130 TPS82130 www.ti.com SLVSCY5E – FEBRUARY 2016 – REVISED OCTOBER 2021 4 Output Voltage Accuracy (%) 1.0 Output Current (A) 3 2 1 VIN = 3.3 V VIN = 5.0 V VIN = 12 V 0 45 55 65 75 85 95 105 Ambient Temperature (°C) 115 0.5 0.0 -0.5 TA = -40°C TA = 25°C TA = 85°C -1.0 1m 125 10m D027 100m Load (A) 1 5 D005 VIN = 12 V Figure 8-14. Thermal Derating, VOUT = 1.0 V Figure 8-15. Load Regulation 5x106 Switching Frequency (Hz) Output Voltage Accuracy (%) 1.0 0.5 0.0 -0.5 TA = -40°C TA = 25°C TA = 85°C -1.0 3 5 7 9 11 Input Voltage (V) 13 15 17 106 105 104 TA = 25°C TA = -40°C TA = 85°C 103 1m 10m 100m Load (A) 1 D009 D006 VOUT = 1.8 V IOUT = 1 A 5 VIN = 12 V Figure 8-17. Switching Frequency Figure 8-16. Line Regulation Switching Frequency (Hz) 3x106 VIN 50mV/DIV AC 2x106 VOUT 10mV/DIV AC 1x106 VOUT = 1.0 V VOUT = 1.8 V VOUT = 2.5 V VOUT = 3.3 V 0x100 3 5 7 9 11 Input Voltage (V) 13 15 Time - 500ns/DIV 17 D007 D018 IOUT = 3 A IOUT = 1 A Figure 8-18. Switching Frequency Figure 8-19. Input and Output Ripple in PWM Mode Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS82130 15 TPS82130 www.ti.com SLVSCY5E – FEBRUARY 2016 – REVISED OCTOBER 2021 VIN 20mV/DIV AC IOUT 2A/DIV VOUT 50mV/DIV AC VOUT 10mV/DIV AC 7LPH V ',9 7LPH V ',9 D008 D010 No Load IOUT = 0 A to 3 A, 1 A/µs Figure 8-20. Input and Output Ripple in PSM Mode Figure 8-21. Load Transient VEN 5V/DIV IOUT 2A/DIV VPG 5V/DIV VOUT 50mV/DIV AC VOUT 1V/DIV IOUT 2A/DIV 7LPH V ',9 7LPH V ',9 D011 D012 IOUT = 0.5 A to 3 A, 1 A/µs No Load Figure 8-22. Load Transient Figure 8-23. Startup without Load VEN 5V/DIV VPG 5V/DIV VOUT 1V/DIV IOUT 2A/DIV 7LPH V ',9 D013 ROUT = 0.68Ω Figure 8-24. Startup / Shutdown with Resistance Load 16 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS82130 TPS82130 www.ti.com SLVSCY5E – FEBRUARY 2016 – REVISED OCTOBER 2021 9 Power Supply Recommendations The devices are designed to operate from an input voltage supply range between 3 V and 17 V. The average input current of the TPS82130 is calculated as: IIN = 1 VOUT ´ IOUT ´ h VIN (8) Ensure that the power supply has a sufficient current rating for the applications. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS82130 17 TPS82130 www.ti.com SLVSCY5E – FEBRUARY 2016 – REVISED OCTOBER 2021 10 Layout 10.1 Layout Guidelines • • • • TI recommends placing all components as close as possible to the IC. The input capacitor placement specifically must be closest to the VIN and GND pins of the device. Use wide and short traces for the main current paths to reduce the parasitic inductance and resistance. To enhance heat dissipation of the device, the exposed thermal pad should be connected to bottom or internal layer ground planes using vias. Refer to Figure 10-1 for an example of component placement, routing, and thermal design. 10.2 Layout Example C3 VIN C1 R2 EN SS/TR VIN PG GND FB VOUT VOUT R1 VOUT GND C2 Figure 10-1. TPS82130 PCB Layout 10.3 Thermal Consideration The output current of the TPS82130 needs to be derated when the device operates in a high ambient temperature or delivers high output power. The amount of current derating is dependent upon the input voltage, output power, PCB layout design, and environmental thermal condition. Care should especially be taken in applications where the localized PCB temperature exceeds 65°C. The TPS82130 module temperature must be kept less than the maximum rating of 125°C. Three basic approaches for enhancing thermal performance are below: • • • Improve the power dissipation capability of the PCB design. Improve the thermal coupling of the TPS82130 to the PCB. Introduce airflow into the system. To estimate approximate module temperature of TPS82130, apply the typical efficiency stated in this data sheet to the desired application condition to find the power dissipation of the module. Then, calculate the module temperature rise by multiplying the power dissipation by its thermal resistance. For more details on how to use the thermal parameters in real applications, see the Thermal Characteristics of Linear and Logic Packages Using JEDEC PCB Designs Application Report and Semiconductor and IC Package Thermal Metrics Application Report. 18 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS82130 TPS82130 www.ti.com SLVSCY5E – FEBRUARY 2016 – REVISED OCTOBER 2021 11 Device and Documentation Support 11.1 Device Support 11.1.1 Development Support 11.1.1.1 Third-Party Products Disclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE. 11.1.1.2 Custom Design with WEBENCH® Tools Click here to create a custom design using the TPS82130 device with the WEBENCH® Power Designer. 1. Start by entering your VIN, VOUT, and IOUT requirements. 2. Optimize your design for key parameters like efficiency, footprint and cost using the optimizer dial and compare this design with other possible solutions from Texas Instruments. 3. The WEBENCH Power Designer provides you with a customized schematic along with a list of materials with real time pricing and component availability. 4. In most cases, you will also be able to: • Run electrical simulations to see important waveforms and circuit performance • Run thermal simulations to understand the thermal performance of your board • Export your customized schematic and layout into popular CAD formats • Print PDF reports for the design, and share your design with colleagues 5. Get more information about WEBENCH tools at www.ti.com/WEBENCH. 11.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 11.3 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 11.4 Trademarks MicroSiP™ is a trademark of TI. DCS-Control™, and TI E2E™ are trademarks of Texas Instruments. WEBENCH® are registered trademarks of Texas Instruments. All trademarks are the property of their respective owners. 11.5 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 11.6 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS82130 19 TPS82130 www.ti.com SLVSCY5E – FEBRUARY 2016 – REVISED OCTOBER 2021 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 20 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS82130 TPS82130 www.ti.com SLVSCY5E – FEBRUARY 2016 – REVISED OCTOBER 2021 PACKAGE OUTLINE SIL0008D MicroSiP TM - 1.53 mm max height SCALE 4.000 MICRO SYSTEM IN PACKAGE 2.9 2.7 B A PIN 1 INDEX AREA (2.5) 3.1 2.9 PICK AREA NOTE 3 (2) 1.53 MAX C 0.08 C 1.1±0.1 EXPOSED THERMAL PAD SYMM (0.1) TYP 5 4 SYMM 2X 1.9±0.1 1.95 1 8 6X 0.65 (45 X0.25) PIN 1 ID 8X 0.52 0.48 8X 0.42 0.38 0.1 0.05 C A C B 4221520/A 07/2015 MicroSiP is a trademark of Texas Instruments NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Pick and place nozzle 1.3 mm or smaller recommended. 4. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. www.ti.com Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS82130 21 TPS82130 www.ti.com SLVSCY5E – FEBRUARY 2016 – REVISED OCTOBER 2021 EXAMPLE BOARD LAYOUT SIL0008D MicroSiP TM - 1.53 mm max height MICRO SYSTEM IN PACKAGE (1.1) 8X (0.5) 8 1 8X (0.4) SYMM (1.9) (0.75) 6X (0.65) 5 4 SYMM ( 0.2) VIA TYP (2.1) LAND PATTERN EXAMPLE SOLDER MASK DEFINED SCALE:20X 0.05 MIN ALL SIDES SOLDER MASK OPENING METAL UNDER SOLDER MASK (R0.05) TYP DETAIL NOT TO SCALE 4221520/A 07/2015 NOTES: (continued) 5. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). www.ti.com 22 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS82130 TPS82130 www.ti.com SLVSCY5E – FEBRUARY 2016 – REVISED OCTOBER 2021 EXAMPLE STENCIL DESIGN SIL0008D MicroSiP TM - 1.53 mm max height MICRO SYSTEM IN PACKAGE SOLDER MASK EDGE 8X (0.5) 1 (R0.05) TYP (1.04) 8 8X (0.4) METAL TYP (0.85) SYMM (1.05) 6X (0.65) 5 4 SYMM (2.1) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 85% PRINTED SOLDER COVERAGE BY AREA SCALE:30X 4221520/A 07/2015 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.com Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS82130 23 TPS82130 www.ti.com SLVSCY5E – FEBRUARY 2016 – REVISED OCTOBER 2021 12.1 Tape and Reel Information REEL DIMENSIONS TAPE DIMENSIONS K0 P1 B0 W Reel Diameter Cavity A0 B0 K0 W P1 A0 Dimension designed to accommodate the component width Dimension designed to accommodate the component length Dimension designed to accommodate the component thickness Overall width of the carrier tape Pitch between successive cavity centers Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Sprocket Holes Q1 Q2 Q1 Q2 Q3 Q4 Q3 Q4 User Direction of Feed Pocket Quadrants 24 Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant TPS82130SILR uSiP SIL 8 3000 330.0 12.4 3.05 3.25 1.68 8.0 12.0 Q1 TPS82130SILT uSiP SIL 8 250 178.0 13.2 3.05 3.25 1.68 8.0 12.0 Q1 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS82130 TPS82130 www.ti.com SLVSCY5E – FEBRUARY 2016 – REVISED OCTOBER 2021 TAPE AND REEL BOX DIMENSIONS Width (mm) W L H Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS82130SILR uSiP SIL 8 3000 383.0 353.0 58.0 TPS82130SILT uSiP SIL 8 250 223.0 194.0 35.0 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS82130 25 PACKAGE OPTION ADDENDUM www.ti.com 13-Oct-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TPS82130SILR ACTIVE uSiP SIL 8 3000 RoHS & Green NIAU Level-2-260C-1 YEAR -40 to 125 H6 TPS82130SILT ACTIVE uSiP SIL 8 250 RoHS & Green NIAU Level-2-260C-1 YEAR -40 to 125 H6 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of