TPS84410
www.ti.com
SLVSAR5A – SEPTEMBER 2011 – REVISED MARCH 2012
2.95-V to 6-V Input, 4-A Synchronous Buck, Integrated Power Solution
Check for Samples: TPS84410
FEATURES
DESCRIPTION
•
The TPS84410RKG is an easy-to-use integrated
power solution that combines a 4-A DC/DC converter
with power MOSFETs, an inductor, and passives into
a low profile, BQFN package. This total power
solution requires as few as 3 external components
and eliminates the loop compensation and magnetics
part selection process.
1
2
•
•
•
•
•
•
•
•
•
•
•
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•
Complete Integrated Power Solution Allows
Small Footprint, Low-Profile Design
Efficiencies Up To 96%
Wide-Output Voltage Adjust
0.8 V to 3.6 V, with ±1% Reference Accuracy
Adjustable Switching Frequency
(500 kHz to 2 MHz)
Synchronizes to an External Clock
Adjustable Slow-Start
Output Voltage Sequencing / Tracking
Power Good Output
Programmable Undervoltage Lockout (UVLO)
Output Overcurrent Protection
Over Temperature Protection
Operating Temperature Range: –40°C to 85°C
Enhanced Thermal Performance: 12°C/W
Meets EN55022 Class B Emissions
For Design Help Including SwitcherPro™ visit
http://www.ti.com/TPS84410
APPLICATIONS
•
•
•
•
•
The 9×11×2.8 mm BQFN package is easy to solder
onto a printed circuit board and allows a compact
point-of-load design with greater than 90% efficiency
and excellent power dissipation with a thermal
impedance of 12°C/W junction to ambient. The
device delivers the full 4-A rated output current at
85°C ambient temperature without airflow.
The TPS84410 offers the flexibility and the featureset of a discrete point-of-load design and is ideal for
powering performance DSPs and FPGAs. Advanced
packaging technology afford a robust and reliable
power solution compatible with standard QFN
mounting and testing techniques.
SIMPLIFIED APPLICATION
TPS84410
Broadband & Communications Infrastructure
Automated Test and Medical Equipment
Compact PCI / PCI Express / PXI Express
DSP and FPGA Point of Load Applications
High Density Distributed Power Systems
VIN
VIN
PWRGD
VOUT
CIN
VOUT
COUT
SENSE+
RT/CLK
Efficiency (%)
100
95
INH/UVLO
90
SS/TR
VADJ
85
STSEL
80
75
PGND AGND
RSET
70
65
60
VIN = 5 V, VOUT = 3.3 V, fSW = 1 MHz
VIN = 3.3 V, VOUT = 1.8 V, fSW = 1 MHz
55
50
0
1
2
Output Current (A)
3
4
G000
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SwitcherPro is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011–2012, Texas Instruments Incorporated
TPS84410
SLVSAR5A – SEPTEMBER 2011 – REVISED MARCH 2012
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION (1)
(1)
TA
PACKAGE
-40°C to 85°C
Plastic Quad Flat
Pack (BQFN)
ORDERABLE
NUMBER
PINS
TPS84410RKGR
TRANSPORT
MEDIA
Tape and Reel
39
TPS84410RKGT
Tape and Reel
MINIMUM
QUANTITY
ECO PLAN
500
Green (RoHS and
no Sb/Br)
250
Green (RoHS and
no Sb/Br)
For the most current package and ordering information, see the Package Option Addendum at the end of this datasheet, or see the TI
website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1) over operating temperature range (unless otherwise noted)
VALUE
Input Voltage
MAX
VIN, PWRGD
–0.3
7
V
INH/UVLO, RT/CLK
–0.3
3.3
V
SS/TR, STSEL, VADJ
–0.3
3
V
SENSE+
-0.3
VOUT
V
–0.6
7
V
VADJ rating must also be met
PH
Output Voltage
PH 10ns Transient
VOUT
VDIFF (GND to exposed thermal pad)
–2
7
V
-0.6
VIN
V
–0.2
0.2
V
RT/CLK, INH/UVLO
Source Current
Sink Current
UNIT
MIN
±100
µA
PH
Current Limit
A
PH
Current Limit
A
SS/TR
PWRGD
±100
µA
10
mA
Operating Junction Temperature
–40
125 (2)
°C
Storage Temperature
–65
150
°C
Mechanical Shock
Mil-STD-883D, Method 2002.3, 1 msec, 1/2 sine, mounted
Mechanical Vibration
Mil-STD-883D, Method 2007.2, 20-2000Hz
(1)
(2)
2
1500
20
G
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
See the temperature derating curves in the Typical Characteristics section for thermal information.
Copyright © 2011–2012, Texas Instruments Incorporated
TPS84410
www.ti.com
SLVSAR5A – SEPTEMBER 2011 – REVISED MARCH 2012
THERMAL INFORMATION
TPS84410
THERMAL METRIC (1)
RKG39
UNIT
39 PINS
θJA
Junction-to-ambient thermal resistance (2)
12
(3)
ψJT
Junction-to-top characterization parameter
ψJB
Junction-to-board characterization parameter (4)
(1)
(2)
(3)
(4)
2.2
°C/W
9.7
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The junction-to-ambient thermal resistance, θJA, applies to devices soldered directly to a 100 mm x 100 mm double-sided PCB with
1 oz. copper and natural convection cooling. Additional airflow reduces θJA.
The junction-to-top characterization parameter, ψJT, estimates the junction temperature, TJ, of a device in a real system, using a
procedure described in JESD51-2A (sections 6 and 7). TJ = ψJT * Pdis + TT; where Pdis is the power dissipated in the device and TT is
the temperature of the top of the device.
The junction-to-board characterization parameter, ψJB, estimates the junction temperature, TJ, of a device in a real system, using a
procedure described in JESD51-2A (sections 6 and 7). TJ = ψJB * Pdis + TB; where Pdis is the power dissipated in the device and TB is
the temperature of the board 1mm from the device.
PACKAGE SPECIFICATIONS
TPS84410
Weight
Flammability
MTBF Calculated reliability
UNIT
0.85 grams
Meets UL 94 V-O
Per Bellcore TR-332, 50% stress, TA = 40°C, ground benign
Copyright © 2011–2012, Texas Instruments Incorporated
32.8 MHrs
3
TPS84410
SLVSAR5A – SEPTEMBER 2011 – REVISED MARCH 2012
www.ti.com
ELECTRICAL CHARACTERISTICS
Over -40°C to 85°C free-air temperature, VIN = 3.3 V, VOUT = 1.8 V, IOUT = 4A,
CIN1 = 47 µF ceramic, CIN2 = 220 µF poly-tantalum, COUT1 = 47 µF ceramic, COUT2 = 100 µF poly-tantalum (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
IOUT
Output current
TA = 85°C, natural convection
VIN
Input voltage range
Over IOUT range
UVLO
VIN Undervoltage lockout
VOUT(adj)
VOUT
Over IOUT range
0.8
TA = 25°C, IOUT = 0A
Temperature variation
-40°C ≤ TA ≤ +85°C, IOUT = 0A
±0.3%
Line regulation
Over VIN range, TA = 25°C, IOUT = 0A
±0.1%
Load regulation
Over IOUT range, TA = 25°C
±0.1%
Total output voltage variation
Includes set-point, line, load, and temperature variation
VINH-L
II(stby)
Inhibit Control
Input standby current
95%
93%
VOUT = 1.8V, fSW = 1 MHz
91%
VOUT = 1.5V, fSW = 1 MHz
89%
VOUT = 1.2V, fSW =750 kHz
87%
VOUT = 1.0V, fSW = 650 kHz
85%
VOUT = 0.8V, fSW = 650 kHz
84%
VOUT = 1.8V, fSW = 1 MHz
90%
VOUT = 1.5V, fSW = 1 MHz
88%
VOUT = 1.2V, fSW = 750 kHz
87%
VOUT = 1.0V, fSW = 650 kHz
84%
VOUT = 0.8V, fSW = 650 kHz
82%
1.0 A/µs load step from 1A to 3A
PWRGD Low Voltage
I(PWRGD) = 0.33 mA
fSW
Switching frequency
Over VIN and IOUT ranges, RT/CLK pin OPEN
fCLK
Synchronization frequency
VCLK-H
CLK High-Level Threshold
VCLK-L
CLK Low-Level Threshold
CLK Control
Thermal Shutdown
(4)
4
Thermal shutdown
Thermal shutdown hysteresis
(2)
mVPP
A
80
µs
VOUT
over/undershoot
90
1.25
–0.3
mV
Open
(3)
1.0
70
Good
93%
Fault
107%
Fault
91%
Good
105%
100
V
µA
0.3
V
600
kHz
500
2000
kHz
2.2
3.3
-0.3
0.4
400
500
75 (4)
CLK_PW CLK Pulse Width
±1.5%
V
Recovery time
INH pin to AGND
VOUT falling
(2)
V
7
Inhibit Low Voltage
PWRGD Thresholds
±1.0%
9
Inhibit High Voltage
VOUT rising
Power
Good
3.6
VOUT = 2.5V, fSW = 1 MHz
20 MHz bandwith
3.135
2.75
VOUT = 3.3V, fSW = 1 MHz
Overcurrent threshold
VINH-H
(3)
V
3.05
Set-point voltage tolerance
Transient response
(1)
(2)
A
6
Output voltage adjust range
Output voltage ripple
UNIT
4
2.5
VIN = 3.3V
IO = 2 A
MAX
0
VIN = decreasing
Efficiency
ILIM
TYP
2.95 (1)
VIN = increasing
VIN = 5 V
IO = 2 A
η
MIN
V
V
ns
175
°C
15
°C
The minimum VIN depends on VOUT and the switching frequency. Please refer to Table 7 for operating limits.
The stated limit of the set-point voltage tolerance includes the tolerance of both the internal voltage reference and the internal
adjustment resistor. The overall output voltage tolerance will be affected by the tolerance of the external RSET resistor.
This control pin has an internal pullup. Do not place an external pull-up resistor on this pin. If this pin is left open circuit, the device
operates when input power is applied. A small low-leakage MOSFET is recommended for control. See the application section for further
guidance.
The maximum synchronization clock pulse width is dependant on VIN, VOUT, and the synchronization frequency. See the
Synchronization (CLK) section for more information.
Copyright © 2011–2012, Texas Instruments Incorporated
TPS84410
www.ti.com
SLVSAR5A – SEPTEMBER 2011 – REVISED MARCH 2012
ELECTRICAL CHARACTERISTICS (continued)
Over -40°C to 85°C free-air temperature, VIN = 3.3 V, VOUT = 1.8 V, IOUT = 4A,
CIN1 = 47 µF ceramic, CIN2 = 220 µF poly-tantalum, COUT1 = 47 µF ceramic, COUT2 = 100 µF poly-tantalum (unless otherwise
noted)
PARAMETER
CIN
TEST CONDITIONS
MIN
Ceramic
External input capacitance
External output capacitance
47
Non-ceramic
(6)
(6)
(7)
UNIT
µF
150
650 (7)
(6)
2000 (7)
100
Equivalent series resistance (ESR)
(5)
MAX
220 (5)
Non-ceramic
Ceramic
COUT
47
TYP
(5)
25
µF
mΩ
A minimum of 47µF of ceramic capacitance is required across the input for proper operation. Locate the capacitor close to the device.
An additional 220µF of bulk capacitance is recommended. See Table 5 for more details.
The amount of required output capacitance varies depending on the output voltage (see Table 3 ). The amount of required capacitance
must include at least 47µF of ceramic capacitance. Locate the capacitance close to the device. Adding additional capacitance close to
the load improves the response of the regulator to load transients. See Table 3 and Table 5 for more details.
When using both ceramic and non-ceramic output capacitance, the combined maximum must not exceed 2200µF.
DEVICE INFORMATION
FUNCTIONAL BLOCK DIAGRAM
Thermal Shutdown
PWRGD
PWRGD
Logic
INH/UVLO
Shutdown
Logic
VIN
UVLO
VSENSE+
VIN
VADJ
PH
+
+
SS/TR
VREF
Power
Stage
and
Control
Logic
Comp
STSEL
VOUT
RT/CLK
PGND
OSC w/PLL
OCP
AGND
TPS84410
Copyright © 2011–2012, Texas Instruments Incorporated
5
TPS84410
SLVSAR5A – SEPTEMBER 2011 – REVISED MARCH 2012
www.ti.com
PIN DESCRIPTIONS
TERMINAL
NAME
NO.
DESCRIPTION
1
5
AGND
29
33
Zero VDC reference for the analog control circuitry. These pins should be connected directly to the PCB
analog ground plane. Not all pins are connected together internally. All pins must be connected together
externally with a copper plane or pour directly under the module. Connect the AGND copper area to the
PGND copper area at a single point; directly at the pin 37 PowerPAD using multiple vias. See the
recommended layout in Figure 34.
34
PowerPAD
(PGND)
37
This pad provides both an electrical and thermal connection to the PCB. This pad should be connected
directly to the PCB power ground plane using multiple vias for good electrical and thermal performance. The
same vias should also be used to connect to the PCB analog ground plane. See the recommended layout in
Figure 34.
2
3
DNC
15
Do not connect. Do not connect these pins to AGND, to another DNC pin, or to any other voltage. These
pins are connected to internal circuitry. Each pin must be soldered to an isolated pad.
16
26
INH/UVLO
28
Inhibit and UVLO adjust pin. Use an open drain or open collector output logic to control the INH function. A
resistor between this pin and AGND adjusts the UVLO voltage.
17
18
19
20
PH
21
22
Phase switch node. These pins should be connected by a small copper island under the device for thermal
relief. Do not connect any external component to this pin or tie it to a pin of another function.
23
24
25
39
PWRGD
27
Power good fault pin. Asserts low if the output voltage is out of tolerance. A pull-up resistor is required.
RT/CLK
4
This pin automatically selects between RT mode and CLK mode. An external timing resistor adjusts the
switching frequency of the device. In CLK mode, the device synchronizes to an external clock.
SENSE+
36
Remote sense connection. Connect this pin to VOUT at the load for improved regulation. This pin must be
connected to VOUT at the load, or at the module pins.
SS/TR
6
Slow-start and tracking pin. Connecting an external capacitor to this pin adjusts the output voltage rise time.
A voltage applied to this pin allows for tracking and sequencing control.
STSEL
7
Slow-start or track feature select. Connect this pin to AGND to enable the internal SS capacitor with a SS
interval of approximately 1.1 ms. Leave this pin open to enable the TR feature.
VADJ
35
Connecting a resistor between this pin and AGND sets the output voltage above the 0.8V default voltage.
30
VIN
31
The positive input voltage power pins, which are referenced to PGND. Connect external input capacitance
between these pins and the PGND plane, close to the device.
32
8
9
10
VOUT
11
12
Output voltage. Connect output capacitors between these pins and the PGND plane, close to the device.
13
14
38
6
Copyright © 2011–2012, Texas Instruments Incorporated
TPS84410
www.ti.com
SLVSAR5A – SEPTEMBER 2011 – REVISED MARCH 2012
1
DNC
2
DNC
3
RT/CLK
4
AGND
VIN
VIN
VIN
35 34 33 32
AGND
36
AGND
VADJ
AGND
SENSE+
RKG PACKAGE
39 PINS
(TOP VIEW)
31 30
29
AGND
28
INH/UVLO
27
PWRGD
26
DNC
5
25
PH
SS/TR
6
24
PH
STSEL
7
23
PH
VOUT
8
22
PH
VOUT
9
21
PH
VOUT
10
20
PH
VOUT
11
37
PGND
PH
39
Copyright © 2011–2012, Texas Instruments Incorporated
17 18
19
PH
PH
DNC
DNC
VOUT
VOUT
VOUT
12 13 14 15 16
PH
VOUT
38
7
TPS84410
SLVSAR5A – SEPTEMBER 2011 – REVISED MARCH 2012
www.ti.com
TYPICAL CHARACTERISTICS (VIN = 5 V) (1)
(2)
14
100
VOUT = 3.3 V, fSW = 1 MHz
VOUT = 2.5 V, fSW = 1 MHz
VOUT = 1.8 V, fSW = 1 MHz
VOUT = 1.2 V, fSW = 750 kHz
VOUT = 0.8 V, fSW = 650 kHz
Output Voltage Ripple (mV)
95
Efficiency (%)
90
85
80
75
70
VOUT = 3.3 V, fSW = 1 MHz
VOUT = 2.5 V, fSW = 1 MHz
VOUT = 1.8 V, fSW = 1 MHz
VOUT = 1.2 V, fSW = 750 kHz
VOUT = 0.8 V, fSW = 650 kHz
65
60
55
50
0
1
2
Output Current (A)
3
12
10
8
6
4
4
0
Figure 1. Efficiency vs. Output Current
2
Output Current (A)
3
4
G000
Figure 2. Voltage Ripple vs. Output Current
90
1.2
VOUT = 3.3 V, fSW = 1 MHz
VOUT = 2.5 V, fSW = 1 MHz
VOUT = 1.8 V, fSW = 1 MHz
VOUT = 1.2 V, fSW = 750 kHz
VOUT = 0.8 V, fSW = 650 kHz
0.9
80
Ambient Temperature (°C)
Power Dissipation (W)
1
G000
0.6
0.3
70
60
50
40
30
All Output Voltages
0
1
2
Output Current (A)
3
4
20
0
120
30
90
20
60
10
30
0
0
−30
−10
4
G000
−60
−20
−40
1000
3
Figure 4. Safe Operating Area
40
−30
2
Output Current (A)
G000
Figure 3. Power Dissipation vs. Output Current
Gain (dB)
1
Natural Convection
Phase (°)
0
Gain
Phase
−90
10000
Frequency (Hz)
100000
−120
500000
G000
Figure 5. VOUT= 1.8 V, IOUT= 4 A, COUT1= 47 µF ceramic, COUT2= 100 µF POSCAP, fSW= 1 MHz
(1)
(2)
8
The electrical characteristic data has been developed from actual products tested at 25°C. This data is considered typical for the
converter. Applies to Figure 1, Figure 2, and Figure 3.
The temperature derating curves represent the conditions at which internal components are at or below the manufacturer's maximum
operating temperatures. Derating limits apply to devices soldered directly to a 100 mm × 100 mm double-sided PCB with 1 oz. copper.
Applies to Figure 4.
Copyright © 2011–2012, Texas Instruments Incorporated
TPS84410
www.ti.com
SLVSAR5A – SEPTEMBER 2011 – REVISED MARCH 2012
TYPICAL CHARACTERISTICS (VIN = 3.3 V) (1)
(2)
14
100
VOUT = 1.8 V, fSW = 1 MHz
VOUT = 1.2 V, fSW = 750 kHz
VOUT = 0.8 V, fSW = 650 kHz
Output Voltage Ripple (mV)
95
Efficiency (%)
90
85
80
75
70
65
VOUT = 1.8 V, fSW = 1 MHz
VOUT = 1.2 V, fSW = 750 kHz
VOUT = 0.8 V, fSW = 650 kHz
60
55
50
0
1
2
Output Current (A)
3
12
10
8
6
4
4
0
Figure 6. Efficiency vs. Output Current
2
Output Current (A)
3
4
G000
Figure 7. Voltage Ripple vs. Output Current
90
1.6
VOUT = 1.8 V, fSW = 1 MHz
VOUT = 1.2 V, fSW = 750 kHz
VOUT = 0.8 V, fSW = 650 kHz
1.2
80
Ambient Temperature (°C)
Power Dissipation (W)
1
G000
0.8
0.4
70
60
50
40
30
All Output Voltages
0
1
2
Output Current (A)
3
4
20
0
120
30
90
20
60
10
30
0
0
−30
−10
4
G000
−60
−20
−40
1000
3
Figure 9. Safe Operating Area
40
−30
2
Output Current (A)
G000
Figure 8. Power Dissipation vs. Output Current
Gain (dB)
1
Natural Convection
Phase (°)
0
Gain
Phase
−90
10000
Frequency (Hz)
100000
−120
500000
G000
Figure 10. VOUT= 1.8 V, IOUT= 4 A, COUT1= 47 µF ceramic, COUT2= 100 µF POSCAP, fSW= 1 MHz
(1)
(2)
The electrical characteristic data has been developed from actual products tested at 25°C. This data is considered typical for the
converter. Applies to Figure 6, Figure 7, and Figure 8.
The temperature derating curves represent the conditions at which internal components are at or below the manufacturer's maximum
operating temperatures. Derating limits apply to devices soldered directly to a 100 mm × 100 mm double-sided PCB with 1 oz. copper.
Applies to Figure 9.
Copyright © 2011–2012, Texas Instruments Incorporated
9
TPS84410
SLVSAR5A – SEPTEMBER 2011 – REVISED MARCH 2012
www.ti.com
APPLICATION INFORMATION
ADJUSTING THE OUTPUT VOLTAGE
The VADJ control sets the output voltage of the TPS84410. The output voltage adjustment range is from 0.8V to
3.6V. The adjustment method requires the addition of RSET, which sets the output voltage, the connection of
SENSE+ to VOUT, and in some cases RRT which sets the switching frequency. The RSET resistor must be
connected directly between the VADJ (pin 35) and AGND (pin 33 & 34). The SENSE+ pin (pin 36) must be
connected to VOUT either at the load for improved regulation or at VOUT of the module. The RRT resistor must
be connected directly between the RT/CLK (pin 4) and AGND (pins 33 & 34).
Table 1 gives the standard external RSET resistor for a number of common bus voltages, along with the
recommended RRT resistor for that output voltage.
Table 1. Standard RSET Resistor Values for Common Output Voltages
RESISTORS
OUTPUT VOLTAGE VOUT (V)
0.8
1.2
1.5
1.8
2.5
3.3
RSET (kΩ)
open
2.87
1.65
1.15
0.673
0.459
RRT (kΩ)
1200
715
348
348
348
348
For other output voltages, the value of the required resistor can either be calculated using the following formula,
or simply selected from the range of values given in Table 2.
1.43
RSET =
(kW )
æ æ VOUT ö ö
çç
÷ - 1÷
è è 0.803 ø ø
(1)
Table 2. Standard RSET Resistor Values
10
VOUT (V)
RSET (kΩ)
RRT(kΩ)
fSW(kHz)
VOUT (V)
RSET (kΩ)
RRT(kΩ)
fSW(kHz)
0.8
open
1200
650
2.3
0.768
348
1000
0.9
11.8
1200
650
2.4
0.715
348
1000
1.0
5.83
1200
650
2.5
0.673
348
1000
1.1
3.83
1200
650
2.6
0.634
348
1000
1.2
2.87
715
750
2.7
0.604
348
1000
1.3
2.32
715
750
2.8
0.576
348
1000
1.4
1.91
715
750
2.9
0.549
348
1000
1.5
1.65
348
1000
3.0
0.523
348
1000
1.6
1.43
348
1000
3.1
0.499
348
1000
1.7
1.27
348
1000
3.2
0.475
348
1000
1.8
1.15
348
1000
3.3
0.459
348
1000
1.9
1.05
348
1000
3.4
0.442
348
1000
2.0
0.953
348
1000
3.5
0.422
348
1000
2.1
0.845
348
1000
3.6
0.412
348
1000
2.2
0.825
348
1000
Copyright © 2011–2012, Texas Instruments Incorporated
TPS84410
www.ti.com
SLVSAR5A – SEPTEMBER 2011 – REVISED MARCH 2012
CAPACITOR RECOMMENDATIONS FOR THE TPS84410 POWER SUPPLY
Capacitor Technologies
Electrolytic, Polymer-Electrolytic Capacitors
When using electrolytic capacitors, high-quality, computer-grade electrolytic capacitors are recommended.
Polymer-electrolytic type capacitors are recommended for applications where the ambient operating temperature
is less than 0°C. The Sanyo OS-CON capacitor series is suggested due to the lower ESR, higher rated surge,
power dissipation, ripple current capability, and small package size. Aluminum electrolytic capacitors provide
adequate decoupling over the frequency range of 2 kHz to 150 kHz, and are suitable when ambient temperatures
are above 0°C.
Ceramic Capacitors
The performance of aluminum electrolytic capacitors is less effective than ceramic capacitors above 150 kHz.
Multilayer ceramic capacitors have a low ESR and a resonant frequency higher than the bandwidth of the
regulator. They can be used to reduce the reflected ripple current at the input as well as improve the transient
response of the output.
Tantalum, Polymer-Tantalum Capacitors
Polymer-tantalum type capacitors are recommended for applications where the ambient operating temperature is
less than 0°C. The Sanyo POSCAP series and Kemet T530 capacitor series are recommended rather than many
other tantalum types due to their lower ESR, higher rated surge, power dissipation, ripple current capability, and
small package size. Tantalum capacitors that have no stated ESR or surge current rating are not recommended
for power applications.
Input Capacitor
The TPS84410 requires a minimum input capacitance of 47 μF of ceramic capacitance. An additional 220 μF
polymer-tantalum capacitor is recommended for applications with transient load requirements. The combined
ripple current rating of the input capacitors must be at least 2000 mArms. Table 5 includes a preferred list of
capacitors by vendor. For applications where the ambient operating temperature is less than 0°C, an additional
1 μF, X5R or X7R ceramic capacitor placed between VIN and AGND is recommended.
Output Capacitor
The required output capacitance is determined by the output voltage of the TPS84410. See Table 3 for the
amount of required capacitance. The required output capacitance must include at least one 47 µF ceramic
capacitor. For applications where the ambient operating temperature is less than 0°C, an additional 100 µF
polymer-tantalum capacitor is recommended. When adding additional non-ceramic bulk capacitors, low-ESR
devices like the ones recommended in Table 5 are required. The required capacitance above the minimum is
determined by actual transient deviation requirements. See Table 4 for typical transient response values for
several output voltage, input voltage and capacitance combinations. Table 5 includes a preferred list of
capacitors by vendor.
Table 3. Required Output Capacitance
VOUT RANGE (V)
(1)
(2)
MINIMUM REQUIRED COUT (µF)
MIN
MAX
0.8
< 1.8
147 (1)
1.8
< 3.3
100 (2)
3.3
3.6
47 (2)
Minimum required must include at least 1 x 47 µF ceramic capacitor plus 1 x 100 µF polymer-tantalum
capacitor.
Minimum required must include at least 47 µF of ceramic capacitance.
Copyright © 2011–2012, Texas Instruments Incorporated
11
TPS84410
SLVSAR5A – SEPTEMBER 2011 – REVISED MARCH 2012
www.ti.com
Table 4. Output Voltage Transient Response
CIN1 = 1 x 47 µF CERAMIC, CIN2 = 220 µF POLYMER-TANTALUM, LOAD STEP = 2 A, 1 A/µs
VOUT (V)
VIN (V)
3.3
0.8
5
3.3
1.2
5
3.3
1.8
5
2.5
3.3
5
5
COUT1 Ceramic
COUT2 BULK
VOLTAGE
DEVIATION (mV)
PEAK-PEAK (mV)
RECOVERY TIME
(µs)
47 µF
100 µF
50
95
60
47 µF
330 µF
45
85
70
47 µF
100 µF
45
85
50
47 µF
330 µF
40
75
65
47 µF
100 µF
70
130
80
47 µF
330 µF
55
100
80
47 µF
100 µF
60
110
65
47 µF
330 µF
50
90
80
47 µF
100 µF
95
185
90
47 µF
330 µF
75
140
110
47 µF
100 µF
80
160
70
47 µF
330 µF
65
125
90
47 µF
100 µF
100
200
80
2x 47 µF
-
140
270
90
47 µF
100 µF
130
255
100
47 µF
-
200
400
120
Table 5. Recommended Input/Output Capacitors (1)
CAPACITOR CHARACTERISTICS
VENDOR
SERIES
PART NUMBER
WORKING
VOLTAGE
(V)
CAPACITANCE
(µF)
ESR (2)
(mΩ)
Murata
X5R
GRM32ER61C476K
16
47
2
TDK
X5R
C3225X5R0J107M
6.3
100
2
Murata
X5R
GRM32ER60J107M
6.3
100
2
TDK
X5R
C3225X5R0J476K
6.3
47
2
Murata
X5R
GRM32ER60J476M
6.3
47
2
Sanyo
POSCAP
10TPE220ML
10
220
25
Kemet
T520
T520V107M010ASE025
10
100
25
Sanyo
POSCAP
6TPE100MPB
6.3
100
25
Sanyo
POSCAP
2R5TPE220M7
2.5
220
7
Kemet
T530
T530D227M006ATE006
6.3
220
6
Kemet
T530
T530D337M006ATE010
6.3
330
10
Sanyo
POSCAP
2TPF330M6
2.0
330
6
Sanyo
POSCAP
6TPE330MFL
6.3
330
15
(1)
(2)
12
Capacitor Supplier Verification
Please verify availability of capacitors identified in this table.
RoHS, Lead-free and Material Details
Please consult capacitor suppliers regarding material composition, RoHS status, lead-free status, and manufacturing process
requirements.
Maximum ESR @ 100kHz, 25°C.
Copyright © 2011–2012, Texas Instruments Incorporated
TPS84410
www.ti.com
SLVSAR5A – SEPTEMBER 2011 – REVISED MARCH 2012
Transient Response
Figure 11. VIN = 5V, VOUT = 0.8V, 2A Load Step
Figure 12. VIN = 3.3V, VOUT = 0.8V, 2A Load Step
Figure 13. VIN = 5V, VOUT = 1.2V, 2A Load Step
Figure 14. VIN = 3.3V, VOUT = 1.2V, 2A Load Step
Copyright © 2011–2012, Texas Instruments Incorporated
13
TPS84410
SLVSAR5A – SEPTEMBER 2011 – REVISED MARCH 2012
14
www.ti.com
Figure 15. VIN = 5V, VOUT = 1.8V, 2A Load Step
Figure 16. VIN = 3.3V, VOUT = 1.8V, 2A Load Step
Figure 17. VIN = 5V, VOUT = 2.5V, 2A Load Step
Figure 18. VIN = 5V, VOUT = 3.3V, 2A Load Step
Copyright © 2011–2012, Texas Instruments Incorporated
TPS84410
www.ti.com
SLVSAR5A – SEPTEMBER 2011 – REVISED MARCH 2012
Application Schematics
VIN
2.95 V to 6 V
VIN
+
CIN2
220 F
TPS84410
PWRGD
CIN1
47 F
VOUT
1.2 V
SENSE+
VOUT
INH/UVLO
COUT1 +
47 F
COUT2
100 F
RT/CLK
RRT
715 k
SS/TR
VADJ
STSEL
PGND
AGND
RSET
2.87 k
Figure 19. Typical Schematic
VIN = 2.95 V to 6.0 V, VOUT = 1.2 V
VIN
4.4 V to 6 V
VIN
+
CIN2
220 F
TPS84410
PWRGD
CIN1
47 F
VOUT
3.3 V
SENSE+
VOUT
INH/UVLO
COUT1
47 F
COUT2
47 F
RT/CLK
RRT
348 k
SS/TR
VADJ
STSEL
PGND
AGND
RSET
459
Figure 20. Typical Schematic
VIN = 4.4 V to 6.0 V, VOUT = 3.3 V
Copyright © 2011–2012, Texas Instruments Incorporated
15
TPS84410
SLVSAR5A – SEPTEMBER 2011 – REVISED MARCH 2012
www.ti.com
Power Good (PWRGD)
The PWRGD pin is an open drain output. Once the voltage on the SENSE+ pin is between 93% and 105% of the
set voltage, the PWRGD pin pull-down is released and the pin floats. The recommended pull-up resistor value is
between 10 kΩ and 100 kΩ to a voltage source that is 6 V or less. The PWRGD pin is in a defined state once
VIN is greater than 1.2 V, but with reduced current sinking capability. The PWRGD pin achieves full current
sinking capability once the VIN pin is above 2.95V. Figure 21 shows the PWRGD waveform during power-up.
The PWRGD pin is pulled low when the voltage on SENSE+ is lower than 91% or greater than 107% of the
nominal set voltage. Also, the PWRGD pin is pulled low if the input UVLO or thermal shutdown is asserted, or if
the INH pin is pulled low.
Power-Up Characteristics
When configured as shown in the front page schematic, the TPS84410 produces a regulated output voltage
following the application of a valid input voltage. During the power-up, internal soft-start circuitry slows the rate
that the output voltage rises, thereby limiting the amount of in-rush current that can be drawn from the input
source. The soft-start circuitry introduces a short time delay from the point that a valid input voltage is
recognized. Figure 21 shows the start-up waveforms for a TPS84410, operating from a 5-V input and with the
output voltage adjusted to 1.8 V. The waveform is measured with a 2-A constant current load.
Figure 21. Start-Up Waveforms
Remote Sense
The SENSE+ pin must be connected to VOUT at the load, or at the device pins.
Connecting the SENSE+ pin to VOUT at the load improves the load regulation performance of the device by
allowing it to compensate for any I-R voltage drop between its output pins and the load. An I-R drop is caused by
the high output current flowing through the small amount of pin and trace resistance. This should be limited to a
maximum of 300 mV.
NOTE
The remote sense feature is not designed to compensate for the forward drop of nonlinear
or frequency dependent components that may be placed in series with the converter
output. Examples include OR-ing diodes, filter inductors, ferrite beads, and fuses. When
these components are enclosed by the SENSE+ connection, they are effectively placed
inside the regulation control loop, which can adversely affect the stability of the regulator.
16
Copyright © 2011–2012, Texas Instruments Incorporated
TPS84410
www.ti.com
SLVSAR5A – SEPTEMBER 2011 – REVISED MARCH 2012
Output On/Off Inhibit (INH)
The INH pin provides electrical on/off control of the device. Once the INH pin voltage exceeds the threshold
voltage, the device starts operation. If the INH pin voltage is pulled below the threshold voltage, the regulator
stops switching and enters low quiescent current state.
The INH pin has an internal pull-up current source, allowing the user to float the INH pin for enabling the device.
If an application requires controlling the INH pin, use an open drain/collector device, or a suitable logic gate to
interface with the pin. Do not place an external pull-up resistor on this pin. Figure 22 shows the typical application
of the inhibit function.
Turning Q1 on applies a low voltage to the inhibit control (INH) pin and disables the output of the supply, as
shown in Figure 23. If Q1 is turned off, the supply executes a soft-start power-up sequence, as shown in
Figure 24. The waveforms were measured with a 2-A constant current load.
INH/UVLO
Q1
INH
Control
AGND
Figure 22. Typical Inhibit Control
Figure 23. Inhibit Turn-Off
Copyright © 2011–2012, Texas Instruments Incorporated
Figure 24. Inhibit Turn-On
17
TPS84410
SLVSAR5A – SEPTEMBER 2011 – REVISED MARCH 2012
www.ti.com
Slow Start (SS/TR)
Connecting the STSEL pin to AGND and leaving SS/TR pin open enables the internal SS capacitor with a slow
start interval of approximately 1.1 ms. Adding additional capacitance between the SS pin and AGND increases
the slow start time. Table 6 shows an additional SS capacitor connected to the SS/TR pin and the STSEL pin
connected to AGND. See Table 6 below for SS capacitor values and timing interval.
SS/TR
CSS
(Optional)
AGND
STSEL
UDG-11119
Figure 25. Slow-Start Capacitor (CSS) and STSEL Connection
Table 6. Slow-Start Capacitor Values and Slow-Start Time
CSS (pF)
open
2200
4700
10000
15000
22000
25000
SS Time (msec)
1.1
1.9
2.8
4.6
6.4
8.8
9.8
Overcurrent Protection
For protection against load faults, the TPS84410 uses current limiting. The device is protected from overcurrent
conditions by cycle-by-cycle current limiting and frequency foldback. During an overcurrent condition the output
current is limited and the output voltage is reduced, as shown in Figure 26. When the overcurrent condition is
removed, the output voltage returns to the established voltage, as shown in Figure 27.
Figure 26. Overcurrent Limiting
18
Figure 27. Removal of Overcurrent Condition
Copyright © 2011–2012, Texas Instruments Incorporated
TPS84410
www.ti.com
SLVSAR5A – SEPTEMBER 2011 – REVISED MARCH 2012
Synchronization (CLK)
An internal phase locked loop (PLL) has been implemented to allow synchronization between 500 kHz and
2 MHz, and to easily switch from RT mode to CLK mode. To implement the synchronization feature, connect a
square wave clock signal to the RT/CLK pin with a minimum pulse width of 75 ns. The maximum clock pulse
width must be calculated using Equation 2. The clock signal amplitude must transition lower than 0.4 V and
higher than 2.2 V. The start of the switching cycle is synchronized to the falling edge of RT/CLK pin. In
applications where both RT mode and CLK mode are needed, the device can be configured as shown in
Figure 28.
Before the external clock is present, the device works in RT mode and the switching frequency is set by RT
resistor (RRT). When the external clock is present, the CLK mode overrides the RT mode. The device switches
from RT mode to CLK mode and the RT/CLK pin becomes high impedance as the PLL starts to lock onto the
frequency of the external clock. The device will lock to the external clock frequency approximately 15 µs after a
valid clock signal is present. It is not recommended to switch from CLK mode back to RT mode because the
internal switching frequency drops to a lower frequency before returning to the switching frequency set by the RT
resistor.
470 pF
1 kΩ
RT/CLK
500 kHz to 2 MHz
External Clock
æ
ö
V
0.75 ´ ç 1 - OUT ÷
ç
VIN(min ) ÷
è
ø
CLK _ PWMAX =
fSW
RRT
AGND
(2)
Figure 28. CLK/RT Configuration
The synchronization frequency must be selected based on the output voltages of the devices being
synchronized. Table 7 shows the allowable frequencies for a given range of output voltages based on a resistive
load. 5V input applications requiring 3.5A or less can synchronize to a wider frequency range. For the most
efficient solution, always synchronize to the lowest allowable frequency. For example, an application requires
synchronizing three TPS84410 devices with output voltages of 1.2V@3.7A, 1.8@2.5AV and 3.3V@ 2.1A, all
powered from VIN = 5V. Table 7 shows that all three output voltages can be synchronized to any frequency
between 750 kHz to 1 MHz. For best efficiency, choose 750 kHz as the sychronization frequency.
Table 7. Synchronization Frequency vs Output Voltage
VIN = 5 V
SYNCHRONIZATION
FREQUENCY (kHz)
RRT
(kΩ)
VIN = 3.3 V
IOUT ≤ 3.5 A
IOUT > 3.5 A
VOUT RANGE (V)
All IOUT
VOUT RANGE (V)
VOUT RANGE (V)
MIN
MAX
MIN
MAX
MIN
MAX
500
open
0.8
1.4
0.8
1.0
0.8
2.2
550
3400
0.8
1.6
0.8
1.1
0.8
2.4
600
1800
0.8
1.8
0.8
1.2
0.8
2.5
650
1200
0.8
2.1
0.8
1.4
0.8
2.5
700
887
0.8
2.6
0.8
1.6
0.8
2.5
750
715
0.9
3.6
0.9
1.8
0.8
2.5
800
590
0.9
3.6
0.9
2.1
0.8
2.5
900
511
1.0
3.6
1.0
3.6
0.8
2.5
1000
348
1.2
3.6
1.2
3.6
0.8
2.4
1250
232
1.4
3.6
1.4
3.6
1.0
2.4
1500
174
1.7
3.6
1.7
3.6
1.1
2.3
1750
137
2.0
3.6
2.0
3.6
1.3
2.2
2000
113
2.3
3.4
2.3
3.3
1.5
2.2
Copyright © 2011–2012, Texas Instruments Incorporated
19
TPS84410
SLVSAR5A – SEPTEMBER 2011 – REVISED MARCH 2012
www.ti.com
Sequencing (SS/TR)
Many of the common power supply sequencing methods can be implemented using the SS/TR, INH and
PWRGD pins. The sequential method is illustrated in Figure 29 using two TPS84410 devices. The PWRGD pin
of the first device is coupled to the INH pin of the second device which enables the second power supply once
the primary supply reaches regulation. Do not place a pull-up resistor on PWRGD in this configuration. Figure 30
shows sequential turn-on waveforms of two TPS84410 devices.
INH/UVLO
PWRGD
INH/UVLO
SS/TR
SS/TR
STSEL
STSEL
PWRGD
UDG-11120
Figure 29. Sequencing Schematic
Figure 30. Sequencing Waveforms
Simultaneous power supply sequencing can be implemented by connecting the resistor network of R1 and R2
shown in Figure 31 to the output of the power supply that needs to be tracked or to another voltage reference
source. Figure 32 shows simultaneous turn-on waveforms of two TPS84410 devices. Use Equation 3 and
Equation 4 to calculate the values of R1 and R2.
R1 =
(VOUT2 ´ 12.6 )
0.803
R2 =
(kW )
(3)
0.803 ´ R1
(kW )
V
( OUT2 - 0.803 )
(4)
VOUT1
VOUT
INH/UVLO
SS/TR
STSEL
VOUT2
VOUT
INH/UVLO
R1
SS/TR
STSEL
R2
Figure 31. Simultaneous Tracking Schematic
20
Figure 32. Simultaneous Tracking Waveforms
Copyright © 2011–2012, Texas Instruments Incorporated
TPS84410
www.ti.com
SLVSAR5A – SEPTEMBER 2011 – REVISED MARCH 2012
Programmable Undervoltage Lockout (UVLO)
The TPS84410 implements internal UVLO circuitry on the VIN pin. The device is disabled when the VIN pin
voltage falls below the internal VIN UVLO threshold. The internal VIN UVLO rising threshold is 3.135 V (max)
with a typical hysteresis of 300 mV.
If an application requires a higher UVLO threshold on the VIN pin, the UVLO pin can be configured as shown in
Figure 33. Table 8 lists standard values for RUVLO to adjust the VIN UVLO voltage up.
VIN
VIN
INH/UVLO
RUVLO
AGND
Figure 33. Adjustable VIN UVLO
Table 8. Standard Resistor values for Adjusting VIN UVLO
VIN UVLO (V) (typ)
3.25
3.5
3.75
4.0
4.25
4.5
4.75
RUVLO (kΩ)
294
133
86.6
63.4
49.9
42.2
35.7
Hysteresis (mV)
325
335
345
355
365
375
385
Copyright © 2011–2012, Texas Instruments Incorporated
21
TPS84410
SLVSAR5A – SEPTEMBER 2011 – REVISED MARCH 2012
www.ti.com
Thermal Shutdown
The internal thermal shutdown circuitry forces the device to stop switching if the junction temperature exceeds
175°C typically. The device reinitiates the power up sequence when the junction temperature drops below 160°C
typically.
Layout Considerations
To achieve optimal electrical and thermal performance, an optimized PCB layout is required. Figure 34, shows a
typical PCB layout. Some considerations for an optimized layout are:
• Use large copper areas for power planes (VIN, VOUT, and PGND) to minimize conduction loss and thermal
stress.
• Place ceramic input and output capacitors close to the module pins to minimize high frequency noise.
• Locate additional output capacitors between the ceramic capacitor and the load.
• Place a dedicated AGND copper area beneath the TPS84410.
• Connect the AGND and PGND copper area at one point; directly at the pin 37 PowerPad using multiple vias.
• Place RSET, RRT, and CSS as close as possible to their respective pins.
• Use multiple vias to connect the power planes to internal layers.
SENSE+
Via
PGND
Vias to
PGND
Layer
CIN1
VIN
SENSE+
Via
Vias to
Topside
PGND
Copper
COUT1
PH
Vias to
Topside
AGND
Copper
PGND
Plane
Vias to
PGND
Layer
VOUT
AGND
RSET
SENSE+
Via
SENSE+
Via
RRT
Figure 34. Typical Top-Layer Recommended
Layout
22
Figure 35. Typical PGND-Layer Recommended
Layout
Copyright © 2011–2012, Texas Instruments Incorporated
TPS84410
www.ti.com
SLVSAR5A – SEPTEMBER 2011 – REVISED MARCH 2012
EMI
The TPS84410 is compliant with EN55022 Class B radiated emissions. Figure 36 and Figure 37 show typical
examples of radiated emissions plots for the TPS84410 operating from 5V and 3.3V respectively. Both graphs
include the plots of the antenna in the horizontal and vertical positions.
Figure 36. Radiated Emissions 5-V Input, 1.8-V
Output, 4-A Load (EN55022 Class B)
Copyright © 2011–2012, Texas Instruments Incorporated
Figure 37. Radiated Emissions 3.3-V Input, 1.8-V
Output, 4-A Load (EN55022 Class B)
23
TPS84410
SLVSAR5A – SEPTEMBER 2011 – REVISED MARCH 2012
www.ti.com
Changes from Original (2011) to Revision A
Page
•
24
Changed the voltage range values in Table 7 .................................................................................................................... 19
Copyright © 2011–2012, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
1-Apr-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPS84410RKGR
ACTIVE
B1QFN
RKG
39
500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
(54418 ~ TPS84410)
TPS84410RKGT
ACTIVE
B1QFN
RKG
39
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
(54418 ~ TPS84410)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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1-Apr-2015
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
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