TPS92210
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SLUS989B – JANUARY 2010 – REVISED SEPTEMBER 2012
NATURAL PFC LED LIGHTING DRIVER CONTROLLER
Check for Samples: TPS92210
FEATURES
DESCRIPTION
•
The TPS92210 is a natural power factor correction
(PFC) light emmitting diode (LED) lighting driver
controller with advanced energy features to provide
high efficiency control for LED lighting applications.
1
•
•
•
•
•
•
•
•
•
Flexible Operation Modes
– Constant On-Time Enables Single Stage
PFC Implementation
– Peak Primary Current
Cascoded MOSFET Configuration
– Fully Integrated Current Control Without
Sense Resistor
– Fast and Easy Startup
Discontinuous Conduction Mode or Transition
Mode Operation
Transformer Zero Energy Detection
– Enables Valley Switching Operation
– Helps to Achieve High Efficiency and Low
EMI
Open LED Detection
Advanced Overcurrent Protection
Output Overvoltage Protection
Line Surge Ruggedness
Internal Over-Temperature Protection
8-Pin SOIC (D) Package
APPLICATIONS
•
•
•
•
A PWM modulation algorithm varies both the
switching frequency and primary current while
maintaining discontinuous or transition mode
operation in all regions of operation. The TPS92210
cascode architecture enables low switching loss in
the primary side and when combined with the
discontinuous conduction mode (DCM) operation
ensures that there is no reverse recovery loss in the
output rectifier. These innovations result in efficiency,
reliability or system cost improvements over a
conventional flyback architecture.
The TPS92210 offers a predictable maximum power
threshold and a timed response to an overload,
allowing safe handling of surge power requirements.
The overload fault response is user-programmed for
retry or latch mode. Additional protection features
include open-LED detection by output overvoltage
protection and thermal shutdown.
The TPS92210 is offered in the 8-pin SOIC (D)
package. Operating junction temperature range is
–40°C to 125°C
TRIAC Dimmable LED Lighting Designs
Residential LED Lighting Drivers for Retrofit
A19 (E27/26, E14), PAR30/38, GU10, MR16, BR
Drivers for Down and Architectural Wall
Sconces, Pathway and Overhead Lighting
Commercial Troffers and Downlights
VIN
AC
+
4
TPS92210
OTM
VCG
5
3
PCL
DRN
6
2
TZE
GND
7
1
FB
VDD
8
VOUT
LED ISENSE
and
Conditioning
UDG-09152
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010–2012, Texas Instruments Incorporated
TPS92210
SLUS989B – JANUARY 2010 – REVISED SEPTEMBER 2012
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
OPERATING
TEMPERATURE
RANGE, TA
PACKAGE
–40°C to 125°C
SOIC
ORDERABLE
DEVICE NUMBER
TPS92210DR
TPS92210D
PINS
8
TRANSPORT MEDIA
QUANTITY
Tape and Reel
2500
Tube
75
ABSOLUTE MAXIMUM RATINGS (1)
All voltages are with respect to GND, –40°C < TJ = TA < 125°C, all currents are positive into and negative out of the specified
terminal (unless otherwise noted)
VALUE
MIN
VDD
–0.5
25
DRN, during conduction
–0.5
2.0
DRN, during non-conduction
Input voltage range
VCG
(2)
–0.5
16
–0.5
7
FB (3)
–0.5
1.0
–7
10
VDD – VCG
(2)
IVCG
Input current range
ITZE, IOTM, IPCL, IFB
10
(3)
–3
1
–6
1.5
DRN
-4
DRN, pulsed 200ns, 2% duty cycle
UNIT
20
TZE, OTM, PCL (3)
Continuous input current
Output current
MAX
V
mA
A
Operating junction temperature
TJ
–40
150
°C
Storage temperature range
Tstg
–65
150
°C
Lead temperature
Soldering, 10 s
260
°C
(1)
(2)
(3)
2
These are stress ratings only. Stress beyond these limits may cause permanent damage to the device. Functional operation of the
device at these or any conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to
absolute maximum rated conditions for extended periods of time may affect device reliability
Voltage on VCG is internally clamped. The clamp level varies with operating conditions. In normal use, VCG is current fed with the
voltage internally limited
In normal use, pins OTM, PCL, TZE, and FB are connected to resistors to GND and internally limited in voltage swing
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THERMAL INFORMATION
TPS92210
THERMAL METRIC (1)
D
UNITS
8 PINS
Junction-to-ambient thermal resistance (2)
θJA
(3)
117.5
θJCtop
Junction-to-case (top) thermal resistance
θJB
Junction-to-board thermal resistance (4)
57.8
ψJT
Junction-to-top characterization parameter (5)
15.3
ψJB
Junction-to-board characterization parameter (6)
57.3
θJCbot
Junction-to-case (bottom) thermal resistance (7)
n/a
(1)
(2)
(3)
(4)
(5)
(6)
(7)
63.7
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Spacer
RECOMMENDED OPERATING CONDITIONS
Unless otherwise noted, all voltages are with respect to GND, –40°C < TJ = TA < 125°C. Components reference Figure 17.
MIN
MAX
VDD
Input voltage
9
20
VCG
Input voltage from low-impedance source
9
13
IVCG
Input current from a high-impedance source
10
2000
25
100
150
750
Shutdown/retry mode
UNIT
V
µA
ROTM
Resistor to GND
RPCL
Resistor to GND
24.3
100
kΩ
RTZE1
Resistor to auxiliary winding
50
200
kΩ
CVCG
VCG capacitor
33
200
nF
CBP
VDD bypass capacitor, ceramic
0.1
1.0
μF
Latch-off mode
kΩ
ELECTROSTATIC DISCHARGE (ESD) PROTECTION
MAX
UNIT
ESD Rating, Human Body Model (HBM)
1.5
kV
ESD Rating, Charged Device Model (CDM)
500
V
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ELECTRICAL CHARACTERISTICS
Unless otherwise stated: VVDD = 12 V, VVCG = 12 V, VTZE = 1 V, IFB = 10 µA, GND = 0 V, a 0.1-μF capacitor exists between
VDD and GND, a 0.1-μF capacitor exists between VCG and GND, RPCL= 33.2 kΩ, ROTM= 380 kΩ, –40°C < TA< +125°C,
TJ = TA
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
VDD and VCG SUPPLY
VCG(OPERATING)
VCG Voltage, Operating
VDD = 14 V, IVCG = 2.0 mA
13
14
15
V
VCG(DISABLED)
VCG Voltage, PWM Disabled
VDD = 12 V, IVCG = 15 μA, IFB = 350 μA
15
16
17
V
ΔVCG
Rise in VCG Clamping Voltage During
UVLO, LPM, or Fault
VCG(DISABLED) – VCG(OPERATING)
1.75
2
2.15
V
IVCG(SREG)
VCG Shunt Regulator Current
VCG = (VCG(DISABLED) – 100 mV),
VDD = 12 V
6
10
μA
ΔVCG(SREG)
VCG Shunt Load Regulation
10 μA ≤ IVCG ≤ 5 mA, IFB = 350 μA
125
200
mV
VCG(LREG)
VCG LDO Regulation Voltage
VDD = 20 V, IVCG = – 2 mA
VCG LDO Dropout Voltage
VDD – VCG, VDD = 11 V, IVCG = – 2 mA
VCG(LREG,
DO)
13
V
1.5
2
2.5
V
VDD(ON)
UVLO Turn-on Threshold
9.7
10.2
10.7
V
VDD(OFF)
UVLO Turn-off Threshold
7.55
8
8.5
V
ΔVDD(UVLO)
UVLO Hysteresis
1.9
2.2
2.5
V
IVDD(OPERATING)
Operating Current
VDD= 20 V
2.5
3
3.7
mA
IVDD(LPM)
Idle Current Between Bursts
IFB = 350 μA
550
900
μA
IVDD(UVLO)
Current for VDD < UVLO
VDD = VDD(on) – 100 mV, increasing
225
300
μA
RDS,ON(VDD)
VDD Switch on Resistance, DRN to VDD
VCG = 12 V, VDD == 7V, IDRN = 50 mA
4
10
Ω
VDD(FAULT
VDD for Fault Latch Reset
5.6
6
6.4
V
7.125
7.5
7.875
μs
31
34
38
μs
2.85
3
3.15
A
RESET)
MODULATION
tSW(HF)
(1)
Minimum switching period, frequency
modulation (FM) mode
IFB = 0 μA,
tSW(LF)
(1)
Maximum switching period, reached at end
of frequency modulation (FM) range
IFB = IFB, CNR3 – 20 μA,
(1)
(1)
IDRN(peak,max)
Maximum peak driver current over amplitude IFB = 0 μA, RPCL = 33. 2 kΩ
modulation (AM) range
IFB = 0 μA, RPCL = 100 kΩ
0.8
0.9
1.0
A
IDRN(peak,min)
Minimum peak driver current reached at end
of AM modulation range
IFB,
CNR2
+ 10 μA, RPCL = 33.2 kΩ
0.7
0.85
1.1
A
IFB,
CNR2
+ 10 μA, RPCL = 100 kΩ
0.2
0.33
0.5
A
KP
Maximum power constant
IDRN(peak,max) = 3 A
0.54
0.60
0.66
W/μH
IDRN(peak,absmin)
Minimum peak driver independent of RPCL or
AM control
RPCL = OPEN
0.3
0.45
0.6
A
tBLANK(ILIM)
Leading ddge current limit blanking time
IFB = 0 μA, RPCL = 100 kΩ, 1.2-A pull-up on
DRN
VPCL
PCL Voltage
IFB,CNR1
(2)
IFB,CNR2 – IFB,CNR1
(2)
IFB,CNR3 – IFB,CNR2
(2)
IFB, LPM-HYST
FB
(1)
(2)
4
(2)
220
ns
IFB = 0 μA
2.94
3
3.06
IFB = (IFB,CNR3 – 20 μA) (1)
0.95
1
1.1
IFB range for FM modulation
IFB increasing, tSW = tSW(LF), and
IDRN(PK,) = IDRN,PK(MAX)
145
165
195
μA
IFB range for AM modulation
tSW = tSW(LF), IDRN PK ranges from
IDRN,PK(MAX) to IDRN,PK(MIN)
35
45
65
μA
IFM range for low power mode(LPM)
modulation
IFB increasing until PWM action is disabled
entering a burst-off state
45
70
90
μA
IFB hysteresis during LPM modulation to
enter burst on and off states
IFB decreasing from above IFB,CNR3
10
25
40
μA
Voltage of FB
IFB = 10 μA
0.34
0.7
0.84
V
V
tSW sets a minimum switching period. Following the starting edge of a PWM on time, under normal conditions, the next on time is
initiated following the first valley switching at TZE after tSW. The value of tSW is modulated by IFB between a minimum of tSW(HF) and a
maximum of tSW(LF) In normal operation, tSW(HF) sets the maximum operating frequency of the power supply and tSW(LF) sets the
minimum operating frequency of the power supply.
Refer to Figure 24.
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ELECTRICAL CHARACTERISTICS (continued)
Unless otherwise stated: VVDD = 12 V, VVCG = 12 V, VTZE = 1 V, IFB = 10 µA, GND = 0 V, a 0.1-μF capacitor exists between
VDD and GND, a 0.1-μF capacitor exists between VCG and GND, RPCL= 33.2 kΩ, ROTM= 380 kΩ, –40°C < TA< +125°C,
TJ = TA
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
5
20
50
mV
-220
-160
-100
mV
0.1
0.15
0.2
TRANSFORMER ZERO ENERGY DETECTION
TZE(TH)
TZE zero crossing threshold
TZE high to low generates switching period
(tSW has expired)
TZE(CLAMP)
TZE low clamp voltage
ITZE = –10 μA
TZE(START)
TZE voltage threshold to enable the internal
start timer
Driver switching periods generated at start
timer rate
tDLY(TZ2D)
Delay from zero crossing to Driver turn-on
150-Ω pull-up to 12-V on DRN
tWAIT(TZE)
Wait time for zero energy detection
Driver turn-on edge generated following tSW
with previous zero current detected
tST
Starter time-out period
TZE = 0 V
RDS(on)(DRN)
Driver on-resistance
IDRN(OFF)
Driver off-leakage current
RDS(on)(HSDRV)
HSDRV on-resistance
HS Driver Current = 50 mA
IDRN,DSCH
DRN Bulk Discharge
VDD open, DRN = 12 V, Fault latch set
150
V
ns
2
2.4
2.8
μs
150
240
300
μs
IDRN = 4.0 A
90
190
mΩ
IDRN = 12 V
1.5
20
μA
6
11
Ω
2
2.8
3.6
mA
4.85
5
5.15
V
0.6
1
1.7
μs
–0.1
μA
DRIVER
OVERVOLTAGE FAULT
TZE(OVP)
Overvoltage fault threshold at TZE
tBLANK,OVP
TZE blanking and OVP sample time from the
turn-off edge of DRN
Fault latch set
ITZE(bias)
TZE Input bias current
TZE = 5 V
–0.1
0
1.5
3
μA
200
250
300
ms
OVERLOAD FAULT
IFB(OL)
Current to trigger overload delay timer
tOL
Delay to overload fault
IFB = 0 A continuously
tRETRY
Retry delay in retry mode or after shutdown
command
ROTM = 76 kΩ
ROTM(TH)
Boundary ROTM between latch-off and retry
modes
See
750
(3)
100
120
ms
150
kΩ
SHUTDOWN THRESHOLD
VOTM(SR)
Shutdown/retry threshold
OTM high to low
0.7
1
1.3
V
IOTM,PU
OTM current when OTM is pulled low
VOTM = VOTM(SR)
–600
–450
–300
μA
Latch-off
ROTM = 383 kΩ
3.43
3.83
4.23
μs
Shutdown/retry
ROTM = 76 kΩ
3.4
3.8
4.2
μs
2.7
3
3.3
V
MAXIMUM ON TIME
tOTM
VOTM
OTM voltage
THERMAL SHUTDOWN
TSD
(4)
TSD_HYS
(3)
(4)
(4)
Shutdown temperature
TJ, temperature rising (4)
Hysteresis
TJ, temperature falling, degrees below tSD
(4)
165
°C
15
°C
A latch-off or a shutdown/retry fault response to a sustained overload is selected by the range of ROTM. To select the latch-off mode,
ROTM should be greater than 150 kΩ and tOTM is given by ROTM × (1.0 × 10-11). To select the shutdown/retry mode, ROTM should be less
than 100 kΩ and tOTM is given by ROTM × (5.0 × 10-11).
Thermal shutdown occurs at temperatures higher than the normal operating range. Device performance at or near thermal shutdown
temperature is not specified or assured.
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DEVICE INFORMATION
Functional Block Diagram
+
VVCG
Fault Latch
Reg
Reset
+
13 V
VVDD
Switch
VVCG
Shunt
10 V/6 V
VDD
8
5
VCG
6
DRN
14 V
HS
Drive
+
2V
10 V/8 V
Enable
PWM
IFB
1
IFB
UVLO
FB
IFB
Feedback
Processing
0 A 210 mA
I =0 Overload
FB
TZE
Freq. Modulator
tSW
1/tSW
Enable
PWM
D
Transformer
Zero Energy
Detect
2
Driver
IFB
Q
7.5 kW
VGATE
Q
OV
Fault
Output
Voltage
Sense
Bulk
Discharge
7
GND
3
PCL
5V
Fault
On-Time Modulation
and Fault Response
Control
IOTM
VGATE
+
1V
4
IP
Latch or
Retry
3V
OTM
IFB Current
Modulator
Fault Timing
& Control
Shutdown
and Restart
Fault Latch
Reset
UVLO
Thermal
Shutdown
IFB
TPS92210
UDG-09157
6
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PIN CONFIGURATION
FB
1
8
VDD
TZE
2
7
GND
PCL
3
6
DRN
OTM
4
5
VCG
PIN DESCRIPTIONS
TERMINAL
NAME
No.
I/O
DESCRIPTION
DRN
6
O
The DRN pin is the drain of the internal low voltage power MOSFET of the TPS92210 and carries the peak primary
inductor current, IPEAK(pri). Connect this pin to the source of the external cascode power MOSFET. A schottky diode
between DRN and VDD is used to provide initial bias at startup.
FB
1
I
The FB pin is regulated at 0.7 V and only detects current input (FB current,IFB) which commands the operating
mode of TPS92210. For peak-current mode control, this pin is connected to the emitter of the feedback opto
coupler. In constant on-time control, the minimum switching period is programmed by forcing a constant current into
this pin.
GND
7
—
This GND pin is the current return terminal for both the analog and power signals in the TPS92210. This terminal
carries the full drain current, IDRN, which is equal to the peak primary current, IPEAK(pri), in addition to the bias supply
current (IVDD) , and the gate voltage current (IVCG).
OTM
4
I
the OTM pin is internally regulated at 3 V and used to program the on-time of the cascode (flyback) switch by
connecting a resistor (ROTM) from this pin to the quiet return of GND. The collector of the opto-coupler is connected
to this pin for constant-on time control. The range of impedance connected at this pin determines the system fault
response (latch-off or shutdown/retry) to overload and brownout fault conditions. An external shutdown/retry
response can be initiated by pulling this pin low below 1 V.
PCL
3
I
The PCL pin programs the peak primary inductor current that is reached each switching cycle. The primary current
is sensed with the RDS(on) of the internal MOSFET and is programmed by setting a threshold by connecting a low
power resistor from this pin to the quiet return of GND.
TZE
2
I
A resistive divider between the primary-side auxiliary winding and this pin is used to detect when the transformer is
demagnetized resulting in transformer zero energy. The ratio of the resistive divider at this pin can also be used to
program the output overvoltage protection (OVP) feature.
VCG
5
—
The VCG pin provides the bias voltage for the gate of the cascode MOSFET. Place a 0.1-µF ceramic capacitor
between VCG and GND, as close as possible to the high-voltage MOSFET. This pin also provides start-up bias
through a resistor RSU, which is connected between this pin and the bulk voltage.
VDD
8
—
VDD is the bias supply pin for the TPS92210. It can be derived from an external source, or an auxiliary winding.
Place a 0.1-µF ceramic capacitor between VDD and GND, as close to the device as possible. This pin also enables
and disables the general functions of the TPS92210 using the UVLO feature.
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TYPICAL CHARACTERISTICS
Unless otherwise stated: VVDD = 12 V, VVCG = 12 V, VTZE = 1 V, IFB = 10 µA, GND = 0 V, a 0.1µF capacitor tied between VDD
and GND, a 0.1-µF capacitor tied between VCG and GND, RPCL = 33.2 kΩ, ROTM = 380 kΩ, –40°C < TA < +125°C, TJ = TA
BIAS SUPPLY CURRENT
vs
BIAS SUPPLY VOLTAGE DURING OPERATION
4.0
IVDD – Bias Supply Current – mA
3.8
3.6
IVDD – Bias Supply Current – mA
IFB = 10 mA
VTZE = 1V
VVCG = OPEN
VVDD decreasing from 20 V
3.4
3.2
3.0
BIAS SUPPLY CURRENT
vs
BIAS SUPPLY VOLTAGE DURING LOW POWER MODE
900
IFB = 280.4 mA
VVCG = OPEN
850
VVDD decreasing from 20 V
800
750
700
650
600
2.8
550
2.6
8
10
12
14
16
18
8
20
14
16
18
Figure 1.
Figure 2.
BIAS SUPPLY CURRENT
vs
TEMPERATURE DURING LOW POWER MODE
OPERATIONAL IVDD – BIAS CURRENT
vs
BIAS VOLTAGE
900
3.5
850
3.0
IVDD – Bias Supply Current – mA
IVDD – Bias Supply Current – mA
12
800
750
700
650
2.5
2.0
VDD rising
0 V to 20V
1.5
IFB= 10 mA,
VDD falling
20V to 0 V
1.0
IFB= 0 mA,
VDD falling
20V to 0 V
0.5
600
550
-40 -25 -10
20
VVDD – Bias Supply Voltage – V
VVDD – Bias Supply Voltage – V
0.0
5
20
35
50
65
80
95 110 125
0
TJ – Junction Temperature – °C
Figure 3.
8
10
5
10
15
20
VVDD – Bias Voltage – V
Figure 4.
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TYPICAL CHARACTERISTICS (continued)
Unless otherwise stated: VVDD = 12 V, VVCG = 12 V, VTZE = 1 V, IFB = 10 µA, GND = 0 V, a 0.1µF capacitor tied between VDD
and GND, a 0.1-µF capacitor tied between VCG and GND, RPCL = 33.2 kΩ, ROTM = 380 kΩ, –40°C < TA < +125°C, TJ = TA
OSCILLATOR FREQUENCY
vs
FEEDBACK CURRENT
MINIMUM SWITCHING PERIOD
vs
TEMPERATURE
160
fSW – Switching Frequency – kHz
Junction
Temperature
(°C)
–40
25
125
TJ = 125°C
and
TJ = 25°C
140
120
100
80
60
TJ = –40°C
40
20
tSW(HF) – Minimum Switching Period – ms
8.0
0
0
50
100
150
200
250
7.4
7.2
5
20
35
50
65
80
95 110 125
IFB – Feedback Control Current – mA
TA – Ambient Temperature – °C
Figure 5.
Figure 6.
SWITCHING PERIOD
vs
AMBIENT TEMPERATURE
PEAK DRN CURRENT
vs
FEEDBACK CURRENT
3.5
During Amplitude
Modulation
3.0
IDRN(pk) – Peak DRN Current – A
tSW(LF) – Minimum Switching Period – ms
7.6
7.0
-40 -25 -10
300
38
37
7.8
36
35
34
33
TA = –40°C
2.5
2.0
TA = 25°C
1.5
Ambient
Temperature
(°C)
–40
25
125
1.0
0.5
32
31
-40 -25 -10
TA = 125°C
0.0
5
20
35
50
65
80
95 110 125
0
50
100
150
200
TA – Ambient Temperature – °C
IFB - Feedback Current - mA
Figure 7.
Figure 8.
250
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TYPICAL CHARACTERISTICS (continued)
Unless otherwise stated: VVDD = 12 V, VVCG = 12 V, VTZE = 1 V, IFB = 10 µA, GND = 0 V, a 0.1µF capacitor tied between VDD
and GND, a 0.1-µF capacitor tied between VCG and GND, RPCL = 33.2 kΩ, ROTM = 380 kΩ, –40°C < TA < +125°C, TJ = TA
PEAK DRN CURRENT
vs
TRANSCONDUCTANCE (1/RPCL)
PEAK DRN CURRENT
vs
AMBIENT TEMPERATURE
5
3.2
IFB = 0 mA
4
IDRN(pk) – Peak DRN Current – A
IDRN(pk) – Peak DRN Current – A
Best Results
24.3 kW < RPCL< 100 kW
3
2
1
3.1
3.0
2.9
Avoid Operation Here
0
0
10
20
30
40
2.8
-40 -25 -10
50
1/RPCL – mS
35
50
65
80
Figure 10.
ON TIME
vs
ON-TIME MODULATION RESISTANCE
ON TIME
vs
JUNCTION TEMPERATURE
95 110 125
4.3
4.2
5
ROTM = 383 kW
4.1
tOTM – Constant On-Time – ms
tOTM – Constant On-Time – ms
20
Figure 9.
6
4
3
2
MODE
Latch Off
Shutdown/Retry
1
0
100
20
300
400
500
4.0
3.9
3.8
3.7
3.6
3.5
3.4
0
10
5
TA – Ambient Temperature – °C
600
3.3
-40 -25 -10
5
20
35
50
65
80
95 110 125
ROTM – On-Time Modulation Resistance – kW
TJ – Junction Temperature – °C
Figure 11.
Figure 12.
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TYPICAL CHARACTERISTICS (continued)
Unless otherwise stated: VVDD = 12 V, VVCG = 12 V, VTZE = 1 V, IFB = 10 µA, GND = 0 V, a 0.1µF capacitor tied between VDD
and GND, a 0.1-µF capacitor tied between VCG and GND, RPCL = 33.2 kΩ, ROTM = 380 kΩ, –40°C < TA < +125°C, TJ = TA
LOW VOLTAGE MOSFET RDS(on)
vs
AMBIENT TEMPERATURE
RDS(on) OF HIGH SIDE DRIVE AND VDD SWITCH
vs
TEMPERATURE
160
12
120
RDS(on) – On-Time Resistance – W
RDS(on) – On-Time Resistance – mW
High-Side
VDD Switch
100
80
60
40
20
-40 -25 -10
5
20
35
50
65
80
10
8
6
4
2
0
-40 -25 -10
95 110 125
TA – Ambient Temperature – °C
35
50
65
80
95 110 125
Figure 14.
SAFE OPERATING AREA
vs
BOARD TEMPERATURE
THERMAL COEFFICIENT – θJB
vs
POWER DISSIPATION
60
50
2.0
qJB – Thermal Coefficient – °C/W
PDISS – Power Dissipation – W
20
Figure 13.
2.5
1.5
1.0
0.5
0
-40 -25 -10
5
TA – Ambient Temperature – °C
40
30
20
10
0.0
5
20
35
50
65
80
95 110 125
0
0.25
0.50
0.75
1.00
1.25
PDISS – Power Dissipation – W
TB – Board Temperature – °C
Figure 15.
Figure 16.
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TPS92210
SLUS989B – JANUARY 2010 – REVISED SEPTEMBER 2012
+ CBULK
VIN
AC
www.ti.com
RSU
NP
NS
CVCG
TPS92210
4
OTM
VCG 5
3
PCL
DRN 6
2
TZE
GND
1
FB
VDD 8
NB
7
CBP
D1
+
CVDD
DBIAS
RTZE1
LED ISENSE
and
Conditioning
UDG-09180
Figure 17. Typical Application
12
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DETAILED DESCRIPTION
BIAS AND START-UP
The TPS92210 controls the turn-ON and turn-OFF of the flyback switch through its source by using the cascode
configuration. The cascode configuration is also used to provide the initial bias during start-up. The cascode
architecture utilizes a low voltage switch whose drain, namely the DRN pin, is connected to the source of the
high voltage MOSFET (HV MOSFET). The gate of the HV MOSFET is held at a constant DC voltage using the
VCG pin. The TPS92210 cascode based HVMOSFET drive architecture is shown in Figure 18.
Bulk
Bulk
Primary
Winding
Primary
Winding
External
High-Voltage
MOSFET
External
High-Voltage
MOSFET
Gate Bias +
14 VDC
+
Cascoded
MOSFET
Pair
PWM
Control
Internal
Low-Voltage
MOSFET
ON
PWM
Control
Internal
Low-Voltage
MOSFET
OFF
UDG-09185
Figure 18. Cascoded Architecture
The start-up bias uses a low-level bleed current from either the AC line or the rectified and filtered AC line
through the startup resistor (RSU). The bleed current off the line (approximately 6 µA) charges a small VCG
capacitor and raises the voltage at the HVMOSFET gate. The HVMOSFET acts as a source follower once the
voltage at VCG pin reaches the threshold voltage of the HVMOSFET and raises the DRN pin voltage. During
startup the TPS92210 is in undervoltage lockout (UVLO) state with the enable pulse-width modulation (PWM)
signal low. This turns on the VDD switch connecting between the DRN pin and the VDD pin, thus allowing VVDD
to also rise with VVCG minus a threshold voltage of HVMOSFET. An external schottky diode between DRN and
VDD is used to steer away potentially high switching currents from flowing through the body diode of the internal
VDD switch. The startup current and the operating current paths in the cascode architecture are shown in
Figure 19. The VCG pin is shunt regulated at 14 V during normal operation and the regulation level is increased
to 16 V during fault, UVLO and startup conditions.
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Bulk
RSU
(~10 MW)
VDD
VDD Operating, LPM Current
8
Primary
Winding
HVMOSFET
CVCG
(100 nF)
VDD Start-up Current
CVDD
(~10 mF)
ISU
VCG
D2
Auxiliary
Winding
5
UVLO
Enable PWM
+
14 V
2V
10 V/8 V Fault
VCG Shunt
VDD
Switch
Internal
Regulators
DRN
6
Enable
PWM
UDG-09182
Figure 19. Start-Up and Operating Current in the Cascode Architecture for TPS92210
14
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PRIMARY SIDE CURRENT SENSE
The TPS92210 integrates all of the current sensing and drive, thereby eliminating the need for a current sense
resistor. The internal low-voltage switch with typical RDS(on) of 90 mΩ drives the HVMOSFET through its source
and the entire primary current of the transformer flows through this switch and out of the GND pin. The
TPS92210 utilizes a current mirror technique to sense and control the primary current. The primary current
flowing through the low-voltage switch is scaled and reflected to the PWM comparator where it is compared with
the PCL pin current. Thus the peak current reached at each switching cycle is sensed and limited by this
comparison.
In peak current-mode control, based on the error signal input at the FB pin, the voltage at the PCL pin and hence
the PCL pin current is modulated by TPS92210. The maximum peak primary current is programmed by
connecting a low-power resistor from (RPCL) from PCL pin to the quiet return of GND.
æ 100kV ö
IDRN(pk ) = ç
÷
è RPCL ø
(1)
At the beginning of each switching cycle a blanking time of approximately 220 ns is applied to the internal current
limiter. This allows the low-voltage switch to turn on without false limiting on the leading edge capacitive
discharge currents. The drain-gate charge in the HVMOSFET does not affect the turn-off speed because the
gate is connected to a low impedance DC source with the help of VCG pin. The cascode configuration enables
very fast turn-off of the HVMOSFET and helps to keep switching losses low. Figure 20 illustrates the internal
current sensing and control exhibited by programming the resistor at the PCL pin.
Current Modulator
I DRN,PK
FB
IFB
1
3
From
Optocoupler
Emitter
IFB
1
210
V PCL, V
IPCL
PCL
3
DRN
1
3
i FB, µA
165
IDRN
IPCL
From High-Voltage
MOSFET Source
6
210
100,000
IDRN
Drive
MOSFET
GND
7
PWM
Comparator
tBLANKCL
R
R
TPS92210
UDG-09186
Figure 20. Peak Current Limit (PCL) Pin Details
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FEEDBACK AND MODULATION
The TPS92210 can be programmed to operate in constant-on time control or in peak-current mode control based
on how the error signal is fed back to its modulator.
Constant-On Time Control Using the OTM Pin
The power factor describes how well an AC load corresponds to a pure resistance. A flyback transformer
operating in discontinuous conduction mode (DCM) creates a peak primary current described in Equation 2
æ
ö
ç
÷
æV
ö çV
´t
÷
IPEAK = ç BULK ON ÷ = ç BULK ÷
L
æ
ö
M
è
ø ç LM ÷
ç ç tON ÷ ÷
øø
èè
where
•
•
•
LM is the magnetizing inductance of the flyback transformer
tON is the on-time of the flyback switch
(LM/tON) is expressed in units of (µH/s)
(2)
thus,
V
IPEAK = BULK (V / W )
æ LM ö
ç
÷
è tON ø
(3)
If the on-time is limited to a fixed value, then the peak primary current in the transformer is directly proportional to
the bulk supply voltage. Consequently, a flyback operating in DCM with a fixed inductance and fixed on-time
behaves much like a pure resistance and exhibits a power factor close to unity when operating with a small bulk
capacitance. The TPS92210 can easily be configured for constant on-time control, allowing fixed-frequency,
single-stage power factor regulation.
In constant-on time control, the on-time of the primary switch can be programmed by connecting a resistor
(ROTM) between the OTM pin and the quiet return of GND. The on-time can be further modulated by connecting
the collector of the opto-coupler to the OTM pin through a resistor as shown in Figure 21.
On-Time Modulation
and
Fault Response Control
IOTM
Fault Timing
and
Control
VGATE
+
OTM
Latch or Retry
3V
1V
UVLO
Shutdown
and Restart
4
Thermal
Shutdown
UDG-09187
Figure 21. On-Time Modulation Detail
16
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The OTM multi-function pin is also used to program the system response to overload and brownout conditions.
Figure 22 shows how the on-time is programmed over the range of between 1.5 µs and 5 µs for either range of
programming resistors. The resistor range determines the controller response to a sustained overload fault (to
either latch-off or to shutdown/retry) which is the same response for a line-sag, or brown out, condition. The ontime is related to the programmed resistor based on the following equations.
(4)
The on-time for the shutdown/retry response to overcurrent faults is shown in Equation 5.
Wö
æ
ROTM = tOTM ´ ç 2 ´ 1010 ÷
sø
è
(5)
tOTM – Constant On-Time – ms
The on-time for latch-off response to overcurrent faults is show in Equation 4.
Wö
æ
ROTM = tOTM ´ ç 1´ 1011 ÷
sø
è
5
Shutdown/
Retry
Latch-off
1.5
120-kW Threshold Retry vs Latch-off
100120
150
500
ROTM – Constant On-Time Resistance – kW
UDG-09183
Figure 22. On-time Programming Range and Overload Fault Response Selection
The OTM pin can also be used to externally shutdown the converter by pulling the OTM pin low below VOTM(SR)
threshold (typically 1 V). The PWM action is disabled and the controller retries after the shutdown/retry delay of
750 ms.
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Peak-Current Mode Control Using the FB Pin
In peak-current mode control, the FB pin is used to feed back the output error signal to the internal modulator. In
this mode of control, the emitter of the opto-coupler is connected to the FB pin and a resistor (RFB) is connected
from FB to the quiet return of GND to bleed off the dark current of the opto-coupler. The FB pin detects current
input only, and the voltage at this pin is normally 0.7 V. The FB pin interface is outlined in Figure 23.
VVDD
VOUT
IFB
To Modulators
ROPT
0 A < IFB < 210 mA
IFB > 210 mA
IFB = 0 A
Low-Power Mode
Overload
U2
Opto-Coupler
FB
RFB Filter
1
IFB
RFB
TPS92210
GND1
CFB Filter
GND1
TL431
GND2
UDG-09188
Figure 23. FB Pin Details for Peak-Current Mode Control
The FB current (IFB) commands the TPS92210 to operate the flyback converter in one of the three modes
• Frequency Modulation (FM) mode
• Amplitude Modulation (AM) mode
• Low power mode (LPM)
The converter operates in FM mode with a large power load (23% to 100% the peak regulated power). The peak
HVMOSFET current reaches its maximum programmed value and FB current regulates the output voltage by
modulating the switching frequency, which is inversely proportional to tSW. The switching frequency range is
nominally from 30 kHz (23% peak power) to 133 kHz (100% peak power).
18
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SLUS989B – JANUARY 2010 – REVISED SEPTEMBER 2012
Peak
Current
Control
Current
Modulator
IDRN, PK
3
IFB
IFB
Frequency
Modulator
tSW
1/tSW
VGATE
IFB
fSW(max)– Max Switching Frequency – (kHz)
IFB
IDRN,PK(max) – % of Maximum Peak DRN Current – %
The maximum programmable HVMOSFET current, IDRN,PK(max), is set by the resistor on the PCL pin, as
described in Equation 1. The converter operates in AM mode at moderate power levels (2.5% to 23% of the peak
regulated power). The FB current regulates the output voltage by modulating the peak HVMOSFET current from
33% to 100% of the maximum programmed value while the switching frequency is fixed at approximately 30 kHz.
The TPS92210 modulates the voltage on the PCL pin from 3 V to 1 V to vary the commanded peak current, as
shown in Figure 24.
FM
Low Power
Mode
AM
IFB,CNR1 IFB,CNR2
(165 mA) (210 mA)
100
IFB,CNR3
(280 mA)
IFB,CNR3 – IFB,CNR2
(70 mA)
33
IFB,CNR2 – IFB,CNR1
(45 mA)
130
IFB,LPM-HYST
(25 mA)
30
0
50
100
150
200
IFB – Feedback Current – mA
250
300
UDG-09156
Figure 24. FB Pin Based Modulation Modes
The converter operates in LPM at light load (0% to 2.5% of the peak regulated power). The FB current regulates
the output voltage in the Low Power Mode with hysteretic bursts of pulses using FB current thresholds. The peak
HVMOSFET current is 33% of the maximum programmed value. The switching frequency within a burst of pulses
is approximately 30 kHz. The duration between bursts is regulated by the power supply control dynamics and the
FB hysteresis. The TPS92210 reduces internal bias power between bursts in order to conserve energy during
light-load and no-load conditions.
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TRANSFORMER ZERO ENERGY DETECTION
The TPS92210 ensures that the flyback converter always operates in DCM and initiates a new switching cycle
only when the primary transformer has been completely reset or when its energy is zero. The TZE pin is
connected through a resistive divider to the primary-side auxiliary winding for zero energy detection. The
transformer zero energy is detected by monitoring the current sourced out of the TZE pin when the primary bias
winding of the flyback converter is negative with respect to GND. The voltage at this pin is clamped at –160 mV
during the negative excursions of the auxiliary winding. A small delay, between 50 ns and 200 ns, can be added
with CTZE to align the turn-on of the primary switch with the resonant valley of the primary winding waveform
enabling valley switching. Figure 25 shows the waveform on the HVMOSFET drain, the voltage at the TZE pin
and the primary current in the transformer. It also illustrates how CTZE delays the voltage at the TZE pin to cause
the TPS92210 to switch at the resonant valley.
High Voltage
MOSFET Drain
CTZE-Based
Delay
TZE Input
Modulated
Switching Time
Switching Time (tSW)
IDRN (= IPRI)
t – Time
UDG-09184
Figure 25. TZE and HVMOSFET Drain Voltages for Valley Switching
The TPS92210 requires that three conditions are satisfied before it can initiate a new switching cycle.
• The time since the last turn-on edge must be equal to or greater than the time that is requested by the
feedback processor as determined by the feedback current, IFB.
• The time since the last turn-on edge must be longer than the minimum period that is built into the device
(nominally 7.5 µs which equals 133 kHz).
• Immediately following a high-to-low zero crossing of the TZE pin voltage. Or, it has been longer than tWAIT,TZE
since the last zero crossing of the current has been detected
The TZE pin is also used to program the output overvoltage protection or open-LED detection feature. The output
voltage is monitored by TPS92210 by sampling the voltage at the auxiliary winding. The voltage is sampled after
a fixed delay of 1 μs after the internal low-voltage switch has turned off. This allows the auxiliary winding to be
sampled after the bias winding voltage settles from the transient. The output over-voltage threshold is set using
the turns ratio of the auxiliary winding to the output secondary and a resistive divider into the TZE pin. The
controller latches-off on an open-LED fault and requires a power recycle to reset the fault latch (VDD recycling
below fault reset threshold of 6 V). The interface to the TZE pin for zero energy detection and OVP feature is
shown in Figure 26.
20
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NP
NS
NB
RTZE1
TZE
2
RTZE2
Transformer
Zero Energy
Detect
CTZE
OV
Fault
Output
Voltage
Sense
TPS92210
Fault Timing
and Control
5V
UDG-09189
Figure 26. TZE and Output Overvoltage Detection
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Terminal Components (1) (2)
NAME
TERMINAL
DESCRIPTION
æ (K P ´ LM ) ö
RPCL = 33.2k W ´ ç
÷
ç
÷
PIN
è
ø
PCL
3
æ 100kV ö
IDRN(pk ) = ç
÷
è RPCL ø
where
KP = 0.54 W/µH
LM is the minimum value of primary inductance
PIN = POUT/η
η = efficiency
DRN
6
M1, power MOSFET with adequate voltage and current ratings, VGS must have at least 20 V static
rating.
D1, Schottky diode, rated for at least 30 V, placed between DRN and VDD
FB
1
100 kΩ
GND
7
Bypass capacitor to VDD, CBP = 0.1 µF, ceramic
For Latch-Off response to overcurrent faults:
ROTM
OTM
4
=
Wö
æ
tOTM ´ ç 1´ 1011 ÷
sø
è
For shutdown/retry response to overcurrent faults:
ROTM
CVDD =
=
Wö
æ
tOTM ´ ç 2 ´ 1010 ÷
sø
è
IVDD(LPM) ´ tBURST
DVDD(burst )
where
ΔVDD(BURST) is the allowed VDD ripple during burst operation
tBURST is the estimated burst period
The typical CVDD value is approximately 48 µF.
VDD
8
DBIAS must have a voltage rating greater than:
VBULK (max ) ö
æN
÷
VDBIAS =³ VOUT ´ ç PS +
ç NPB
÷
NPB
è
ø
where
VDBIAS is the reverse voltage rating of diode D2
VBULK(max) is the maximum rectified voltage of CBULK at the highest line voltage
VCG
5
CVCG = at least 10xCGS of the HVMOSFET, usually
CVCG = 0.1 µF
RTZE1 =
TZE
2
(VOUT + VF ) ´ N PS
100 mA
RTZE2
=
NPB
TZEOVP ´ RTZE1
æ
NPS
ç VOUT(pk) ´
NPB
è
ö
÷ - TZEOVP
ø
where
VOUT is the average output voltage of the secondary
VF is the forward bias voltage of the secondary rectifier
VOUT(pk) is the desired output overvoltage fault level
(1)
(2)
22
Refer to the Electrical Characteristics Table for all constants and measured values, unless otherwise noted.
Refer to Figure 17 for all component locations in the Terminal Components Table
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SLUS989B – JANUARY 2010 – REVISED SEPTEMBER 2012
REVISION HISTORY
Changes from Original (JANUARY 2010) to Revision A
Page
•
Changed Corrected Pin 2 name ........................................................................................................................................... 1
•
Changed Corrected Pin 2 name ......................................................................................................................................... 12
•
Changed location of Zener diode in Figure 19. .................................................................................................................. 14
Changes from Revision A (DECEMBER 2010) to Revision B
Page
•
Added clarity to conditions in ELECTRICAL CHARACTERISTICS table ............................................................................. 4
•
Changed maximum PCL voltage specification from "1.05" to "1.1" in ELECTRICAL CHARACTERISTICS table .............. 4
•
Changed minimum IFM range for low power mode(LPM) modulation from "50" to "45" in ELECTRICAL
CHARACTERISTICS table ................................................................................................................................................... 4
•
Added clarity to conditions in ELECTRICAL CHARACTERISTICS table ............................................................................. 5
•
Changed minimum TZE low clamp voltage from "–200" to "–220" in ELECTRICAL CHARACTERISTICS table ............... 5
•
Added clarity to FUNCTIONAL BLOCK DIAGRAM .............................................................................................................. 6
•
Added clarity to "conditions" statement in TYPICAL CHARACTERISTICS ......................................................................... 8
•
Added clarity to Figure 23 ................................................................................................................................................... 18
•
Added clarity to Figure 24 ................................................................................................................................................... 19
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PACKAGE OPTION ADDENDUM
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19-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TPS92210D
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
92210
Samples
TPS92210DR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
92210
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
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RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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