TPS92311
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SNVS811B – MAY 2012 – REVISED MAY 2013
Off-Line Primary Side Sensing Converter with PFC
Check for Samples: TPS92311
FEATURES
DESCRIPTION
•
The TPS92311 is an off-line converter specifically
designed to drive high power LEDs for lighting
applications. Features include an integrated 3.75Ω
600V power MOSFET, adaptive constant on-time
control, quasi-resonant switching, and capable of
operating in various topologies via mode selection
pins. The TPS92311 is ideally suited for driving 8W
LED loads and below. Power Factor Correction is
inherent if the TPS92311 is operated in the constant
on-time mode with an adaptive algorithm. Resonant
switching allows for a reduced EMI signature and
increased system efficiency. Low external parts count
is realized with its simplified and high level of
integration. The control algorithm of TPS92311
adjusts the on time with reference to the primary side
inductor peak current and secondary side inductor
discharge time dynamically, the response time of
which is set by an external capacitor. Other
supervisory features of the TPS92311 include cycleby-cycle primary side inductor current limit, VCC
under-voltage lockout, output over-voltage protection
and thermal shutdown. The TPS92311 is available in
16–pin narrow SOIC package.
1
2
•
•
•
•
•
•
Integrated 600V Power MOSFET With Superior
Avalanche Energy Capability
Regulates LED Current Without Secondary
Side Sensing
Adaptive ON-Time Control With Inherent PFC
Critical-Conduction-Mode (CRM) With ZeroCurrent Detection (ZCD) for Valley Switching
Programmable Switch Turn ON Delay
Programmable Constant ON-Time (COT) and
Peak Current Control
Over-Temperature Protection
APPLICATIONS
•
•
LED Lamps: A19 (E26/27, E14), PAR30/38,
GU10
Solid State Lighting
Typical Application
LED+
D4
CIN
0.1 PF
R1
D1
D3
AC
IN
T1
LP
D3
1A 100V
LS
COUT
6±7
LED
R4
20Q
D2
LAUX
R2
*Z1
LED-
R3
CY1
CZCD
TPS92311
*Optional
DZCD
CVCC
SW
SW
SW
SW
NC
NC
ZCD
ISNS
GND
GND
VIN
MODE1
NC
MODE2
COMP
DLY
RISNS
RDLY
CCOMP
Figure 1. Typical Application
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012–2013, Texas Instruments Incorporated
TPS92311
SNVS811B – MAY 2012 – REVISED MAY 2013
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Connection Diagram
Top View
SW
1
16 SW
SW
2
15 SW
NC
3
14 NC
ZCD
4
13 ISNS
GND
5
12 GND
VIN
6
11 MODE1
NC
7
10 MODE2
COMP
8
9
DLY
Figure 2. 16–Lead Narrow SOIC package
PIN DESCRIPTIONS
2
Pin
Name
Description
1, 2, 15, 16
SW
Drain
Application Information
3, 7, 14
NC
No Connection
4
ZCD
Zero crossing detection input
5, 12
GND
Ground
6
VIN
Power supply Input
8
COMP
Compensation network
9
DLY
Delay control input
Connect a resistor from this pin to ground to set the delay
between switching ON and OFF periods.
10
MODE2
Mode selection input 2
Select operating mode for isolated or non-isolated mode.
11
MODE1
Mode selection input 1
Select operating mode for peak current mode or constant ON
time.
13
ISNS
Current sense voltage feedback
Internal power MOSFET drain pin
No connection pin
The pin senses the voltage of the auxiliary winding for zero
current detection.
Circuit ground.
This pin provides power to the internal control
Output of the error amplifier. Connect a capacitor from this pin to
ground to set the frequency response of the LED current
regulation loop.
Switch current sensing input.
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings
(1) (2)
SW to GND
-0.3V to 600V
VCC to GND
-0.3V to 40V
DLY, COMP, ZCD to GND
-0.3V to 7V
ISNS to GND
-0.3V to 7V
MODE1 to GND
-0.3V to 7V
MODE2 to GND
-0.3V to 7V
SW FET Drain Current
Peak
1.2A
Continuous
Continuous Power Dissipation
ESD Susceptibility
Limited by TJ-MAX
Internally Limited
HBM
(3)
Storage Temperature Range
±2 kV
-65°C to +150°C
Junction Temperature (TJ-MAX)
+125°C
Maximum Lead Temperature (Solder and Reflow)
(1)
(2)
(3)
260°C
Absolute maximum ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions for which the
device is intended to be functional, but device parameter specifications may not be ensured. For ensured specifications and test
conditions, see the Electrical Characteristics. All voltages are with respect to the potential at the GND pin, unless otherwise specified.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
Human Body Model, applicable std. JESD22-A114-C.
Operating Conditions
Supply Voltage range VCC
13V to 36V
Junction Temperature (TJ)
Thermal Resistance (θJA)
(1)
-40°C to +125°C
(1)
95°C/W
This RθJA typical value determined using JEDEC specifications JESD51-1 to JESD51-11. However junction-to-ambient thermal
resistance is highly boardlayout dependent. In applications where high maximum power dissipation exists, special care must be paid to
thermal dissipation issues during board design. In high-power dissipation applications, the maximum ambient temperature may have to
be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125°C),
the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the
part/package in the application (RθJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (RθJA × PD-MAX).
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Electrical Characteristics
VCC = 18V unless otherwise indicated. Typicals and limits appearing in plain type apply for TA = TJ = +25°C. Limits appearing
in boldface type apply over the full Operating Temperature Range. Data sheet minimum and maximum specification limits
are specified by design, test or statistical analysis.
Symbol
Min
Typ (1)
Max
Units
VCC Turn on
threshold
23.4 / 23
25.6
27.8 / 29
V
VCCTurn off
threshold
11.1 / 10.4
13
14.7 / 15.7
V
Parameter
Conditions
SUPPLY VOLTAGE INPUT (VCC)
VCC-UVLO
Hysteresis
12.6
ISTARTUP
Startup Current
VCC = VCC-UVLO–3.0V
10
12.5
14.75
µA
IVCC
Operating supply
current
Not switching
0.9
1.2
1.5
mA
65kHz switching
2
mA
ZERO CROSS DETECT (ZCD)
IZCD
ZCD bais current
VZCD-OVP
ZCD over-voltage
threshold
VZCD= 5V
TOVP
Over voltage debounce time
VZCD-ARM
ZCD Arming
threshold
VZCD = Increasing
1.16
1.24
1.3
V
VZCD-TRIG
ZCD Trigger
threshold
VZCD = Decreasing
0.48
0.6
0.77
V
VZCD-HYS
ZCD Hysteresis
VZCD-ARM-VZCD-TRIG
4.1
0.1
1
uA
4.3
4.5
V
3
cycle
0.64
V
COMPENSATION (COMP)
ICOMP-
Internal reference
current for primary
side current
regulation
VCOMP = 2.0V, VISNS = 0V, Measure at
COMP pin
27
µA
gmISNS
ISNS error amp
trans-conductance
Δ VISNS to Δ ICOMP @ VCOMP = 2.0V
100
µmho
VCOMP
COMP operating
range
SOURCE
2.0
3.5
V
1.26
V
DELAY CONTROL (DLY)
VDLY
DLY pin internal
reference voltage
1.21
IDLY-MAX
DLY source current VDLY = 0V
250
1.23
µA
CURRENT SENSE (ISNS)
VISNS-OCP
Over Current
Detection
Threshold
Non isolation mode
0.56
0.61
0.68
V
VISNS-OCP
Over Current
Detection
Threshold
Isolation mode
3.2
3.4
3.6
V
IISNS
Current Sense
Bias Current
VISNS = 5V
-1
1
µA
TOCP
Over current
Detection
Propagation Delay
RSNS = 1K, Measure ISNS pin pulse width
with VSW = 6V
210
ns
660
V
OUTPUT MOSFET (SW FET)
VBVDS
(1)
4
SW to ISNS
breakdown voltage
600
Typical numbers are at 25°C and represent the most likely norm.
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Electrical Characteristics (continued)
VCC = 18V unless otherwise indicated. Typicals and limits appearing in plain type apply for TA = TJ = +25°C. Limits appearing
in boldface type apply over the full Operating Temperature Range. Data sheet minimum and maximum specification limits
are specified by design, test or statistical analysis.
Parameter
Conditions
IDS
SW to ISNS
leakage current
VSW-VISNS = 600V
RDS
SW to ISNS switch
on resistance
TON-MIN
Minimum ON time
330
540
900
ns
TON-MAX
Maximum ON time
28
44
58
µs
TOFF-MIN
Minimum OFF time
1.04
1.5
1.93
µs
TOFF-MAX
Maximum OFF
time
50
70
94
µs
(2)
Min
Typ (1)
Symbol
Max
Units
1.35
µA
Ω
3.75
RSNS = 1K, Measure ISNS pull-down
period with VSW = 6V and VZCD = 0V
THERMAL SHUTDOWN
TSD
Thermal shutdown
temperature
(3)
Thermal Shutdown
hysteresis
(2)
(3)
165
°C
20
°C
High voltage devices such as the TPS92311 are susceptible to increased leakage currents when exposed to high humidity and high
pressure operating environments. Users of this device are cautioned to satisfy themselves as to the suitability of this product in the
intended end application and take any necessary precautions (e.g. system level HAST/HALT testing, conformal coating, potting, etc.) to
ensure proper device operation.
Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ = 165°C (typ.) and
disengages at TJ = 145°C (typ).
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Typical Performance Characteristics
All curves taken at VCC=18V with configuration in typical application for driving seven power LEDs with ILED=350mA shown in
this datasheet. TA=25°C, unless otherwise specified.
15.0
VCC-UVLO vs Temperature
VCC Startup Voltage vs Temperature
28
VCCSTARTUP VOLTAGE (V)
14.5
VCC-UVLO(V)
14.0
13.5
13.0
12.5
12.0
11.5
11.0
-50
80
27
26
25
24
23
22
-25
0
25 50 75
TEMPERATURE (°C)
Figure 3.
100 125
-50
TOFF-MAX vs Temperature
-25
0
25
50
75
TEMPERATURE (°C)
Figure 4.
100 125
TON-MIN vs Temperature
600
78
580
74
TON-MIN(ns)
TOFF-MAX(us)
76
72
70
68
66
64
560
540
520
500
62
60
-50
1.50
480
-25
0
25
50
75
TEMPERATURE ( °C)
Figure 5.
100 125
-50
IVCC-SD vs Temperature
5.2
1.45
VZCD-OVP(V)
IVCC-SD(mA)
100 125
VZCD-OVP vs Temperature
4.8
1.35
1.30
1.25
1.20
1.15
4.6
4.4
4.2
4.0
1.10
3.8
1.05
6
0
25 50 75
TEMPERATURE (°C)
Figure 6.
5.0
1.40
1.00
-50
-25
-25
0
25 50 75
TEMPERATURE (°C)
Figure 7.
100 125
3.6
-50
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-25
0
25 50 75
TEMPERATURE (°C)
Figure 8.
100 125
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Typical Performance Characteristics (continued)
All curves taken at VCC=18V with configuration in typical application for driving seven power LEDs with ILED=350mA shown in
this datasheet. TA=25°C, unless otherwise specified.
1.50
VZCD-ARM vs Temperature
0.80
1.45
0.75
0.70
1.35
VZCD-TRIG(V)
VZCD-ARM(V)
1.40
1.30
1.25
1.20
1.15
0.60
0.56
0.45
1.05
-25
0
25 50 75
TEMPERATURE (°C)
Figure 9.
0.40
-50
100 125
VISNS-OCP (Isolated Mode) vs Temperature
4.2
4.0
0.9
3.8
0.8
3.6
3.4
3.2
0
25 50 75
TEMPERATURE (°C)
Figure 10.
100 125
0.7
0.6
0.5
0.4
3.0
0.3
2.8
2.6
-50
-25
VISNS-OCP (Non-Isolated Mode) vs Temperature
1.0
VISNS-OCP(V)
VISNS-OCP(V)
0.65
0.50
1.10
1.00
-50
VZCD-TRIG vs Temperature
0.2
-25
0
25 50 75
TEMPERATURE (°C)
Figure 11.
100 125
-50
-25
0
25 50 75
TEMPERATURE (°C)
Figure 12.
100 125
RDS vs Temperature
9
8
RDS(ON)( )
7
6
5
4
3
2
1
0
-50
-25
0
25
50
75
TEMPERATURE (°C)
Figure 13.
100
125
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Simplified Internal Block Diagram
SW
VCC
VC1
SW
VREF
SW
BIAS & VRef
SW
UVLO
MODE1
MODE
Decode
ISNS
TSD
MODE2
ZC
ZCD
LEB
GND
ON
VTRIG/VARM
CONTROL
iLimit
LEB
OCP
OVP
TON
TON Peak
Hold
VONpk
VC1
TON
Control
COMP
IREF
GND
D
UVLO
DRV
COMP
OFT
ZC
DELAY
VONpk
ON
IDLY
V/I
DLY
Figure 14. Simplified Block Diagram
APPLICATION INFORMATION
The TPS92311 is an off-line convertor specifically designed to drive LEDs. This device operates in Critical
Conduction Mode (CRM) with adaptive Constant ON-Time control, so that high power factor can be achieved
naturally. The TPS92311can be configured as an isolated or non-isolated off-line converter. Please refer to
TPS92311 typical application Figure 1, on the front page, in the following discussion. The TPS9231 flyback
converter consists of a transformer which includes three windings LP, LS and LAUX, an internal MOSFET Q1 and
inductor current sensing resistor RISNS. Secondary side components are secondary side transformer winding LS,
output diode D3, and output capacitor COUT. An auxiliary winding is required, and serves two functions. Auxiliary
power is developed from the winding to power the TPS92311 after start-up, and detect the zero crossing point
due to the end of a complete switching cycle. During the on-period, Q1 is turned on, and current flows through LP,
Q1 and RISNS to ground, input energy is stored in the primary inductor LP. Simultaneously, the ISNS pin of the
device monitors the voltage of the current sensing resistor RISNS to perform the cycle-by-cycle inductor current
limit function. During the time MOSFET Q1 is off, current flow in LP ceases and the energy stored during the on
cycle is released to output and auxiliary circuits. During Q1 off-time current in the secondary winding LScharges
the output capacitor COUT through D3 and supplies the LED load. During Q1 on-time, COUT is responsible to
supply load current to LED load during subsequent on-period. Also during Q1 off-time current is delivered to the
auxiliary winding through D2 and powers the TPS92311. The voltage across LAUX, VLAUX is fed back to the ZCD
pin through a resistor divider network formed by R2 and R3 to perform zero crossing detection of VLAUX, which
determines the end of the off-period of a switching cycle. The next on period of a new cycle will be initiated after
an inserted delay of 2 x tDLY. The tDLY is programmable by a single resistor connecting the DLY pin and ground.
8
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The setting of the delay time, tDLY will be described in a separate paragraph. During steady state operation, the
duration of the on-period tON can be determined with two different modes: the Constant On-Time (COT) mode
and the Peak Current Mode (PCM), which are configured by setting the MODE1 and MODE2 pins. For the COT
mode, tON is generated by comparing an internal generated saw-tooth waveform with the voltage on the COMP
pin (VCOMP). Since VCOMP is slow varying, tON is nearly constant within an AC line cycle. For the PCM, the onperiod is terminated when the voltage of the ISNS pin (VISNS) reaches a threshold determined by VCOMP. Since
the instantaneous input voltage (AC voltage) varies, tON varies accordingly within an AC line cycle. The duration
of the off-period (tOFF) is determined by the rate of discharging of the secondary current through the transformer.
Also,
(1)
where n is the turn ratio of LP and LS. Figure 15 shows the typical waveforms in normal operation.
VSW
2xtDLY
t
ILP
VCOMP
t
tON
ILS
ILED
VZCD
t
tOFF
VZCD-OVP
VZCD-PEAK
VZCD-ARM
VZCD-TRIG
t
tDLY
Figure 15. Primary and Secondary Side Current Waveforms
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Startup Bias and UVLO
During startup, the TPS92311 is powered from the AC line through R1 and D1 (Figure 1). In the startup state,
most of the internal circuits of the TPS92311 are shut down in order to minimize internal quiescent current. When
VCC reaches the rising threshold of the VCC-UVLO (typically 25.6V), the TPS92311 is operating in a low switching
frequency mode, where tON and tOFF are fixed to 1.5μs and 72μs. When VZCD–PEAK is higher than VZCD-ARM, the
TPS92311 enters normal operation.
VSW
Low Freq state
Steady state
Startup
state
t
VCC
25.6V
13V
t
VZCD
VZCD-OVP
VZCD-ARM
t
Figure 16. Start up Bias Waveforms
Mode Decoder
The TPS92311 is capable of operating in two control modes as an isolated topology, Peak Current Mode (PCM)
or Constant On-Time (COT). The TPS92311 can also be configured in a non-isolated topology using COT
operation. Depending on system requirements, the designer will chose between the two modes of operation.
COT mode gives a high power factor, PCM can achieve a lower output current ripple. COT mode using a nonisolated topology can achieve a higher efficiency and good load regulation. The above modes can be selected by
setting the MODE1 and MODE2 pins according to Table 1.
Table 1. MODE Configuration
10
MODE1
MODE2
Mode of operation
OPEN
OPEN
COT mode using isolated topology
GND
OPEN
PCM using isolated topology
OPEN
GND
COT mode using non-isolated topology
GND
GND
Reserved
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Zero Crossing Detection
To minimized the switching loss of the internal power MOSFET, a zero crossing detection circuit is embedded in
the TPS92311. VLAUX is AC voltage coupled from VSW by means of the transformer, with the lower part of the
waveform clipped by DZCD. VLAUX is fed back to the ZCD pin to detect a zero crossing point through a resistor
divider network which consists of R2 and R3. The next turn on time of Q1 is selected VSW is the minimum, an
instant corresponding to a small delay after the zero crossing occurs. (Figure 17) The actual delay time depends
on the drain capacitance of the Q1 and the primary inductance of the transformer (LP). Such delay time is set by
a single external resistor as described in Delay Setting section.
During the off-period at steady state, VZCD reaches its maximum VZCD-PEAK (Figure 15), which is scalable by the
turn ratio of the transformer and the resistor divider network R2 and R3. It is recommended that VZCD-PEAK is set to
3V during normal operation.
n u VLED +VIN
n u VLED
VSW
tDLY
Figure 17. Switching Node Waveforms
Delay Time Setting
In order to reduce EMI and switching loss, the TPS92311 inserts a delay between the off-period and the onperiod. The delay time is set by a single resistor which connects across the DLY pin and ground, and their
relationship is shown in Figure 18. The optimal delay time depends on the resonance frequency between LP and
the drain to source capacitance of Q1 (CDS). Circuit designers should optimize the delay time according to the
following equation.
(2)
(3)
After determining the delay time, tDLY can be implemented by setting RDLY according to the following equation:
where
•
KDLY = 32MΩ/ns is a constant.
(4)
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60
RDLY(k )
50
40
30
20
10
0
0
400
800
1200 1600
DELAY TIME (ns)
2000
Figure 18. Delay Time Setting
Protection Features
OUTPUT OPEN CIRCUIT PROTECTION
If the LED string is disconnected from the output of the TPS92311, The output voltage (VLED) increases and thus
VZCD-PEAK increases. When VZCD-PEAK is greater than VZCD-OVP for 3 continues switching cycles, the Over Voltage
Protection (OVP) feature is triggered. Switching of Q1 is stopped, and VCC decreases until it drops below the
falling threshold of VCC-UVLO, the TPS92311 restarts, and re-enter into startup state (Figure 20).
OUTPUT SHORT CIRCUIT PROTECTION
If the LED string is shorted, VZCD-PEAK drops, and as VZCD-PEAK drops below VZCD-TRIG, the TPS92311 will enter
low switching frequency operation. During low switching frequency operation, power supplied from LAUX to VCC is
not enough to maintain VCC. If the short remains VCC will drop below the falling threshold of VCC-UVLO, the
TPS92311 will attempt to restart at this time (Figure 19). When the short is removed the TPS92311 will restore to
steady state operation.
12
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VSW
Steady
state
Low freq
state
Low freq
state
t
VCC
25.6V
13V
t
VZCD
VZCD-OVP
VZCD-ARM
t
VLED
t
Figure 19. Output Short Circuit waveforms
OVER CURRENT PROTECTION
Over Current Protection (OCP) limits the drain current of internal MOSFET and prevents inductor / transformer
saturation. When VISNS reaches a threshold, the OCP is triggered and the internal MOSFET will turn off
immediately. The threshold is typically 3.4V and 0.64V when the TPS92311 is using an isolated topology and a
non-isolated topology respectively.
THERMAL PROTECTION
Thermal protection is implemented by an internal thermal shutdown circuit, which activates at 160°C (typically).
In this case, the internal switching power MOSFET will turn off. Capacitor CVCC will discharge until UVLO. When
the junction temperature of the TPS92311 falls back below 130°C, the TPS92311 resumes normal operation.
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Steady state
Startup
state
Low Freq state
VSW
OV state
Steady
state
Disconnect LED
Reconnect LED
Steady
state
Startup
state
Startup
state
Startup
state
Low
Freq
state
VCC
25.6V
13V
VZCD
VZCD-OVP
VZCD-ARM
VLED
ILED
Steady
state
Force output short circuit
Steady
state
Figure 20. Auto Restart Operation
14
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DESIGN EXAMPLE
The following design example illustrates the procedures to calculate the external component values for the
TPS92311 isolated single stage fly-back LED driver with PFC.
Design Specifications:
Input voltage range, VAC_RMS = 85VAC – 132VAC
Nominal input voltage, VAC_RMS(NOM) = 110VAC
Number of LED in serial =7
LED current, ILED = 350mA
Forward voltage drop of single LED = 3.0V
Forward voltage of LED stack, VLED = 21V
Key operating Parameters:
Converter minimum switching frequency, fSW = 75kHz
Output rectifier maximum reverse voltage, VD3(MAX) = 100V
Power MOSFET rating, VQ1(MAX) = 600V (3.75Ω)
Power MOSFET Output Capacitance, CDS = 37pF (estimated)
Nominal output power, POUT = 8W
START UP BIAS RESISTOR
During start up, the VCC will be powered by the rectified line voltage through external resistor, R1. The VCC start
up current, IVCC(SU) must set in the range IVCC(MIN)>IVCC(SU)>ISTARTUP(MAX) to ensure proper restart operation during
OVP fault. In this example, a value of 0.55mA is suggested. The resistance of R1 can be calculated by dividing
the nominal input voltage in RMS by the start up current suggested.
So, R1 = 110V/0.55mA = 200KΩ is recommended.
TRANSFORMER TURN RATIO
The transformer winding turn ratio, n is governed by the internal MOSFET Q1 maximum rated voltage, (VQ3(MAX)),
highest line input peak voltage (VAC-PEAK) and output diode maximum reverse voltage rating (VD3(MAX)). The
output diode rating limits the lower bound of the turn ratio and the internal power MOSFET rating provide the
upper bound of the turn ratio. The transformer turn ratio must be selected in between the bounds. If the
maximum reverse voltage of D3 (VD3(MAX)) is 100V. the minimum transformer turn ratio can be calculated with the
equation in below.
(5)
(6)
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In operation, the voltage at the switching node, VSW must be small than the internal MOSFET maximum rated
voltage VQ1(MAX) , For reason of safety, 10% safety margin is recommended. Hence, 90% of VQ1(MAX) is used in
the following equation.
(7)
where
•
VOS is the maximum switching node overshoot voltage allowed, in this example, 50V is assumed
(8)
As a rule of thumb, lower turn ratio of transformer can provide a better line regulation and lower secondly side
peak current. In here, turn ratio n = 3.8 is recommended.
SWITCHING FREQUENCY SELECTION
TPS92311 can operate at high switching frequency in the range of 60kHz to 150kHz. In most off-line
applications, with considering of efficiency degradation and EMC requirements, the recommended switching
frequency range will be 60kHz to 80kHz. In this design example, switching frequency at 75kHz is selected.
SWITCHING ON TIME
The maximum power switch on-time, tON depends on the low line condition of 85VAC. At 85VAC the switching
frequency was chosen at 75kHz. This transformer design will follow the formulae as shown below.
(9)
(10)
TRANSFORMER PRIMARY INDUCTANCE
The primary inductance, LP of the transformer is related to the minimum operating switching frequency fSW,
converter output power POUT, system efficiency η and minimum input line voltage VAC_RMS(MIN). For CRM
operation, the output power, POUT can be described by the equation in below.
(11)
By re-arranging terms, the transformer primary inductance required in this design example can be calculated with
the equation follows:
(12)
The converter minimum switching frequency is 75kHz, tON is 5.3µs, VAC_RMS(MIN) = 85V and POUT = 8W, assume
the system efficiency, η = 85%. Then,
(13)
From the calculation in above, the inductance of the primary winding required is 0.81mH.
16
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Calculate The Current Sensing Resistor
After the primary inductance and transformer turn ratio is determined, the current sensing resistor, RISNS can be
calculated.
The resistance for RISNS is governed by the output current and transformer turn ratio, the equation in below can
be used.
where
•
VREF is fixed to 0.14V internally.
(14)
Transformer turn ratio, NP : NS is 3.8 : 1 and ILED = 0.35A
(15)
TPS92311
SW
SW
NC
ISNS
GND
SW
SW
NC
ZCD
GND
VIN
NC
COMP
RISNS
MODE1
MODE2
DLY
Figure 21. RISNS Resistor Interface
D2
VCC
L3
R2
ZCD
CZCD
PGND
R3
DZCD
PGND
PGND
Figure 22. Auxiliary Winding Interface to ZCD
Auxiliary Winding Interface To ZCD
In Figure 22, R2 and R3 forms a resistor divider which sets the thresholds for over voltage protection of VLED,
VZCD-OVP, and VZCD-PEAK. Before the calculation, we need to set the voltage of the auxiliary winding, VLAUX at open
circuit.
For example :
Assume the nominal forward voltage of LED stack (VLED) is 21V.
To avoid false triggering ZCDOVP voltage threshold at normal operation, select ZCDOVP voltage at 1.3 times of the
VLED is typical in most applications. In case the transformer leakage is higher, the ZCDOVP threshold can be set
to 1.5 times of the VLED.
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In this design example, open circuit AUX winding OVP voltage threshold is set to 30V. Assume the current
through the AUX winding is 0.4mA typical.
As a result, R2 is 66kΩ and R3 is 11kΩ. Also, for suppressing high frequency noise at the ZCD pin, a 15pF
capacitor connects the ZCD pin to ground is recommended.
Auxiliary Winding Vcc Diode Selection
The VCC diode D2 provides the supply current to the converter, low temperature coefficient , low reverse
leakage and ultra fast diode is recommended.
Compensation Capacitor And Delay Timer Resistor Selection
To achieve PFC function with a constant on time flyback converter, a low frequency response loop is required. In
most applications, a 3.3µF CCOMP capacitor is suitable for compensation.
TPS92311
DZCD
CVCC
CCOMP
SW
SW
SW
SW
NC
NC
ZCD
ISNS
GND
GND
MODE1
VIN
NC
MODE2
COMP
DLY
RISNS
RDLY
Figure 23. Compensation and DLY Timer connection
The resistor RDLY connecting the DLY pin to ground is used to set the delay time between the ZCD trigger to
power MOSFET turn on. The delay time required can be calculated with the parasitic capacitance at the drain of
MOSFET to ground and primary inductance of the transformer. Equation in below can be used to find the delay
time and Figure 18 in previous page can help to find the resistance once the delay time is calculated
(16)
For example, using a transformer with primary inductance LP = 1mH, and power MOSFET drain to ground
capacitor CDS=37pF, the tDLY can be calculated by the upper equation. As a result, tDLY=302ns and RDLY is
6.31kΩ. The delay time may need to change according to the primary inductance of the transformer. The typical
level of output current will shift if inappropriate delay time is chosen.
Output Flywheel Diode Selection
To increase the overall efficiency of the system, a low forward voltage schottky diode with appropriate rating
should be used.
Primary Side Snubber Design
The leakage inductance can induce a high voltage spike when power MOSFET is turned off. Figure 24 illustrates
the operation waveform. A voltage clamp circuit is required to protect the power MOSFET. The voltage of
snubber clamp (VSN) must be higher than the sum of over shoot voltage (VOS), LED open load voltage multiplied
by the transformer turn ratio (n). In this examples, the VOS is 50V and LED maximum voltage, VLED(MAX) is 30V,
transformer turn ratio is 3.8. The snubber voltage required can be calculated with following equations.
18
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VOS
VSN
VMOS_BV
n u VLED
VAC_PEAK
Vsw
Figure 24. Snubber Waveform
where
•
n is the turn ratio of the transformer.
(17)
(18)
At the same time, sum of the snubber clamp voltage and VAC peak voltage (VAC_PEAK) must be smaller than the
MOSFET breakdown voltage (VMOS_BV). By re-arranging terms, equation in below can be used.
(19)
In here, snubber clamp voltage, VSN = 250V is recommended.
Output Capacitor
The capacitance of the output capacitor is determined by the equivalent series resistance (ESR) of the LED,
RLED and the ripple current allowed for the application. The equation in below can be used to calculate the
required capacitance.
(20)
Assume the ESR of the LED stack contains 7 LEDs and is 2.6Ω, AC line frequency fAC is 60Hz.
In this example, LED current ILED is 350mA and output ripple current is 30% of ILED:
(21)
Then, COUT = 480μF.
In here, a 470μF output capacitor with 10μF ceramic capacitor in parallel is suggested.
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PCB Layout Considerations
The performance of any switching power supplies depend as much upon the layout of the PCB as the
component selection. Good layout practices are important when constructing the PCB. The layout must be as
neat and compact as possible, and all external components must be as close as possible to their associated
pins. High current return paths and signal return paths must be separated and connect together at single ground
point. All high current connections must be as short and direct as possible with thick traces. The SW pin of the
internal MOSFET should be connected close to the transformer pin with short and thick trace to reduce potential
electro-magnetic interference. For off-line applications, one more consideration is the safety requirements. The
clearance and creepage to high voltage traces must be complied to all applicable safety regulations.
L1 3.3 mH
NP : NS : NAUX = 3.8 : 1 : 1
LED+
D3
1A 100V
250V
D1
0.5A 600V
0.5A
CIN
0.1 PF
R1a
100k
T1
C1
0.1PF
LS COUTa
10 PF
LP
1A 600V
90-135VAC
CAC
47 nF
VR1
R1b
100k
D2
BAV20
COUTb
470 PF
6±7
LED
R4
20Q
RAC
22: / 1W
ZCD
R2
66 kQ
CZCD
15p
R3
11 kQ
LAUX
35V*
SCR*
LED2200 pF
CY1
6k*
DZCD
CUSU4148
10 F
*Optional for short circuit protection
CVCC
3.3 F
CCOMP
SW
SW
SW
SW
NC
NC
ZCD
ISNS
GND
GND
VIN
MODE1
NC
MODE2
COMP
DLY
TPS92311
RISNS 1.52Q
RDLY
6.34k
Figure 25. Isolated topology schematic
20
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L1
3.3 mH
0.5A 600V
0.5A
D1
C1
0.1 PF
CIN
0.1 PF
R1a
100 k:
NP:NAUX = 1:1
LP = LS
90-135
VAC
VR1
R1b
100 k:
CAC
47 nF
D2
0.1A 600V
R4 20Q
T1
RAC
LAUX
COUT
6-7
LED
470 PF
R2
68 k:
22: 1W
35V*
R3
11 k:
CZCD
15 pF
D3
1A 600V
SCR*
6k*
DZCD
CUSU4148
* Optional for short circuit protection
10 F
3.3 F
CVCC
CCOMP
SW
SW
SW
SW
NC
NC
ZCD
ISNS
GND
GND
MODE1
VIN
NC
MODE2
DLY
COMP
TPS92311
RISNS 0.4Ÿ
RDLY
6.34k
Figure 26. Non-isolated topology schematic
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REVISION HISTORY
Changes from Revision A (May 2013) to Revision B
•
22
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 21
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