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TPS92515, TPS92515-Q1, TPS92515HV, TPS92515HV-Q1
SLUSBZ6A – APRIL 2016 – REVISED AUGUST 2016
TPS92515x 2-A, Buck LED Driver with Integrated N-channel FET,
High-Side Current Sense, and Shunt FET PWM Dimming Capability
1 Features
•
•
•
1
•
•
•
•
•
•
•
AEC-Q100 Grade 1 Qualified
Integrated 290-mΩ (typ) Internal N-Channel FET
Input Voltage Range:
– TPS92515x: 5.5 V to 42 V
– TPS92515HVx: 5.5 V to 65 V
– Operation Down to 5.15 V After Start-Up
Low Offset High-side Peak Current Comparator
Constant Average Current, up to 2 A
Inherent Cycle-by-Cycle Current Limit
Multiple Dimming Methods
– 10,000:1 Shunt PWM Dimming Range
– 1000:1 PWM Dimming Range
– 200:1 Analog Dimming Range
Simple Constant Off-time Control
– No Loop Compensation
– Fast Transient Response
Thermally Enhanced HVSSOP Package
Integrated Thermal Protection
2 Applications
•
•
•
•
Automotive Lighting: LED Switched Matrix AFS
Headlamps, DRL, High/Low Beam, Fog, Rear,
Turn Signal, Side Marker, Aftermarket
Industrial Lighting: Factory Automation, Time of
Flight (TOF), Appliances, Retail Illumination,
Machine Vision and Inspection, Emergency, Exit
and/or Safety Lighting, Medical Lighting, Stage
and Area Lighting
Agricultural, Marine, and Heavy Industry Lighting
High Contrast Shunt FET Dimming
The regulator operates using a constant off-time,
peak current control. The operation is simple: after an
off-time based on the output voltage, an on-time
begins. The on-time ends once the inductor peak
current threshold is reached. The TPS92515 device
can be configured to maintain a constant peak-topeak ripple during the ON and OFF periods of a
shunt FET dimming cycle. This is ideal for
maintaining a linear response across the entire shunt
FET dimming range.
Steady-state accuracy is aided by the inclusion of a
low-offset, high-side comparator. LED current can be
modulated using either Analog or PWM dimming, or
both simultaneously. Other features include UVLO,
wide input voltage operation, inherent LED Open
operation and wide operating temperature range with
thermal shut-down.
The TPS92515 and TPS92515-Q1 devices have an
operational input range up to 42 V. The TPS92515HV
and TPS92515HV-Q1 offer high-voltage options with
an input range up to 65 V. All are available in a
thermally enhanced 10-pin HVSSOP package.
Device Information(1)
PART NUMBER
TPS92515-Q1
TPS92515HV
BODY SIZE (NOM)
HVSSOP (10)
3 mm x 3 mm
TPS92515HV-Q1
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Buck LED Driver Application
TPS92515
6
DRN
7
CSN
8
VIN
9
PWM
3 Description
The TPS92515 family of devices are compact
monolithic switching regulators integrating a low
resistance N-Channel MOSFET. The devices are
intended for high-brightness LED lighting applications
where efficiency, high bandwidth, PWM and/or analog
dimming and small size are important.
PACKAGE
TPS92515
VIN
10 IADJ
SW
5
BOOT
4
GND
3
VCC
2
COFF
1
VOUT
PAD
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS92515, TPS92515-Q1, TPS92515HV, TPS92515HV-Q1
SLUSBZ6A – APRIL 2016 – REVISED AUGUST 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
7.1
7.2
7.3
7.4
7.5
7.6
4
4
4
4
5
7
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information.................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 9
8.1
8.2
8.3
8.4
Overview ................................................................... 9
Functional Block Diagram ......................................... 9
Feature Description................................................. 10
Device Functional Modes........................................ 20
9
Application and Implementation ........................ 21
9.1 Application Information............................................ 21
9.2 Typical Application ................................................. 21
9.3 Dos and Don'ts ....................................................... 29
10 Power Supply Recommendations ..................... 30
10.1 Input Source Direct from Battery........................... 30
10.2 Input Source from a Boost Stage ......................... 30
11 Layout................................................................... 30
11.1 Layout Guidelines ................................................. 30
11.2 Layout Example .................................................... 31
12 Device and Documentation Support ................. 32
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support .......................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
32
32
32
32
32
32
13 Mechanical, Packaging, and Orderable
Information ........................................................... 32
4 Revision History
Changes from Original (April 2016) to Revision A
•
2
Page
Data sheet status changed from Product Preview to Production Data ................................................................................. 1
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TPS92515, TPS92515-Q1, TPS92515HV, TPS92515HV-Q1
www.ti.com
SLUSBZ6A – APRIL 2016 – REVISED AUGUST 2016
5 Device Comparison Table
MAXIMUM
VOLTAGE (V)
DEVICE
TPS92515HV-Q1
65
TPS92515-Q1
42
TPS92515HV
65
TPS92515
42
LM3409HV-Q1
75
LM3409-Q1
42
LM3409HV
75
LM3409
42
LM3406HV-Q1
75
LM3406-Q1
42
LM3406HV
75
LM3406
42
AUTOMOTIVE
QUALIFIED
CONTROL METHOD
Y
Internal N-channel FET, constant OFF-time
Y
N
N
External P-channel FET, constant OFF-time
External P-channel FET, constant OFF-time
Y
Y
N
N
Y
Internal N-channel FET, controlled ON-time
Y
N
N
6 Pin Configuration and Functions
DGQ Package
HVSSOP 10-Pin with PowerPAD
Top View
COFF
1
10
IADJ
VCC
2
9
PWM
GND
3
8
VIN
BOOT
4
7
CSN
SW
5
6
DRN
Thermal Pad
Table 1. Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
BOOT
4
I
Connect a ceramic capacitor between BOOT and SW and a diode from VCC to BOOT to
power the high-side FET drive circuitry.
COFF
1
I
Connect a resistor from VOUT, and a capacitor to GND to set the OFF-time.
CSN
7
I
Current sense negative input. Connect current sense resistor from VIN to CSN for high-side
current sense control.
DRN
6
I
Internal FET drain. Connect to CSN node
GND
3
G
Ground
IADJ
10
I
Output current adjust. Connect to an external divider, reference or tie to VCC.
PWM
9
I
PWM dimming input. Connect to PWM control signal. Output current is pulse-width
modulated (PWM) dimmed from the maximum analog controlled level. Connect to VCC if not
used.
SW
5
O
Internal FET Source. Connect to output inductor
VCC
2
O
5-V Regulator Output. Use a decoupling capacitor from VCC to ground. See section on VCC
capacitor selection.
VIN
8
I
Connect to input voltage. VIN is also the current sense positive input.
Thermal pad
—
Copyright © 2016, Texas Instruments Incorporated
Connect to ground
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TPS92515, TPS92515-Q1, TPS92515HV, TPS92515HV-Q1
SLUSBZ6A – APRIL 2016 – REVISED AUGUST 2016
www.ti.com
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VIN, DRN, CSN to GND
SW to GND
MIN
MAX
TPS92515, TPS92515-Q1
–0.3
45.0
TPS92515HV, TPS92515HV-Q1
–0.3
65.0
TPS92515, TPS92515-Q1
-1.0
45.0
TPS92515HV, TPS92515HV-Q1
-1.0
65.0
TPS92515, TPS92515-Q1
–0.3
45.0
TPS92515HV, TPS92515HV-Q1
–0.3
65.0
TPS92515, TPS92515-Q1
–0.3
50.5
TPS92515HV, TPS92515HV-Q1
–0.3
70.5
COFF, IADJ, PWM to GND
–0.3
5.5
BOOT to SW
–0.3
5.5
VCC to GND
-0.3
5.5
–0.3
0.3
DRN to SW
BOOT to GND
VIN to CSN
SW to GND, 10-ns transient
(2)
(2)
V
–2.0
Storage temperature, Tstg
(1)
UNIT
-40
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DRN to SW. Absolute maximum not to be exceeded.
7.2 ESD Ratings
VALUE
Electrostatic
discharge
V(ESD)
(1)
Human-body model (HBM), per AEC Q100-002
(1)
UNIT
±2000
Charged-device model (CDM), per AEC Q100-011
V
±750
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
TPS92515, TPS92515-Q1
5.5
42
TPS92515HV, TPS92515HV-Q1
5.5
65
UNIT
VIN
Input voltage
TA
Operating ambient temperature
125
°C
TJ
Operating junction temperature
150
°C
7.4
V
Thermal Information
TPS92515
THERMAL METRIC (1)
HVSSOP
UNIT
10 PINS
RθJA
Junction-to-ambient thermal resistance
56.2
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
44.7
°C/W
RθJB
Junction-to-board thermal resistance
32.1
°C/W
ψJT
Junction-to-top characterization parameter
1.5
°C/W
ψJB
Junction-to-board characterization parameter
31.8
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
5.3
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and device Package Thermal Metrics
application report, SPRA953.
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SLUSBZ6A – APRIL 2016 – REVISED AUGUST 2016
7.5 Electrical Characteristics
VIN = 40 V, –40°C ≤ TJ ≤ 150°C, VBOOT is referenced to SW pin, unless otherwise specified.
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
VIADJ = VCC
224
VIADJ = 2.2 V
211.5
240
251
mV
220
223.5
PEAK CURRENT COMPARATOR
VCST
VIN– VCSN peak current threshold
AADJ
VIADJ to VIN – VCSN threshold gain 0.1 ≤ VIADJ ≤ 2.2 V
ICSN
Current sense pin, input bias
current
tDEL
CSN pin falling delay
CSN fall to SW fall
tLEB
Minimum ON-time
Minimum pulse width
0.1
–5
mV
V/V
0
µA
75
130
ns
195
275
ns
Not switching, VIADJ = VVCC
0.85
1.5
mA
IDRN-SW = 200mA, VBOOT = 5 V,
TJ = 25°C
290
500
IDRN-SW = 200mA, VBOOT = 5 V,
TJ = 150°C
290
600
IDRN-SW = 200mA, VBOOT = 3.5 V,
TJ = 25°C
310
500
IDRN-SW = 200mA, VBOOT = 3.5 V,
TJ = 150°C
310
650
75
SYSTEM CURRENTS
Icq
Operating current
INTEGRATED N-Channel MOSFET AND DRIVER
RDS(on)
FET ON-resistance
IDRN-SW(off)
FET leakage current
VDRN-SW = 6 V, VSW = 0 V
VBOOT-UVLO
Voltage where gate drive is
disabled
VBOOT falling
VBOOT-UVLO(hys)
BOOT pin UVLO Hysteresis
IPD(PWM/UVLO)
Pull down from SW when PWM
low.
PWM low, VBOOT = 5 V , VSW = 8 V
IPD(BOOT)
Pull down from SW when VBOOT
reaches VBOOT-UVLO
PWM high, VBOOT < BOOT-UVLO, VSW
=8V
IBOOT_Q
BOOT pin quiescent current
VBOOT = 5.5 V, 0 V ≤ VSW ≤ 65 V
mΩ
10
2.0
2.8
µA
3.5
125
V
mV
100
130
µA
5
7
mA
60
90
µA
5.0
5.2
V
0.1
0.2
V
4.2
4.4
V
VCC/REFERENCE REGULATOR
VCC
Regulated pin voltage
IVCC(ext) ≤ 500 µA
VCCDO
Drop out voltage
IVCC(ext) ≤ 500 µA
VCCUVLO
VCC undervoltage lockout
Falling threshold, VIN = 10 V
VCCUVLO_hys
VCC undervoltage lockout
hysteresis
IVCC(ILIM)
VCC regulator current limit
VINUVLO
VINUVLO_hys
4.8
4.0
0.22
VCC shorted to GND
V
14
19
23
mA
VIN UVLO Falling Threshold
4.65
4.90
5.15
V
VIN UVLO Hysteresis
150
190
225
mV
VOFT
OFF-time threshold
0.95
1.00
1.05
V
tD(off)
COFF threshold
68
120
tOFF(max)
Maximum OFF-time
OFF-TIMER
COFF to SW rising delay
230
ns
µs
PWM/UVLO (Enable)
IPWM(uvlo)
PWM/UVLO pin current
VPWM(uvlo) = 5.5 V
VPWM(uvlo)
PWM/UVLO pin threshold
PWM pin rising
VPWM(uvlo-hys)
PWM/UVLO pin hysteresis
Difference between rising and falling
threshold
tPWM(uvlo)
PWM/UVLO pin delay
IPWM(uvlo-hys)
PWM/UVLO hysteresis current
Copyright © 2016, Texas Instruments Incorporated
10
nA
0.95
1.0
1.05
V
50
100
150
mV
PWM pin rising to SW pin rising
75
130
ns
PWM pin falling to SW pin falling
100
170
ns
–20
–15
μA
VPWM(uvlo) = 2 V
–25
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www.ti.com
Electrical Characteristics (continued)
VIN = 40 V, –40°C ≤ TJ ≤ 150°C, VBOOT is referenced to SW pin, unless otherwise specified.
THERMAL SHUTDOWN
TSD
Thermal shutdown temperature
TSD(hyst)
Thermal shutdown hysteresis
6
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175
10
°C
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TPS92515 TPS92515-Q1 TPS92515HV TPS92515HV-Q1
TPS92515, TPS92515-Q1, TPS92515HV, TPS92515HV-Q1
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SLUSBZ6A – APRIL 2016 – REVISED AUGUST 2016
7.6 Typical Characteristics
225
245
224
244
223
243
222
242
221
241
VCST (mV)
VCST (mV)
TJ = TA = 25°C unless otherwise specified. Characteristics are identical for TPS92515x and TPS92515HVx. VIN >42 V curves
apply to TPS92515HVx only.
220
219
240
239
218
238
217
237
216
236
215
-40
-20
0
VIADJ = 2.2 V
20
40
60
80 100
Junction Temperature (oC)
120
140
235
-40
160
VIN = 40 V
IVCC= 0mA
IVCC=4mA
140
160
D009
VIN = 40 V
1.002
VOFF - COFF Threshold (V)
VCC Voltage (V)
120
Figure 2. VCST vs. Junction Temperature
1
0.998
0.996
0.994
Vin=6
Vin=40
Vin=65
0.992
-20
0
20
40
60
80 100
Junction Temperature (oC)
120
140
0.99
-40
160
tD(OFF) - COFF to SW Rising Delay (ns)
84
82
80
78
76
74
72
0
20
40
60
80 100
Junction Temperature (oC)
0
120
140
20
40
60
80 100
Junction Temperature (oC)
120
140
160
D011
Figure 4. VOFF vs. Junction Temperature
86
-20
-20
D021
Figure 3. VCC vs. Junction Temperature
tDEL - CSN Falling Delay (ns)
20
40
60
80 100
Junction Temperature (oC)
1.004
88
70
-40
0
VIADJ = VCC
Figure 1. VCST vs. Junction Temperature
5.1
5.09
5.08
5.07
5.06
5.05
5.04
5.03
5.02
5.01
5
4.99
4.98
4.97
4.96
4.95
-40
-20
D008
160
74
73.5
73
72.5
72
71.5
71
70.5
70
69.5
69
68.5
68
67.5
67
66.5
-40
D012
-20
0
20
40
60
80 100
Junction Temperature (oC)
120
140
160
D013
VIN = 40 V
VIN = 6 V
Figure 5. CSN Pin Falling Delay Time vs. Junction
Temperature
Copyright © 2016, Texas Instruments Incorporated
Figure 6. Off-Time Delay vs. Junction Temperature
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Typical Characteristics (continued)
TJ = TA = 25°C unless otherwise specified. Characteristics are identical for TPS92515x and TPS92515HVx. VIN >42 V curves
apply to TPS92515HVx only.
1.05
205
ILED (A) and Efficiency (X100%)
202.5
200
197.5
tLEB (ns)
195
192.5
190
187.5
185
182.5
Vin=6
Vin=40
Vin=65
180
177.5
175
-40
-20
0
20
40
60
80 100
Junction Temperature (oC)
120
140
1.03
1.01
0.99
ILED
Efficiency (%)
0.97
0.95
0.93
0.91
0.89
0.87
30
160
35
60
65
D015
RSENSE = 0.196 Ω
1.04
ILED (A) and Efficiency (X100%)
ILED (A) and Efficiency (X100%)
55
Figure 8. EVM Configuration Result
1.04
1.02
ILED (Amps)
Efficiency
1
0.98
0.96
40
42
44
VIN (V)
VIADJ=2.4 V
46
48
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50
1.02
1
ILED (Amps)
Efficiency
0.98
0.96
0.94
0.92
0.9
30
31
32
33
34
D016
RSENSE = 0.196 Ω
Figure 9. EVM Configuration Result
8
50
VIADJ=2.4 V
Figure 7. Leading-Edge Blanking Time vs. Junction
Temperature
VLED = 35 V
45
VIN
VLED = 22 V
0.94
38
40
D014
VLED = 13 V
35
36
VIN (V)
VIADJ=2.4 V
37
38
39
40
D017
RSENSE = 0.196 Ω
Figure 10. EVM Configuration Result
Copyright © 2016, Texas Instruments Incorporated
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SLUSBZ6A – APRIL 2016 – REVISED AUGUST 2016
8 Detailed Description
8.1 Overview
The TPS92515 is an internal N-channel MOSFET (monolithic NFET) hysteric control, buck regulator. Hysteretic
operation allows a high control bandwidth and is ideal for shunt FET and LED matrix applications (series LED
switched network). The high-side differential current sense with low adjustable threshold voltage via a 10:1
divider, provides an excellent method for regulating output current while maintaining high system efficiency. The
device uses a controlled OFF-time (COFT) architecture to allow the converter to operate in both continuous
conduction mode (CCM) and discontinuous conduction mode (DCM) with no external control loop compensation,
and provides an inherent cycle-by-cycle current limit.
The adjustable current sense threshold provides the capability for analog dimming the LED current over the full
range and the PWM dimming input allows for high-frequency PWM dimming control requiring no external
components. Configuration options allow for easy implementation of external shunt FET dimming. See also the
OFF-Timer, Shunt FET Dimming or Shunted Output Condition section.
The device does not internally limit the maximum attainable average LED current. It does have a thermal limit
based on the maximum junction temperature. The maximum junction temperature is a function of the system
operating points (efficiency, ambient temperature, thermal management), component choices, and switching
frequency. This functionality allows the device to provide constant currents up to 1 A in a wide variety of
applications and up to 2 A in a smaller sub-set of applications. This simple regulator contains all the features
necessary to implement a high-efficiency, versatile, high-performance LED driver.
8.2 Functional Block Diagram
R
VIN
+
IADJ
2.4 V
+
+
R
CSN
10 R
VCC
Regulator
VCC
LEB
VCCUVLO
T
DRN
Thermal
Shutdown
T
Thermal
Shutdown
Gate
20 µA
Internal
N-channel FET
5 NŸ
PWM
SW
+
Control
Logic
1.0 V
Boot
UVLO
BOOT
COFF
+
5 mA
1.0 V
100 µA
Gate
250-µs (max)
off-time
VCCUVLO
PWM
GND
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8.3 Feature Description
8.3.1 General Operation
The TPS92515 operates using a peak-current, constant OFF-time as described in Figure 11. Two states dictate
the high-side FET control. The switch turns on and stays on until the programmed peak current is reached. The
peak current is controlled by monitoring the voltage across the sense resistor. When the voltage drop is higher
than the programmed threshold, the peak current is reached, and the switch is turned OFF, which initiates the
OFF-time period. A capacitor on the COFF pin is then charged through a resistor connected to the output. When
the COFF pin voltage reaches the 1-V (typical) threshold, the OFF-time ends. The COFF pin capacitor resets
and the main switch turns ON, and the next cycle begins.
VIADJ and RSENSE
adjust
the peak inductor
current
The Inductance
(L) and tOFF define
'IL-PP
The average output current
equals the peak minus half
the peak to peak inductor
ripple
ûIL-PP = (VLED * tOFF ) / L
ILave = ILED = IL-Peak ± (ûIL-PP / 2)
IL-Peak = [ VIADJ /10 ] / RSENSE
tON
t
tOFF
Figure 11. Hysteretic Operation
Although commonly referred to as constant OFF-time, the OFF-time control voltage is normally derived from the
output voltage. This connection ensures constant peak-to-peak ripple. To maintain a constant ripple over various
input and output voltages, the converter OFF-time becomes shorter or longer resulting in a change in frequency.
If the input voltage and output voltage are relatively constant, the frequency also remains constant. If either the
input voltage or the output voltage changes, the frequency changes. For a fixed input voltage, the device
operates at the maximum frequency at 50% duty cycle and the frequency reduces as the duty cycle becomes
shorter or longer. A graphical representation is shown in Figure 12. For a fixed output voltage (VLED), the
frequency is always the maximum at the highest input voltage as shown in Figure 13.
10
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SLUSBZ6A – APRIL 2016 – REVISED AUGUST 2016
Frequency (Hz)
Frequency (Hz)
Feature Description (continued)
0
VIN/2
Output Voltage (V)
Maximum
Fixed input voltage
65
Input Voltage (V)
Fixed LED voltage
Figure 12. Frequency vs LED Output Voltage
Figure 13. Frequency vs Input Voltage (VIN)
By making the OFF-time proportional to the output voltage, it is possible to illustrate how VLED can be removed
from the output current equation. When VLED >> VOFT , the output ripple can be defined as shown in Equation 1.
ΔIL-PP = (VLED x dt)/L
where
•
dt is defined by the OFF-timer
(1)
.
dt
Cdv
i
COFF (1V)
ª VLED º
«R
»
¬ OFF ¼
COFFR OFF (1V)
VLED
(2)
Substitute dt in Equation 1 to create Equation 3.
'IL
ILED
PP
Vdt
L
VLEDdt
L
VIADJ
10
RSENSE
ª C R (1V) º
VLED « OFF OFF
»
VLED
¬
¼
L
COFFROFF (1V)
L
(3)
COFFROFF (1V)
2L
(4)
When VLED >≈ 10 V, use the ILED calculation Equation 4. The Detailed Design Procedure section describes a
design example that uses the more detailed equation. A VLED > 10 V ensures a linear charging ramp below 1 V.
If VLED
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