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TPS92518-Q1
SLUSCZ1 – MAY 2017
TPS92518-Q1 Automotive Dual Channel Buck LED Controller with SPI Interface,
Analog and PWM Dimming
1 Features
3 Description
•
The TPS92518-Q1 family of parts are dual channel
buck LED current controllers with a SPI
communications interface. The serial communication
interface provides a singular communication path for
multichannel and platform lighting driver module
(LDM) applications.
1
•
•
•
•
AEC-Q100 Qualified for Automotive Applications
– Grade 1: –40°C to 125°C Ambient Operating
Temperature
– Device HBM Classification Level H2
– Device CDM Classification Level C5
Wide Input Voltage Range 6.5 V to 65 V
Two independent Buck LED Controllers
– High Bandwidth, Quasi-Hysteretic Control
– Adjustable High-Side Sense
– Direct PWM Dimming Input
– Cycle-by-Cycle Current Limit
SPI Communications Interface
– Software configurable Set Points (8-bit)
– Digital Calibration and Binning
– Fault Monitoring and Reporting
Advanced, High Precision Dimming
– 10,000:1 PWM Dimming Range
– 255:1 Analog Dimming Range
– High Frequency Shunt FET Dimming
The TPS92518-Q1 uses a quasi-hysteretic control
method that supports switching frequencies ranging
from 1 kHz to 2 MHz. This control method enables
superior, high frequency shunt FET dimming and also
handles the demanding dynamic loads of adaptive
LED matrix based headlamp systems.
Software programmable SPI set points (Precision
Peak Current, Controlled Off-Time and Output
Voltage Sense) enables designers to develop a single
LED driver solution for multiple load configurations
that can be quickly reconfigured for future LED driver
design requirements.
The TPS92518-Q1 device has an input range up to
42 V. The TPS92518HV-Q1 is a high-voltage option
with an input range up to 65 V.
Device Information(1)
PART NUMBER
2 Applications
•
•
•
•
•
TPS92518-Q1
Automotive LED Lighting: High and Low Beam,
DRL, Turn, Position
Constant Current LED Driver
Switched Matrix Headlamps
AFS Headlamps
LED General Lighting
TPS92518HV-Q1
PACKAGE
BODY SIZE (NOM)
HTSSOP (24)
7.7 mm x 4.4 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
Input Voltage
Battery or Boost
Regulator
Buck CH1
EN/UV
µC
PWM2
x
x
x
x
x
Peak
Off time
Enable
Faults
Temp
VLED1
PWM1
SPI
TPS92518-Q1
Input Voltage
Buck CH2
VLED2
MCU VCC
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS92518-Q1
SLUSCZ1 – MAY 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
5
5
7
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information .................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
8.5 Registers ................................................................. 29
8.6 Programming .......................................................... 41
9
9.1 Application Information............................................ 43
9.2 Typical Application ................................................. 43
9.3 Dos and Don'ts ....................................................... 45
10 Power Supply Recommendations ..................... 46
10.1 Input Source Direct from Battery........................... 46
10.2 Input Source from a Boost Stage.......................... 46
11 Layout................................................................... 47
11.1 Layout Guidelines ................................................. 47
11.2 Layout Example .................................................... 47
12 Device and Documentation Support ................. 48
Parameter Measurement Information .................. 9
12.1
12.2
12.3
12.4
12.5
7.1 CSN Pin Falling Delay (tDEL)..................................... 9
7.2 Off-Timer (tOFF) ........................................................ 9
8
Detailed Description ............................................ 10
8.1
8.2
8.3
8.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Serial Interface ........................................................
Application and Implementation ........................ 43
10
11
12
25
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
48
48
48
48
48
13 Mechanical, Packaging, and Orderable
Information ........................................................... 48
4 Revision History
2
DATE
REVISION
NOTES
May 2017
*
Initial release.
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5 Pin Configuration and Functions
PWP Package
24-Pin HTTSOP
Top View
VIN
1
24
EN/UV
CSP1
2
23
CSP2
CSN1
3
22
CSN2
GATE1
4
21
GATE2
SW1
5
20
SW2
BOOT1
6
19
BOOT2
VCC1
7
18
VCC2
GND
8
17
GND
VLED1
9
16
VLED2
PWM1
10
15
PWM2
SSN
11
14
MOSI
SCK
12
13
MISO
Pin Functions
PINS
NAME
NO.
I/O
DESCRIPTION
BOOT1
6
I
Channel 1 bootstrap voltage input
BOOT2
19
I
Channel 2 bootstrap voltage input
CSN1
3
I
Channel 1 negative current sense input
CSN2
22
I
Channel 2 negative current sense input
CSP1
2
I
Channel 1 positive current sense input
CSP2
23
I
Channel 2 positive current sense input
EN/UV
24
I
Device enable. If not configured as under voltage lock out or enable, tie to VCCx. Tie to >23.6V to bypass SPI
communication and enable default register values.
GATE1
4
O
Channel 1 gate drive output. Connect to FET gate
GATE2
21
O
Channel 2 gate drive output. Connect to FET gate
G
System ground
GND
8
17
MISO
13
O
SPI data output
MOSI
14
I
SPI data input
PWM1
10
I
Channel 1 PWM dimming input. Tie to VCCx if PWM pin control is not required.
PWM2
15
I
Channel 2 PWM dimming input. Tie to VCCx if PWM pin control is not required.
SCK
12
I
SPI clock input
SSN
11
I
SPI slave select input
SW1
5
I
Channel 1 switch node connection
SW2
20
I
Channel 2 switch node connection
VCC1
7
O
Channel 1 supply voltage output. May be used to power low current external circuits. See Application and Implementation
section.
VCC2
18
O
Channel 2 supply voltage output. May be used to power low current external circuits. See Application and Implementation
section.
VIN
1
I
Device power supply voltage input. May be common to CSP1, CSP2 or an independent supply.
VLED1
9
I
Channel 1 output voltage sense.
VLED2
16
I
Channel 2 output voltage sense.
G
Connect to ground. Add vias to improve thermal performance.
Exposed thermal pad
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
TPS92518HV-Q1
VIN, EN/UV, CSPx, CSNx, SWx, VLEDx to GND
TPS92518-Q1
MIN
MAX
–0.3
67
-0.3
44
MOSI, MISO, SCK, SSN to GND
–0.3
5.5
PWMx, VCCx to GND
–0.3
8.8
GATEx, BOOTx to SWx
GATEx, BOOTx to GND
–0.3
8.8
TPS92518HV-Q1
–0.3
75
TPS92518-Q1
-0.3
52
–0.3
5.5
CSPx to CSNx
SWx to GND, 10ns transient
–2
Junction temperature, TJ
–40
150
Storage temperature , Tstg
–65
165
(1)
UNIT
V
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002 (1)
±2000
Charged-device model (CDM), per V AEC Q100-011
±750
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VIN
Input Voltage
TA
Operating ambient temperature
TJ
Operating junction temperature
(1)
4
MIN
MAX
TPS92518HV-Q1
6.5
65
TPS92518-Q1
6.5
42
V
-40
125
°C
-40
150
°C
(1)
UNIT
V
The TPS92518-Q1 can operate at an ambient temperature of up to +125ºC as long as the junction temperature maximum of +150ºC is
not exceeded.
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6.4 Thermal Information
TPS92518-Q1
THERMAL METRIC (1)
PWP (HTSSOP)
UNIT
24 PINS
RθJA
Junction-to-ambient thermal resistance
32.5
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
17.9
°C/W
RθJB
Junction-to-board thermal resistance
15.7
°C/W
ψJT
Junction-to-top characterization parameter
0.4
°C/W
ψJB
Junction-to-board characterization parameter
15.5
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
1.8
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
VVIN = 14 V, -40 °C ≤ TJ ≤ 150 °C, unless otherwise specified
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
6.9
7.5
8.25
V
VCCx, VIN
VCCx
VCCx Voltage
VVIN = 40 V or VVIN = 65 V, 0 A ≤
External Load ≤ 500 µA
VCCx2
VCCx Voltage with External Load
External Load = 500 µA
6.9
7.5
8.25
V
VCCx_UVLO
VCCx undervoltage lockout
Falling threshold, VVIN = 10 V
5.65
5.9
6.1
V
VCCx_UVHYS
VCCx undervoltage lockout Hysteresis
IVCCx-LIM
VCCx regulator current limit
VCC shorted to GND.
48
mA
IVIN
Operating Current
Not Switching
3
4
mA
VDO
LDO drop-out voltage
IVCC = 5 mA, VVIN = 5 V
90
225
mV
0.25
25
38
V
Peak Current Comparator (CSPx, CSNx)
VCSTx
VCSPx-VCSNx peak current threshold
LEDx_PKTH_DAC = 255
245
255
265
mV
LEDx_PKTH_DAC = 127
118.5
127
135.5
mV
LEDx_PKTH_DAC = 10
ICSN
10
CSN input bias current
tDEL
CSN pin falling delay
CSNx fall to GATEx fall (1V/us
stimulus)
tLEB
Leading edge blanking (minimum ontime)
Minimum Pulse Width
CSPUVLO
CSPx UVLO Falling Threshold
CSPUVLO-H
CSPx UVLO Hysteresis
mV
0.4
1.5
µA
58
110
ns
165
200
235
ns
4.65
4.90
5.15
V
520
mV
Ω
Gate Drivers (GATEx, SWx and BOOTx)
RDSP
GATEx PFET ( RDS High )
7.3
RDSN
GATEx NFET ( RDS Low )
2.8
VBOOT-UVLO
Voltage where gate drive is disabled
VBOOT to VSW , VBOOT falling
VBOOT-UVLO-HYS
Hysteresis on BOOTx UVLO
VBOOTx to VSWx
200
IPD
PWMx
Pull down from SWx when PWMx Low
PWMx low, (BOOTx to SWx) = 5V,
VSWx= 8V
200
260
µA
IPD
BOOTx
VBOOTx -VSWx < VBOOT-UVLO
PWMx high, (BOOTx to SWx) <
BOOT_UVLO, VSWx = 8 V
5
7
mA
BOOTx quiescent current
(BOOTx to SWx) = 5.5 V, 0 V ≤ VSWx
≤ 65 V
100
200
µA
tOFF
Off-time
VLEDx = 30 V, tOFFXDAC = 255
4.1
4.8
µs
tD-OFF
COFF threshold to gate rising delay
Specified by design
50
ns
tOFF-MAX
Maximum off-time
tOFF-MAXDAC = 255
65
µs
IBOOT_Q
3.6
4.4
Ω
5.2
V
mV
OFF-TIMER
3.2
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Electrical Characteristics (continued)
VVIN = 14 V, -40 °C ≤ TJ ≤ 150 °C, unless otherwise specified
PARAMETER
TEST CONDITIONS
MIN
TYP
1.18
1.24
MAX
UNIT
Enable and Input UVLO
VEN/UV1
EN/UV pin threshold
EN/UV pin rising
VEN/UV-HYS1
EN/UV pin hysteresis
Difference between rising and falling
threshold
100
mV
tEN/UV1
EN/UV pin delay
EN/UV pin rising to GATEx pin rising.
LEDx_MAXOFF_DAC = 0
300
ns
IEN/UV-HYST1
EN/UV Hysteresis Current
EN/UV = 2 V
VEN/UV2
EN/UV LED1_EN and LED2_EN
override threshold
EN/UV pin rising writes LED1_EN and
LED2_EN = 1
VEN/UV-HYS2
EN/UV pin hysteresis
tEN/UV2
EN/UV pin delay 2
EN/UV pin falling to GATEx pin falling
1.30
470
12
16
V
ns
28
µA
23.4
V
Difference between rising and falling
threshold
3
V
EN/UV pin rising to GATEx pin rising.
LEDx_MAXOFF_DAC = 0
520
ns
PWM, MOSI, SCK, SSN
ILKG
Leakage current
VIL
Low level input voltage threshold
VIH
High level input voltage threshold
tPWM
PWM pin delay
1
0.8
µA
V
1.8
V
PWM pin rising to GATE pin rising
68
105
ns
PWM pin falling to GATE pin falling
55
100
ns
0.51
MISO
VOL
MISO low, IMISO applied
IMISO = 10 mA
0.26
RDS
MISO Pull-down resistance
IMISO = 10 mA
26
Ω
V
ADC Reading T = –40°C
104
Code
ADC Reading T = 25°C
130
Code
ADC Reading T= 150°C
171
ADC
ADCTEMP
ADCLEDx
Code
ADC Reading VLEDx= 60 V
226
230
240
Code
ADC Reading VLEDx = 10 V
37
38
39
Code
ADC Reading VLEDx = 1 V
2
3
4
Code
SPI Interface
tSS_SU
SSN Setup Time
Falling edge of SSN to 1st SCK rising
edge
500
ns
tSS_H
SSN Hold Time
Falling edge of 16th SCK to SSN
rising edge
250
ns
tSCK
SCK Period
Clock period
500
DSCK
SCK Duty Cycle
Clock duty cycle
40
tSU
MOSI Setup Time
MOSI valid to rising edge SCK
250
ns
tH
MOSI Hold Time
MOSI valid after rising edge SCK
275
ns
tHI_Z
MISO Tri-State Time
Time to tri-state (deactivate low-side
switch) MISO after SSN rising edge
110
tMISO_HL
MISO Valid High-to-Low
Time to place valid "0" on MISO after
falling SCK edge
tMISO_LH
MISO Valid Low-to-High
Time to tri-state (deactivate the
internal low-side switch) MISO after
falling SCK edge. tRC is the time
added by the application total
capacitance and resistance.
tZO_HL
MISO Drive Time High-to-Low
SSN Falling Edge to MISO Falling
SSN High Time
How long SSN must remain high
between transactions
tSS
ns
60
1000
%
320
ns
320
ns
320+tRC
ns
320
ns
ns
THERMAL SHUTDOWN
TSD
Thermal shutdown temperature
175
TSD HYST
Thermal shutdown hysteresis
10
6
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6.6 Typical Characteristics
VVIN = 14 V unless otherwise specified. Temperature = Junction Temperature. Note: Any difference between channels does
not necessarily illustrate a systematic difference between them.
127
-0.36
126.9
-0.39
4.8
-0.42
CSP1 UVLO Falling Threshold
CSP2 UVLO Falling Threshold
CSP1 UVLO Hysteresis
CSP2 UVLO Hysteresis
4.65
4.5
-0.45
-0.48
4.35
-0.51
126.8
VCST Threshold (mV)
4.95
CSPx UVLO Hysteresis (V)
126.7
126.6
126.5
126.4
VCST1 (CSP1-CSN1)
VCST2 (CSP2-CSN2)
126.3
126.2
126.1
4.2
-40
-0.54
-20
0
20
40
60
80
Temperature (qC)
100
120
126
-40
140
-20
0
20
D001
40
60
80
Temperature (qC)
VVIN = 42 V
256
255.5
10.4
10.2
10
9.8
D002
LEDx_PKTH_DAC = 127
254.5
254
253.5
253
252.5
9.6
VCST1
VCST2
VCST1
VCST2
252
251.5
VCST2 (CSP2-CSN2)
VCST1 (CSP1-CSN1)
9.4
9.2
-20
0
20
40
60
80
Temperature (qC)
VVIN = 42 V
100
120
251
-40
140
20
40
60
80
Temperature (qC)
100
VVIN=42
VVIN=42
VVIN=65
VVIN=65
120
140
D004
LEDx_PKTH_DAC = 255
D003
Figure 4. Current Sense Threshold Voltage
BOOTx Under Voltage Falling Threshold (V)
76
72
68
64
60
56
52
48
44
0
0
(CSP1-CSN1)
(CSP2-CSN2)
(CSP1-CSN1)
(CSP2-CSN2)
LEDx_PKTH_DAC = 10
80
-20
-20
VVIN = 42 V and 65 V
Figure 3. Current Sense Threshold Voltage
tDEL - CSN Pin Falling Delay (ns)
140
255
10.6
VCSTx Threshold (mV)
VCSTx Threshold (mV)
11
10.8
40
-40
120
Figure 2. Current Sense Threshold Voltage
Figure 1. CSPx UVLO Falling Level and Hysteresis
9
-40
100
20
40
60
80
Temperature (qC)
100
120
140
4.8
0.6
BOOT1 UV FALL
0.55
BOOT2 UV FALL
BOOT1 HYST
0.5
BOOT2 HYST
0.45
4.72
4.64
4.56
4.48
0.4
4.4
0.35
4.32
0.3
4.24
0.25
4.16
0.2
4.08
4
-40
BOOTx Hysteresis (V)
CSPx UVLO Falling Threshold (V)
5.1
0.15
0.1
-20
0
D005
20
40
60
80
Temperature (qC)
100
120
140
D006
VVIN = 42 V
Figure 5. CSN Pin Falling Delay (tDEL )
Figure 6. BOOT Undervoltage Lock-out Falling Threshold
and Hysteresis
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Typical Characteristics (continued)
VVIN = 14 V unless otherwise specified. Temperature = Junction Temperature. Note: Any difference between channels does
not necessarily illustrate a systematic difference between them.
1.244
MAXOFF_TIME1
MAXOFF_TIME2
1.243
64.2
64
VUV/EN1
Maximum Off-Time (Ps)
64.4
0.108
EN_THRES1_RISING
EN_THRES1_HYS
63.8
63.6
0.1065
1.242
0.105
1.241
0.1035
1.24
0.102
1.239
0.1005
1.238
0.099
63.4
1.237
0.0975
63.2
1.236
0.096
63
1.235
0.0945
62.8
-40
-20
0
20
40
60
80 100
Temperature (qC)
120
140
1.234
-40
160
VUV/EN1-HYST1
64.6
0.093
-20
0
20
40
60
80
Temperature (qC)
100
120
140
D008
D007
LEDx_MAXOFF_DAC = 255
Figure 8. Enable/UV Threshold
Figure 7. Maximum Off-Time
39
158
38
157
37
156
36
155
35
154
34
153
33
152
ADC LED1 40V
ADC LED1 10V 32
151
31
150
-40
30
-20
0
20
40
60
80
Temperature (qC)
100
120
140
tPWM - PWM RISE or FALL DELAY (ns)
159
90
2.8
PWM RISE DELAY
PWM FALL DELAY
PWM FALL THRESH
PWM RISE THRESH
80
2.4
70
2
60
1.6
50
1.2
40
-40
-21
-2
17
D009
36
55
74
Temperature (qC)
93
112
131
VINPUT-RISE or FALL (V)
40
LED1_MOST_RECENT (10V)
LED1_MOST_RECENT (40V)
160
0.8
150
D010
Readings shown are TPS92518-Q1 register values
Figure 10. PWM Input Characteristics
24
21
21
18
18
VTHERM Register Value (Decimal)
TJ = -40°C
6
5
13
13
4
13
3
13
2
1
VTHERM Register Value (Decimal)
D024
TJ = 25°C
Figure 11. VTHERM Performance
8
13
D022
12
8
0
11
9
10
8
7
10
10
10
10
10
10
6
0
5
0
4
3
3
3
2
6
0
9
6
13
9
12
13
12
15
9
15
12
Number of Units
27
24
10
Number of Units
Figure 9. ADC (Analog to Digital) LED Readings
27
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Figure 12. VTHERM Performance
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Typical Characteristics (continued)
25
25
22.5
22.5
20
17.5
10
VTHERM Register Value
18
5
VTHERM Register Value (Decimal)
D025
TJ = 125°C
D021
TJ = 150°C
Figure 13. VTHERM Performance
Figure 14. VTHERM Performance
93
.7
.4
93
.1
93
.5
.2
.8
92
92
92
.9
.6
91
91
91
.3
7
6.5
6
5.5
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
91
Number of Units
18
4
17
7
17
5
17
4
17
3
17
0
17
2
0
17
1
0
16
9
5
2.5
16
8
5
2.5
18
3
7.5
18
2
7.5
12.5
18
1
10
18
0
12.5
15
17
9
15
17
8
Number of Units
20
17.5
16
7
Number of Units
VVIN = 14 V unless otherwise specified. Temperature = Junction Temperature. Note: Any difference between channels does
not necessarily illustrate a systematic difference between them.
EVM - Two Channel Efficiency (%)
25 x TPS92518EVM-878 EVM's Tested
LEDx_PKTH_DAC = 88
VVIN= VCSPx= 50 V
LEDx_TOFF_DAC=70
D017
22.3 V VBOOT-UVLO) and Full Drop-Out (Boot Capacitor Voltage reaching VBOOT-UVLO) .
8.3.7.1 Early Drop-Out (Boot Capacitor Voltage >> VBOOT-UVLO)
the first effects of drop-out can be seen when the input voltage approaches a few volts above the output voltage.
Unless there is sufficient output capacitance, the change in the LED voltage during the ramp up of the inductor
and output current can cause a non-linearity in the ramp.
18
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(1)
'IL
(VIN
PP
(2)
VLED ) * t OFF
L
'IL
(VIN
PP
'VLED ) * t OFF
L
ILED
A
VLED
tON
tOFF
tON
t
tOFF
Figure 24. Inductor on-time Current Non-linearity
In case (1) shown in , VIN-VLED is sufficiently large that variations in VLED are not relevant and/or not present
because of sufficient output capacitance.
In case (2), VIN and VLED are closer in value making the difference lower and more easily affected by variations in
VLED. ΔVLED is the total variation in the voltage across the inductor and includes the ILED x RL-DCR voltage drop
which also changes with IL and impacts the inductor current linearity. The combination of factors leads to an
inductor current on-time non-linearity which increases the average value of the inductor current, and hence the
LED current. This means the first affect of approaching drop-out is always an increase in LED current.
It is important to note that the output current is always limited to the peak limit set by the internal programmed
reference and the sense resistor. (The peak current threshold) This means a design having a smaller overall
inductor current ripple (smaller ΔIL-PP) will have less error when a drop-out condition occurs.
8.3.7.2 Full Drop-Out (Boot Capacitor Voltage reaching VBOOT-UVLO)
If VIN and VLED are sufficiently close the duty cycle demand increases. Because of the TPS92518-Q1 hysteretic
control method, the high-side FET attempts to remain ON until the programmed peak current is reached.
Keeping the high-side FET ON requires energy from the BOOT capacitor which depletes the BOOT capacitor
voltage. If the high-side FET is ON for sufficient duration, the BOOT capacitor voltage eventually reaches VBOOTUVLO level at which point the high-side FET is turned off. This allows for long on-times and duty cycles >99.5%,
since the time the high-side FET can remain ON is long (>1 ms) compared to the time required the recharge the
BOOT capacitor (approximately 100 ns). The typical maximum on-time can be estimated by Equation 18
C dv CBOOT x (VCC VBOOT UVLO ) 0.1PF x (7.5 4.6)
tON MAX(TYP)
|
| 2.9ms
i
IBOOT Q
100P A
(18)
8.3.7.3 Minimum BOOT Voltage and FET Control
The minimum VBOOT-UVLO is also the minimum voltage available to drive the external FET. Check the FET Output
Characteristics (ID versus VDS) at the minimum BOOT voltage and ensure the FET is sufficiently enhanced under
this condition. If the turn-on is marginal, the FET may operate in the linear region causing increased losses and
possibly damage the device.
8.3.7.4 BOOT Controlled internal Pull-Down
Each time VBOOT ≤ VBOOT-UVLO an internal pull-down (IPD BOOTx = 5 mA typical) from the SWx pin to ground is
enabled. This behavior occurs during drop-out conditions such as Full Drop-Out (Boot Capacitor Voltage
reaching VBOOT-UVLO) . This behavior also occurs at Start-Up if the output is pre-charged.
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19
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SLUSCZ1 – MAY 2017
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If the TPS92518-Q1 application uses an output capacitor and the output is disabled and re-enabled before the
output voltage reduces (or is otherwise pre-charged) a condition can be created where the SWx pin voltage is
not low enough for the BOOT capacitor to charge. (VSWx
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