TPS99000S-Q1
TPS99000S-Q1
DLPS202
– OCTOBER 2020
DLPS202 – OCTOBER 2020
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TPS99000S-Q1 System Management and Illumination Controller
1 Features
3 Description
•
•
The TPS99000S-Q1 system management and
illumination controller is part of the DLP553x-Q1
chipset, which also includes the DLPC230S-Q1 DMD
display controller. The chipset provides all functions
needed to support and exceed typical 5000:1 display
dimming requirements for Head-Up Display (HUD)
applications, with typical requirements of 3 to 15,000
nits brightness range and tight color point control.
•
•
•
•
Qualified for automotive applications
AEC-Q100 qualified with the following results:
– Temperature grade 2: –40°C to 105°C ambient
operating temperature
– Device HBM ESD classification level 2
– Device CDM ESD classification level C4B
Functional Safety Quality-Managed
– Documentation available to aid ISO 26262
functional safety system design up to ASIL-B
Automotive system management device for TI
DLP® Products:
– Advanced power monitoring, sequencing, and
protection circuits
– Two die temperature monitors, MCU external
watchdog timer, clock frequency monitor
– System over-brightness detection
– SPI port with parity, checksum, and password
register protection
– Second SPI port for independent system
monitoring
On-chip DMD mirror voltage regulators
– Generates +16-V, +8.5-V and –10-V DMD
control voltages
High dynamic range dimming and color control,
enabling > 5000:1 dimming range with high bit
depth and white color balance:
– Two transimpedance amplifiers (TIA) with wide
dynamic range supporting numerous optical
designs
– 12-bit ADC with up to 63 time sequence
samples per frame
– DAC and comparator functions for color and
pulse control
– FET drivers for LED and shunt control
An integrated DMD high-voltage regulator supplies
DMD mirror reference voltages, meeting the required
tight tolerances. The power supply sequencer and
monitor provide robust coordination of power-up and
power-down events for the entire chipset.
The TPS99000S-Q1 illumination controller integrates
a 12-bit ADC, two DACs (12-bit and 10-bit), and two
high-performance photodiode signal conditioning
transimpedance amplifiers (TIAs) as the core
components of the illumination control system. The
ADC is capable of automatic sampling up to 63 events
per video frame.
Advanced system status monitoring circuits provide
real-time visibility into display sub-system operational
condition, including two processor watchdog circuits,
two die temperature monitors, comprehensive supply
monitoring for overvoltage and undervoltage
detection, checksum and password register protection
with byte-level parity on SPI bus transactions, an
excessive brightness monitor circuit, and other built-in
test functions.
Device Information
PACKAGE(1)
PART NUMBER
TPS99000S-Q1
(1)
HTQFP (100)
•
Wide field of view and augmented reality head-up
display (HUD) systems
Digital cluster, navigation, and infotainment
windshield displays
14.00 mm × 14.00 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
•
BODY SIZE (NOM)
Voltage
Monitor and
Enables
Power
Regulation
TPS99000S-Q1
1.1V
1.8V
3.3V
6.5V
LED dimming
SPI
DLPC230S-Q1
ARM®
Cortex®-R4F
VRESET
DLP5530S-Q1
SubLVDS
DMD video
processing &
control
Video
memory
VOFFSET
VBIAS
Video
LED
ENABLE
System
diagnostics
DMD power
management
SPI
TMP411
Temperature
Sensor
I2C
SPI
0.55" DMD
2:1 aspect ratio
1.3M pixels
Flash
Typical Standalone System
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
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Incorporated
intellectual
property
matters
and other important disclaimers. PRODUCTION DATA.
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DLPS202 – OCTOBER 2020
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
Pin Functions - Initialization, Clock, and Diagnostics........4
Pin Functions - Power and Ground...................................5
Pin Functions - Power Supply Management.....................6
Pin Functions - Illumination Control ................................. 7
Pin Functions - Serial Peripheral Interfaces......................8
Pin Functions - Analog to Digital Converter...................... 9
6 Specifications................................................................ 10
6.1 Absolute Maximum Ratings...................................... 10
6.2 ESD Ratings............................................................. 10
6.3 Recommended Operating Conditions.......................10
6.4 Thermal Information.................................................. 11
6.5 Electrical Characteristics - Transimpedance
Amplifier Parameters...................................................12
6.6 Electrical Characteristics - Digital to Analog
Converters...................................................................14
6.7 Electrical Characteristics - Analog to Digital
Converter.....................................................................15
6.8 Electrical Characteristics - FET Gate Drivers........... 16
6.9 Electrical Characteristics - Photo Comparator ......... 16
6.10 Electrical Characteristics - Voltage Regulators....... 17
6.11 Electrical Characteristics - Temperature and
Voltage Monitors..........................................................18
6.12 Electrical Characteristics - Current Consumption... 19
6.13 Power-Up Timing Requirements............................. 20
6.14 Power-Down Timing Requirements........................ 22
6.15 Timing Requirements - Sequencer Clock............... 24
6.16 Timing Requirements - Host / Diagnostic Port
SPI Interface................................................................25
6.17 Timing Requirements - ADC Interface.................... 25
6.18 Switching Characteristics........................................25
7 Detailed Description......................................................27
7.1 Overview................................................................... 27
7.2 Functional Block Diagram......................................... 28
7.3 Feature Description...................................................29
7.4 Device Functional Modes..........................................54
7.5 Register Maps...........................................................56
8 Application and Implementation.................................. 59
8.1 Application Information............................................. 59
8.2 Typical Applications.................................................. 59
9 Power Supply Recommendations................................69
9.1 TPS99000S-Q1 Power Supply Architecture............. 69
9.2 TPS99000S-Q1 Power Outputs................................69
9.3 Power Supply Architecture........................................69
10 Layout...........................................................................73
10.1 Layout Guidelines................................................... 73
11 Device and Documentation Support..........................78
11.1 Device Support........................................................78
11.2 Receiving Notification of Documentation Updates.. 78
11.3 Support Resources................................................. 78
11.4 Trademarks............................................................. 78
11.5 Electrostatic Discharge Caution.............................. 78
11.6 Glossary.................................................................. 78
12 Mechanical, Packaging, and Orderable
Information.................................................................... 79
4 Revision History
2
DATE
REVISION
NOTES
October 2020
*
Initial Release
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5 Pin Configuration and Functions
Figure 5-1. PZP Package 100-Pin HTQFP Top View
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Pin Functions - Initialization, Clock, and Diagnostics
PIN
NO.
4
NAME
6
WD1
7
8
TYPE
DESCRIPTION
I
Watch Dog Interrupt Channel 1
WD2
I
Watch Dog Interrupt Channel 2
PARK_Z
O
DMD Mirror Parking Signal (active low)
9
RESET_Z
O
Reset output to the DLPC230S-Q1. TPS99000S-Q1 controlled.
10
INT_Z
O
Interrupt output signal to DLPC230S-Q1 (open drain). Recommended to pull
up to the DLPC230S-Q1 3.3 V rail controlled by the TPS99000S-Q1 's
ENB_3P3V signal.
11
PROJ_ON
I
Input signal to enable/disable the IC and DLP projector
16
SEQ_START
I
PWM Shadow Latch Control; indicates a Start of Sequence
17
SEQ_CLK
I
Sequencer Clock
40
DMUX0
O
Digital test point output
41
DMUX1
O
Digital test point output
57
AMUX1
O
Analog Test Mux Output 1
61
AMUX0
O
Analog Test Mux Output 0
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DLPS202 – OCTOBER 2020
Pin Functions - Power and Ground
PIN
NO.
NAME
TYPE
DESCRIPTION
13, 35
VSS_IO
GND
14, 36
VDD_IO
POWER
24
DVSS
Ground Connection for Digital IO Interface
3.3 V power input for IO rail supply
GND
Digital Core Ground Return
25, 60, 75, 99
PBKG
GND
Substrate Tie and ESD Ground Return
26
DVDD
POWER
3.3 V power input for digital core supply
42
DRVR_PWR
POWER
6 V or 3.3 V power input for FET driver power. Supply for S_EN1, S_EN2,
R_EN, G_EN, & B_EN outputs
48
VSS_DRVR
49
DMD_VOFFSET
POWER
VOFFSET output rail. Connect a 1μF ceramic capacitor to ground
50
DMD_VBIAS
POWER
VBIAS output rail. Connect a 0.47μF ceramic capacitor to ground
51
DMD_VRESET
POWER
VRESET output rail. Connect a 1μF ceramic capacitor to ground. Connect to
DRST_HS_IND through external diode. Connect anode of diode to
DMD_VRESET.
53
DRST_PGND
55
VIN_DRST
POWER
56
VSS_DRST
GND
59
AVDD
POWER
3.3 V power supply input for analog circuit
63
VLDOT_M8
POWER
Dedicated TIA Interface –8 V LDO output
64
VLDOT_5V
POWER
Filter Cap Interface for 5 V TIA LDO
65
VIN_LDOT_5V
POWER
6 V power input for 5 V TIA LDO
66
GND_LDO
67
VIN_LDOT_3P3V
POWER
68
VLDOT_3P3V
POWER
71
VSS_TIA2
GND
TIA2 Dedicated Ground
72
VSS_TIA1
GND
TIA1 Dedicated Ground
78, 100
AVSS
GND
Analog Ground
79
VIN_LDOA_3P3
POWER
6 V power input for dedicated ADC interface 3.3 V LDO supply
80
VLDOA_3P3
POWER
Dedicated ADC Interface 3.3 V LDO Filter Cap Output
81, 84, 87, 89, 91
VSSL_ADC
GND
95
ADC_VREF
POWER
GND
GND
GND
Ground Connection for FET driver power
Power ground for DMD power supply. Connect to ground plane
6 V input for DMD power supply
Ground Supply for DMD power supply
Power ground return for LDO
6 V power input for 3.3 V TIA LDO
Filter Cap Interface for 3.3 V TIA LDO
External ADC Channel Bondwire and Lead Frame Isolation Ground
ADC Reference voltage output
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DLPS202 – OCTOBER 2020
Pin Functions - Power Supply Management
PIN
NO.
6
NAME
TYPE
DESCRIPTION
1
ENB_1P1V
O
External 1.1 V Buck Enable. 3.3 V Output
2
ENB_1P8V
O
External 1.8 V Buck Enable. 3.3 V Output
3
ENB_3P3V
O
External 3.3 V Buck Enable. 3.3 V Output
52
DRST_LS_IND
ANA
Connection for the DMD power supply inductor (10μH). Connect a 330pF 50
V capacitor to ground. X7R recommended
54
DRST_HS_IND
ANA
Connection for the DMD power supply inductor (10μH)
58
VMAIN
I
Main intermediate voltage monitor input. Use external resistor divider to set
voltage input for brownout monitoring
62
VIN_LDOT_M8
O
Dedicated TIA Interface –8 V LDO external regulation FET drive signal
96
V3P3V
I
External 3.3 V Buck Voltage Monitor Input
97
V1P8V
I
External 1.8 V Buck Voltage Monitor Input
98
V1P1V
I
External 1.1 V Buck Voltage Monitor Input
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DLPS202 – OCTOBER 2020
Pin Functions - Illumination Control
PIN
NO.
NAME
TYPE
DESCRIPTION
12
COMPOUT
O
Photodiode (PD) Interface High-speed comparator output
15
SYNC
O
External LED buck driver sync strobe output
18
D_EN
I
LED Interface; Buck High-Side FET Drive Enable
19
S_EN
I
LED Bypass Shunt Strobe Input
20
LED_SEL_0
I
LED Enable Strobe 0 Input
21
LED_SEL_1
I
LED Enable Strobe 1 Input
22
LED_SEL_2
I
LED Enable Strobe 2 Input
23
LED_SEL_3
I
LED Enable Strobe 3 Input
37
EXT_SMPL
I
Reserved. Connect to ground
38
DRV_EN
O
Drive enable for LM3409
39
CMODE
O
Capacitor selection output (allows for a smaller capacitance to be used in CM
mode for less over/under shoot). Open drain
43
S_EN1
O
Low resistance shunt NFET drive enable [High means shunt active]
44
S_EN2
O
High resistance shunt NFET drive enable [High means shunt active]
45
R_EN
O
Red channel select. Drive for low side NFET
46
G_EN
O
Green channel select. Drive for low side NFET
47
B_EN
O
Blue channel select. Drive for low side NFET
69
TIA_PD2_FILT
O
TIA2 External Filter Cap - Low Bandwidth Sampling
70
TIA_PD2
I
TIA2 Photodiode Cathode Driver
73
TIA_PD1
I
TIA1 Photodiode Cathode Driver
74
TIA_PD1_FILT
O
TIA1 External Filter Cap - Low Bandwidth Sampling
76
R_IADJ
ANA
External resistance for IADJ voltage to current transformation
77
IADJ
ANA
Current output used to adjust external LED controller drive current set point
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DLPS202 – OCTOBER 2020
Pin Functions - Serial Peripheral Interfaces
PIN
NO.
8
NAME
TYPE
DESCRIPTION
27
SPI1_CLK
I
SPI Control interface (DLPC230S-Q1 Master, TPS99000S-Q1 slave), clock
input
28
SPI1_SS_Z
I
SPI Control interface (DLPC230S-Q1 Master, TPS99000S-Q1 slave), chip
select (active low)
29
SPI1_DOUT
O
SPI Control interface (DLPC230S-Q1 Master, TPS99000S-Q1 slave),
Transmit data output
30
SPI1_DIN
I
SPI Control interface (DLPC230S-Q1 Master, TPS99000S-Q1 slave),
Receive data input
31
SPI2_DIN
I
SPI Diagnostic Port (slave), Receive data input. For read-only monitoring
32
SPI2_DOUT
O
SPI Diagnostic Port (slave), Transmit data output. For read-only monitoring
33
SPI2_SS_Z
I
SPI Diagnostic Port (slave), chip select (active low). For read-only monitoring
34
SPI2_CLK
I
SPI Diagnostic Port (slave), clock input. For read-only monitoring
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DLPS202 – OCTOBER 2020
Pin Functions - Analog to Digital Converter
PIN
NO.
NAME
TYPE
DESCRIPTION
4
ADC_MISO
O
ADC 2-wire Interface - data Output. DLPC230S-Q1 master, TPS99000S-Q1
slave.
5
ADC_MOSI
I
ADC 2-wire Interface - data Input. DLPC230S-Q1 master, TPS99000S-Q1
slave.
82
LS_SENSE_N
I
Low side current sense ADC negative input, see Table 7-2
83
LS_SENSE_P
I
Low side current sense ADC positive input, see Table 7-2
85
ADC_IN1
I
External ADC Channel 1, see Table 7-2
86
ADC_IN2
I
External ADC Channel 2, see Table 7-2
88
ADC_IN3
I
External ADC Channel 3, see Table 7-2
90
ADC_IN4
I
External ADC Channel 4, see Table 7-2
92
ADC_IN5
I
External ADC Channel 5, see Table 7-2
93
ADC_IN6
I
External ADC Channel 6, see Table 7-2
94
ADC_IN7
I
External ADC Channel 7, see Table 7-2
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
Input
voltage
Outputs
MIN
MAX
VDD_IO to VSS_IO
–0.3
4
DVDD to DVSS
–0.3
4
AVDD to DVSS
–0.3
4
All "VSS" to other "VSS" (grounds)
–0.1
0.1
All digital input signals to ground (WD1, WD2, ADC_MOSI,
PROJ_ON, SEQ_START, SEQ_CLK, SPI1_CLK, SPI1_DIN,
SPI1_SS, SPI2_DIN, SPI2_CLK, SPI2_SS, EXT_SMPL)
–0.3
3.6
DRVR_PWR to ground
–0.3
7.5
VIN_LDO_5V
–0.3
7.5
V3P3V to ground
–0.3
5
V1P8V to ground
–0.3
5
V1P1V to ground
–0.3
5
VIN_LDOA_3P3 to ground
–0.3
7.5
VIN_LDOT_3P3 to ground
–0.3
7.5
ADC_IN(7:1) to ground
–0.3
3.6
LS_SENSE_N and LS_SENSE_P to ground
-0.3
3.6
IADJ to ground
–0.3
18
R_IADJ to ground
–0.3
5
VIN_LDOT_M8 to ground
–18
0.3
DRST_LS_IND to DRST_PGND
–0.3
27
VIN_DRST to ground
–0.3
7.5
VMAIN
–0.3
7.5
UNIT
V
INT_Z
–0.3
7.5
V
Operating junction temperature, TJ
–40
130
°C
Storage temperature, Tstg
–65
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
6.2 ESD Ratings
VALUE
Human-body model (HBM), per AEC
V(ESD)
(1)
Electrostatic
discharge
Q100-002(1)
Charged-device model (CDM), per AEC
Q100-011
UNIT
±2000
All pins
±500
Corner pins
±750
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
TEMPERATURE
TA
Operating ambient temperature(1)
–40
105
°C
TJ
Operating junction temperature
–40
125
°C
VOLTAGE
10
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over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
VDD_IO
IO 3.3 V Voltage Supply
3
3.3
3.6
UNIT
V
DVDD
Digital 3.3 V Supply
3
3.3
3.6
V
AVDD
Analog 3.3 V Supply
3
3.3
3.6
V
ADC
ADC(7:1) Inputs
0.1
1.6
V
VIN_DRST
DMD Reset Regulator Input
5.5
6
7
V
VIN_LDOT_5V
Power supply input to 5 V TIA LDO
5.5
6
7
V
VIN_LDOA_3P3V Power supply input to 3.3 V ADC LDO
5.5
6
7
V
VIN_LDOT_3P3V
Power supply input to 3.3 V TIA LDO
5.5
6
7
V
DRVR_PWR
Gate driver power supply
3
6
7
V
(1)
–40°C to 105°C ambient, free air convection, AEC Q100 grade 2.
6.4 Thermal Information
TPS99000S-Q1
THERMAL
METRIC(1) (2)
PZP (HTQFP)
UNIT
100 PINS
RθJC(top)
Junction-to-case (top) thermal resistance
6.9
°C/W
RθJB
Junction-to-board thermal resistance
8.3
°C/W
ψJT
Junction-to-top characterization parameter
0.1
°C/W
ψJB
Junction-to-board characterization parameter
8.2
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
0.4
°C/W
(1)
(2)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953).
Operating ambient temperature is dependent on system thermal design. Operating junction temperature may not exceed its specified
range across ambient temperature conditions.
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6.5 Electrical Characteristics - Transimpedance Amplifier Parameters
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
TIA1 AND TIA2
IIN_TOT
TIA1 and TIA2 Combined Input
Current
0
7(3)
mA
TRANSIMPEDANCE AMPLIFIER #1 (TIA1)
IIN
RGB trim
