Order
Now
Product
Folder
Support &
Community
Tools &
Software
Technical
Documents
TPSM82480
SLVSDT1C – JULY 2017 – REVISED JUNE 2020
TPSM82480 5.5-V Input, 6-A, Step-Down Converter Module with Integrated Inductor
1 Features
3 Description
•
•
•
•
•
•
•
•
•
•
The TPSM82480 is a synchronous step-down DC-DC
converter module for low profile point-of-load power
supplies. The input voltage range of 2.4 V to 5.5 V
enables operation from typical 3.3-V or 5-V interface
supplies as well as from backup circuits dropping
down as low as 2.4 V.
1
•
•
•
•
•
•
Ultra small 3.6 × 7.9 × 1.55 mm power module
CISPR11 Class B compliant
Feedback voltage accuracy: ±1%
Input voltage range: 2.4 V to 5.5 V
Output voltage range: 0.6 V to 5.5 V
Output current: 6-A with no derating at TA = 85 °C
Typical quiescent current: 23 µA
Output voltage select (two user-defined values)
Phase-shifted operation
Automatic power save mode or forced PWM
option
Adjustable soft-start and tracking
Power good and thermal good outputs
Undervoltage lockout protection
Overcurrent and short-circuit protection
Over-temperature protection
Operating temperature range: –40°C to 125°C
2 Applications
•
•
•
•
•
Low profile point-of-load supply
Aerospace and defense
Factory automation and control
Optical modules
Professional audio, video and signage
The output current is up to 6 A continuously provided
by two phases of 3 A each, which run out-of-phase,
reducing pulse current noise significantly.
The TPSM82480 provides an automatically entered
power save mode to maintain high efficiency down to
very light loads. This incorporates an automatic
phase adding and shedding feature using both or
only one phase according to the actual load. The
power save mode can be switched off using the
MODE feature.
The device offers a power good signal and an
adjustable soft-start period. Also, the device features
a thermal good signal to indicate excessive internal
temperature. The output voltage can be changed to a
preselected value by VSEL pin. TPSM82480 is able
to operate in 100% duty cycle mode.
Device Information(1)
PART NUMBER
TPSM82480MOP
PACKAGE
QFM (24)
BODY SIZE (NOM)
7.90 × 3.60 x 1.55 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
space
space
Typical Application
space
2.4 V to 5.5 V
VOUT
6A
TPSM82480
VIN1
VOUT
VIN2
EN
Efficiency vs Output Current
space
space
R1
FB
10 PF
R3
COUT
RS
3.3 nF
VSEL
MODE
SS/TR
PG
AGND
TG
PGND
R2
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPSM82480
SLVSDT1C – JULY 2017 – REVISED JUNE 2020
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
4
5
7
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 8
7.1
7.2
7.3
7.4
Overview ................................................................... 8
Functional Block Diagram ......................................... 8
Feature Description................................................... 9
Device Functional Modes........................................ 10
8
Application and Implementation ........................ 12
8.1 Application Information............................................ 12
8.2 Typical Application ................................................. 12
8.3 System Examples .................................................. 22
9 Power Supply Recommendations...................... 22
10 Layout................................................................... 23
10.1 Layout Guidelines ................................................. 23
10.2 Layout Example .................................................... 23
11 Device and Documentation Support ................. 24
11.1
11.2
11.3
11.4
11.5
11.6
Documentation Support .......................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
24
24
24
24
24
24
12 Mechanical, Packaging, and Orderable
Information ........................................................... 24
12.1 Tape and Reel Information ................................... 25
4 Revision History
Changes from Revision B (May 2020) to Revision C
Page
•
Added hyperlinks to end applications list ............................................................................................................................... 1
•
Updated Typical Application
space ..................................................................................................................................................................................... 1
•
Added application report references in Setting VOUT2 Using the VSEL Feature ................................................................. 13
•
Added footnote to Table 2 ................................................................................................................................................... 14
•
Added user's guide reference to Layout Guidelines section ................................................................................................ 23
Changes from Revision A (March 2018) to Revision B
•
Added EMI performance curves ........................................................................................................................................... 18
Changes from Original (July 2017) to Revision A
•
2
Page
Page
Changed data sheet status from Advance Information to Production Data. .......................................................................... 1
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: TPSM82480
TPSM82480
www.ti.com
SLVSDT1C – JULY 2017 – REVISED JUNE 2020
5 Pin Configuration and Functions
20
8
7
9
15
1
16
11
22
17
9
8
7
6
23
21
10
11
12
23
5
4
10
2
12
24
6
24
22
2
3
4
5
3
13
18
21
14
19
15
16
17
20
18
1
19
MOP Package
24-Pin QFM
14
13
BOTTOMVIEW
TOPVIEW
PIN1 Marker
Pin Functions
PIN
NAME
NO.
VOUT1
1
PGND1
2, 3, 20,21
VIN1
I/O
DESCRIPTION
Output voltage node phase 1 (master), must be connect with VOUT2
Power ground phase 1 (master)
4, 24
Supply voltage phase 1 (master)
EN
5
I
Enable input (high=enabled, low = disabled) do not leave floating
PG
6
O
Power good (open drain, requires pull-up resistor). Connect to GND or leave unconnected if
not used.
VSEL
7
I
Output voltage select (high = VOUT2, low = VOUT1) , VOUT1 < VOUT2
TG
8
O
Thermal good (open drain, requires pull-up resistor). Connect to GND or leave unconnected
if not used.
9
I
Operating mode selection (Low=Automatic PWM/PSM, high = forced PWM)
MODE
VIN2
10, 23
Supply voltage phase 2
PGND2
11,12, 14, 22
Power ground phase 2
VOUT2
13
Output voltage node phase 2, Must be connected with VOUT1
SS/TR
15
Soft-start and tracking. An external capacitor connected to this pin sets the output voltage
rise time. The voltage rating of the capacitor must be larger than the input voltage.
AGND
16
Analog ground. Must be externally connected to PGND.
FB
17
Output voltage feedback. Connect resistive voltage divider to this pin.
RS
18
VO
19
O
Resistor select. Connect resistor that sets the level for the second output voltage here
(activated by VSEL= high). Connect to GND or leave unconnected if not used.
VOUT detection (connect to VOUT, output discharge is internally connected to this pin)
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: TPSM82480
3
TPSM82480
SLVSDT1C – JULY 2017 – REVISED JUNE 2020
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
MIN
MAX
UNIT
VIN
-0.3
6
V
EN, VSEL, MODE, SS/TR, PG, TG
-0.3
6
V
FB, RS
-0.3
3
V
10
mA
Operating Junction Temperature Range, TJ
-40
150
°C
Storage Temperature Range, Tstg
-65
150
°C
Pin Voltage Range (1)
Power Good / Thermal Good Sink Current
(1)
PG, TG
All voltages are with respect to network ground terminal.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1)
±1000
Charged device model (CDM), per JEDEC specification JESD22-C101,
all pins (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
TYP
MAX
UNIT
Supply Voltage Range, VIN
2.4
5.5
V
Output Voltage Range, VOUT
0.6
5.5
V
125
°C
Maximum Output Current, IOUT
6
Operating junction temperature, TJ
A
–40
6.4 Thermal Information
TPSM82480
THERMAL METRIC (1)
MOP 24 PINS
UNIT
JEDEC 51-5 with
thermal vias
RθJA
Junction-to-ambient thermal resistance
32.2
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
13.6
°C/W
RθJB
Junction-to-board thermal resistance
11.5
°C/W
ψJT
Junction-to-top characterization parameter
0.53
°C/W
ψJB
Junction-to-board characterization parameter
11.3
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: TPSM82480
TPSM82480
www.ti.com
SLVSDT1C – JULY 2017 – REVISED JUNE 2020
6.5 Electrical Characteristics
over operating junction temperature range (TJ = –40°C to 125°C) and VIN = 2.4 V to 5.5 V. Typical values at VIN = 3.6 V and
TJ = 25°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY
VIN
Input Voltage Range
IQ
Operating Quiescent Current
ISD
Shutdown Current
VUVLO
Undervoltage Lockout Threshold
TSD
VIN rising
2.6
5.5
VIN falling
2.4
5.5
EN = High, VIN ≥ 3 V, IOUT = 0 mA, device not
switching,
TJ = -40°C to +85°C
23
100% Mode operation
EN = Low (≤ 0.3 V), TJ = -40°C to +85°C
Falling Input Voltage
2.2
V
38
µA
3.5
6.5
mA
0.5
18.5
µA
2.3
2.4
Hysteresis
200
Thermal Shutdown Temperature
PWM Mode, Rising Junction Temperature
160
Thermal Shutdown Hysteresis
PWM Mode
V
mV
°C
10
CONTROL (EN, VSEL, MODE, SS/TR, PG, TG)
VH
Input Threshold Voltage (EN,
VSEL, MODE)
to ensure High Level
VL
Input Threshold Voltage (EN,
VSEL, MODE)
to ensure Low Level
ILKG(EN)
Input Leakage Current (EN)
EN = VIN or GND
ILKG(MODE)
Input Leakage Current (MODE,
VSEL)
ISS/TR
SS/TR pin source current
VTH(TG)
Thermal Good Threshold
Temperature
PWM Mode
120
Thermal Good Hysteresis
PWM Mode
10
1.2
V
0.4
4.7
10
200
nA
10
200
nA
5.25
5.8
µA
°C
Rising (%VOUT)
93%
96%
99%
Falling (%VOUT)
89%
92%
95%
0.4
V
Input Leakage Current (PG)
2
700
nA
ILKG(TG)
Input Leakage Current (TG)
2
100
nA
tSS
Internal Soft-Start Time
tDELAY
Time from EN rising until start
switching
VTH(PG)
Power Good Threshold Voltage
VL(PG)
Output Low Threshold (PG, TG)
ILKG(PG)
IPG = -2 mA
SS/TR = VIN or floating
80
100
µs
200
400
µs
36
98
mΩ
29
72
mΩ
5.0
5.8
A
POWER SWITCH
Phase1
High-Side MOSFET
ON-Resistance
VIN ≥ 3 V
RDS(ON)
Low-Side MOSFET
ON-Resistance
ILIM
High-Side MOSFET
Current Limit
Phase2
Phase1
Phase2
per phase
4.2
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: TPSM82480
5
TPSM82480
SLVSDT1C – JULY 2017 – REVISED JUNE 2020
www.ti.com
Electrical Characteristics (continued)
over operating junction temperature range (TJ = –40°C to 125°C) and VIN = 2.4 V to 5.5 V. Typical values at VIN = 3.6 V and
TJ = 25°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT
VREF
Internal Reference Voltage
ILKG(FB)
Input Leakage Current (FB)
ILKG(RS)
Input Leakage Current (RS)
RRS
Internal resistance (RS to GND)
VOUT
Output Voltage Range
VIN ≥ VOUT
VOUT
Feedback Voltage Accuracy
PWM Mode,
VIN ≥ VOUT + 1
V
VOUT
Feedback Voltage Accuracy
Power Save Mode, L = 0.47 µH,
COUT = 4 x 22 µF (1)
Output Discharge Current (2)
EN = Low, VOUT = 2.5 V
120
mA
Load Regulation
VOUT = 1.8 V, PWM mode operation
0.02
%/A
Line Regulation
2.6 V ≤ VIN ≤ 5.5 V, VOUT = 1.8 V, IOUT = 6 A,
PWM mode operation
0.02
%/V
(1)
(2)
6
0.6
EN = High
V
VFB = 0.6 V
1
65
nA
VSEL = Low, VRS = 0.6 V
1
65
nA
VSEL = High, IRS = 1 mA
TJ = –20°C to 85°C
TJ = –40°C to 125°C
50
Ω
0.6
10
5.5
V
-1%
1%
-1.4%
1.3%
-1.4%
2.5%
The output voltage accuracy in Power Save Mode can be improved by increasing the output capacitor value, reducing the output voltage
ripple.
For detailed information on output discharge see Active Output Discharge.
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: TPSM82480
TPSM82480
www.ti.com
SLVSDT1C – JULY 2017 – REVISED JUNE 2020
6.6 Typical Characteristics
Figure 2. Quiescent Current
Figure 3. Shutdown Current
Figure 4. High-Side MOSFET Resistance
Figure 5. Low-Side MOSFET Resistance
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: TPSM82480
7
TPSM82480
SLVSDT1C – JULY 2017 – REVISED JUNE 2020
www.ti.com
7 Detailed Description
7.1 Overview
The TPSM82480 is a high efficiency synchronous switched mode step-down converter module based on a 2phase peak current control topology. It is designed for smallest solution size low-profile applications, converting a
2.4 V to 5.5 V input voltage into a lower 0.6 V to 5.5 V output voltage. While an outer voltage loop sets the
regulation threshold for the inner current loop, based on the actual VOUT level, the inner current loop regulates to
the actual peak inductor current level for every switching cycle. The regulation network is internally compensated.
While the ON-time is determined by duty cycle, inductance and cycle peak current, the switching frequency of
typically 2.2 MHz is set by a predicted OFF-time. The device features a Power Save Mode (PSM) to keep the
conversion efficiency high over the whole load current range.
The TPSM82480 is a 2-phase converter, sharing the load among the phases. Identical in construction, the
second phase control is connected with an adaptive delay to the first phase. Both the phases use the same
regulation threshold and cycle-by-cycle peak current setpoint. This ensures a phase-shifted as well as currentbalanced operation. Using the advantages of the 2-phase topology, a 6-A continuous output current is provided
with high performance and as small as possible solution size.
7.2 Functional Block Diagram
space
PG
VIN2
VIN1
VO
EN
PG control
UVLO
Power Save
Mode
VIN
VIN1
HS1
VIN
EN
VOUT
off-timer
VOUT1
VIN2
gate
drive
power
control
control logic
HS2
MODE
phase shift
VOUT2
HS2
tON2
SS/TR
Thermal
Shutdown
VREF
HS2
OCP
HS1
gm
tON1
VSEL
FB
gmout
delay
VREF
HS1
VSEL
RS
VSEL
TG control
TG
AGND
PGND1
PGND2
Copyright © 2017, Texas Instruments Incorporated
Figure 6. TPSM82480
8
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: TPSM82480
TPSM82480
www.ti.com
SLVSDT1C – JULY 2017 – REVISED JUNE 2020
7.3 Feature Description
7.3.1 Enable and Shutdown (EN)
The device starts operation, when VIN is present and enable (EN) is set High. Because the boundary EN
thresholds are specified with 1.2 V for rising and 0.4 V for falling voltages, the typical values are 0.85 V (rising)
and 0.65 V (falling). The device is disabled by pulling EN Low. Leaving the EN pin floating is not recommended.
7.3.2 Soft-Start (SS), Pre-biased Output
The internal soft-start circuit controls the output voltage slope during startup. This avoids excessive inrush
current and provides an adjustable controlled output-voltage rise time. The soft-start period also prevents
unwanted voltage drop from high impedance power sources or batteries.
When EN is set to start device operation, the device starts switching after a delay of typically 200 µs and VOUT
rises with a slope, controlled by the external capacitor which is connected to the SS/TR pin (soft start). Leaving
the SS/TR pin floating or connecting to VIN provides internally set fastest startup with a soft-start slope of
approxiimately 80 µs. See Application Curves for typical startup operation.
The device can start into a pre-biased output. In this case, the device starts switching, only when the internal set
point for VOUT increases above the pre-biased voltage level.
7.3.3 Tracking (TR)
The device tracks an external voltage applied to the SS/TR pin. The FB voltage tracks the external voltage as
long as it is below approxiimately 0.6V. Above 0.6V the device goes to normal operation. If the voltage at the
SS/TR pin decreases below approxiimately 0.6V, the FB voltage tracks again this voltage. See Tracking for
further details.
7.3.4 Output Voltage Select (VSEL)
A resistive divider (VOUT to FB to AGND) sets the output voltage of the TPSM82480. Providing a logic High
level at the VSEL pin, the RS pin is pulled to ground, so that a resistor, between FB and RS pins is connected in
parallel to the lower resistor of the divider. This sets a different higher output voltage and can be used for
dynamic voltage scaling (see Setting VOUT2 Using the VSEL Feature).
If the VSEL pin is set Low, the device connects an internal pull down resistor to the pin, keeping the internal logic
level Low, even if the pin is floating afterwards. The device disconnects the resistor, if the pin is set to High.
7.3.5 Forced PWM (MODE)
To avoid Power Save Mode (PSM) Operation, the device can be forced to PWM mode operation by pulling the
MODE pin High. In this case the device operates continuously with it's nominal switching frequency and the
minimum peak current can go as low as -500 mA.
If the MODE pin is set Low, the device connects an internal pull down resistor to keep the internal logic level
Low, even if the pin is floating afterwards. The device disconnects the resistor, if the pin is set to High.
7.3.6 Power Good (PG)
The TPSM82480 has a built in power good function. The PG pin goes High, when the output voltage has
reached its nominal value. Otherwise, including when disabled, in UVLO or thermal shutdown, PG is Low. The
PG pin is an open drain output that requires a pull-up resistor and can sink typically 2mA. If not used, the PG pin
can be left floating or grounded.
7.3.7 Thermal Good (TG)
As long as the junction temperature of the TPSM82480 is below the thermal good temperature of typically 120°C,
the logic level at the TG pin is High. If the junction temperature exceeds that temperature, the TG pin goes Low.
This can be used for the system to take action preventing excessive heating or even thermal shutdown. The TG
pin is an open drain output that requires a pull-up resistor and can sink typically 2mA. If not used, the TG pin can
be left floating or grounded.
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: TPSM82480
9
TPSM82480
SLVSDT1C – JULY 2017 – REVISED JUNE 2020
www.ti.com
Feature Description (continued)
7.3.8 Active Output Discharge
The VO pin, connected to the output voltage, provides an active discharge path when the device is switched off
by setting EN Low or UVLO event. In case of being activated, this discharge circuit sinks typically 120mA for
output voltages of typically 1 V and above. If VOUT is lower, the active current sink enters linear operation mode
and the discharge current decreases.
7.3.9 Undervoltage Lockout (UVLO)
The undervoltage lockout prevents misoperation of the device, if the input voltage drops below the UVLO
threshold which is set to typically 2.3 V. The converter starts operation again once the input voltage exceeds the
threshold by a hysteresis of typically 200 mV.
7.3.10 Thermal Shutdown
The junction temperature (TJ) of the device is monitored by an internal temperature sensor. If TJ exceeds 160°C
(typical), the device goes in thermal shutdown with a hysteresis of approxiimately 10°C. Both the power FETs are
turned off and the PG pin goes Low. Once TJ has decreased enough, the device resumes normal operation with
the soft-start sequence.
7.4 Device Functional Modes
7.4.1 Pulse Width Modulation (PWM) Operation
The TPSM82480 is based on a predictive OFF-time peak current control topology, operating with PWM in
continuous conduction mode for current loads larger than half the ripple current. The switching frequency is
typically 2.2MHz. Both the master and follower phase regulate to the same VOUT level, each with a separate
current loop, using the same peak current set point, cycle by cycle. This provides excellent peak current
balancing, independent of inductor dc resistance matching. Because the follower phase operates with an
adaptive delay to the master phase, phase shifted operation is always obtained. If the load current decreases,
the device runs with the master phase only (see Phase Add/Shed and Current Balancing).
PWM only mode can be forced by pulling MODE pin High. If MODE is set Low, the device features an automatic
transition into Power Save Mode, entered at light loads, running in discontinuous conduction mode (DCM).
7.4.2 Power Save Mode (PSM) Operation
As the load current decreases to half the ripple current, the converter enters Power Save Mode operation. During
PSM, the converter operates with reduced switching frequency maintaining high conversion efficiency. Power
Save Mode is based on an adaptive peak current target, to keep output voltage ripple low. Because each pulse
shifts VOUT up, a pause time happens until VOUT trips the internal VOUT_Low threshold again and the next pulse
takes place.
The switching frequency in PSM (one phase operation) calculates as:
space
fSW (PSM) =
2 × IOUT × VOUT (VIN - VOUT )
2
L × IPEAK
× VIN
(1)
7.4.3 Minimum Duty Cycle and 100% Mode Operation
The minimum on-time, which is typically 70ns, normally determines a limit on the minimum operating duty cycle.
The calculation is:
space
DCmin = 70ns × 100% × fSW [Hz]
(2)
space
However, a frequency foldback lowers the switching frequency depending on the duty cycle and ensures proper
regulation for every duty cycle.
10
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: TPSM82480
TPSM82480
www.ti.com
SLVSDT1C – JULY 2017 – REVISED JUNE 2020
Device Functional Modes (continued)
There is no limit towards maximum duty cycle. When the input voltage becomes close to the output voltage, the
device enters automatically 100% duty cycle mode and both high-side FETs switch on as long as VOUT remains
lower than the regulation setpoint. In this case, the voltage drop across the high-side FETs and the inductors
determines the output voltage level. An estimate for the minimum input voltage to maintain output voltage
regulation is:
space
kRDS :on ; + 20 mÀo
VIN:min ; = VOUT :min ; + IOUT × F
G
2
where
•
•
typical DCR of each inductor is 20 mΩ
the maximum DCR of each inductor is 27 mΩ
(3)
In 100% duty cycle mode, the low-side FETs are switched off. The typical quiescent current in 100% mode is
3.5 mA.
7.4.4 Phase Shifted Operation
Using an inherent benefit of the two-phase conversion, the two phases of TPSM82480 run out of phase. For
every switching cycle, the second phase is not allowed to turn on its high-side FET until the master phase has
reached its peak current value. This limits the input RMS current and corresponding switching noise.
7.4.5 Phase Add/Shed and Current Balancing
When the load current is below the internal threshold, only the master phase operates. The second phase
activates, if the load current exceeds the threshold of typically 1.7 A. The second phase powers off with a
hysteresis of approxiimately 0.5 A, when the load current decreases.
7.4.6 Current Limit and Short Circuit Protection
Each phase has a separate integrated peak current limit. The dc values are specified in the Electrical
Characteristics. While its minimum value limits the output current of the phase, the maximum number gives the
current that must be considered to flow in some operating case (e.g. overload). At the peak current limit, the
device provides its maximum output current.
However, if the current limit situation remains for 512 consecutive switching cycles, the peak current folds back to
approxiimately 1/3 of the regular limit. This limits the output power for over current and short circuit events. The
foldback current limit is released to the normal one only if the load current has decreased as far as needed to
undercut the (foldback) peak current limit.
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: TPSM82480
11
TPSM82480
SLVSDT1C – JULY 2017 – REVISED JUNE 2020
www.ti.com
8 Application and Implementation
space
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
space
8.1 Application Information
The TPSM82480 is a switched mode step-down converter module, able to convert a 2.4-V to 5.5-V input voltage
into a lower 0.6-V to 5.5-V output voltage, providing up to 6 A continuous output current. It needs a minimum
amount of external components. Apart from the output and input capacitors, additional resistors or capacitors are
only needed to enable features such as soft-start timing, adjustable and selectable output voltage as well as
power good and/or thermal good confirmation. The required power inductors are integrated inside the
TPSM82480. The inductors are shielded and have an inductance of 0.47 µH with approximately a +/- 20%
tolerance.
8.2 Typical Application
space
C1
VIN1
VOUT2
VOUT1
VIN2
VO
VIN
2.4 to 5.5V
VOUT/6A
C2
R1
TPSM82480
FB
EN
VPG
VTG
MODE
R4
R5
C5
VSEL
PG
TG
PGND
R3
C3/C4
C7/C8
RS
R2
SS/TR
AGND
PGND1
PGND2
PGND
Copyright © 2017, Texas Instruments Incorporated
space
Figure 7. Typical Application using TPSM82480 for a 6A Point-Of-Load Power Supply
space
8.2.1 Design Requirements
The following design guideline provides a range for the component selection to operate within the recommended
operating conditions. Table 1 shows the components selection that was used for the measurements shown in the
Application Curves.
12
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: TPSM82480
TPSM82480
www.ti.com
SLVSDT1C – JULY 2017 – REVISED JUNE 2020
Typical Application (continued)
Table 1. List of Components
REFERENCE
DESCRIPTION
MANUFACTURER
Power Module
5.5-V, 6-A step-down module with integrated inductor
TPSM82480MOP, Texas Instruments
C1, C2
2x22-µF, 10-V, ceramic, 0603, X5R
GRM188R61A226ME15#, muRata
C3, C4, C7, C8
4x22-µF, 25-V, ceramic, 0805, X5R
GRM21BR61E226ME44L, muRata
C5
3300-pF, 10-V, ceramic, 0402
Standard
R1, R2, R3
Depending on Vout1 and Vout2, chip, 0402, 0.1%
Standard
R4, R5
470-kΩ, chip, 0603, 1/16-W, 1%
Standard
8.2.2 Detailed Design Procedure
8.2.2.1 Setting the Output Voltage
Choose resistors R1 and R2 to set the output voltage within a range of 0.6 V to 5.5 V, according to Equation 4.
To keep the feedback (FB) net robust from noise, set R2 equal to or lower than 120 kΩ to have at least 5 µA of
current in the voltage divider. Lower values of FB resistors achieve better noise immunity, and lower light-load
efficiency, as explained in the application report, Design Considerations For A Resistive Feedback Divider In A
DC/DC Converter.
VOUT
R1 = R2 × l
F 1p
VFB
(4)
8.2.2.2 Setting VOUT2 Using the VSEL Feature
A different output voltage is dynamically set by connecting R3 between FB and RS pins and pulling VSEL High.
R3 is calculated using Equation 5.
space
R3 =
V1 × R1 × R22
( V2 - V1) × (R1 × R2 + R22 )
for ( V2 > V1)
where
•
•
V1 is the lower level output voltage
V2 the higher level output voltage.
(5)
space
8.2.2.3 Feedforward Capacitance
A feedforward capacitor (CFF) is recommended in parallel with R1. The CFF value may be further optimized for a
specific application, as explained in the application report, Optimizing Transient Response of Internally
Compensated DC-DC Converters.
8.2.2.4 Output Capacitor Selection
The recommended minimum output capacitance is 4 x 22 µF, that can be ceramic capacitors exclusively. A
larger value of output capacitance may be needed for VOUT ≤ 1.8 V, to improve transient response performance,
as well as for VOUT > 3.3 V to compensate for voltage bias effects of the ceramic capacitors. The usage of an
additional feed forward capacitor can help reducing amount of output capacitance that is needed to achieve a
certain transient response target (see Table 3).
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: TPSM82480
13
TPSM82480
SLVSDT1C – JULY 2017 – REVISED JUNE 2020
www.ti.com
The TPSM82480 provides a wide output voltage range from 0.6 V to 5.5 V. While stability is a critical criteria for
the output filter selection, the output capacitor value also determines transient response behavior, ripple and
accuracy of VOUT. The internal compensation is designed for an output capacitance range from approxiimately 50
µF to 150 µF effectively. Because ceramic capacitors are used preferably, this translates into nominal values of 4
x 22 µF to 4 x 47 µF and mainly depends on the output voltage. The following table shows recommended
capacitor combinations for different output voltage ranges. Combinations without checkmark may not be suitable
for all applications:
Table 2. Recommended Output Capacitor Values (nominal) (1)
VOUT ≤ 1.0 V
1.0 V ≤ VOUT ≤ 3.3 V
VOUT ≥ 3.3 V
2 × 22 µF
√
4 × 22 µF
√
4 × 47 µF
√
√
6 × 47 µF
(1)
The values in the table are nominal values. The effective capacitance can differ significantly,
depending on package size, voltage rating and dielectric material.
space
Beyond the recommendations in Table 2, other values can be chosen and might be suitable depending on VOUT
and actual effective capacitance. In such case, stability needs to be checked within the actual environment.
Even if the output capacitance is sufficient for stability, a different value might be desirable to improve the
transient response behavior. Table 3 can be used to determine capacitor values for specific transient response
targets:
Table 3. Recommended Output Capacitor Values (nominal)
Output Voltage [V]
1.0
1.8
2.5
3.3
(1)
Load Step [A]
0-3
3-6
0-3
3-6
0-3
3-6
0-3
3-6
Output Capacitor Value (1)
Feedforward Capacitor (1)
4 x 47 µF
4 x 22 µF
-
36 pF
4 x 22 µF
36 pF
4 x 47 µF
36 pF
Typical Transient
Response Accuracy
±mV
±%
50
5
50
5
50
3
50
3
62
2.5
50
2
100
3
80
2.5
The values in the table are nominal values. The effective capacitance can differ significantly, depending on package size, voltage rating
and dielectric material.
space
The architecture of the TPSM82480 allows the use of tiny ceramic output capacitors with low equivalent series
resistance (ESR). These capacitors provide low output voltage ripple and are recommended. To keep its low
resistance up to high frequencies and to get narrow capacitance variation with temperature, it is recommended to
use X5R or X7R dielectrics. Using even higher values than demanded for stability and transient response has
further advantages like smaller voltage ripple and tighter dc output accuracy in Power Save Mode.
8.2.2.5 Input Capacitor Selection
The input current of a buck converter is pulsating. Therefore, a low ESR input capacitor is required to prevent
large voltage transients at the source but still providing peak currents to the device. The recommended
Capacitance value for most applications is 2 x 10 µF, split between the VIN1 and VIN2 inputs and placed as
close as possible to these pins and PGND pins. If additional capacitance is needed, it can be added as bulk
capacitance. To ensure proper operation, the effective capacitance at the VIN pins must not fall below 2 x 5 µF.
14
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: TPSM82480
TPSM82480
www.ti.com
SLVSDT1C – JULY 2017 – REVISED JUNE 2020
Low ESR multilayer ceramic capacitors are recommended for best filtering. Increasing with input voltage, the dc
bias effect reduces the nominal capacitance value significantly. To decrease input ripple current further, larger
values of input capacitors can be used.
8.2.2.6 Soft-Start Capacitor Selection
The soft-start ramp time can be set externally connecting a capacitor between the SS/TR and AGND pins. The
capacitor value CSS that is needed to get a specific rising time ΔtSS calculates as:
space
CSS = Dt SS ×
5.25mA
0 .6 V
(6)
space
Because the device has an internal delay time ΔtDELAY from EN=High to start switching, the overall startup time is
longer as shown in Figure 8.
H
PG
L
H
EN
L
nom
VOUT
0
Dt DELAY
Dt SS
Figure 8. Soft-Start Timing (ΔtSS)
If very large output capacitances are used (e.g. >4x47µF), the use of a soft-start capacitor is mandatory to avoid
current limit foldback during startup (see Current Limit and Short Circuit Protection).
8.2.2.7 Tracking
For values up to 0.6V, an external voltage, connected to the SS/TR pin, drives the voltage level at the FB pin. In
doing so, the voltage at the FB pin is directly proportional to the voltage at the SS/TR pin.
When choosing the resistive divider proportion according to Equation 7, VOUT tracks VTR simultaneously.
space
R1 R3
=
R2 R 4
(7)
space
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: TPSM82480
15
TPSM82480
SLVSDT1C – JULY 2017 – REVISED JUNE 2020
www.ti.com
VTR
VOUT
TPSM82480
R3
R1
SS/TR
R4
FB
0.6V
R2
0V
Copyright © 2017, Texas Instruments Incorporated
Figure 9. Voltage Tracking
space
Following the example of Setting the Output Voltage with VOUT = 1.8 V, R1 = 240 kΩ and R2 = 120 kΩ,
Equation 8 and Equation 9 calculate R3 and R4, connected to the SS/TR pin. Different to the resistive divider at
the FB pin, a larger current must be chosen, to avoid a tracking offset caused by the 5.25 µA current that flows
out of the SS/TR pin. Assuming a 250 µA current, R4 calculates as follows:
space
R4 =
0 .6 V
= 2.4kW
250mA
(8)
space
R3 calculates now rearranging Equation 7:
space
R3 = R 4 ×
R1
240kW
= 2.4kW ×
= 4.8kW
R2
120kW
(9)
space
However, the following limitations can influence the tracking accuracy:
• The upper limit of the SS/TR voltage that can be tracked is approxiimately 0.6V. Because it is detected
internally by a comparator, process variation and ramp speed can cause up to ±30 mV different threshold.
• In case that the voltage at SS/TR ramps up immediately when VIN is supplied or EN is set High, the internal
startup delay, ΔtDELAY, delays the ramp of VOUT. The internal ramp starts after ΔtDELAY at the voltage level,
which is actually present at the SS/TR pin.
• The tracking down speed is limited by the RC time constant of the internal output discharge (always
connected when tracking down) and the actual load with the output capacitance. Note: The device tracks
down with the same behavior for MODE High (Forced PWM) and Low (Auto PSM).
8.2.2.8 Thermal Good
The Thermal Good pin provides an open drain output. The logic level is given by the pull up source which can be
VOUT. In this case, TG goes or stays Low, when the device switches off due to EN, UVLO or Thermal
Shutdown.
When using an independent source for the pull up logic, the logic behavior at shutdown differs, because the TG
pin internally goes high impedance. As before, TG goes Low when TG threshold is reached, but goes back High
in the event of being switched off (e.g. Thermal Shutdown).
16
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: TPSM82480
TPSM82480
www.ti.com
SLVSDT1C – JULY 2017 – REVISED JUNE 2020
8.2.3 Application Curves
VIN= 3.6 V, VOUT = 1.8V (R1 / R2 = 240 kΩ / 120 kΩ), TA = 25°C, MODE = Low, (unless otherwise noted)
VOUT = 3.2 V
VOUT = 3.2 V
Figure 10. Efficiency vs Output Current
VOUT = 1.8 V
Figure 11. Efficiency vs Input Voltage
VOUT = 1.8 V
Figure 12. Efficiency vs Output Current
VOUT = 0.9 V
Figure 13. Efficiency vs Input Voltage
VOUT = 0.9 V
Figure 14. Efficiency vs Output Current
Figure 15. Efficiency vs Input Voltage
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: TPSM82480
17
TPSM82480
SLVSDT1C – JULY 2017 – REVISED JUNE 2020
www.ti.com
MODE = High
MODE = High
Figure 16. Output Voltage vs Output Current
(Load Regulation)
VOUT = 0.6 V
Figure 17. Output Voltage vs Input Voltage
(Line Regulation)
VOUT = 5.5 V
Figure 18. Maximum Output Current
VOUT = 2.5 V
VOUT = 1 V
Figure 20. Switching Frequency vs Output Current
18
Figure 19. Maximum Output Current
Figure 21. Switching Frequency vs Output Current
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: TPSM82480
TPSM82480
www.ti.com
SLVSDT1C – JULY 2017 – REVISED JUNE 2020
70
60
70
Horizontal - QPK
Vertical - QPK
CISPR11 Group 1 Class B
60
50
Level (dBµV/m)
Level (dBµV/m)
50
40
30
40
30
20
20
10
10
0
30
H - QPK
V - QPK
CISPR11 Group 1 Class B
40 50 6070
100
200
300 400500
Frequency (MHz)
VIN = 6 V (battery supply) RLOAD = 0.33 Ω
EMI test board without filters
700 1000
0
30
40 50 6070
D027
D026
VOUT = 1.8 V
VSEL Low
Figure 22. TPSM82480 Radiated Emissioins
VOUT = 1.8 V
100
200
300 400500
Frequency (MHz)
VIN = 6 V (battery supply) RLOAD = 0.47 Ω
EMI test board without filters
700 1000
D026
VOUT = 2.5 V
VSEL High
Figure 23. TPSM82480 Radiated Emissioins
VOUT = 1.8 V
Figure 24. Startup into 3.3 Ω resistor
VOUT = 2.5 V
Figure 25. Startup into 0.3 Ω resistor
no load
VOUT = 1 V
Figure 26. Output Discharge
no load
Figure 27. Output Discharge
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: TPSM82480
19
TPSM82480
SLVSDT1C – JULY 2017 – REVISED JUNE 2020
www.ti.com
IOUT = 50 mA
Figure 28. Typical Operation PWM
Figure 29. Typical Operation PSM
Figure 30. Adding 2nd Phase
Figure 31. Shedding 2nd Phase
Cff = 36 pF (nom)
Figure 32. Load Transient Response (PSM-PWM),
Load Step 0 to 3 A
20
Figure 33. Load Transient Response (PSM-PWM),
Load Step 0 to 3 A
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: TPSM82480
TPSM82480
www.ti.com
SLVSDT1C – JULY 2017 – REVISED JUNE 2020
Cff = 36 pF (nom)
Figure 34. Load Transient Response (PWM-PWM),
Load Step 3 to 6 A
Cff = 36 pF (nom)
IOUT = 10 A
Figure 36. Load Transient Response (PWM-PWM),
Load Step 0 to 6 A
VIN = 5 V
Figure 35. Load Transient Response (PWM-PWM),
Load Step 3 to 6 A
Figure 37. Current Limit Fold-Back at Overload
VIN = 5 V
VOUT = 3.3 V
Figure 38. Maximum Ambient Temperature for TJ=125°C
(TPSM82480 EVM)
VOUT = 3.3 V
IOUT = 6 A
Figure 39. Device Temperature (TPSM82480 EVM)
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: TPSM82480
21
TPSM82480
SLVSDT1C – JULY 2017 – REVISED JUNE 2020
www.ti.com
8.3 System Examples
This section provides typical schematics for commonly used output voltage values.
space
space
22µF
1.8V & 2.5V/6A
VIN
VIN1
VOUT2
VOUT1
VIN2
VO
22µF
240k
TPSM82480
FB
EN
VTG
VPG
206k
MODE
3.3nF
470k
2x
22µF
120k
SS/TR
AGND
VSEL
PG
470k
2x
22µF
RS
PGND1
PGND2
TG
PGND
PGND
Copyright © 2017, Texas Instruments Incorporated
Figure 40. A typical 1.8 V & 2.5 V, 6 A Power Supply
space
Table 4. Resistive Divider Values for Combinations of
Output Voltages
VOUT
R1
R2
R3
2.5 V and 3.3 V
380 kΩ
120 kΩ
285 kΩ
1.2 V and 1.8 V
120 kΩ
120 kΩ
120 kΩ
0.9 V and 1.0 V
60 kΩ
120 kΩ
360 kΩ
space
9 Power Supply Recommendations
The TPSM82480 is designed to operate from a 2.4-V to 5.5-V input voltage supply. The input power supply's
output current needs to be rated according to the output voltage and the output current of the power rail
application.
22
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: TPSM82480
TPSM82480
www.ti.com
SLVSDT1C – JULY 2017 – REVISED JUNE 2020
10 Layout
10.1 Layout Guidelines
A recommended PCB layout for the TPSM82480 dual phase solution is shown below. It ensures best electrical
and optimized thermal performance considering the following important topics:
- Both VOUT1 and VOUT2 must be connected to build a common VOUT structure.
- The input capacitors must be placed as close as possible to the appropriate pins of the device. This provides
low resistive and inductive paths for the high di/dt input current. The input capacitance is split, as is the VIN
connection, to avoid interference between the input lines.
- The VOUT regulation loop is closed with COUT and its ground connection. To avoid PGND noise crosstalk, PGND
is kept split for the regulation loop. If a ground layer or plane is used, a direct connection by vias, as shown, is
recommended. Otherwise the connection of COUT to GND must be short for good load regulation.
- The FB node is sensitive to dv/dt signals. Therefore the resistive divider should be placed close to the FB (and
RS pin in case of using R3) pin, avoiding long trace distance.
For more detailed information about the actual EVM solution, see the TPSM82480EVM-002 User's Guide.
space
10.2 Layout Example
space
space
C3
PGND1
RS
PG
AGND
PGND
PGND2
PGND VOUT
R2
PGND2
SS/TR
C5
VOUT2
VIN2
PGND2
C2
PGND2
VB
TG
MODE
R1
R3
VO
VSEL
VIN2
VIN
VIN1
EN
C4
VOUT1
PGND1
VIN1
C1
PGND1
PGND1
PGND
C7
C8
Figure 41. TPSM82480 Board Layout
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: TPSM82480
23
TPSM82480
SLVSDT1C – JULY 2017 – REVISED JUNE 2020
www.ti.com
11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• TPSM82480EVM-BSR002 Evaluation Module User's Guide, SLVUB57
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
24
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: TPSM82480
TPSM82480
www.ti.com
SLVSDT1C – JULY 2017 – REVISED JUNE 2020
12.1 Tape and Reel Information
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
B0 W
Reel
Diameter
Cavity
A0
B0
K0
W
P1
A0
Dimension designed to accommodate the component width
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1
Q2
Q1
Q2
Q3
Q4
Q3
Q4
User Direction of Feed
Pocket Quadrants
Device
Package
Type
Package
Drawing
Pins
SPQ
Reel
Diameter
(mm)
Reel
Width W1
(mm)
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
TPSM82480MOPR
QFM
MOP
24
3000
330.0
16.0
3.85
8.15
1.7
8.0
16.0
Q2
TPSM82480MOPT
QFM
MOP
24
250
180.0
16.0
3.85
8.15
1.7
8.0
16.0
Q2
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: TPSM82480
25
TPSM82480
SLVSDT1C – JULY 2017 – REVISED JUNE 2020
www.ti.com
TAPE AND REEL BOX DIMENSIONS
Width (mm)
L
W
26
H
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPSM82480MOPR
QFM
MOP
24
3000
383.0
353.0
58.0
TPSM82480MOPT
QFM
MOP
24
250
223.0
194.0
35.0
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: TPSM82480
PACKAGE OPTION ADDENDUM
www.ti.com
14-Feb-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPSM82480MOPR
ACTIVE
QFM
MOP
24
3000
RoHS & Green
Call TI
Level-2-260C-1 YEAR
-40 to 125
82480
TPSM82480MOPT
ACTIVE
QFM
MOP
24
250
RoHS & Green
Call TI
Level-2-260C-1 YEAR
-40 to 125
82480
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
