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TPSM84209
SLVSE31C – JANUARY 2018 – REVISED JULY 2018
TPSM84209 4.5-V to 28-V Input, 1.2-V to 6-V Output, 2.5-A Power Module
1 Features
3 Description
•
The TPSM84209 power module is an easy-to-use
integrated power supply that combines a 2.5-A
DC/DC converter with a shielded inductor and
passives into a low-profile QFN package. This total
power solution allows as few as four external
components while maintaining an ability to adjust key
parameters to meet specific design requirements.
Complete Integrated Power Solution Allows
Small Footprint, Low-Profile Design
4.5-mm × 4-mm × 2-mm QFN Package
Wide-Output Voltage Range (1.2 V to 6 V)
Fixed Switching Frequency (750 kHz)
Advanced Eco-mode™ for Light Load Efficiency
Programmable Undervoltage Lockout (UVLO)
Overtemperature Thermal Shutdown Protection
Overcurrent Protection (Hiccup Mode)
Safe Prebias Output Start-Up
Operating IC Junction Range: –40°C to +125°C
Operating Ambient Range: –40°C to +85°C
Enhanced Thermal Performance: 29.5°C/W
Meets EN55011 Radiated EMI Standards
– Integrated Shielded Inductor
Create a Custom Design Using the TPSM84209
With the WEBENCH® Power Designer
1
•
•
•
•
•
•
•
•
•
•
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The QFN package is easy to solder to a printed
circuit board and has excellent power dissipation
capability. The TPSM84209 offers flexibility with
many features and is ideal for powering a wide range
of devices and systems.
Device Information(1)
DEVICE NUMBER
TPSM84209H
PACKAGE
QFN (9)
BODY SIZE
4.50 mm × 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
•
•
•
•
The wide input voltage range and small package size
of the TPSM84209 makes the device an excellent fit
for power rails that require up to 2.5 A of output
current.
Industrial and Motor Controls
Automated Test Equipment
Medical and Imaging Equipment
High-Density Power Systems
space
space
space
space
space
space
Simplified Application
Efficiency vs Output Current
100
VOUT
VOUT
VIN
RFBT
TPSM84209
CIN
EN
90
COUT
FB
GND
RFBB
Efficiency (%)
VIN
80
70
60
Copyright © 2018, Texas Instruments Incorporated
VOUT = 5.0 V
VIN = 12 V
VIN = 24 V
50
40
0.0
0.5
1.0
1.5
Output Current (A)
2.0
2.5
Eff1
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPSM84209
SLVSE31C – JANUARY 2018 – REVISED JULY 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
4
4
4
5
5
7
8
9
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics (VIN = 5 V)............................
Typical Characteristics (VIN = 12 V)..........................
Typical Characteristics (VIN = 24 V)..........................
Detailed Description ............................................ 10
7.1
7.2
7.3
7.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
10
10
11
20
8
Application and Implementation ........................ 21
8.1 Application Information............................................ 21
8.2 Typical Application .................................................. 21
9 Power Supply Recommendations...................... 23
10 Layout................................................................... 24
10.1
10.2
10.3
10.4
Layout Guidelines .................................................
Layout Examples...................................................
EMI........................................................................
Package Specifications .........................................
24
24
25
26
11 Device and Documentation Support ................. 27
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Device Support ....................................................
Custom Design With WEBENCH® Tools .............
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
27
27
27
27
27
27
28
12 Mechanical, Packaging, and Orderable
Information ........................................................... 28
12.1 Tape and Reel Information ................................... 32
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (June 2018) to Revision C
Page
•
Changed Package column in from "B3QFN (43)" to "QFN (9)" to correct error..................................................................... 1
•
Changed "RVQ Package" to "RKH Package", "43-pin B3QFN" to "9-Pin QFN" ................................................................... 3
Changes from Revision A (April 2018) to Revision B
•
Changed Min Storage temperature to -55°C.......................................................................................................................... 4
Changes from Original (January 2018) to Revision A
•
2
Page
Page
First release of production-data data sheet ........................................................................................................................... 1
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5 Pin Configuration and Functions
RKH Package
9-Pin QFN
Top View
SW
DNC
6
DNC
7
8
9
EN
5
GND
SW
VOUT
3
4
2
VIN
1
FB
Pin Functions
PIN
TYPE
(1)
DESCRIPTION
NAME
NO.
DNC
6, 7
—
EN
9
I
Enable pin. An open drain/collector device can be used to control the EN function. The module is
disabled when this pin is pulled low. This pin can also be connected to an external resistor divider
connected between VIN and GND to adjust the UVLO above the internal default setting. Float this
pin when not used.
FB
1
I
Feedback input. To adjust the output voltage connect this pin to the center point of an external
resistor divider connected between VOUT and GND.
GND
8
G
Ground pin. This is the return current path for the device. Connect this pin to the input source
return, the load return, and to the ground side of the VIN and VOUT bypass capacitors using power
ground planes on the PCB.
SW
4, 5
O
Switch node. These pins are connected to the input side of the internal output inductor. Do not
place any external components on these pins or tie them to a pin of another function.
VIN
2
I
Input voltage. Connect this pin to the input source and connect external bypass capacitors between
this pin and GND, close to the module.
VOUT
3
O
Output voltage. This pin is connected to the internal output inductor. Connect this pin to the output
load and connect external bypass capacitors between this pin and GND close to the module.
(1)
Do Not Connect. Do not connect these pins to GND or to any other voltage. These pins are
connected to internal circuitry. Each pin must be soldered to an isolated pad.
G = Ground, I = Input, O = Output
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6 Specifications
6.1 Absolute Maximum Ratings
Over operating ambient temperature range (unless otherwise noted) (1)
Input voltage
Output voltage
MIN
MAX
UNIT
VIN
–0.3
30
V
EN, FB
–0.3
7
V
SW
–0.3
30
V
–5
30
V
SW (20 ns transient)
VOUT
–0.3
Mechanical shock
Mil-STD-883D, Method 2002.3, 1 msec, 1/2 sine, mounted
Mechanical vibration
Mil-STD-883D, Method 2007.2, 20 to 2000 Hz
Operating IC junction temperature, TJ
Operating ambient temperature, TA
(2)
(2)
Storage temperature, Tstg
(1)
(2)
7
V
1500
G
20
G
–40
125
°C
–40
85
°C
–55
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or anyother conditions beyond those indicated under the
recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect
device reliability.
The ambient temperature is the air temperature of the surrounding environment. The junction temperature is the temperature of the
internal power IC when the device is powered. Operating below the maximum ambient temperature, as shown in the safe operating area
(SOA) curves in the typical characteristics sections, ensures that the maximum junction temperature of any component inside the
module is never exceeded.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2500
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
Over operating ambient temperature range (unless otherwise noted)
Input voltage, VIN
Output voltage, VOUT
MIN
MAX
UNIT
4.5 (1)
28 (2)
V
1.2
6
V
EN voltage, VEN
0
6
V
Output current, IOUT
0
2.5 (3)
A
°C
Operating ambient temperature, TA
–40
85
Operating IC junction temperature, TJ
–40
125
(1)
(2)
(3)
4
The minimum recommended input voltage is 4.5 V or (VOUT × 1.3), whichever is greater.
The maximum input voltage varies depending on the output voltage (see Operating Range ).
The maximum output current that the TPSM84209 can deliver is a function of input voltage, output voltage, and ambient temperature
(see Output Current Rating ).
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6.4 Thermal Information
TPSM84209
THERMAL METRIC (1)
RKH (QFN)
UNIT
9 PINS
RθJA
Junction-to-ambient thermal resistance (2)
(3)
ψJT
Junction-to-top characterization parameter
ψJB
Junction-to-board characterization parameter (4)
(1)
(2)
(3)
(4)
32.7
°C/W
2.2
°C/W
17
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
The junction-to-ambient thermal resistance, RθJA, applies to devices soldered directly to a 63 mm × 50 mm, 4-layer PCB with 2 oz.
copper and natural convection cooling. Additional airflow reduces RθJA.
The junction-to-top characterization parameter, ψJT, estimates the junction temperature, TJ, of a device in a real system, using a
procedure described in JESD51-2A (section 6 and 7). TJ = ψJT × Pdis + TT; where Pdis is the power dissipated in the device and TT is
the temperature of the top of the device.
The junction-to-board characterization parameter, ψJB, estimates the junction temperature, TJ, of a device in a real system, using a
procedure described in JESD51-2A (sections 6 and 7). TJ = ψJB × Pdis + TB; where Pdis is the power dissipated in the device and TB is
the temperature of the board 1mm from the device.
6.5 Electrical Characteristics
Over –40°C to +85°C ambient temperature, VIN = 12 V, VOUT = 3.3 V, IOUT = 2.5 A, (unless otherwise noted); CIN1 = 10-µF, 50V, 1210 ceramic; CIN2 = 100-µF, 35-V, electrolytic; COUT = 2 × 47-µF, 16-V, 1210 ceramic.
Minimum and maximum limits are specified through production test or by design. Typical values represent the expected value
for the given test conditions and may or may not be production tested.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
28 (2)
V
V
INPUT VOLTAGE (VIN)
VIN
Input voltage
UVLO
VIN undervoltage lockout
ISHDN
Shutdown supply current
4.5 (1)
Over IOUT range
VIN increasing
3.8
4.1
4.4
VIN decreasing
3.3
3.6
3.9
VEN = 0 V
2
V
µA
OUTPUT VOLTAGE (VOUT)
VOUT(ADJ)
Output voltage adjust
Over IOUT range
1.2
6
VOUT(Ripple)
Output voltage ripple
20-MHz bandwidth
Feedback voltage (3)
TA = 25°C, IOUT = 0.2 A
Temperature variation
–40°C ≤ TJ ≤ 125°C, IOUT = 0.2 A
Line regulation
TA = 25°C, 4.5 V ≤ VIN ≤ 28 V, IOUT = 0.2 A
0.2
%
Load regulation
Over IOUT range, TA = 25°C
0.5
%
Output current
Natural convection, TA = 25°C
22
V
mV
FEEDBACK
VFB
0.581
0.596
0.611
V
0.5%
CURRENT
IOUT
Overcurrent threshold
2.5 (4)
0
4.8
A
A
PERFORMANCE
VIN = 24 V,
IOUT = 1 A
ƞ
Efficiency
VIN = 12 V,
IOUT = 1 A
Transient response
(1)
(2)
(3)
(4)
VOUT = 5 V
86.5%
VOUT = 3.3 V
82.7%
VOUT = 2.5 V
79.3%
VOUT = 5 V
91.7%
VOUT = 3.3 V
89.0%
VOUT = 2.5 V
86.8%
25% to 75% load step Over/undershoot
1 A/µs slew rate
Recovery Time
90
mV
125
µs
The minimum recommended input voltage is 4.5 V or (VOUT × 1.3), whichever is greater.
The maximum input voltage varies depending on the output voltage (see Operating Range ).
The overall output voltage tolerance will be affected by the tolerance of the external RFBT and RFBB resistors.
The maximum output current that the TPSM84209 can deliver is a function of input voltage, output voltage, and ambient temperature
(see Output Current Rating ).
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Electrical Characteristics (continued)
Over –40°C to +85°C ambient temperature, VIN = 12 V, VOUT = 3.3 V, IOUT = 2.5 A, (unless otherwise noted); CIN1 = 10-µF, 50V, 1210 ceramic; CIN2 = 100-µF, 35-V, electrolytic; COUT = 2 × 47-µF, 16-V, 1210 ceramic.
Minimum and maximum limits are specified through production test or by design. Typical values represent the expected value
for the given test conditions and may or may not be production tested.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SOFT START
TSS
Internal soft-start time
5
ms
SWITCHING FREQUENCY
FSW
Switching frequency
578
750
923
kHz
1.21
1.28
V
ENABLE (EN)
VEN-RISING
VEN-FALLIN
IEN
EN threshold
Rising
Falling
1.1
1.19
V
0.7
µA
VEN = 1.5 V
1.55
µA
Shutdown temperature
165
°C
10
°C
EN Input current
VEN = 1 V
EN Hysteresis current
THERMAL
TSHDN
Thermal shutdown
Hysteresis
CAPACITANCE
CIN
External input capacitance
COUT
(5)
(6)
(7)
6
External output
capacitance
Ceramic type
10 (5)
Ceramic type
Non-ceramic type
µF
47 (5)
Non-ceramic type
min (6)
µF
500 (7)
µF
(7)
µF
500
A minimum of 10 µF ceramic input capacitance is required for proper operation. An additional 47 µF of bulk capacitance is
recommended for applications with transient load requirements.
The minimum amount of required output capacitance varies depending on the output voltage (see Output Capacitor Selection ). A
minimum amount of ceramic capacitance is required. Locate the capacitance close to the device. Adding additional ceramic or nonceramic capacitance close to the load improves the response of the regulator to load transients.
The maximum output capacitance of 500 µF can be made up of all ceramic type or a combination of both ceramic and non-ceramic
type.
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6.6 Typical Characteristics (VIN = 5 V)
TA = 25°C, unless otherwise noted.
1.8
100
1.5
Power Dissipation (W)
Efficiency (%)
90
80
70
60
VOUT
3.3 V
2.5 V
1.8 V
1.2 V
50
40
0.0
0.5
1.0
1.5
Output Current (A)
2.0
1.2
0.9
0.6
0.3
0.0
0.0
2.5
0.5
D001
Figure 1. Efficiency vs Output Current
1.0
1.5
Output Current (A)
2.0
2.5
D002
Figure 2. Power Dissipation vs Output Current
50
95
VOUT
1.2 V
1.8 V
2.5 V
3.3 V
40
85
Ambient Temperature (°C)
Output Voltage Ripple (mV)
VOUT
3.3 V
2.5 V
1.8 V
1.2 V
30
20
10
75
65
55
45
35
0
0.0
0.5
1.0
1.5
Output Current (A)
2.0
2.5
Airflow
100LFM
Nat Conv
25
0.0
0.5
D003
1.0
1.5
Output Current (A)
2.0
2.5
D004
VOUT = 2.5 V
Minimum Required COUT
Figure 4. Safe Operating Area
Figure 3. Voltage Ripple vs Output Current
95
Ambient Temperature (°C)
85
75
65
55
45
35
25
0.0
Airflow
100LFM
Nat Conv
0.5
1.0
1.5
Output Current (A)
2.0
2.5
D005
VOUT = 3.3 V
Figure 5. Safe Operating Area
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6.7 Typical Characteristics (VIN = 12 V)
TA = 25°C, unless otherwise noted.
1.8
100
1.5
Power Dissipation (W)
Efficiency (%)
90
80
70
60
VOUT
5.0 V
3.3 V
2.5 V
1.8 V
50
40
0.0
VOUT
5.0 V
3.3 V
2.5 V
1.8 V
0.5
1.0
1.5
Output Current (A)
2.0
1.2
0.9
0.6
0.3
0.0
0.0
2.5
Figure 6. Efficiency vs Output Current
VOUT
1.8 V
2.5 V
3.3 V
5.0 V
2.5
D007
80
85
Ambient Temperature (°C)
100
60
40
75
65
55
45
Airflow
100LFM
Nat Conv
35
0
0.0
0.5
1.0
1.5
Output Current (A)
2.0
25
0.0
2.5
0.5
D008
85
85
Ambient Temperature (°C)
95
75
65
55
45
25
0.0
Airflow
100LFM
Nat Conv
0.5
2.5
D009
75
65
55
45
Airflow
200LFM
100LFM
Nat Conv
35
1.0
1.5
Output Current (A)
2.0
Figure 9. Safe Operating Area
Figure 8. Voltage Ripple vs Output Current
95
35
1.0
1.5
Output Current (A)
VOUT = 2.5 V
Minimum Required COUT
Ambient Temperature (°C)
2.0
Figure 7. Power Dissipation vs Output Current
20
2.0
2.5
25
0.0
0.5
D010
VOUT = 3.3 V
1.0
1.5
Output Current (A)
2.0
2.5
D011
VOUT = 5 V
Figure 10. Safe Operating Area
8
1.0
1.5
Output Current (A)
95
120
Output Voltage Ripple (mV)
0.5
D006
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Figure 11. Safe Operating Area
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6.8 Typical Characteristics (VIN = 24 V)
TA = 25°C, unless otherwise noted.
1.8
100
1.5
Power Dissipation (W)
Efficiency (%)
90
80
70
60
VOUT
5.0 V
3.3 V
50
40
0.0
0.5
1.0
1.5
Output Current (A)
2.0
1.2
0.9
0.6
0.3
0.0
0.0
2.5
Figure 12. Efficiency vs Output Current
1.0
1.5
Output Current (A)
2.0
2.5
D013
Figure 13. Power Dissipation vs Output Current
95
VOUT
3.3 V
5.0 V
160
140
85
Ambient Temperature (°C)
Output Voltage Ripple (mV)
0.5
D012
180
120
100
80
60
40
75
65
55
45
35
20
0
0.0
VOUT
5.0 V
3.3 V
0.5
1.0
1.5
Output Current (A)
2.0
2.5
Airflow
200LFM
100LFM
Nat Conv
25
0.0
0.5
D014
1.0
1.5
Output Current (A)
2.0
2.5
D015
VOUT = 3.3 V
COUT = 2× 47 µF ceramic
Figure 15. Safe Operating Area
Figure 14. Voltage Ripple vs Output Current
95
Ambient Temperature (°C)
85
75
65
55
45
35
25
0.0
Airflow
400LFM
200LFM
100LFM
Nat conv
0.5
1.0
1.5
Output Current (A)
2.0
2.5
D016
VOUT = 5 V
Figure 16. Safe Operating Area
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7 Detailed Description
7.1 Overview
The TPSM84209 is a highly integrated 28-V input, 2.5-A, synchronous step-down power module with PWM,
MOSFETs, inductor, and control circuitry integrated into a low-profile, overmolded, QFN package. This device
enables small designs by integrating all but the input and output capacitors and voltage-setting resistor divider
while keeping the ability to adjust key parameters to meet specific design requirements. The TPSM84209
operates at a 750-kHz fixed switching frequency and features advanced Eco-mode™ pulse-skip operation for
improved light-load efficiency. The TPSM84209 provides an adjustable output-voltage range of 1.2 V to 6 V using
a simple external-resistor divider. The TPSM84209 provides accurate voltage regulation for a variety of loads by
using an internal voltage reference that is 2.5% accurate over temperature. The output-voltage rise time is
controlled by a fixed 5-ms soft start. Input UVLO is internally set at 4.1 V, but can be adjusted upward using a
resistor divider on the EN pin of the module. The EN pin can also be pulled low to put the module in standby
mode to reduce input quiescent current. Thermal shutdown and current limit features protect the device during an
overload condition. A 9-pin, 4-mm × 4.5-mm B3QFN package that includes exposed bottom pads provides a
thermally enhanced solution for space-constrained applications.
7.2 Functional Block Diagram
Shutdown
Logic
EN
Thermal
Shutdown
FB
VIN
UVLO
VIN
SW
OCP
2.2 µH
+
+
Comp
VREF
Power
Stage
and
Control
Logic
Soft
Start
VOUT
GND
Oscillator
10
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7.3 Feature Description
7.3.1 Adjusting the Output Voltage
A resistor divider connected to the FB pin (pin 1) programs the output voltage of the TPSM84209. The output
voltage adjustment range is from 1.2 V to 6 V. Figure 17 shows the feedback resistor connection for setting the
output voltage. The recommended value of RFBT is 10 kΩ. Table 1 lists the closest standard E96 value for the
RFBB resistor for a number of common output voltages. For other output voltages, the value of the required RFFB
resistor can be calculated using Equation 1.
RFBB =
6
(VOUT ± 0.6)
(k )
(1)
VOUT
RFBT
10 k
FB
RFBB
GND
Figure 17. Setting the Output Voltage
Table 1. Standard RFBB Resistor Values
VOUT (V)
RFBB (kΩ)
VOUT (V)
RFBB (kΩ)
1.2
10.0
3.7
1.96
1.3
8.45
3.8
1.87
1.4
7.50
3.9
1.82
1.5
6.65
4.0
1.74
1.6
6.04
4.1
1.69
1.7
5.36
4.2
1.65
1.8
4.99
4.3
1.62
1.9
4.64
4.4
1.58
2.0
4.22
4.5
1.54
2.1
4.02
4.6
1.50
2.2
3.74
4.7
1.47
2.3
3.48
4.8
1.43
2.4
3.32
4.9
1.40
2.5
3.16
5.0
1.37
2.6
3.01
5.1
1.33
2.7
2.87
5.2
1.30
2.8
2.74
5.3
1.27
2.9
2.61
5.4
1.24
3.0
2.49
5.5
1.22
3.1
2.37
5.6
1.20
3.2
2.32
5.7
1.18
3.3
2.21
5.8
1.15
3.4
2.15
5.9
1.13
3.5
2.05
6.0
1.10
3.6
2.00
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Product Folder Links: TPSM84209
11
TPSM84209
SLVSE31C – JANUARY 2018 – REVISED JULY 2018
www.ti.com
7.3.2 Input Capacitor Selection
The TPSM84209 requires a ceramic input capacitor with a minimum effective capacitance of 10 μF. Use only
high-quality ceramic type X5R or X7R capacitors with sufficient voltage rating. An additional 47 µF of nonceramic capacitance is recommended for applications with transient load requirements. The voltage rating of
input capacitors must be greater than the maximum input voltage. To compensate for the derating of ceramic
capacitors, TI recommends a voltage rating of twice the maximum input voltage. At worst case, when operating
at 50% duty cycle and maximum load, the combined ripple current rating of the input capacitors must be at least
1.25 Arms. Table 2 includes a preferred list of capacitors by vendor.
Table 2. Recommended Input Capacitors (1)
CAPACITOR CHARACTERISTICS
VENDOR
SERIES
PART NUMBER
WORKING VOLTAGE (V)
CAPACITANCE
(µF)
(2)
ESR (3)
(mΩ)
TDK
X5R
C3225X5R1H106K
50
10
3
Murata
X7R
GRM32ER71H106K
50
10
2
Murata
X7R
GRM32ER71J106K
63
10
2
Panasonic
ZA
EEHZA1H101P
50
100
28
Panasonic
ZA
EEHZA1J560P
63
56
30
(1)
(2)
(3)
Capacitor Supplier Verification, RoHS, Lead-free and Material Details
Consult capacitor suppliers regarding availability, material composition, RoHS and lead-free status, and manufacturing process
requirements for any capacitors identified in this table.
Specified capacitance values
Maximum ESR at 100 kHz, 25°C.
7.3.3 Undervoltage Lockout (UVLO)
The TPSM84209 device has an internal UVLO circuit which prevents the device from operating until the VIN
voltage exceeds the UVLO rising threshold, (4.1 V (typical)). The device is disabled when the VIN pin voltage
falls below the internal VIN UVLO threshold. The internal VIN UVLO threshold has a hysteresis of 500 mV.
Applications may require a higher UVLO threshold to prevent early turnon, for sequencing requirements or to
prevent input current draw at lower input voltages. An external resistor divider can be added to the EN pin to
adjust the UVLO threshold higher. The external resistor divider can be configured as shown in Figure 18. Table 3
lists standard values for RUVLO1 and RUVLO2 to adjust the UVLO voltage higher.
VIN
RUVLO1
EN
RUVLO2
GND
Figure 18. Adjustable UVLO
Table 3. Standard Resistor Values for Adjusting UVLO
12
VIN UVLO (V)
4.5
10
15
18
20
RUVLO1 (kΩ)
68.1
68.1
68.1
68.1
68.1
RUVLO2 (kΩ)
25.5
9.53
6.04
4.99
4.42
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Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TPSM84209
TPSM84209
www.ti.com
SLVSE31C – JANUARY 2018 – REVISED JULY 2018
7.3.4 Output Capacitor Selection
The minimum amount of required output capacitance for the TPSM84209 varies depending on the output voltage
and whether or not a feed-forward capacitor, CFF, is used (see Feed-Forward Capacitor for more information on
CFF). Table 4 lists the minimum output capacitance for several output voltage ranges when not using CFF. The
required output capacitance must be comprised of all ceramic capacitors or a combination of ceramic and
polymer-type capacitors. The effects of temperature and capacitor voltage rating must be considered when
selecting capacitors to meet the minimum required capacitance.
When adding additional output capacitance, ceramic capacitors or a combination of ceramic and polymer-type
capacitors can be used. The required capacitance above the minimum is determined by actual transient
deviation requirements. See Table 5 for a preferred list of output capacitors by vendor.
Table 4. Minimum Required Output Capacitance
VOUT RANGE (V)
(1)
Minimum Required COUT
MIN
MAX
1.2
< 1.5
188 µF (4 x 47 µF ceramic) (1)
1.5
< 2.5
141 µF (3 x 47 µF ceramic) (1)
2.5
