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TPSM84A21
SLVSDF7A – DECEMBER 2016 – REVISED JULY 2017
TPSM84A21, 8-V to 14-V Input, 0.508-V to 1.35-V Output, 10-A SWIFT™ Power Module
1 Features
3 Description
•
The TPSM84A21 is an easy-to-use integrated power
solution that combines the TPS54A20, a 10-A,
DC/DC, synchronous, step-down converter with
power MOSFETs, shielded inductors, input and
output capacitors, and passives into a low profile
package. This total power solution requires only one
voltage-setting resistor, and eliminates the loop
compensation and magnetics part selection from the
design process.
1
•
•
•
•
•
•
•
•
•
•
•
•
•
Fully Integrated Power Solution Includes Input and
Output Capacitors
Only Requires a Single Voltage Setting Resistor
9 mm × 15 mm Footprint
– 2.3 mm Max Height
– Pin Compatible With TPSM84A22
Ultra-Fast Load Step Response
Efficiencies up to 88%
1% Output Voltage Accuracy
4 MHz Switching Frequency
Synchronizes to an External Clock
Power Good Output
Pre-Bias Output Start-Up
Programmable Under-Voltage Lockout (UVLO)
Operating IC Junction Range: –40°C to +125°C
Operating Ambient Range: –40°C to +85°C
Meets EN55022 Class B Emissions
The 9 × 15 mm PCB footprint is easy to solder onto a
printed circuit board and allows a compact, low-profile
point-of-load design.
Device Information(1)
PART NUMBER
2 Applications
•
•
•
The completely integrated power solution allows
standard applications to operate with no additional
input or output capacitors and only a single external
resistor to set the output voltage. High frequency
operation, ultra-fast transient response, and accurate
voltage regulation allow the TPSM84A21 to meet tight
regulation specs.
TPSM84A21
Telecom and Wireless Infrastructure
Test and Measurement
Compact PCI/ PCI Express/ PXI Express
PACKAGE
QFM
BODY SIZE (NOM)
9.00 mm × 15.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Device Comparison
PART NUMBER
VOUT ADJUST RANGE
TPSM84A21
0.55 V - 1.35 V
TPSM84A22
1.2 V - 2.05 V
SPACE
Simplified Schematic
VIN
VIN
Transient Response
VS+
EN/UVLO
VOUT
VOUT
TPSM84A21
PGOOD
VG
SYNC
ILIM
VADJ
AGND PGND
RSET
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPSM84A21
SLVSDF7A – DECEMBER 2016 – REVISED JULY 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
4
4
4
5
5
7
7
8
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Package Specifications .............................................
Typical Characteristics .............................................
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ....................................... 10
7.3 Feature Description................................................. 11
7.4 Device Functional Modes........................................ 15
8
Application and Implementation ........................ 16
8.1 Application Information............................................ 16
8.2 Typical Application ................................................. 16
9 Power Supply Recommendations...................... 18
10 Layout................................................................... 19
10.1 Layout Guidelines ................................................. 19
10.2 Layout Examples................................................... 19
10.3 EMI........................................................................ 21
11 Device and Documentation Support ................. 22
11.1
11.2
11.3
11.4
11.5
11.6
Documentation Support .......................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
22
22
22
22
22
22
12 Mechanical, Packaging, and Orderable
Information ........................................................... 22
12.1 Tape and Reel Information ................................... 23
4 Revision History
Changes from Original (December 2016) to Revision A
Page
•
Deleted Feature MSL 3 / 245°C Peak Reflow........................................................................................................................ 1
•
Added the EMI section ......................................................................................................................................................... 21
2
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SLVSDF7A – DECEMBER 2016 – REVISED JULY 2017
5 Pin Configuration and Functions
PGOOD
SYNC
18
VG
PGND
VS+
17
VADJ
VIN
AGND
MOJ Package
20-Pin QFM
Top View
16
15
14
13
12
11
3
4
5
6
7
PGND
2
PGND
1
PGND
PGND
PGND
19
ILIM
VIN
EN/UVLO
20
PGND
10
PGND
9
VOUT
8
PGND
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
AGND
16
—
EN/UVLO
2
I
Enable and UVLO adjust pin. When this pin voltage is low, the device is disabled. Use an open drain,
open collector, or a suitable logic gate device to control the enable function. A resistor divider
between this pin, PGND, and VIN adjusts the UVLO voltage.
ILIM
3
I
Current limit setting pin. Leave this open for the full current limit threshold of 15 A. Connect a 47 kΩ
resistor between this pin and PGND to reduce the current limit threshold to 11.25 A.
1, 4, 5, 6, 7,
8, 10, 18, 20
—
Power ground of the device. Connect these pins to the power ground plane of the PCB. Thermal vias
to internal ground planes should be added beneath pin 20.
PGOOD
12
O
Power good indicator. This pin is an open-drain output and will assert low if the output voltage is
greater than ±5% from the programmed value or due to thermal shutdown, under-voltage, or EN
shutdown. A pull-up resistor is required. VG can be used as a PGOOD pull-up source.
VS+
14
I
Remote sense connection. This pin must be connected to VOUT at the load or at the device pins.
Connect the pin to VOUT at the load for improved regulation.
SYNC
11
I
External clock synchronization pin. An external clock signal can be applied to this pin to synchronize
the switching frequency within ±10% of the nominal switching frequency (4 MHz).
VADJ
15
I
Output voltage adjust pin. Connecting a resistor between this pin and AGND sets the output voltage.
VG
13
I
Gate driver supply pin. If this pin is left open, an internal LDO will generate the gate driver supply
voltage from the VIN pin. To reduce power consumption and improve efficiency, power this pin with
an external 5-V supply. This pin can be used as a PGOOD pull-up source.
VIN
17, 19
I
Input Voltage. These pins supply all of the power to the converter. Connect VIN to a supply voltage
between 8 V and 14 V.
9
O
Output voltage. Connect any external output capacitors between these pins and PGND.
PGND
VOUT
Zero voltage reference for analog control circuitry. Connect RSET between this pin and VADJ close
to the device. Do not connect this pin to PGND; the connection is made internal to the device.
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SLVSDF7A – DECEMBER 2016 – REVISED JULY 2017
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Input voltage
MIN
MAX
UNIT
VIN
–0.3
15
V
EN/UVLO
–0.3
7
V
PGOOD, SYNC, VG
–0.3
6
V
ILIM, VADJ, VS+
–0.3
3
V
V
PGND
–0.3
0.3
Output voltage
VOUT
–0.3
3
V
Source current
EN/UVLO
100
µA
VG
100
mA
4
mA
Sink current
PGOOD
Mechanical shock
Mil-STD-883D, Method 2002.3, 1 msec, 1/2 sine, mounted
500
G
Mechanical vibration
Mil-STD-883D, Method 2007.2, 20-2000Hz
20
G
Operating IC junction temperature, TJ
(2)
–40
125
°C
Operating ambient temperature, TA (2)
–40
85
°C
Storage temperature, Tstg
–55
150
°C
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The ambient temperature is the air temperature of the surrounding environment. The junction temperature is the temperature of the
internal power IC when the device is powered. Operating below the maximum ambient temperature, as shown in the safe operating area
(SOA) curves, ensures that the maximum junction temperature of any component inside the module is never exceeded.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2500
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VIN
Input voltage
VOUT
Output voltage
VVG
Gate drive voltage
VEN
VPGOOD
NOM
MAX
UNIT
8
14
V
0.55
1.35
V
5.0
5.5
V
EN voltage
0
5.5
V
PGOOD pull-up voltage
0
5.5
V
VSYNC
SYNC voltage
0
5.5
V
IOUT
Output current
TJ
Operating IC junction temperature
TA
Operating ambient temperature
(1)
4
(1)
(1)
0
10
A
–40
125
°C
–40
85
°C
The ambient temperature is the air temperature of the surrounding environment. The junction temperature is the temperature of the
internal power IC when the device is powered. Operating below the maximum ambient temperature, as shown in the safe operating area
(SOA) curves, ensures that the maximum junction temperature of any component inside the module is never exceeded.
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6.4 Thermal Information
TPSM84A21
THERMAL METRIC (1)
MOJ (QFM)
UNIT
20 PINS
RθJA
Junction-to-ambient thermal resistance
(2)
(3)
ψJT
Junction-to-top characterization parameter
ψJB
Junction-to-board characterization parameter
(1)
(2)
(3)
(4)
(4)
14.9
°C/W
2.2
°C/W
5.7
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
The junction-to-ambient thermal resistance, ΘJA, applies to devices soldered directly to a 50 mm x 100 mm double-sided PCB with 2 oz.
copper and natural convection cooling. Additional airflow reduces ΘJA.
The junction-to-top board characterization parameter, ΘJT, estimates the junction temperature, TJ, of a device in a real system, using a
procedure described in JESD51-2A (section 6 and 7). TJ = ψJT * Pdis + TT; where Pdis is the power dissipated in the device and TT is
the temperature of the top of the device.
The junction-to-board characterization parameter, ψJB, estimates the junction temperature, TJ, of a device in a real system, using a
procedure described in JESD51-2A (sections 6 and 7). TJ = ψJB * Pdis + TB; where Pdis is the power dissipated in the device and TB is
the temperature of the board 1mm from the device.
6.5 Electrical Characteristics
Over –40°C to +85°C free-air temperature range, VIN = 12 V, VOUT = 1.0 V, IOUT = IOUT max, FSW = 4 MHz,
External CIN = 2 × 22 µF 25 V 1210 ceramic plus 1 × 100 µF electrolytic (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
INPUT VOLTAGE (VIN)
VIN
VIN input voltage range
VIN_UVLO
VIN under voltage lock out
VIN_HYS
VIN UVLO hysteresis
IVIN_EN
VIN standby current
Over VOUT range
8
14
V
7.95
V
VIN increasing
7.65
VIN decreasing
7.4
V
250
mV
47
µA
EN = 0 V
OUTPUT VOLTAGE (VOUT)
VOUT(ADJ)
VOUT
VOUT
Ripple
Output voltage adjust range
Over IOUT range
Set-point voltage tolerance
VOUT = 1.0 V, TA = 25°C, IOUT = 0 A
Temperature variation
VOUT = 1.0 V, –40°C ≤ TA ≤ 85°C, IOUT = 0 A
Line regulation
VOUT = 1.0 V, over VIN range, IOUT = 0 A, TA = 25°C
Load regulation
VOUT = 1.0 V, over IOUT range, TA = 25°C
Output Voltage Ripple
20-MHz Bandwidth, peak-to-peak
0.55
1.35
-1.0%
(1)
+1.0%
V
±0.2% (2)
±0.03%
±0.1%
8
mV
OUTPUT CURRENT
Output current
IOUT
(1)
(2)
Overcurrent threshold
See SOA graph for derating over temperature.
ILIM = open
ILIM = 47 kΩ
0
10
A
15
A
11.25
A
The stated limit of the set-point tolerance includes the tolerance of both the internal voltage reference and the internal adjustment
resistor. The overall output voltage tolerance will be affected by the tolerance of the external RSET resistor.
Specified by design. Not production tested.
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Electrical Characteristics (continued)
Over –40°C to +85°C free-air temperature range, VIN = 12 V, VOUT = 1.0 V, IOUT = IOUT max, FSW = 4 MHz,
External CIN = 2 × 22 µF 25 V 1210 ceramic plus 1 × 100 µF electrolytic (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
PERFORMANCE
Efficiency (2)
ƞ
VOUT = 0.8 V, VG = open
79.8%
VOUT = 0.8 V, VG = 5 V
82.5%
VOUT = 1.0 V, VG = open
82.6%
VOUT = 1.0 V, VG = 5 V
84.9%
VOUT = 1.2 V, VG = open
84.5%
VOUT = 1.2 V, VG = 5 V
86.5%
1 A/µs load step,
25% to 75% IOUT(max),
COUT= 0 µF
VOUT over/undershoot
10
mV
Recovery Time
10
µs
5 A/µs load step,
25% to 75% IOUT(max),
COUT= 0 µF
VOUT over/undershoot
25
mV
Recovery Time
10
µs
4.1
ms
VIN = 12 V, IOUT = 5 A
Transient Response (2)
SOFT START
Internal soft start time (2)
TSS
INTERNAL REGULATOR (VG)
VVG
VG pin output voltage
4.4
4.8
5.0
1.17
1.23
1.27
V
ENABLE AND UNDER-VOLTAGE LOCK-OUT (EN/UVLO)
VEN
EN threshold range
IEN
V
Input current
EN threshold + 50 mV
–4
µA
Hysteresis current
EN threshold – 50 mV
–1
µA
POWER GOOD (PGOOD)
VVOUT falling (Fault)
VPGOOD
PGOOD Thresholds
(2)
89%
VVOUT rising (Good)
95%
VVOUT rising (Fault)
109%
VVOUT falling (Good)
104%
Minimum VIN for valid
PGOOD (2)
VPGOOD ≤ 0.5 V at 100 µA
PGOOD Low Voltage
IPGOOD = 1.7 mA
1.2
2.75
V
0.25
0.3
V
THERMAL SHUTDOWN
Thermal shutdown threshold
135
°C
Thermal shutdown hysteresis
20
°C
µF
CAPACITANCE
CIN
External Input Capacitance
COUT
External Output Capacitance
Ceramic type
0 (3)
44
Non-ceramic type
0 (3)
100
Ceramic type
0
Non-ceramic type
0 (4)
Equivalent series resistance (ESR)
(3)
(4)
(5)
6
(4)
µF
1000
(5)
µF
2200 (5)
µF
35
mΩ
Internal to the device, 66.1 µF (nominal) ceramic input capacitance is present. This device does not require additional input capacitance.
If adding additional input capacitance, locate the capacitors close to the device.
Internal to the device, 185 µF (nominal) ceramic output capacitance is present. This device does not require additional output
capacitance to operate. Adding additional output capacitance near the load improves the response of the device to load transients.
The maximum output capacitance listed in the table is the maximum amount that has been tested and validated for proper start-up,
stability, and transient response. It may be possible to operate with additional output capacitance, however, additional validation is
required.
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6.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
3.7
4
4.3
MHz
4.4
MHz
FREQUENCY AND SYNCHRONIZATION (SYNC)
(1)
FSW
Switching frequency
SYNC = open
FSYNC
Synchronization frequency range
3.6
VSYNC-H
SYNC high threshold
2.0
VSYNC-L
SYNC low threshold
DSYNC
SYNC duty cycle
(1)
SYNC Control
V
0.8
20%
V
80%
Specified by design. Not production tested.
6.7 Package Specifications
TPSM84A21
Weight
Flammability
Meets UL 94 V-O
MTBF Calculated Reliability
Per Bellcore TR-332, 50% stress, TA = 40°C, ground benign
VALUE
UNIT
0.91
grams
30.6
MHrs
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6.8 Typical Characteristics
The electrical characteristic data has been developed from actual products tested at 25°C. This data is
considered typical for the converter. Applies to Figure 1 through Figure 4.
95
95
90
90
85
85
80
80
Efficiency (%)
Efficiency (%)
The temperature derating curves represent the conditions at which internal components are at or below the
manufacturer's maximum operating temperatures. Derating limits apply to devices soldered directly to a 50 mm ×
100 mm double-sided PCB with 2 oz. copper. Applies to Figure 5 and Figure 6.
75
70
65
VOUT
1.35 V
1.2 V
1.0 V
0.8 V
0.55 V
60
55
50
75
70
65
VOUT
1.35 V
1.2 V
1.0 V
0.8 V
0.55 V
60
55
50
45
45
0
1
2
3
VIN = 12 V
4
5
6
Output Current (A)
7
8
9
0
10
1
2
3
D001
VG = open
VIN = 12 V
7
8
9
10
D004
VG = 5 V
Figure 1. Efficiency
Figure 2. Efficiency
3.0
16
2.4
2.1
Output Ripple Voltage (mV)
VOUT
1.35 V
1.2 V
1.0 V
0.8 V
0.55
2.7
Power Dissipation (W)
4
5
6
Output Current (A)
1.8
1.5
1.2
0.9
VOUT
1.35 V
1.2 V
1.0 V
0.8 V
0.55
14
12
10
8
0.6
0.3
6
0
1
2
VIN = 12 V
3
4
5
6
Output Current (A)
7
8
VG = open
9
10
0
1
3
4
5
6
Output Current (A)
7
8
9
10
D003
VIN = 12 V
Figure 3. Power Dissipation
8
2
D002
D001
Figure 4. Output Voltage Ripple
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90
90
80
80
Ambient Temperature (°C)
Ambient Temperature (°C)
Typical Characteristics (continued)
70
60
50
40
30
70
60
50
40
Airflow
100 LFM
Nat conv
30
Airflow
Nat conv
20
20
0
1
2
3
VIN = 12 V
4
5
6
Output Current (A)
7
8
9
10
0
1
VOUT = 0.8 V
VOUT = 1.0 V
IOUT = 1 A
VOUT = 1.0 V
4
5
6
Output Current (A)
7
8
9
10
D005
VOUT = 1.2 V
Figure 6. Safe Operating Area
VIN = 12 V
Figure 7. VIN Start-up Waveforms
VIN = 12 V
3
VIN = 12 V
Figure 5. Safe Operating Area
VIN = 12 V
2
D005
VOUT = 1.0 V
IOUT = 1 A
Figure 8. VIN Shut-down Waveforms
IOUT = 1 A
VIN = 12 V
Figure 9. EN Start-up Waveforms
VOUT = 1.0 V
IOUT = 1 A
Figure 10. EN Shut-down Waveforms
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7 Detailed Description
7.1 Overview
The TPSM84A21 is a 14-V, 10-A, synchronous series capacitor step-down (buck) power module. The
TPSM84A21 combines a 10-A DC/DC converter with power MOSFETs, shielded inductors, series capacitor,
input and output capacitors, and passives into a low profile, overmolded package. The integrated input and
output capacitors allows standard applications to operate with no additional input or output capacitors and only a
single resistor to set the output voltage.
The integrated components allow for high-efficiency, high-density, complete power supply designs with
continuous output currents up to 10 A. The TPSM84A21 reduces the external component count by integrating
both the input and output capacitors. The TPSM84A21 input voltage range is 8 V to 14 V with an output voltage
range of 0.508 V to 1.35 V.
The TPSM84A21 is a two-phase power supply with each phase switching at a fixed 2 MHz frequency, resulting
in the internal oscillator frequency of 4 MHz. An external synchronization clock can also be provided via the
SYNC pin.
The TPSM84A21 starts up safely into loads with pre-biased outputs (non-zero volts at startup). The device
implements an internal input voltage under voltage lockout (UVLO) feature which can be adjusted higher by
adding an external resistor divider on the EN/UVLO pin. Electrical ON/OFF control is provided using the enable
(EN) feature. The TPSM84A21 is disabled by pulling the EN pin low. When the device is disabled, the supply
current is typically less than 50 μA.
The TPSM84A21 has a power good comparator (PGOOD) which monitors the output voltage through the VS+
pin. The PGOOD pin is an open-drain MOSFET which is held low until the output voltage is within ±5% of the set
voltage. The PGOOD pin is held low during startup or when a fault occurs.
7.2 Functional Block Diagram
ILIM
VG
TPSM84A21
VIN
UVLO
REG
Protection
and
Supervisory
Circuits
EN/UVLO
PGOOD
VIN
Oscillator
SYNC
Power
Stage
and
Control
Logic
VOUT
4 MHz
10 O
VOUT
VS+
1 kO
VADJ
Error
Amp
Soft
Start
VREF
AGND
PGND
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7.3 Feature Description
7.3.1 Adjusting the Output Voltage (VADJ)
The VADJ pin programs the output voltage of the TPSM84A21. The output voltage adjustment range is from
0.508 V to 1.35 V. The adjustment method requires the addition of RSET connected between VADJ and AGND. If
an RSET resistor is not populated, the module will default to 0.508 V. The VS+ pin (pin 14) must be connected to
VOUT. TI recommends to make the VS+ connection at the load for the best load regulation performance. The
RSET resistor must be connected directly between the VADJ pin (pin 15) and AGND (pin 16).
Equation 1 can be used to calculate the ideal RSET resistor value for a given output voltage, VOUT. Use
Equation 2 to calculate the actual VOUT for a given RSET resistor. Table 1 lists the ideal RSET resistor values for a
number of common voltages. Table 1 also lists the closest E96 standard resistor values to the ideal RSET values
along with the actual output voltage and the set-point error when using the E96 resistor value. For the most
accurate output voltage set-point it is best to use the ideal resistor value. The ideal resistor value may not be a
standard value and may require two standard value resistors in series or parallel to obtain the desired output
voltage.
1
(k )
VOUT
±1
0.508
1
VOUT = 0.508 *
+1
RSET (k )
RSET =
(
(1)
) (V)
(2)
Table 1. RSET Resistor Values
Closest E96 Resistor Value
VOUT (V)
Ideal RSET (kΩ)
RSET (kΩ)
Actual VOUT (V)
%
0.508
Open
Open
0.508
–
0.55
12.095
12.1
0.549
–0.003
0.60
5.522
5.49
0.601
0.088
0.65
3.578
3.57
0.65
0.046
0.70
2.646
2.67
0.698
–0.248
0.75
2.099
2.10
0.749
–0.013
0.80
1.739
1.74
0.799
–0.006
0.85
1.485
1.50
0.847
–0.392
0.9
1.296
1.30
0.899
–0.137
0.95
1.149
1.15
0.949
–0.027
1.00
1.033
1.02
1.006
0.603
1.05
0.937
0.931
1.053
0.348
1.10
0.858
0.866
1.095
–0.490
1.15
0.791
0.787
1.153
0.303
1.20
0.734
0.732
1.202
0.166
1.25
0.685
0.681
1.254
0.317
1.30
0.641
0.649
1.291
–0.712
1.35
0.603
0.604
1.349
–0.070
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7.3.2 Input and Output Capacitance
The TPSM84A21 requires no external input or output capacitance to operate. Internal to the TPSM84A21 there is
66.1 µF (nominal) of ceramic input capacitance. Additionally, internal to the TPSM84A21 there is 185 µF
(nominal) of ceramic output capacitance.
Applications requiring additional ripple voltage reduction should add ceramic input and output capacitors directly
at the VIN and VOUT pins of the device. Applications requiring improved transient response can also benefit by
adding additonal ceramic or low-ESR bulk output capacitance. See the Capacitance section of the Electrical
Characteristics table for more information when adding external input and output capacitors.
7.3.3 Transient Response
The exceptional transient response of the TPSM84A21 allows many applications to operate with little or no
additional output capacitance. Figure 11 through Figure 14 show typical transient waveforms for the
TPSM84A21.
7.3.3.1 Transient Response Waveforms
VIN = 12 V
VOUT = 0.8 V
COUT = 0 µF
Load Step = 5 A
Slew Rate = 1 A/µs
VIN = 12 V
Figure 11. Transient Response
VIN = 12 V
VOUT = 1.0 V
COUT = 0 µF
Load Step = 5 A
Slew Rate = 1 A/µs
Load Step = 5 A
Slew Rate = 5 A/µs
Figure 12. Transient Response
VIN = 12 V
Figure 13. Transient Response
12
VOUT = 0.8 V
COUT = 300 µF
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COUT = 100 µF
Load Step = 5 A
Slew Rate = 5 A/µs
Figure 14. Transient Response
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7.3.4 Oscillator Frequency
The oscillator frequency of this converter is set at 4 MHz. The per phase switching frequency of the converter is
half the oscillator frequency, or 2 MHz per phase. The oscillator frequency is fixed internally.
During load transients, the internal control loop will momentarily change the switching frequency in order to meet
the output voltage recovery.
7.3.5 External Clock Syncronization
An external clock can be connected to the SYNC pin. The external clock signal overrides the internal oscillator
and is used as the system clock. This feature enables the user to synchronize the switching events to a master
clock on their board. The internal phase locked loop (PLL) has been implemented to allow synchronization at
frequencies between ±10% of the nominal oscillator frequency. This allows the user to easily switch between the
internal oscillator mode and the external clock mode while converting power. Before the external clock is present
or after it is removed, the device with default to the internal oscillator setting.
To implement the synchronization feature, connect a square wave clock signal to the SYNC pin with a duty cycle
between 20% and 80%. The clock signal amplitude must transition lower than 0.8 V and higher than 2 V. The
start of the switching cycle is synchronized to the rising edge of the SYNC pin. The device can be configured for
operation in applications where both an internal oscillator mode and an external synchronization clock mode are
needed. Before the external clock is present, the switching frequency of the device is set by the internal
oscillator. When the external clock is present, the SYNC mode overrides the internal oscillator. The first time the
SYNC pin is pulled above the SYNC high threshold (2 V), the device switches from the internal oscillator mode to
the SYNC mode and the PLL starts to lock onto the frequency of the external clock. When the external SYNC
clock is removed, the converter will transition back to the internal oscillator after 4 internal clock cycles.
7.3.6 Soft Start
The TPSM84A21 has a pre-programmed soft start time of 4.1 ms (typ). The soft start time is the time it takes for
the output voltage to rise from zero volts to the voltage set by the RSET resistor. Soft start is an important feature
that limits inrush current and reduces the load on the input supply to this device. During soft start, the internal
reference voltage is slowly ramped up to the internal reference voltage. This slowly increases the commanded
output voltage of the converter and reduces the initial surge in current. During soft start PGOOD remains low, the
PLL is not active, and output UVP/OVP faults are disabled.
7.3.7 Power Good (PGOOD)
The Power Good (PGOOD) pin is an open drain output. After startup, when the VADJ pin is typically between
95% and 105% of the internal voltage reference, the PGOOD pin pull-down is released and the pin floats. The
recommended pull-up resistor value is between 10 kΩ and 100 kΩ to a voltage source of 5.5 V or less. For
convenience, VG can be used as the pull-up voltage. The PGOOD is in a defined state once the VIN input
voltage is greater than approximately 1.2 V, but with reduced current sinking capability. The PGOOD achieves
full current sinking capability once the VIN input voltage is above the input UVLO. The PGOOD pin is pulled low
when the VADJ pin voltage is typically lower than 95% or greater than 105% of the nominal internal reference
voltage. The PGOOD pin is also pulled low if a fault is detected, the EN pin is pulled low, or the converter is
performing its soft-start power up sequence.
7.3.8 Gate Driver (VG)
A linear regulator internal to the TPSM84A21 generates a 4.8 V internal supply rail on the VG pin. The input of
the linear regulator comes from the VIN pin. The VG supply rail is used to power the internal gate drivers and is
the input to another regulator that generates the internal supply rails used by the controller. To improve converter
efficiency, an external 5 V supply is recommended to be connected to the VG pin, thereby overriding the internal
4.8 V regulator. This external supply must be between 5.0 V and 5.5 V and must be present before applying
input voltage to the VIN pin. If not supplying an external voltage to this pin, leave this pin open.
7.3.9 Startup into Pre-biased Outputs
The TPSM84A21 prevents the low-side MOSFETs from discharging a pre-biased output. During pre-biased
startup, the low-side MOSFETs do not turn on until after the high-side MOSFETs have started switching. The
high-side MOSFETs do not start switching until the internal soft-start reference voltage exceeds the voltage at
the VADJ pin.
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7.3.10 Thermal Shutdown
The internal thermal shutdown fault is triggered if the junction temperature exceeds 135°C (typ). This interrupts
regulation by making the output high impedance. The device reinitiates the power up sequence when the junction
temperature drops below 115°C (typ).
7.3.11 Overcurrent Protection
For protection against load faults, the TPSM84A21 incorporates output overcurrent protection. Applying a load
that exceeds the module's overcurrent threshold causes the output to shut down and PGOOD is pulled low.
Following shut down, the module attempts to restart after a 32.8-ms hiccup interval counter has expired. This
provides a hiccup response to an overcurrent condition. During this period, the average current flowing into the
fault is significantly reduced which reduces power dissipation. Once the fault is removed, the module
automatically recovers and returns to normal operation.
The TPSM84A21 overcurrent trip point is 15 A (typ) when the ILIM pin is left open. This provides enough margin
for brief overshoots in inductor currents during a load transient while at the same time protecting against short
circuits or other potentially catastrophic faults on the output. The overcurrent trip point can be reduced to
11.25 A (typ) by placing a 47 kΩ between the ILIM pin and PGND. Programming resistors with up to ±5%
variation can be used. The current limit selection is latched in at power up and cannot be changed without
cycling input power or the EN pin voltage.
7.3.12 Output Undervoltage/Overvoltage Protection
The device incorporates an output undervoltage/overvoltage protection (UVP/OVP) circuit to prevent damage to
the load. This fault can be triggered during large, fast load transients if insufficient output capacitance is used.
The UVP/OVP feature compares the VADJ pin voltage to internal thresholds. If the VADJ pin voltage is lower
than 90% or greater than 110% of the nominal internal reference voltage, the module is turned off, a fault is
triggered, and the PGOOD pin is pulled low. When the fault hiccup interval is complete, the module will attempt
to restart.
7.3.13 Enable (EN)
The EN pin provides electrical on and off control of the TPSM84A21. Once the EN pin voltage exceeds the
threshold voltage, the device starts operation. If the EN pin voltage is pulled below the threshold voltage, the
module stops switching and enters a low power state. There is no voltage hysteresis in the EN threshold. The
rising and falling voltage thresholds occur at the same level. The EN pin has an internal pull-up current source,
allowing the user to float the EN pin for enabling the device.
If an application requires controlling the EN pin, use an open drain/collector device or a suitable logic gate to
interface with the pin. Figure 15 shows controlling the EN/UVLO pin using a MOSFET, Q1. Turning Q1 on,
disables the device. Using a voltage superviser to control the EN pin allows control of the turn-on and turn-off of
the device as opposed to relying on the ramp up or down of the input voltage source.
VIN
EN/
UVLO
Q1
EN
Control
PGND
Figure 15. Enable Control
14
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7.3.14
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Undervoltage Lockout (UVLO)
The TPSM84A21 implements internal UVLO circuitry on the VIN pin. The device is disabled when the VIN pin
voltage is below the internal VIN UVLO threshold. The internal VIN UVLO rising threshold is 7.65 V(max) with a
typical hysteresis of 250 mV.
If an application requires a higher UVLO threshold, the UVLO pin can be configured as shown in Figure 16. The
value of RUVLO1 and RUVLO2 can be calculated using Equation 3 and Equation 4 or selected from Table 2. It is
recommended to set the UVLO hysteresis of approximately 500mV in order to avoid repeated chatter during start
up or shut down. Table 2 shows recommended RUVLO1 and RUVLO2 values for various VIN UVLO rising
thresholds, with 500 mV of hysteresis.
VIN(RISE) ± VIN(FALL)
RUVLO1 =
3 µA
(3)
RUVLO1 x 1.23
RUVLO2 =
VIN(FALL) ± 1.23 + (RUVLO1 x 4 µA)
(4)
VIN
RUVLO1
EN/
UVLO
RUVLO2
PGND
Figure 16. Adjustable UVLO
Table 2. Standard Resistor Values For Adjusting VIN UVLO
VIN UVLO RISING THRESHOLD (V)
8.0
8.5
9.0
9.5
VIN UVLO FALLING THRESHOLD (V)
7.5
8.0
8.5
9.0
10.0
9.5
RUVLO1 (kΩ)
169
169
169
169
169
RUVLO2 (kΩ)
29.4
27.4
25.5
24.3
22.6
7.4 Device Functional Modes
7.4.1 Active Mode
The TPSM84A21 is in Active Mode when VIN is above the UVLO threshold and the EN/UVLO pin voltage is
above the EN high threshold. The simplest way to enable the TPSM84A21 is to leave the EN/UVLO pin floating.
This allows self start-up of the TPSM84A21 when the input voltage is above the UVLO threshold.
7.4.2 Light Load Operation
The TPSM84A21 operates in forced continuous conduction mode (FCCM) under light load conditions. When
operating in FCCM, the switching frequency remains constant and the high side and low side MOSFETs are
turned on and off in a complementary fashion allowing negative inductor current for part of the switching cycle.
7.4.3 Shutdown Mode
The EN/UVLO pin provides electrical ON and OFF control for the TPSM84A21. When the EN/UVLO pin voltage
is below the EN threshold, the device is in shutdown mode. In shutdown mode the stand-by current is typically
less than 50 μA. The TPSM84A21 also employs under voltage lock out protection. If VIN is below the UVLO
level, the output of the regulator turns off.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPSM84A21 is a synchronous series capacitor step down DC-DC power module. It is used to convert a
higher DC voltage to a lower DC voltage with a maximum output current of 10 A. The following design
procedure can be used to select components for the TPSM84A21. Alternately, the WEBENCH® software
may be used to generate complete designs. When generating a design, the WEBENCH software utilizes an
iterative design procedure and accesses comprehensive databases of components. Please visit
www.ti.com/webench for more details.
8.2 Typical Application
The TPSM84A21 includes both input and output capacitors internal to the device, therefore it only requires a
voltage setting resistor and possibly a pull-up resistor on the PGOOD pin in most applications. Figure 17 shows a
typical TPSM84A21 schematic with only the minimum required components.
TPSM84A21
12 V
5V
VIN
VS+
VG
VOUT
PGOOD
VADJ
1.0 V
10 kO
AGND
PGND
1.02 kO
Copyright © 2016, Texas Instruments Incorporated
Figure 17. Typical Application Schematic
8.2.1 Design Requirements
For this design example, use the parameters listed in Table 3 and follow the design procedures below.
Table 3. Design Parameters
DESIGN PARAMETER
VALUE
Input Voltage VIN
12 V typical
Output Voltage VOUT
1.0 V
Output Current Rating
10 A
Key care-abouts
Tight transient response, small footprint, high efficiency, PGOOD signal
Transient Response Requirements
±2% voltage deviation, 5 A load step, 5 A/µs slew rate
16
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8.2.2 Detailed Design Procedure
8.2.2.1 Setting the Output Voltage
The output voltage of the TPSM84A21 is externally adjustable using a single resistor (RSET). Select the value of
RSET from or calculate using Equation 5:
1
Rset =
(kW )
Vout
-1
0.508
(5)
To set the output voltage to 1.0 V, the calculated value for RSET is 1.03 kΩ. The closest E96 value is 1.02 kΩ.
8.2.2.2 Input and Output Capacitance
The TPS84A21 requires no external input or output capacitance to operate. Input and output capacitors can be
added to improve ripple or transient response. In this design example, in order to meet the ±2% voltage deviation
for a 5-A, 5-A/µs load step, 100 µF of output capacitance is required.
8.2.2.3 Power Good (PGOOD)
Applications requiring voltage rail sequencing can benefit from the PGOOD signal present with the TPSM84A21.
The PGOOD pin is an open drain output. When the output voltage is typically between 95% and 105% of the set
point, the PGOOD pin pull-down is released and the pin floats, requiring an external pull-up resistor for a high
signal. A 10-kΩ pull-up resistor is placed between the PGOOD pin and an external 5V rail.
8.2.2.4 External VG Voltage
The VG supply rail is used to power the internal gate drivers and other internal supply rails used by the
controller. For best efficiency, supply an external 5 V to the VG pin, thereby overriding the internal 4.8 V
regulator. Expect a 2-3% efficiency improvement by driving the VG pin with an external 5V.
8.2.3 Application Curves
VIN = 12 V
VOUT = 1.0 V
VIN = 12 V
Figure 18. Start-up Waveforms
VOUT = 1.0 V
COUT = 100 µF
Load Step = 5 A
Slew Rate = 1 A/µs
Figure 19. Application Transient Response
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9 Power Supply Recommendations
The TPSM84A21 is designed to operate from an input voltage supply range between 8 V and 14 V. This input
supply should be well regulated and able to withstand maximum input current and maintain a stable voltage. The
resistance of the input supply rail should be low enough that an input current transient does not cause a high
enough drop at the supply voltage that can cause a false UVLO fault triggering and system reset.
If the input supply is located more than a few inches from the TPSM84A21, additional bulk capacitance may be
required at the input pins. A typical recommended amount of bulk input capacitance is 47 μF - 100 μF.
18
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10 Layout
10.1 Layout Guidelines
To achieve optimal electrical and thermal performance, an optimized PCB layout is required. Figure 20 and
Figure 22 show typical, top-side PCB layouts. Some considerations for an optimized layout are:
• Use large copper areas for power planes (VIN, VOUT, and PGND) to minimize conduction loss and thermal
stress.
• When adding input and output ceramic capacitors, place them close to the device pins to minimize high
frequency noise.
• Locate any additional output capacitors between the ceramic capacitors and the load.
• Keep AGND and PGND separate from one another. The connection is made internal to the device.
• Place RSET as close as possible to the VADJ pin.
• Use multiple vias to connect the power planes to internal layers.
10.2 Layout Examples
The layout shown in Figure 20 shows the minimum solution size with only a single voltage setting resistor (R1)
as the only additional required component. Figure 21 shows a typical internal PCB layer with a trace connecting
the VS+ pin to VOUT near the load.
Figure 20. Minimum Component Layout
Figure 21. VS+ Trace on Internal Layer
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Layout Examples (continued)
Figure 22 shows a layout with the placement of additional ceramic input capacitors (C1, C3) and ceramic output
capacitors (C2, C4) for designs that require additional ripple reduction or improved transient response. Figure 23
shows a typical internal PCB layer with a trace connecting the VS+ pin to VOUT near the load
Figure 22. Layout with Optional CIN and COUT
Figure 23. VS+ Trace on Internal Layer
20
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10.3 EMI
The TPSM84A21 is compliant with EN55022 Class B radiated emissions. Figure 24 to Figure 27 show typical
examples of radiated emissions plots for the TPSM84A21. Graphs included show plots of the antenna in the
horizontal and vertical positions.
Figure 24. Radiated Emissions 12-V Input, 0.8-V Output,
10-A Load, Horizontal Antenna
Figure 25. Radiated Emissions 12-V Input, 0.8-V Output,
10-A Load, Vertical Antenna
Figure 26. Radiated Emissions 12-V Input, 1.2-V Output,
10-A Load, Horizontal Antenna
Figure 27. Radiated Emissions 12-V Input, 1.2-V Output,
10-A Load, Vertical Antenna
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• TPSM84A22, 8-V to 14-V Input, 1.2-V to 2.05-V Output, 10-A SWIFT™ Power Module, SLVSDF8
• TPS54A20 8-V to 14-V Input, 10-A, up to 10-MHz SWIFT™ Step Down Converter, SLVSCQ8
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
SWIFT, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
22
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12.1 Tape and Reel Information
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
B0 W
Reel
Diameter
Cavity
A0
B0
K0
W
P1
A0
Dimension designed to accommodate the component width
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1
Q2
Q1
Q2
Q3
Q4
Q3
Q4
User Direction of Feed
Pocket Quadrants
Device
Package
Type
Package
Drawing
Pins
SPQ
Reel
Diameter
(mm)
Reel
Width W1
(mm)
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
TPSM84A21MOJR
QFM
MOJ
20
500
330.0
24.4
9.35
15.35
3.1
16.0
24.0
Q1
TPSM84A21MOJT
QFM
MOJ
20
250
330.0
24.4
9.35
15.35
3.1
16.0
24.0
Q1
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TAPE AND REEL BOX DIMENSIONS
Width (mm)
L
W
24
H
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPSM84A21MOJR
QFM
MOJ
20
500
383.0
353.0
58.0
TPSM84A21MOJT
QFM
MOJ
20
250
383.0
353.0
58.0
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PACKAGE OPTION ADDENDUM
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19-Dec-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPSM84A21MOJR
ACTIVE
QFM
MOJ
20
500
RoHS (In
Work) & Green
(In Work)
NIAU
Level-3-260C-168 HR
-40 to 85
TPSM84A21
TPSM84A21MOJT
ACTIVE
QFM
MOJ
20
250
RoHS (In
Work) & Green
(In Work)
NIAU
Level-3-260C-168 HR
-40 to 85
TPSM84A21
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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