TRF372017IRGZR

Sample & Buy Product Folder Support & Community Tools & Software Technical Documents TRF372017 SLWS224E – AUGUST 2010 – REVISED JANUARY 2016 TRF372017 Integrated IQ Modulator PLL/VCO 1 Features 3 Description • • • TRF372017 is a high-performance, direct upconversion device, integrating a high-linearity, lownoise IQ modulator and an integer-fractional PLL/VCO. The VCO uses integrated frequency dividers to achieve a wide, continuous tuning range of 300 MHz to 4800 MHz. The LO is available as an output with independent frequency dividers. The device also accepts input from an external LO or VCO. The modulator baseband inputs can be biased either internally or externally. Internal DC offset adjustment enables carrier cancellation. The device is controlled through a 3-wire serial programming interface (SPI). A control pin invokes power-save mode to reduce power consumption while keeping the VCO locked for fast start-up. 1 • • • • • • • Fully Integrated PLL/VCO and IQ Modulator LO Frequency from 300 MHz to 4.8 GHz 76-dBc Single-Carrier WCDMA ACPR at –8-dBm Channel Power OIP3 of 26 dBm P1dB of 11.5 dBm Integer/Fractional PLL Phase Noise –132 dBc/Hz (at 1 MHz, fVCO of 2.3 GHz) Low Noise Floor: –160 dBm/Hz Input Reference Frequency Range: Up to 160 MHz VCO Frequency Divided by 1-2-4-8 Output Device Information(1) 2 Applications • • • • PART NUMBER TRF372017 Wireless Infrastructure – CDMA: IS95, UMTS, CDMA2000, TD-SCDMA – TDMA: GSM, IS-136, EDGE/UWC-136 – LTE Wireless Local Loop Point-to-Point Wireless Access Wireless MAN Wideband Transceivers PACKAGE VQFN (48) BODY SIZE (NOM) 7.00 mm × 7.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. spacing LO_OUT BBQ From Div1/2/4/ 8 SPI Vcm D/A VTUNE EXT_VCO Block Diagram CP_OUT Charge Pump PolyPhase PFD From SPI PS Pwr save Vcm D/A From SPI SD control N- Divider REFIN VCCs GNDs S From SPI From SPI RF Divider R Div Lock det LD Prescaler div p/p+1 Serial Interface LE DATA CLK RFOUT Div2/ 4/8 BBI 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TRF372017 SLWS224E – AUGUST 2010 – REVISED JANUARY 2016 www.ti.com Table of Contents 1 2 3 4 5 6 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 6.1 6.2 6.3 6.4 6.5 6.6 6.7 7 1 1 1 2 3 5 Absolute Maximum Ratings ...................................... 5 Recommended Operating Conditions....................... 5 Thermal Information .................................................. 5 Electrical Characteristics........................................... 6 Timing Requirements - SPI: Writing Phase .............. 8 Timing Requirements - SPI: Read-Back Phase........ 8 Typical Characteristics ............................................ 10 Detailed Description ............................................ 23 7.1 Overview ................................................................. 23 7.2 Functional Block Diagram ....................................... 23 7.3 Feature Description................................................. 23 7.4 Device Functional Modes........................................ 33 7.5 Register Maps ......................................................... 34 8 Application and Implementation ........................ 46 8.1 Application Information............................................ 46 8.2 Typical Application ................................................. 46 9 Power Supply Recommendations...................... 50 10 Layout................................................................... 51 10.1 Layout Guidelines ................................................. 51 10.2 Layout Example .................................................... 51 11 Device and Documentation Support ................. 52 11.1 11.2 11.3 11.4 11.5 Device Support...................................................... Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 52 52 52 52 52 12 Mechanical, Packaging, and Orderable Information ........................................................... 52 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision D (September 2013) to Revision E • Added Feature Description section, Device Functional Modes section, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .................................................................................................. 1 Changes from Revision C (May 2012) to Revision D • Page Changed text string from Reg 1, B[30..28] = [000] to Reg 0, B[30..28] = [000] in the Description column associated with RB_REG, RB_REG, and RB_REG ............................................................................................................ 44 Changes from Revision B (March 2012) to Revision C • Page Page Added graph titles to Figure 56 and 57 that were missing in Revision B............................................................................. 17 Changes from Revision A (August 2010) to Revision B Page • Deleted Comments column from Table 1............................................................................................................................... 8 • Changed Figures 12 through Figure 27 ............................................................................................................................... 10 • Changed the text under Integer and Fractional Mode Selection through Practical Limit on Maximum PFD Frequency. .... 23 • Changed RDIV = 20 to RDIV = 2 in Setup Example for Fractional Mode............................................................................ 26 • Changed Recommended Value of EN_LD_ISOURCE from 1 to 0 in Table 1..................................................................... 27 • Changed column heading from Default Value to Reset Value in register tables 1, 2, 3, 4, 5, 6, and 7............................... 34 • Added recommended programming [xx] to various Description statements in register tables 2, 5, 6, and 7. ..................... 37 • Changed Register 4, Bit21/Bit22 Description statement from Off to Normal. ...................................................................... 39 • Changed Column heading from Default Value to Reset Value in Readback mode section, Register 0.............................. 43 • Changed Bit5 name from CHIP_ID to CHIP_ID _0 and changed Bit6 name from NU to CHIP_ID_1, Reset Value to 1.... 44 • Changed image in Figure 87. .............................................................................................................................................. 48 • Changed the text in the Application Layout, and added link to Figure 95............................................................................ 51 2 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated TRF372017 www.ti.com SLWS224E – AUGUST 2010 – REVISED JANUARY 2016 5 Pin Configuration and Functions GND VCC_PLL CP_OUT GND VTUNE GND 41 40 39 38 37 43 42 GND REFIN 44 DATA LE 45 CLK 47 46 SCAN_EN 48 RGZ Package 48-Pin VQFN Top View PS 1 36 EXT_VCO RDBK 2 35 VCC_VCO1 VCC_DIG 3 34 LO_OUT_P GND_DIG 4 33 LO_OUT_N GND 24 GND 23 25 GND 12 22 GND 21 GND GND 26 VCC_MIX 11 20 BBI_P GND 19 BBI_N 27 GND 28 10 VCC_D2S 9 BBQ_P 18 BBQ_N 17 GND GND 29 RFOUT 8 16 VCC_LO2 GND GND 30 15 7 GND GND VCC_LO1 14 VCC_VCO2 31 13 32 6 GND 5 RSVD LD GND Pin Functions PIN I/O DESCRIPTION NAME NO. BBI_P 27 I Base-band in-phase input: positive terminal. Internal 5 kΩ to VCM generator. If VCM is internally generated (PWD_BB_VCM = 0), external AC coupling caps and 100-Ω differential termination to BBI_N is required. BBI_N 28 I Base-band in-phase input: negative terminal. Internal 5 kΩ to VCM generator. If VCM is internally generated (PWD_BB_VCM = 0), external AC coupling caps and 100-Ω differential termination to BBI_P is required. BBQ_N 9 I Base-band in-quadrature input: negative terminal. Internal 5 kΩ to VCM generator. If VCM is internally generated (PWD_BB_VCM = 0), external AC coupling caps and 100-Ω differential termination to BBQ_P is required. BBQ_P 10 I Base-band in-quadrature input: positive terminal. Internal 5 kΩ to VCM generator. If VCM is internally generated (PWD_BB_VCM = 0), external AC coupling caps and 100-Ω differential termination to BBQ_N is required. CLK 47 I SPI clock input. Digital input. High impedance. CP_OUT 40 O Charge pump output DATA 46 I SPI data input. Digital input. High impedance. External local oscillator input. High impedance. Normally AC-coupled. EXT_VCO 36 I 6, 8, 11, 12, 13, 15, 16, 17, 19, 22, 23, 24, 25, 26, 29, 31, 37, 39, 42, 44 — Ground GND_DIG 4 — Digital ground LD 5 O PLL lock detect output, as configured by MUX_CTRL. Digital output pins can source or sink up to 8 mA of current. LE 45 I SPI latch enable. Digital input. High impedance. GND Copyright © 2010–2016, Texas Instruments Incorporated Submit Documentation Feedback 3 TRF372017 SLWS224E – AUGUST 2010 – REVISED JANUARY 2016 www.ti.com Pin Functions (continued) PIN NAME NO. I/O DESCRIPTION LO_OUT_N 33 O Local oscillator output: negative terminal. Open collector output. A pullup is required. Normally AC-coupled. LO_OUT_P 34 O Local oscillator output: positive terminal. Open collector output. A pullup is required. Normally AC-coupled. PS 1 I Power saving mode enable (Low = normal mode; High = power saving mode) RDBK 2 O SPI internal registers readback output. Digital output pins can source or sink up to 8 mA of current. REFIN 43 I Reference clock input. High impedance. Normally AC-coupled. RFOUT 18 O RF output. Internally matched to 50-Ω output. Normally AC-coupled. RSVD 14 — Reserved. Normally open. SCAN_EN 48 I VCC_D2S 20 — 5-V modulator output buffer power supply VCC_DIG 3 — 3.3-V digital power supply VCC_LO1 7 — 3.3-V Tx path local oscillator chain power supply VCC_LO2 30 — 3.3-V output local oscillator chain power supply VCC_MIX 21 — 5-V modulator power supply VCC_PLL 41 — 3.3-V PLL power supply VCC_VCO1 35 — 3.3-V VCO power supply VCC_VCO2 32 — 3.3-V to 5-V VCO power supply VTUNE 38 I 4 Submit Documentation Feedback Internal testing mode digital input. Connect to ground in normal operation VCO control voltage input Copyright © 2010–2016, Texas Instruments Incorporated TRF372017 www.ti.com SLWS224E – AUGUST 2010 – REVISED JANUARY 2016 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) (2) MIN MAX UNIT Supply voltage (3) –0.3 5.5 V Digital I/O voltage –0.3 VCC + 0.5 V TJ Operating virtual junction temperature –40 150 °C TA Operating ambient temperature –40 85 °C Tstg Storage temperature –40 150 °C (1) (2) (3) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. ESD rating not valid for RF sensitive pins. All voltage values are with respect to network ground terminal. 6.2 Recommended Operating Conditions VCC5V 5-V power supply voltage VCC3V 3.3-V power supply voltage VCC_VCO2 3.3-V to 5-V power supply voltage MIN NOM MAX 4.5 5 5.5 UNIT V 3 3.3 3.6 V 3 3.3 5.5 V TA Operating ambient temperature –40 85 °C TJ Operating virtual junction temperature –40 125 °C 6.3 Thermal Information TRF372017 THERMAL METRIC (1) RGZ (VQFN) UNIT 48 PINS RθJA Junction-to-ambient thermal resistance 30.0 °C/W RθJC(top) Junction-to-case (top) thermal resistance 10.0 °C/W RθJB Junction-to-board thermal resistance 8.0 °C/W ψJT Junction-to-top characterization parameter 0.5 °C/W ψJB Junction-to-board characterization parameter 7.0 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 0.5 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Copyright © 2010–2016, Texas Instruments Incorporated Submit Documentation Feedback 5 TRF372017 SLWS224E – AUGUST 2010 – REVISED JANUARY 2016 www.ti.com 6.4 Electrical Characteristics VCC5V = 5 V, VCC3V = 3.3 V, VCC_VCO2 = 3.3 V, TA = 25°C, internal LO, internal VCM (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 3.3-V power supply, LO on 200 250 mA 5-V power supply, LO on 117 148 mA 3 5 mA 121 130 mA VCC_D2S 43 60 mA VCC_MIX 74 90 mA VCC_VCO1 20 28 VCC_VCO2 17 20 LO_OUT_N and LO_OUT_P 17 28 mA DC PARAMETERS Total supply current, LO on (1) ICC VCC_DIG, LO on VCC_LO1 and VCC_LO2 Supply current, LO on (1) VCC_PLL Total supply current, LO off (1) Total supply current, PS on (1) mA 24 40 mA 3.3-V power supply, LO off 165 204 mA 5-V power supply, LO off 117 149 mA 3.3-V power supply, PS on 65 94 mA 5-V power supply, PS on 51 73 mA BASEBAND INPUTS Vcm I and Q input DC common voltage (2) BW 1-dB input frequency bandwidth ZI Input Impedance Externally generated 1.7 Set internally 1.6 1.7 V 1.85 1000 V MHz Resistance 5 kΩ Parallel Capacitance 3 pF Number of bits Programmed through SPI 8 Programmable DC offset setting |BBI_P - BBI_N| or |BBQ_P - BBQ_N|, 100-Ω differential load BASEBAND INPUT DC OFFSET CONTROL D/A (3) 0.02 V DIGITAL INTERFACE VIH High-level input voltage 2 VIL Low-level input voltage 0 VOH High-level output voltage Referenced to VCC_DIG VOL Low-level output voltage Referenced to VCC_DIG 3.3 V 0.8 0.8 × Vcc V V 0.2 × Vcc V REFERENCE OSCILLATOR PARAMETERS Fref Reference frequency Reference input sensitivity Reference input impedance 0.2 Parallel capacitance 160 MHz 3.3 Vp-p 5 Parallel resistance pF Ω 3900 PFD CHARGE PUMP PFD frequency (4) ICP Charge pump current 100 SPI programmable 1.94 MHz mA IQ MODULATOR OUTPUT, FLO = 750 MHz Output RMS voltage over se input I (or Q) RMS voltage G Voltage gain P1dB Output compression point 11 dBm IP3 Output IP3 2 input tones at 4.5 and 5.5 MHz 26 dBm IP2 Output IP2 2 input tones at 4.5 and 5.5 MHz 56.5 dBm Carrier feedthrough Unadjusted –43.5 dBm Sideband suppression Unadjusted –46 dBc 10 dB Output return loss (1) (2) (3) (4) 6 –4 –3.2 –2.4 dB Maximum current is worst-case overvoltage, temperature, and expected process variations. The TRF372017 can generate the input common voltage internally or can accept an external common mode voltage. The two modes are selectable through SPI. When the internal input common mode voltage is selected, it is possible to apply some DC offset with the integrated D/A. See Application Information for discussion on selection of PFD frequency. Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated TRF372017 www.ti.com SLWS224E – AUGUST 2010 – REVISED JANUARY 2016 Electrical Characteristics (continued) VCC5V = 5 V, VCC3V = 3.3 V, VCC_VCO2 = 3.3 V, TA = 25°C, internal LO, internal VCM (unless otherwise noted) PARAMETER Output noise TEST CONDITIONS MIN DC only to BB inputs; 13-MHz offset from LO; Pout = –10 dBm TYP MAX –162 UNIT dBm/Hz IQ MODULATOR OUTPUT, FLO = 900 MHz Output RMS voltage over se input I (or Q) RMS voltage G Voltage gain –4 P1dB Output compression point 11 dBm IP3 Output IP3 2 input tones at 4.5 and 5.5 MHz 26.5 dBm IP2 Output IP2 2 input tones at 4.5 and 5.5 MHz 56.5 dBm Carrier feedthrough Unadjusted –43 dBm Sideband suppression Unadjusted –45 dBc 10 dB Output return loss Output noise DC only to BB inputs; 13-MHz offset from LO; Pout = –10 dBm –3.4 –2.4 –160 dB dBm/Hz IQ MODULATOR OUTPUT, FLO = 2150 MHz Output RMS voltage over se input I (or Q) RMS voltage G Voltage gain –4.2 P1dB Output compression point 11.5 dBm IP3 Output IP3 2 input tones at 4.5 and 5.5 MHz 25 dBm IP2 Output IP2 2 input tones at 4.5 and 5.5 MHz 56 dBm Carrier feedthrough Unadjusted –40 dBm Sideband suppression Unadjusted –32 dBc 10 dB Output return loss Output noise ACPR Adjacent-channel power ratio DC only to BB inputs; 13-MHz offset from LO; Pout = –10 dBm –3.1 –2 –158 1 WCDMA signal; Pout = –8 dBm dB dBm/Hz –75 2 WCDMA signals; Pout = –11 dBm per carrier dBc 71 IQ MODULATOR OUTPUT, FLO = 2700 MHz Output RMS voltage over se input I (or Q) RMS voltage G Voltage gain –4.1 P1dB Output compression point 12 dBm IP3 Output IP3 2 input tones at 4.5 and 5.5 MHz 26.5 dBm IP2 Output IP2 2 input tones at 4.5 and 5.5 MHz 50 dBm Carrier feedthrough Unadjusted –43 dBm Sideband suppression Unadjusted –41 dBc 10 dB Output return loss Output noise DC only to BB inputs; 13-MHz offset from LO; Pout = –10 dBm –2.7 –1.3 –153 dB dBm/Hz LOCAL OSCILLATOR FVCO PLO (5) Frequency range VCO range 2400 4800 Divide by 2 1200 2400 Divide by 4 600 1200 Divide by 8 300 MHz 600 Free running VCO 10 kHz –85 dBc/Hz Phase noise, Fout = 2.3 GHz 1 MHz –132 dBc/Hz 10 MHz –150 dBc/Hz 50 MHz –153 dBc/Hz LO output power (5) 100-Ω differential, external load; single-ended –2.5 3 dBm With VCO frequency at 4.6 GHz and LO in divide-by-2 mode at 2.3 GHz Copyright © 2010–2016, Texas Instruments Incorporated Submit Documentation Feedback 7 TRF372017 SLWS224E – AUGUST 2010 – REVISED JANUARY 2016 www.ti.com 6.5 Timing Requirements - SPI: Writing Phase (1) MIN TYP MAX UNIT th Hold time, data to clock 20 ns tSU1 Setup time, data to clock 20 ns T(CH) Clock low duration 20 ns T(CL) Clock high duration 20 ns tSU2 Setup time, clock to enable 20 ns t(CLK) Clock period 50 ns tW Enable time 50 ns tSU3 Setup time, latch to data 70 ns (1) See Figure 1 for timing diagram. 6.6 Timing Requirements - SPI: Read-Back Phase (1) MIN TYP MAX UNIT th Hold time, data to clock 20 ns tSU1 Setup time, data to clock 20 ns T(CH) Clock low duration 20 ns T(CL) Clock High duration 20 ns tSU2 Setup time, clock to enable 20 ns td Delay time, clock to readback data output 10 ns tW Enable time (2) 50 ns t(CLK) Clock period 50 ns (1) (2) See Figure 2 for timing diagram. Equals Clock period tsu1 REGISTER WRITE t(CLK) t(CH) 32nd Write clock pulse 1st Write clock pulse CLOCK DB0 (LSB) Address Bit0 DATA t(CL) th DB1 Address Bit1 DB2 Address Bit2 DB3 Address Bit3 DB29 tsu3 DB30 DB31 (MSB) tsu2 tw End of Write Cycle pulse LATCH ENABLE Figure 1. SPI Write Timing Diagram 8 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated TRF372017 www.ti.com SLWS224E – AUGUST 2010 – REVISED JANUARY 2016 t su1 th t(CLK) T(CL) st REGISTER WRITE CLOCK 1 Write clock pulse T(CH) DB0 (LSB) Address Bit 0 DB1 Address Bit1 DB2 Address Bit 2 DB3 Address Bit 3 DB29 32nd Write clock pulse DB31(MSB) DB30 DATA LATCH ENABLE nd READBACK CLOCK 32 Write clock pulse tsu3 1st Read clock pulse nd rd 32 Read clock pulse 33 Read clock pulse tsu2 “End of Write Cycle” pulse LATCH ENABLE nd 2 Read clock pulse td tw ReadBack Data Bit 0 READBACK DATA Read Back Data Bit1 Read Back Data Bit29 ReadBack Data Bit30 ReadBack Data Bit31 Figure 2. SPI Read-Back Timing Diagram Copyright © 2010–2016, Texas Instruments Incorporated Submit Documentation Feedback 9 TRF372017 SLWS224E – AUGUST 2010 – REVISED JANUARY 2016 www.ti.com 6.7 Typical Characteristics VCM = 1.7 V (internal), VinBB = 300 mVrms single-ended sine wave in quadrature, VCC3V = 3.3 V, VCC5V = 5 V, fBB = 4.5 MHz and 5.5 MHz, internal LO, TA = 25°C; FPFD = 1.6 MHz (unless otherwise noted). -40 -40 F_LO_OUT = 2.6 GHz VCC = 3.3, 5 V F_LO_OUT = 3.35 GHz VCC = 3.3, 5 V -60 Phase Noise (dBc/Hz) Phase Noise (dBc/Hz) -60 -80 T A = 85°C -100 -120 T A = -40°C -80 T A = 85°C -100 -120 T A = -40°C -140 -140 T A = 25°C -160 1k 10k T A = 25°C 100k 1M Frequency (Hz) 10M -160 1k 40M 10k 100k 1M Frequency (Hz) 10M G001 G002 Figure 3. Open-Loop Phase Noise vs Frequency and Temperature Figure 4. Open Loop Phase Noise vs Frequency and Temperature -40 -40 F_LO_OUT = 4.05 GHz VCC = 3.3, 5 V F_LO_OUT = 4.7 GHz VCC = 3.3, 5 V -60 Phase Noise (dBc/Hz) Phase Noise (dBc/Hz) -60 -80 T A = 85°C -100 -120 -80 T A = 85°C -100 -120 T A = -40°C -140 T A = -40°C -140 T A = 25°C T A = 25°C -160 1k 10k 100k 1M Frequency (Hz) 10M -160 1k 40M 10k 100k 1M Frequency (Hz) 10M G003 Figure 6. Open Loop Phase Noise vs Frequency and Temperature -40 -40 F_LO_OUT = 2.6 GHz T A = 25°C F_LO_OUT = 3.35 GHz T A = 25°C -60 Phase Noise (dBc/Hz) Phase Noise (dBc/Hz) -60 -80 VCC = 3.6 V -100 VCC = 3 V -80 VCC = 3.6 V -100 -120 VCC = 3 V -140 -140 VCC = 3.3 V -160 1k 10k 100k 1M Frequency (Hz) VCC = 3.3 V 10M 40M G005 Figure 7. Open Loop Phase Noise vs Frequency and Supply Voltage 10 40M G004 Figure 5. Open Loop Phase Noise vs Frequency and Temperature -120 40M Submit Documentation Feedback -160 1k 10k 100k 1M Frequency (Hz) 10M 40M G006 Figure 8. Open Loop Phase Noise vs Frequency and Supply Voltage Copyright © 2010–2016, Texas Instruments Incorporated TRF372017 www.ti.com SLWS224E – AUGUST 2010 – REVISED JANUARY 2016 Typical Characteristics (continued) VCM = 1.7 V (internal), VinBB = 300 mVrms single-ended sine wave in quadrature, VCC3V = 3.3 V, VCC5V = 5 V, fBB = 4.5 MHz and 5.5 MHz, internal LO, TA = 25°C; FPFD = 1.6 MHz (unless otherwise noted). -40 -40 F_LO_OUT = 4.05 GHz T A = 25°C F_LO_OUT = 4.7 GHz T A = 25°C -60 -60 VCC = 3 V Phase Noise (dBc/Hz) Phase Noise (dBc/Hz) VCC = 3 V -80 -100 VCC = 3.6 V -120 VCC = 3.3 V -140 -80 -100 VCC = 3.6 V VCC = 3.3 V -120 -140 -160 1k 10k 100k 1M Frequency (Hz) 10M -160 1k 40M 10k 100k 1M Frequency (Hz) 10M G007 G008 Figure 9. Open Loop Phase Noise vs Frequency and Supply Voltage Figure 10. Open Loop Phase Noise vs Frequency and Supply Voltage -40 -40 F_LO_OUT = 2.6 GHz VCC = 3.3, 5 V Div 1 Mode -80 TA = 85°C -100 TA = -40°C -120 F_LO_OUT = 1.3 GHz VCC = 3.3, 5 V Div 2 Mode -60 Phase Noise (dBc/Hz) -60 Phase Noise (dBc/Hz) 40M -80 -100 TA = 85°C -120 TA = -40°C -140 -140 TA = 25°C TA = 25°C -160 1k 10k 100k 1M Frequency (Hz) 10M -160 1k 40M 10k 100k 1M Frequency (Hz) 10M Figure 11. Closed Loop Phase Noise vs Frequency and Temperature Figure 12. Closed Loop Phase Noise vs Frequency and Temperature -40 -40 F_LO_OUT = 650 MHz VCC = 3.3, 5 V Div 4 Mode -80 -100 F_LO_OUT = 325 MHz VCC = 3.3, 5 V Div 8 Mode -60 Phase Noise (dBc/Hz) -60 Phase Noise (dBc/Hz) 40M G010 G009 TA = 85°C -120 -80 TA = 25°C -100 -120 TA = 25°C TA = -40°C TA = 85°C -140 TA = -40°C -140 -160 1k 10k 100k 1M Frequency (Hz) 10M 40M G011 Figure 13. Closed Loop Phase Noise vs Frequency and Temperature Copyright © 2010–2016, Texas Instruments Incorporated -160 1k 10k 100k 1M Frequency (Hz) 10M 40M G012 Figure 14. Closed Loop Phase Noise vs Frequency and Temperature Submit Documentation Feedback 11 TRF372017 SLWS224E – AUGUST 2010 – REVISED JANUARY 2016 www.ti.com Typical Characteristics (continued) VCM = 1.7 V (internal), VinBB = 300 mVrms single-ended sine wave in quadrature, VCC3V = 3.3 V, VCC5V = 5 V, fBB = 4.5 MHz and 5.5 MHz, internal LO, TA = 25°C; FPFD = 1.6 MHz (unless otherwise noted). -40 -40 F_LO_OUT = 3.4 GHz VCC = 3.3, 5 V Div 1 Mode -60 Phase Noise (dBc/Hz) Phase Noise (dBc/Hz) -60 -80 TA = 85°C -100 -120 TA = -40°C TA = 85°C -100 -120 -140 TA = 25°C 10k -80 TA = -40°C -140 -160 1k F_LO_OUT = 1.7 GHz VCC = 3.3, 5 V Div 2 Mode 100k 1M Frequency (Hz) TA = 25°C 10M -160 1k 40M 10k 100k 1M Frequency (Hz) 10M G013 G014 Figure 15. Closed Loop Phase Noise vs Frequency and Temperature Figure 16. Closed Loop Phase Noise vs Frequency and Temperature -40 -40 F_LO_OUT = 850 MHz VCC = 3.3, 5 V Div 4 Mode -80 TA = 85°C -100 F_LO_OUT = 425 MHz VCC = 3.3, 5 V Div 8 Mode -60 Phase Noise (dBc/Hz) -60 Phase Noise (dBc/Hz) 40M -120 -80 -100 TA = 85°C -120 TA = -40°C TA = 25°C -140 TA = -40°C -140 TA = 25°C -160 1k 10k 100k 1M Frequency (Hz) 10M -160 1k 40M 10k 100k 1M Frequency (Hz) 10M Figure 17. Closed Loop Phase Noise vs Frequency and Temperature Figure 18. Closed Loop Phase Noise vs Frequency and Temperature -40 -40 F_LO_OUT = 4 GHz VCC = 3.3, 5 V Div 1 Mode -80 TA = 85°C -100 TA = -40°C -120 -140 F_LO_OUT = 2 GHz VCC = 3.3, 5 V Div 2 Mode -60 Phase Noise (dBc/Hz) -60 Phase Noise (dBc/Hz) 40M G016 G015 -80 TA = 85°C -100 -120 TA = -40°C -140 TA = 25°C TA = 25°C -160 1k 10k 100k 1M Frequency (Hz) 10M 40M G017 Figure 19. Closed Loop Phase Noise vs Frequency and Temperature 12 Submit Documentation Feedback -160 1k 10k 100k 1M Frequency (Hz) 10M 40M G018 Figure 20. Closed Loop Phase Noise vs Frequency and Temperature Copyright © 2010–2016, Texas Instruments Incorporated TRF372017 www.ti.com SLWS224E – AUGUST 2010 – REVISED JANUARY 2016 Typical Characteristics (continued) VCM = 1.7 V (internal), VinBB = 300 mVrms single-ended sine wave in quadrature, VCC3V = 3.3 V, VCC5V = 5 V, fBB = 4.5 MHz and 5.5 MHz, internal LO, TA = 25°C; FPFD = 1.6 MHz (unless otherwise noted). -40 -40 F_LO_OUT = 1 GHz VCC = 3.3, 5 V Div 4 Mode -60 Phase Noise (dBc/Hz) Phase Noise (dBc/Hz) -60 F_LO_OUT = 500 MHz VCC = 3.3, 5 V Div 8 Mode -80 TA = 85°C -100 -120 TA = 25°C TA = -40°C -80 -100 TA = 85°C -120 TA = 25°C -140 TA = -40°C -140 -160 1k 10k 100k 1M Frequency (Hz) 10M -160 1k 40M 10k 100k 1M Frequency (Hz) 10M Figure 21. Closed Loop Phase Noise vs Frequency and Temperature Figure 22. Closed Loop Phase Noise vs Frequency and Temperature -40 -40 F_LO_OUT = 4.6 GHz VCC = 3.3, 5 V Div 1 Mode -80 F_LO_OUT = 2.3 GHz VCC = 3.3, 5 V Div 2 Mode -60 Phase Noise (dBc/Hz) -60 Phase Noise (dBc/Hz) 40M G020 G019 TA = 85°C -100 TA = -40°C -120 -80 TA = 85°C -100 TA = 25°C -120 TA = -40°C TA = 25°C -140 -160 1k 10k 100k 1M Frequency (Hz) -140 10M -160 1k 40M 10k 100k 1M Frequency (Hz) 10M G021 G022 Figure 23. Closed Loop Phase Noise vs Frequency and Temperature Figure 24. Closed Loop Phase Noise vs Frequency and Temperature -40 -40 F_LO_OUT = 1.15 GHz VCC = 3.3, 5 V Div 4 Mode F_LO_OUT = 575 MHz VCC = 3.3, 5 V Div 8 Mode -60 Phase Noise (dBc/Hz) -60 Phase Noise (dBc/Hz) 40M -80 TA = 85°C -100 -120 -80 -100 TA = 85°C -120 TA = 25°C TA = -40°C TA = 25°C TA = -40°C -140 -140 -160 1k 10k 100k 1M Frequency (Hz) 10M 40M G023 Figure 25. Closed Loop Phase Noise vs Frequency and Temperature Copyright © 2010–2016, Texas Instruments Incorporated -160 1k 10k 100k 1M Frequency (Hz) 10M 40M G024 Figure 26. Closed Loop Phase Noise vs Frequency and Temperature Submit Documentation Feedback 13 TRF372017 SLWS224E – AUGUST 2010 – REVISED JANUARY 2016 www.ti.com Typical Characteristics (continued) VCM = 1.7 V (internal), VinBB = 300 mVrms single-ended sine wave in quadrature, VCC3V = 3.3 V, VCC5V = 5 V, fBB = 4.5 MHz and 5.5 MHz, internal LO, TA = 25°C; FPFD = 1.6 MHz (unless otherwise noted). -130 -130 VCC = 3.3, 5 V Internal VCO PO = -10 dBm -140 Noise at 13-MHz Offset (dBm/Hz) Noise at 13-MHz Offset (dBm/Hz) -140 T A = 85°C -150 -160 T A = 25°C T A = -40°C -170 -180 T A = 25°C Internal VCO PO = -10dBm VCC = 3 V -150 VCC = 3.3 V -160 VCC = 3.6 V -170 -180 -190 350 700 -190 350 1050 1400 1750 2100 2450 2800 3150 3500 Frequency (MHz) 700 1050 1400 1750 2100 2450 2800 3150 3500 Frequency (MHz) G025 Figure 27. Noise at 13-MHz Offset vs Frequency and Temperature With Internal VCO G026 Figure 28. Noise at 13-MHz Offset vs Frequency and Supply Voltage With Internal VCO -130 -130 VCC = 3.3, 5 V External VCO PO = -10dBm -140 T A = 85°C Noise at 13-MHz Offset (dBm/Hz) Noise at 13-MHz Offset (dBm/Hz) -140 -150 -160 T A = 25°C T A = -40°C -170 -180 T A = 25°C External VCO PO = -10dBm VCC = 3.3 V -150 -160 VCC = 3.6 V VCC = 3 V -170 -180 -190 350 700 -190 350 1050 1400 1750 2100 2450 2800 3150 3500 Frequency (MHz) 700 1050 1400 1750 2100 2450 2800 3150 3500 Frequency (MHz) G027 Figure 29. Noise at 13-MHz Offset vs Frequency and Temperature With External VCO G028 Figure 30. Noise at 13-MHz Offset vs Frequency and Supply Voltage With External VCO -130 Noise at 13-MHz Offset (dBm/Hz) -140 -145 2 VCC = 3.3, 5 V T A = 25°C 1 f = 2140 MHz f = 3500 MHz 0 f = 2700 MHz -1 Voltage Gain (dB) -135 -150 -155 -160 f = 900 MHz T A = 25°C -2 T A = -40°C -3 -4 -165 f = 750 MHz -5 -170 T A = 85°C f = 450 MHz -6 -175 -180 -15 -10 -5 0 Output Power (dBm) 5 10 G029 Figure 31. Noise at 13-MHz Offset vs Output Power and Frequency 14 Submit Documentation Feedback -7 300 800 1300 1800 2300 2800 3300 3800 4300 4800 Frequency (MHz) G030 Figure 32. Voltage Gain vs Frequency and Temperature Copyright © 2010–2016, Texas Instruments Incorporated TRF372017 www.ti.com SLWS224E – AUGUST 2010 – REVISED JANUARY 2016 Typical Characteristics (continued) VCM = 1.7 V (internal), VinBB = 300 mVrms single-ended sine wave in quadrature, VCC3V = 3.3 V, VCC5V = 5 V, fBB = 4.5 MHz and 5.5 MHz, internal LO, TA = 25°C; FPFD = 1.6 MHz (unless otherwise noted). -3 -3.2 T A = 25°C -3.25 -3.1 T A = -40°C Voltage Gain (dB) Voltage Gain (dB) -3.3 -3.2 T A = -40°C -3.3 -3.35 -3.4 -3.45 T A = 25°C T A = 85°C -3.5 -3.4 T A = 85°C -3.55 -3.5 720 725 730 735 740 745 750 755 Frequency (MHz) 760 765 -3.6 880 770 885 890 895 900 905 Frequency (MHz) 910 915 G031 920 G032 Figure 33. Voltage Gain vs Frequency and Temperature at 750 MHz Figure 34. Voltage Gain vs Frequency and Temperature at 900 MHz -3.6 -3.4 -3.5 -3.7 -3.6 T A = -40°C -3.7 T A = -40°C Voltage Gain (dB) Voltage Gain (dB) -3.8 -3.9 T A = 25°C -4 -3.8 -3.9 -4 -4.1 -4.1 T A = 25°C -4.2 T A = 85°C -4.2 T A = 85°C -4.3 -4.3 1465 1470 1475 1480 1485 1490 1495 1500 1505 1510 Frequency (MHz) -4.4 2100 2110 2120 2130 2140 2150 Frequency (MHz) 2160 G033 G034 Figure 35. Voltage Gain vs Frequency and Temperature at 1500 MHz Figure 36. Voltage Gain vs Frequency and Temperature at 2150 MHz -2.7 -2.4 -2.6 -2.8 f = 2700 MHz -2.8 T A = -40°C -2.9 -3 Voltage Gain (dB) T A = 25°C Voltage Gain (dB) 2170 -3 -3.1 -3.2 f = 750 MHz -3.2 -3.4 f = 900 MHz -3.6 f = 2150 MHz -3.8 -3.3 -4 T A = 85°C -3.4 -3.5 2610 -4.2 2620 2630 2640 2650 2660 Frequency (MHz) 2670 2680 2690 G035 Figure 37. Voltage Gain vs Frequency and Temperature at 2650 MHz Copyright © 2010–2016, Texas Instruments Incorporated -4.4 1.55 f = 1500 MHz 1.6 1.65 1.7 1.75 1.8 Common-Mode Voltage (V) 1.85 1.9 G036 Figure 38. Voltage Gain vs Common-Mode Voltage and Frequency Submit Documentation Feedback 15 TRF372017 SLWS224E – AUGUST 2010 – REVISED JANUARY 2016 www.ti.com Typical Characteristics (continued) VCM = 1.7 V (internal), VinBB = 300 mVrms single-ended sine wave in quadrature, VCC3V = 3.3 V, VCC5V = 5 V, fBB = 4.5 MHz and 5.5 MHz, internal LO, TA = 25°C; FPFD = 1.6 MHz (unless otherwise noted). -2.5 1 f = 2700 MHz -2.7 0 -2.9 f = 750 MHz -1 -3.3 Voltage Gain (dB) Voltage Gain (dB) -3.1 f = 900 MHz -3.5 -3.7 f = 2150 MHz -2 VCC = 3.3 V -3 -3.9 VCC = 3.6 V -4.1 -4 f = 1500 MHz -4.3 VCC = 3 V BB Voltage is Single-Ended RMS -4.5 0 100 200 300 400 500 600 700 800 Baseband Voltage Amplitude (mV) -5 300 900 1000 800 1300 1800 2300 2800 3300 3800 4300 4800 Frequency (MHz) G037 Figure 39. Voltage Gain vs Baseband Voltage Amplitude and Frequency G038 Figure 40. Voltage Gain vs Frequency and Supply Voltage 15 11.3 14 13 T A = 25°C 11.2 T A = 25°C 11.1 11 11 10 P1dB (dBm) P1dB (dBm) 12 T A = 85°C T A = -40°C 9 T A = 85°C 10.9 10.8 8 10.7 7 T A = -40°C 10.6 6 5 300 800 10.5 700 1300 1800 2300 2800 3300 3800 4300 4800 Frequency (MHz) 710 720 730 740 750 760 770 Frequency (MHz) 780 G039 Figure 41. P1dB vs Frequency and Temperature G040 11.5 11.3 11.4 T A = 25°C 11.2 P1dB (dBm) 11.1 P1dB (dBm) T A = 25°C 11.3 11.2 11 T A = 85°C 10.9 11.1 11 T A = 85°C 10.9 T A = -40°C 10.8 10.8 10.7 10.7 10.6 10.6 T A = -40°C 860 870 880 890 900 910 920 Frequency (MHz) 930 940 950 G041 Figure 43. P1dB vs Frequency and Temperature at 900 MHz 16 800 Figure 42. P1dB vs Frequency and Temperature at 750 MHz 11.4 10.5 850 790 Submit Documentation Feedback 10.5 1450 1460 1470 1480 1490 1500 1510 1520 1530 1540 1550 Frequency (MHz) G042 Figure 44. P1dB vs Frequency and Temperature at 1500 MHz Copyright © 2010–2016, Texas Instruments Incorporated TRF372017 www.ti.com SLWS224E – AUGUST 2010 – REVISED JANUARY 2016 Typical Characteristics (continued) VCM = 1.7 V (internal), VinBB = 300 mVrms single-ended sine wave in quadrature, VCC3V = 3.3 V, VCC5V = 5 V, fBB = 4.5 MHz and 5.5 MHz, internal LO, TA = 25°C; FPFD = 1.6 MHz (unless otherwise noted). 12.2 12.6 12 12.4 T A = 25°C T A = 25°C 12.2 11.8 P1dB (dBm) P1dB (dBm) 12 11.6 T A = -40°C 11.4 11.8 T A = -40°C 11.6 11.2 11.4 11 T A = 85°C T A = 85°C 11.2 10.8 2100 2110 2120 2130 2140 2150 2160 2170 2180 2190 2200 Frequency (MHz) 11 2650 2660 2670 2680 2690 2700 2710 2720 2730 2740 2750 Frequency (MHz) G043 Figure 45. P1dB vs Frequency and Temperature at 2150 MHz G044 Figure 46. P1dB vs Frequency and Temperature at 2700 MHz 15 14 14 f = 2700 MHz 13 13 f = 2150 MHz 12 P1dB (dBm) P1dB (dBm) 12 VCC = 3.6 V 11 f = 1500 MHz 10 VCC = 3.3 V 10 9 f = 900 MHz VCC = 3 V 8 f = 750 MHz 9 11 7 8 1.55 1.6 1.65 1.7 1.75 1.8 Common-Mode Voltage (V) 1.85 6 300 1.9 800 1300 1800 2300 2800 3300 3800 4300 4800 Frequency (MHz) G045 Figure 47. P1dB vs Common-Mode Voltage and Frequency G046 Figure 48. P1dB vs Frequency and Supply Voltage 34 28 32 T A = -40°C 30 27.5 T A = 25°C T A = -40°C 27 26.5 26 OIP3 (dBm) OIP3 (dBm) 28 24 22 26 T A = 85°C T A = 25°C 25.5 T A = 85°C 20 25 18 24.5 16 14 300 800 1300 1800 2300 2800 3300 3800 4300 4800 Frequency (MHz) G047 Figure 49. OIP3 vs Frequency and Temperature Copyright © 2010–2016, Texas Instruments Incorporated 24 880 885 890 895 900 905 Frequency (MHz) 910 915 920 G048 Figure 50. OIP3 vs Temperature and Frequency at 900 MHz Submit Documentation Feedback 17 TRF372017 SLWS224E – AUGUST 2010 – REVISED JANUARY 2016 www.ti.com Typical Characteristics (continued) VCM = 1.7 V (internal), VinBB = 300 mVrms single-ended sine wave in quadrature, VCC3V = 3.3 V, VCC5V = 5 V, fBB = 4.5 MHz and 5.5 MHz, internal LO, TA = 25°C; FPFD = 1.6 MHz (unless otherwise noted). 28 26 27.5 25.5 T A = 25°C T A = -40°C 27 25 26.5 24.5 OIP3 (dBm) OIP3 (dBm) T A = -40°C 26 25.5 24 23.5 T A = 25°C T A = 85°C 25 23 24.5 22.5 24 1000 1005 1010 1015 1020 1025 Frequency (MHz) 1030 1035 T A = 85°C 22 1620 1625 1630 1635 1640 1645 1650 1655 1660 1665 1670 Frequency (MHz) 1040 G049 Figure 51. OIP3 vs Frequency and Temperature at 1030 MHz G050 Figure 52. OIP3 vs Frequency and Temperature at 1650 MHz 30 27 T A = -40°C 29 26 T A = 25°C 28 OIP3 (dBm) OIP3 (dBm) 25 24 T A = 25°C 27 T A = -40°C 26 23 25 22 T A = 85°C 21 2260 2270 T A = 85°C 24 2280 2290 2300 Frequency (MHz) 2310 23 2770 2320 2780 2790 2800 2810 2820 Frequency (MHz) 2830 2840 2850 G051 Figure 53. OIP3 vs Frequency and Temperature at 2300 MHz G052 Figure 54. OIP3 vs Frequency and Temperature at 2850 MHz 30 29 f = 900 MHz f = 900 MHz 29 28 28 27 f = 2150 MHz f = 2700 MHz f = 2700 MHz 27 25 OIP3 (dBm) OIP3 (dBm) 26 f = 2150 MHz 24 26 25 24 f = 750 MHz f = 1500 MHz 23 f = 1500 MHz 23 f = 750 MHz 22 22 21 BB Voltage is Single-Ended RMS TA = 25°C 21 1.5 20 1.55 1.6 1.65 1.7 1.75 1.8 Common-Mode Voltage (V) 1.85 0 1.9 G053 Figure 55. OIP3 vs Common-Mode Voltage and Frequency 18 Submit Documentation Feedback 100 200 300 400 500 600 700 800 Baseband Voltage Amplitude (mV) 900 1000 G083 Figure 56. OIP3 vs Baseband Voltage Amplitude and Frequency Copyright © 2010–2016, Texas Instruments Incorporated TRF372017 www.ti.com SLWS224E – AUGUST 2010 – REVISED JANUARY 2016 Typical Characteristics (continued) VCM = 1.7 V (internal), VinBB = 300 mVrms single-ended sine wave in quadrature, VCC3V = 3.3 V, VCC5V = 5 V, fBB = 4.5 MHz and 5.5 MHz, internal LO, TA = 25°C; FPFD = 1.6 MHz (unless otherwise noted). 70 58 65 57.5 T A = -40°C T A = 85°C 60 T A = 25°C 57 OIP2 (dBm) OIP2 (dBm) 55 50 45 T A = 25°C 56.5 56 40 T A = -40°C T A = 85°C 55.5 35 30 300 800 55 730 1300 1800 2300 2800 3300 3800 4300 4800 Frequency (MHz) 735 740 745 750 755 Frequency (MHz) 760 765 770 G054 Figure 57. OIP2 vs Frequency and Temperature G055 Figure 58. OIP2 vs Frequency and Temperature at 750 MHz 58 58 57.5 T A = -40°C 57.5 57 T A = 85°C T A = 25°C 57 OIP2 (dBm) OIP2 (dBm) 56.5 56.5 55.5 T A = 25°C 56 56 55 T A = 85°C 55.5 T A = -40°C 54.5 55 880 885 890 895 900 905 Frequency (MHz) 910 915 54 1470 920 1475 1480 1485 1490 1495 Frequency (MHz) 1500 1505 G056 Figure 59. OIP2 vs Frequency and Temperature at 900 MHz G057 Figure 60. OIP2 vs Frequency and Temperature at 1500 MHz 57 54 56.5 53 T A = -40°C T A = 25°C 56 51 OIP2 (dBm) OIP2 (dBm) T A = 85°C 52 55.5 55 50 49 54.5 T A = 85°C 54 T A = 25°C 48 47 53.5 53 2100 1510 2110 2120 2130 2140 2150 Frequency (MHz) 2160 2170 2180 G058 Figure 61. OIP2 vs Frequency and Temperature at 2150 MHz Copyright © 2010–2016, Texas Instruments Incorporated 46 2620 T A = -40°C 2630 2640 2650 2660 2670 Frequency (MHz) 2680 2690 G059 Figure 62. OIP2 vs Frequency and Temperature at 2650 MHz Submit Documentation Feedback 19 TRF372017 SLWS224E – AUGUST 2010 – REVISED JANUARY 2016 www.ti.com Typical Characteristics (continued) VCM = 1.7 V (internal), VinBB = 300 mVrms single-ended sine wave in quadrature, VCC3V = 3.3 V, VCC5V = 5 V, fBB = 4.5 MHz and 5.5 MHz, internal LO, TA = 25°C; FPFD = 1.6 MHz (unless otherwise noted). 46.5 50 Unadjusted Sideband Suppression (dBc) Unadjusted Sideband Suppression (dBc) 55 T A = 85°C T A = -40°C 45 40 35 T A = 25°C 30 25 300 800 T A = 25°C 46 T A = 85°C 45.5 T A = -40°C 45 880 1300 1800 2300 2800 3300 3800 4300 4800 Frequency (MHz) 885 890 895 900 905 Frequency (MHz) 910 915 G060 G061 Figure 63. Unadjusted Sideband Suppression vs Frequency and Temperature Figure 64. Unadjusted Sideband Suppression vs Frequency and Temperature at 900 MHz 43 47 42.5 Unadjusted Sideband Suppression (dBc) Unadjusted Sideband Suppression (dBc) 46.5 T A = -40°C 46 45.5 T A = 25°C 45 44.5 T A = 85°C 44 42 T A = -40°C 41.5 T A = 85°C 41 40.5 40 T A = 25°C 39.5 43.5 43 1000 920 1005 1010 1015 1020 1025 Frequency (MHz) 1030 1035 39 1610 1040 1620 1630 1640 1650 Frequency (MHz) 1660 Figure 65. Unadjusted Sideband Suppression vs Frequency and Temperature at 1030 MHz 1670 G063 G062 Figure 66. Unadjusted Sideband Suppression vs Frequency and Temperature at 1650 MHz 37 44 Unadjusted Sideband Suppression (dBc) Unadjusted Sideband Suppression (dBc) 36 T A = -40°C 35 34 T A = 25°C 33 32 T A = 85°C T A = -40°C 43 T A = 85°C 42 41 T A = 25°C 40 31 30 2250 2260 2270 2280 2290 2300 Frequency (MHz) 2310 2320 2330 G064 Figure 67. Unadjusted Sideband Suppression vs Frequency and Temperature at 2300 MHz 20 Submit Documentation Feedback 39 2760 2770 2780 2790 2800 2810 2820 2830 2840 2850 Frequency (MHz) G065 Figure 68. Unadjusted Sideband Suppression vs Frequency and Temperature at 2850 MHz Copyright © 2010–2016, Texas Instruments Incorporated TRF372017 www.ti.com SLWS224E – AUGUST 2010 – REVISED JANUARY 2016 Typical Characteristics (continued) VCM = 1.7 V (internal), VinBB = 300 mVrms single-ended sine wave in quadrature, VCC3V = 3.3 V, VCC5V = 5 V, fBB = 4.5 MHz and 5.5 MHz, internal LO, TA = 25°C; FPFD = 1.6 MHz (unless otherwise noted). 50 -21 T A = 25°C -24 f = 750 MHz Unadjusted Carrier Suppression (dBm) Unadjusted Sideband Suppression (dBc) 48 46 44 f = 2700 MHz f = 900 MHz 42 40 f = 1500 MHz 38 36 34 1.55 f = 2150 MHz 1.6 -27 -30 T A = -40°C T A = 25°C -33 -36 -39 -42 -45 -48 1.65 1.7 1.75 1.8 Common-Mode Voltage (V) 1.85 -51 300 1.9 T A = 85°C 800 G066 1300 1800 2300 2800 3300 3800 4300 4800 Frequency (MHz) G067 Figure 69. Unadjusted Sideband Suppression vs Common-Mode Voltage and Frequency Figure 70. Unadjusted Carrier Suppression vs Frequency and Temperature -41 -42 -42.5 Unadjusted Carrier Suppression (dBm) Unadjusted Carrier Suppression (dBm) -41.5 -42 T A = -40°C -42.5 T A = 25°C -43 -43.5 -44 -44.5 T A = 85°C -45 -43 -43.5 -44 -44.5 T A = -40°C -45 T A = 85°C -45.5 -45.5 -46 880 T A = 25°C 885 890 895 900 905 Frequency (MHz) 910 915 -46 990 920 1000 1010 1020 1030 Frequency (MHz) 1040 Figure 71. Unadjusted Carrier Suppression vs Frequency and Temperature at 900 MHz Figure 72. Unadjusted Carrier Suppression vs Frequency and Temperature at 1030 MHz -43 -35 -36 T A = 25°C -44 Unadjusted Carrier Suppression (dBm) Unadjusted Carrier suppression (dBm) -43.5 T A = 85°C -44.5 -45 -45.5 -46 -46.5 -47 1610 1050 G069 G068 T A = -40°C 1620 1630 1640 1650 Frequency (MHz) T A = -40°C -37 -38 -39 -40 -41 T A = 25°C -42 T A = 85°C -43 -44 1660 1670 G070 Figure 73. Unadjusted Carrier Suppression vs Frequency and Temperature at 1650 MHz Copyright © 2010–2016, Texas Instruments Incorporated -45 2250 2260 2270 2280 2290 2300 Frequency (MHz) 2310 2320 2330 G071 Figure 74. Unadjusted Carrier Suppression vs Frequency and Temperature at 2300 MHz Submit Documentation Feedback 21 TRF372017 SLWS224E – AUGUST 2010 – REVISED JANUARY 2016 www.ti.com Typical Characteristics (continued) VCM = 1.7 V (internal), VinBB = 300 mVrms single-ended sine wave in quadrature, VCC3V = 3.3 V, VCC5V = 5 V, fBB = 4.5 MHz and 5.5 MHz, internal LO, TA = 25°C; FPFD = 1.6 MHz (unless otherwise noted). -39 -34 T A = -40°C Unadjusted Carrier Suppression (dBm) Unadjusted Carrier Suppression (dBm) -38 -40 f = 2150 MHz -40 -36 T A = 25°C -42 -44 T A = 85°C -46 -48 f = 2700 MHz -41 -42 -43 -44 -45 f = 900 MHz -46 f = 1500 MHz -47 -50 -48 -52 2760 2770 2780 2790 2800 2810 2820 2830 2840 2850 Frequency (MHz) -49 1.5 f = 750 MHz 1.55 1.6 T A = 25°C 1.65 1.7 1.75 1.8 1.85 Common-Mode Voltage (V) 1.9 1.95 2 G073 G072 Figure 76. Unadjusted Carrier Suppression vs Common-Mode Voltage and Frequency Figure 75. Unadjusted Carrier Suppression vs Frequency and Temperature at 2850 MHz 20 2 T A = -40°C T A = 25°C T A = 85°C 15 1.8 BBIP Baseband Voltage Offset (mV) Common-Mode Voltage (V) 1.9 T A = 25°C 1.7 T A = -40°C 1.6 T A = 85°C 1.5 10 5 0 DCOFFSET_I = 1 -5 -10 -15 DCOFFSET_I = 3 -20 -25 -30 1.4 0 1 2 3 4 VREF_SEL Setting 5 6 7 G074 Figure 77. Common-Mode Voltage vs VREF_SEL Setting and Temperature 22 Submit Documentation Feedback 0 30 60 90 120 150 IOFF Setting 180 210 240 G075 Figure 78. Baseband Voltage Offset vs IOFF Setting and Temperature Copyright © 2010–2016, Texas Instruments Incorporated TRF372017 www.ti.com SLWS224E – AUGUST 2010 – REVISED JANUARY 2016 7 Detailed Description 7.1 Overview The TRF372017 is a high-performance, direct up-conversion device, integrating a high-linearity, low-noise IQ modulator and an integer-fractional PLL/VCO. The VCO uses integrated frequency dividers to achieve a wide, continuous tuning range of 300 MHz to 4800 MHz. The LO is available as an output with independent frequency dividers. The device also accepts input from an external LO or VCO. The modulator baseband inputs can be biased either internally or externally. Internal DC offset adjustment enables carrier cancellation. The device is controlled through a 3-wire serial programming interface (SPI). A control pin invokes power-save mode to reduce power consumption while keeping the VCO locked for fast start-up. LO_OUT BBQ From Div1/2/4/ 8 SPI Vcm D/A VTUNE EXT_VCO 7.2 Functional Block Diagram CP_OUT Charge Pump PolyPhase PFD From SPI PS Pwr save Vcm D/A From SPI SD control N- Divider REFIN GNDs VCCs S From SPI From SPI RF Divider R Div Lock det LD Prescaler div p/p+1 Serial Interface LE DATA CLK RFOUT Div2/ 4/8 BBI 7.3 Feature Description 7.3.1 Integer and Fractional Mode Selection The PLL is designed to operate in either Integer mode or Fractional mode. If the desired local oscillator (LO) frequency is an integer multiple of the phase frequency detector (PFD) frequency, fPFD, then Integer mode can be selected. The normalized in-band phase noise floor in Integer mode is lower than in Fractional mode. In Integer mode, the feedback divider is an exact integer, and the fraction is zero. While operating in Integer mode, the register bits corresponding to the fractional control are don’t care. In Fractional mode, the feedback divider fractional portion is non-zero on average. With 25-bit fractional resolution, RF stepsize fPFD/225 is less than 1 Hz with a fPFD up to 33 MHz. The appropriate fractional control bits in the serial register must be programmed. Copyright © 2010–2016, Texas Instruments Incorporated Submit Documentation Feedback 23 TRF372017 SLWS224E – AUGUST 2010 – REVISED JANUARY 2016 www.ti.com Feature Description (continued) 7.3.2 Description of PLL Structure EXT_VCO VCO0 fREF REFIN Divide fPFD by R fComp PHASE FREQUENCY DETECTOR + CHARGE PUMP CP_OUT LOOP FILTER Z(f) Divide by 1/2/4/8 VCO1 VTUNE fVCO VCO2 Divide by 1/2/4/8 fLO LOP,LON fmixer VCO3 RF Div Dig Div Divide fN Prescaler fPM by N.f 4/5 or 8/9 Divide by 1/2/4 NINT & NFRAC Div Figure 79. Block Diagram of the PLL Loop The output frequency is given by Equation 1: fVCO = fREF NFRAC (PLL_DIV_SEL) NINT + RDIV 225 (1) The rate at which phase comparison occurs is fREF/RDIV. In Integer mode, the fractional setting is ignored and Equation 2 is applied. fVCO = NINT ´ PLL_DIV_SEL fPFD (2) The feedback divider block consists of a programmable RF divider, a prescaler divider, and an NF divider. The prescaler can be programmed as either a 4/5 or an 8/9 prescaler. The NF divider includes an A counter and an M counter. 7.3.2.1 Selecting PLL Divider Values Operation of the PLL requires the LO_DIV_SEL, RDIV, PLL_DIV_SEL, NINT, and NFRAC bits to be calculated. The LO or mixer frequency is related to fVCO according to divide-by-1/-2/-4/-8 blocks and the operating range of fVCO. a. LO_DIV_SEL LO_DIV_SEL = 1 2400 MHz £ fRF £ 4800 MHz 2 1200 MHz £ fRF £ 2400 MHz 3 600 MHz £ fRF £ 1200 MHz 4 300 MHz £ fRF £ 600 MHz Therefore: fVCO = LO_DIV_SEL ´ fRF 24 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated TRF372017 www.ti.com SLWS224E – AUGUST 2010 – REVISED JANUARY 2016 Feature Description (continued) b. PLL_DIV_SEL Given fVCO, select the minimum value for PLL_DIV_SEL so that the programmable RF divider limits the input frequency into the prescaler block, fPM, to a maximum of 3000 MHz. PLL _ DIV _ SEL = min(1, 2, 4) such that fPM ≤ 3000 MHz This calculation can be restated as Equation 3. PLL_DIV_SEL = Ceiling ( LO_DIV_SEL ´ fRF 3000 MHz ( (3) Higher values of fPFD correspond to better phase noise performance in Integer mode or Fractional mode. fPFD, along with PLL_DIV_SEL, determines the fVCO stepsize in Integer mode. Therefore, in Integer mode, select the maximum fPFD that allows for the required RF stepsize, as shown by Equation 4. fPFD = fVCO, Stepsize f ´ LO_DIV_SEL = RF, Stepsize PLL_DIV_SEL PLL_DIV_SEL (4) In Fractional mode, a small RF stepsize is accomplished through the Fractional mode divider. A large fPFD should be used to minimize the effects of fractional controller noise in the output spectrum. In this case, fPFD may vary according to the reference clock and fractional spur requirements (for example, fPFD = 20 MHz). c. RDIV, NINT, NFRAC, PRSC_SEL RDIV = fREF fPFD ( NINT = floor fVCORDIV fREFPLL_DIV_SEL NFRAC = floor (( ( fVCORDIV fREFPLL_DIV_SEL ( - NINT 225 ( The P/(P+1) programmable prescaler is set to 8/9 or 4/5 through the PRSC_SEL bit. To allow proper fractional control, set PRSC_SEL according to Equation 5. 8 NINT ³ 75 in Fractional Mode or NINT ³ 72 in Integer mode 9 PRSC_SEL = 4 23 £ NINT < 75 in Fractional mode or 20 £ NINT < 72 in Integer mode 5 (5) The PRSC_SEL limit at NINT < 75 applies to Fractional mode with third-order modulation. In Integer mode, the PRSC_SEL = 8/9 should be used with NINT as low as 72. The divider block accounts for either value of PRSC_SEL without requiring NINT or NFRAC to be adjusted. Then, calculate the maximum frequency to be input to the digital divider at fN. Use the lower of the possible prescaler divide settings, P = (4,8), as shown by Equation 6. Copyright © 2010–2016, Texas Instruments Incorporated Submit Documentation Feedback 25 TRF372017 SLWS224E – AUGUST 2010 – REVISED JANUARY 2016 www.ti.com Feature Description (continued) fN,Max = fVCO PLL_DIV_SEL ´ P (6) Verify that the frequency into the digital divider, fN, is less than or equal to 375 MHz. If fN exceeds 375 MHz, choose a larger value for PLL_DIV_SEL and recalculate fPFD, RDIV, NINT, NFRAC, and PRSC_SEL. 7.3.2.2 Setup Example for Integer Mode Suppose the following operating characteristics are desired for Integer mode operation: • fREF = 40 MHz (reference input frequency) • Step at RF = 2 MHz (RF channel spacing) • fRF = 1600 MHz (RF frequency) The VCO range is 2400 MHz to 4800 MHz. Therefore: • LO_DIV_SEL = 2 • fVCO = LO_DIV_SEL × 1600 MHz = 3200 MHz To keep the frequency of the prescaler less than 3000 MHz: • PLL_DIV_SEL = 2 The desired stepsize at RF is 2 MHz, so: • fPFD = 2 MHz • fVCO, stepsize = PLL_DIV_SEL × fPFD = 4 MHz Using the reference frequency along with the required fPFD gives: • RDIV = 20 • NINT = 800 NINT ≥ 75; therefore, select the 8/9 prescaler. fN,Max = 3200 MHz/(2 × 8) = 200 MHz < 375 MHz This example shows that Integer mode operation gives sufficient resolution for the required stepsize. 7.3.2.3 Setup Example for Fractional Mode Suppose the following operating characteristics are desired for Fractional mode operation: • fREF = 40 MHz (reference input frequency) • Step at RF = 5 MHz (RF channel spacing) • fRF = 1,600,000,045 Hz (RF frequency) The VCO range is 2400 MHz to 4800 MHz. Therefore: • LO_DIV_SEL = 2 • fVCO = LO_DIV_SEL × 1,600,000,045 Hz = 3,200,000,090 Hz To keep the frequency of the prescaler less than 3000 MHz: • PLL_DIV_SEL = 2 Using a typical fPFD of 20 MHz: • RDIV = 2 • NINT = 80 • NFRAC = 75 NINT ≥ 75; therefore, select the 8/9 prescaler. fN,Max = 3200 MHz/(2 × 8) = 200 MHz < 375 MHz 26 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated TRF372017 www.ti.com SLWS224E – AUGUST 2010 – REVISED JANUARY 2016 Feature Description (continued) The actual frequency at RF is: • fRF = 1600000044.9419 Hz Which yields a frequency error of –0.058 Hz. 7.3.3 Fractional Mode Setup Optimal operation of the PLL in fractional mode requires several additional register settings. Recommended values are listed in Table 1. Optimal performance may require tuning the MOD_ORD, ISOURCE_SINK, and ISOURCE_TRIM values according to the chosen frequency band. Table 1. Fractional Mode Register Settings REGISTER BIT REGISTER ADDRESSING RECOMMENDED VALUE EN_ISOURCE Reg4B18 1 EN_DITH Reg4B25 1 MOD_ORD Reg4B[27..26] B[27..26] = [10] DITH_SEL Reg4B28 0 DEL_SD_CLK Reg4B[30..29] B[30..29] = [10] EN_LD_ISOURCE Reg5B31 0 ISOURCE_SINK Reg7B19 0 ISOURCE_TRIM Reg7B[22..20] B[22..20] = [100] 7.3.4 Selecting the VCO and VCO Frequency Control To achieve a broad frequency tuning range, the TRF372017 includes four VCOs. Each VCO is connected to a bank of capacitors that determine its valid operating frequency. For any given frequency setting, the appropriate VCO and capacitor array must be selected. The device contains logic that automatically selects the appropriate VCO and capacitor bank. Set bit EN_CAL to initiate the calibration algorithm. During the calibration process, the device selects a VCO and a capacitor state so that VTune matches the reference voltage set by VCO_CAL_REF_n. Accuracy of the tune is increased through bits CAL_ACC_n. Because a calibration begins immediately when EN_CAL is set, all registers must contain valid values before initiating calibration. Calibration logic is driven by a CAL_CLK clock derived from the phase frequency detector frequency scaled according to the setting in CAL_CLK_SEL. Faster CAL_CLK frequency enables faster calibration, but the logic is limited to clock frequencies around 1 MHz. Table 2 provides suggested CAL_CLK_SEL scaling recommendations for several phase frequency detector frequencies. The flag R_SAT_ERR is evaluated during the calibration process to indicate calibration counter overflow errors, which occurs if CAL_CLK runs too fast. If R_SAT_ERR is set during a calibration, the resulting calibration is not valid and CAL_CLK_SEL must be used to slow the CAL_CLK. CAL_CLK frequencies should not be set to less than 0.1 MHz. Table 2. Example CAL_CLK_SEL Scaling PFD FREQUENCY (MHz) CAL_CLK_SEL SCALING CAL_CLK FREQUENCY (MHz) 20 1/32 0.625 1 1 1 0.1 8 0.8 When VCOSEL_MODE is 0, the device automatically selects both the VCO and capacitor bank within 23 CAL_CLK cycles. When VCOSEL_MODE is 1, the device uses the VCO selected in VCO_SEL_0 and VCO_SEL_1 and automatically selects the capacitor array within 17 CAL_CLK cycles. The VCO and capacitor array settings resulting from calibration cannot be read from the VCO_SEL_n and VCO_TRIM_n bits in registers 2 and 7. They can only be read from register 0. Copyright © 2010–2016, Texas Instruments Incorporated Submit Documentation Feedback 27 TRF372017 SLWS224E – AUGUST 2010 – REVISED JANUARY 2016 www.ti.com Automatic calibration can be disabled by setting CAL_BYPASS to 1. In this manual cal mode, the VCO is selected through register bits VCO_SEL_n, while the capacitor array is selected through register bits VCO_TRIM_n. Calibration modes are summarized in Table 3. After calibration is complete, the PLL is released from calibration mode to reach an analog lock. During the calibration process, the TRF372017 scans through many frequencies. RF and LO outputs should be disabled until calibration is complete. At power up, the RF and LO output are disabled by default. Once a calibration has been performed at a given frequency setting, the calibration is valid over all operating temperature conditions. Table 3. VCO Calibration Modes CAL_BYPASS VCOSEL_MODE MAX CYCLES CAL_CLK 0 0 46 0 1 34 VCO_SEL_n automatic 1 don't care na VCO_SEL_n VCO_TRIM_n VCO CAPACITOR ARRAY Automatic 7.3.5 External VCO An external LO or VCO signal may be applied. EN_EXTVCO powers the input buffer and selects the buffered external signal instead of an internal VCO. Dividers, the pfd, and the charge pump remain enabled and may be used to drive an external VCO. NEG_VCO must correspond to the gain of the external VCO. 7.3.6 VCO Test Mode Setting VCO_TEST_MODE forces the currently selected VCO to the edge of its frequency range by disconnecting the charge pump input from the pfd and loop filter and forcing its output high or low. The upper or lower edge of the VCO range is selected through COUNT_MODE_MUX_SEL. VCO_TEST_MODE also reports the value of a frequency counter in COUNT, which can be read back in register 0. COUNT reports the number of digital N divider cycles in the PLL, directly related to the period of fN, that occur during each CAL_CLK cycle. Counter operation is initiated through the bit EN_CAL. Table 4. VCO Test Mode VCO_TEST_MODE COUNT_MODE_MUX_SEL VCO OPERATION REGISTER 0 B[30..13] B[30..24] = undefined B[23..22] = VCO_SEL selected during autocal B21 = undefined B[20..13] = VCO_TRIM selected during autocal 0 don't care Normal 1 0 Max frequency B[30..13] = Max frequency counter 1 1 Min frequency B[30..13] = Min frequency counter 7.3.7 Lock Detect The lock detect signal is generated in the phase frequency detector by comparing the VCO target frequency against the VCO actual frequency. When the phase of the two compared frequencies remains aligned for several clock cycles, an internal signal goes high. The precision of this comparison is controlled through the LD_ANA_PREC bits. This internal signal is then averaged and compared against a reference voltage to generate the LD signal. The number of averages used is controlled through LD_DIG_PREC. Therefore, when the VCO is frequency locked, LD is high. When the VCO frequency is not locked, LD may pulse high or exhibit periodic behavior. By default, the internal lock detect signal is driven on the LD terminal. Register bits MUX_CTRL_n can be used to control a mux to output other diagnostic signals on the LD output. The LD control signals are shown in Table 5. 28 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated TRF372017 www.ti.com SLWS224E – AUGUST 2010 – REVISED JANUARY 2016 Table 5. LD Control Signals ADJUSTMENT REGISTER BITS BIT ADDRESSING Lock detect precision LD_ANA_PREC_0 Register 4 Bit 19 Unlock detect precision LD_ANA_PREC_1 Register 4 Bit 20 LD averaging count LD_DIG_PREC Register 4 Bit 24 Diagnostic Output MUX_CTRL_n Register 7 Bits 18..16 Table 6. LD Control Signal Mode Settings CONDITION RECOMMENDED SETTINGS Integer Mode LD_ANA_PREC_0 = 0 LD_ANA_PREC_1 = 0 LD_DIG_PREC = 1 Fractional Mode LD_ANA_PREC_0 = 1 LD_ANA_PREC_1 = 1 LD_DIG_PREC = 1 7.3.8 Tx Divider The Tx divider, illustrated in Figure 80, converts the differential output of the VCO into differential I and Q mixer components. The divide by 1 differential quadrature phases are provided through a polyphase. Divide by 2, 4, and 8 differential quadrature phases are provided through flip-flop dividers. Only one of the dividers operates at a time, and the appropriate output is selected by a mux. DIVn bits are controlled through TX_DIV_SELn. TX_DIV_I determines the bias level for the divider blocks. The SPEEDUP control is used to bypass a stabilization resistor and reach the final bias level faster after a change in the divider selection. SPEEDUP should be disabled during normal operation. DIV8 DIV4 DIV2 DIV1 PWD_TX_DIV VCO P/N Polyphase Imix P/N Div2 Div4 Qmix P/N Div8 Speedup bias Tx_DIV_I Figure 80. Tx Divider 7.3.9 LO Divider The LO divider is shown in Figure 81. It frequency divides the VCO output. Only one of the dividers operates at a time, and the appropriate output is selected by a mux. DIVn bits are controlled through LO_DIV_SELn. The output is buffered and provided on output pins LO_OUT_P and LO_OUT_N. The output level is controlled through BUFOUT_BIASn. Copyright © 2010–2016, Texas Instruments Incorporated Submit Documentation Feedback 29 TRF372017 SLWS224E – AUGUST 2010 – REVISED JANUARY 2016 www.ti.com LO_DIV_I determines the bias level for the divider blocks. The SPEEDUP control is used to bypass a stabilization resistor and reach the final bias level faster after a change in the divider selection. SPEEDUP should be disabled during normal operation. Although SPEEDUP controls both the Tx and LO divider biases, the Tx and LO divider biases are generated independently. DIV8 DIV4 DIV2 DIV1 PWD_LO_DIV Buffer VCO P/N BUFOUT_BIASn Div2 LO_OUT_P/N Div4 PWD_OUT_BUFF Div8 Speedup bias LO_DIV_I Figure 81. LO Divider 7.3.10 Mixer A diagram of the mixer is shown in Figure 82. The mixer is followed by a differential to single-ended converter and buffer for output. Imix P Imix N BBI_P BBI_N Diff2Single RFOUT Qmix N Qmix P BBQ_N BBQ_P Figure 82. Mixer 7.3.11 Disabling Outputs RF frequency outputs are generated at the RFOUT and LO* terminals. Unused RF frequency outputs should be disabled to minimize power consumption and noise generation. Table 7 lists settings used to disable the outputs. Power-save mode can also be used to disable outputs. 30 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated TRF372017 www.ti.com SLWS224E – AUGUST 2010 – REVISED JANUARY 2016 Table 7. Register Controls for Disabling Outputs DISABLED OUTPUT REGISTER BIT SETTING RFOUT PWD_TX_DIV 1 PWD_OUT_BUFF 1 PWD_LO_DIV 1 LOP and LON 7.3.12 Power Supply Distribution BB VCM Gen VCC_MIX (p21) LODIV VCC_D2S (p20) PLL IQ Offset VCC_LO1 (p7) Divider Buffer Buffer Bias VCC_PLL AN DIG VCO Tank VCC_LO1 (p7) VCC_VCO1 (p35) VCC_LO2 (p30) VCC_LO2 (p30) VCC_VCO2 (p32) VCC_VCO1 (p35) VCC_DIG VCC_PLL Power supply distribution for the TRF372017 is shown in Figure 83. Proper isolation and filtering of the supplies is critical for low noise operation of the device. Each supply pin should be supplied with local decoupling capacitance and isolated with a ferrite bead. VCC_VCO2 is tolerant of 5-V supply voltages to permit additional supply filtering. VCC VCC Buffer Mixer SPI & EEPROM TxDIV Mod Figure 83. Power Supply Distribution 7.3.13 Carrier Feedthrough Cancellation The structure of the baseband current DAC is shown in Figure 84. For each input pair, there is a programmable reference current. The reference current for each pair (I and Q) is identical and is programmed through the same register bits, but the reference current source itself is duplicated in the device for both I and Q inputs. This current can be set to change the total current flowing into the P and N nodes, which in turn changes the offset programmability range. The reference current is then mirrored and multiplied before getting injected into the input node. The total mirrored current is routed into the two sides of the differential pair and routed according to eight programmable bits. As the 8-bit setting is changed, current is shifted from one side of the pair into the other side for each of the I and Q input pairs. In practical usage, the offset current routing distributes the adjustment for each side of the pair, while the reference current sets the range of adjustment. This effect can be seen in Figure 78, which shows that the gain of the current routing is greater when the reference current setting is higher. However the step size also increases with increase in range. Figure 78 shows the effect on common mode voltage of varying the DAC reference current. Adjustment register bits are shown in Table 8. Offset adjustment may be provided by an external source, such as a DAC QMC block, for DC-coupled systems. Copyright © 2010–2016, Texas Instruments Incorporated Submit Documentation Feedback 31 TRF372017 SLWS224E – AUGUST 2010 – REVISED JANUARY 2016 www.ti.com Current Mirror I/Q Offset Ref Current, 8 bit Iref ----1 B0 DC Offset Iref Iref ----2 B1 ... Iref ----128 B8 Iref ----1 B8 Iref ----2 B7 ... IP Iref ----128 B0 IN Figure 84. Block Diagram of the Programmable Current DAC Table 8. Baseband Differential Offset Adjustment Factors ADJUSTMENT REGISTER BITS BIT ADDRESS I input differential offset programmability I Offset Ref Curr IOFF_n Register 6 Bits 12..5 Q input differential offset programmability Q Offset Ref Curr QOFF Register 6 Bits 20..13 Offset Programmability Range DCoffset_I_n Register 7 Bits 30..29 7.3.14 Internal Baseband Bias Voltage Generation The TRF372017 has the ability to generate DC voltage levels for its baseband inputs internally. Register settings in the device allow the user to adjust common mode voltage of the I and Q signals separately. There are three adjustment factors for the baseband inputs. These are described in Table 9. Table 9. Baseband Adjustment Factors 32 ADJUSTMENT REGISTER BITS BIT ADDRESSING VCM setting VREF_SEL_n Register 6 Bits 23..21 VCM Enable PWD_BB_VCM Register 4 Bit 15 Bias select IB_VCM_SEL Register 7 Bit 25 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated TRF372017 www.ti.com SLWS224E – AUGUST 2010 – REVISED JANUARY 2016 Each baseband input pair includes the circuitry depicted in Figure 85. The Vref set voltage impacts all four terminals: IP, IN, QP, and QN. The effect of changing the reference voltage is shown in Figure 77. Each node also includes a programmable current DAC that injects current into the positive and negative terminals of each input. IDAC IDAC 100 (external) external external IN IP 5000 5000 Vref Set Figure 85. Block Diagram of the Baseband I Input Nodes Table 10. Frequency Range Operation VCO FREQUENCY DIV BY 2 DIV BY 4 DIV BY 8 Fmin Fmax Fmin Fmax Fmin Fmax Fmin Fmax 2400 4800 1200 2400 600 1200 300 600 7.4 Device Functional Modes 7.4.1 Powersave Mode Powersave mode can be used to put the device into a low power consumption mode. The PLL block remains active in Powersave mode, reducing the time required for start-up. However, the modulator, dividers, output buffers, and baseband common mode generation blocks are powered down. The SPI block remains active, and registers are addressable. Use the PS pin to activate powersave mode. Copyright © 2010–2016, Texas Instruments Incorporated Submit Documentation Feedback 33 TRF372017 SLWS224E – AUGUST 2010 – REVISED JANUARY 2016 www.ti.com 7.5 Register Maps 7.5.1 Serial Interface Programming Registers Definition The TRF372017 features a 3-wire serial programming interface (SPI) that controls an internal 32-bit shift register. There are a total of 3 signals that must be applied: the clock (CLK, pin 47), the serial data (DATA, pin 46) and the latch enable (LE, pin 45). The TRF372017 has an additional pin (RDBK, pin 2) for read-back functionality. This pin is a digital pin and can be used to read-back values of different internal registers. The DATA (DB0-DB31) is loaded LSB first and is read on the rising edge of the CLOCK. The LE is asynchronous to the CLOCK and at its rising edge the data in the shift register gets loaded onto the selected internal register. The 5 LSB of the Data field are the address bits to select the available internal registers. 7.5.1.1 PLL SPI Registers 7.5.1.1.1 Register 1 Table 11. Register 1 Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit8 Register address Bit16 Bit17 …. Bit18 RSV Bit19 REF INV Bit9 Bit10 Bit11 Bit12 Bit13 Bit14 Bit15 Reference Clock Divider Bit20 VCO NEG Bit21 Bit22 Bit23 Bit24 Charge Pump Current Bit25 Bit26 CP DOUBLE Bit27 Bit28 Bit29 Bit30 VCO Cal CLK div/Mult Bit31 RSV Table 12. Register 1 Field Descriptions REGISTER 1 34 NAME RESET VALUE DESCRIPTION Bit0 ADDR_0 1 Bit1 ADDR_1 0 Bit2 ADDR_2 0 Bit3 ADDR_3 1 Bit4 ADDR_4 0 Bit5 RDIV_0 1 Bit6 RDIV_1 0 Bit7 RDIV_2 0 Bit8 RDIV_3 0 Bit9 RDIV_4 0 Bit10 RDIV_5 0 Bit11 RDIV_6 0 Bit12 RDIV_7 0 Bit13 RDIV_8 0 Bit14 RDIV_9 0 Bit15 RDIV_10 0 Bit16 RDIV_11 0 Bit17 RDIV_12 0 Bit18 RSV 0 Bit19 REF_INV 0 Invert Reference Clock polarity; 1 = use falling edge Bit20 NEG_VCO 1 VCO polarity control; 1= negative slope (negative Kv) Bit21 ICP_0 0 Bit22 ICP_1 1 Bit23 ICP_2 0 Bit24 ICP_3 1 Bit25 ICP_4 0 Bit26 ICPDOUBLE 0 Submit Documentation Feedback Register address bits 13-bit Reference Divider value (minimum value Rmin= 1, B[17..5] = [00 0000 0000 001]; maximum value Rmax=8191, B[17..5] = [11 1111 1111 111]; Program Charge Pump DC current, ICP 1.94mA, B[25..21] = [00 000] 0.47mA, B[25..21] = [11 111] 0.97mA, default value, , B[25..21] = [01 010] 1 = set ICP to double the current Copyright © 2010–2016, Texas Instruments Incorporated TRF372017 www.ti.com SLWS224E – AUGUST 2010 – REVISED JANUARY 2016 Table 12. Register 1 Field Descriptions (continued) REGISTER 1 NAME RESET VALUE Bit27 CAL_CLK_SEL_0 0 Bit28 CAL_CLK _SEL_1 0 Bit29 CAL_CLK _SEL_2 0 Bit30 CAL_CLK _SEL_3 1 Bit31 RSV 0 DESCRIPTION Multiplication or division factor to create VCO calibration clock from PFD frequency CAL_CLK_SEL[3..0]: Set the frequency divider value used to derive the VCO calibration clock from the phase detector frequency. Table 13. Scaling Factors CAL_CLK_SEL SCALING FACTOR 1111 1/128 1110 1/64 1101 1/32 1100 1/16 1011 1/8 1010 1/4 1001 ½ 1000 1 0110 2 0101 4 0100 8 0011 16 0010 32 0001 64 0000 128 ICP[4..0]: Set the charge pump current. Table 14. ICP and Current ICP[4..0] CURRENT (mA) 00 000 1.94 00 001 1.76 00 010 1.62 00 011 1.49 00 100 1.38 00 101 1.29 00 110 1.21 00 111 1.14 01 000 1.08 01 001 1.02 01 010 0.97 01 011 0.92 01 100 0.88 01 101 0.84 01 110 0.81 01 111 0.78 10 000 0.75 10 001 0.72 Copyright © 2010–2016, Texas Instruments Incorporated Submit Documentation Feedback 35 TRF372017 SLWS224E – AUGUST 2010 – REVISED JANUARY 2016 www.ti.com Table 14. ICP and Current (continued) ICP[4..0] CURRENT (mA) 10 010 0.69 10 011 0.67 10 100 0.65 10 101 0.63 10 110 0.61 10 111 0.59 11 000 0.57 11 001 0.55 11 010 0.54 11 011 0.52 11 100 0.51 11 101 0.5 11 110 0.48 11 111 0.47 7.5.1.1.2 Register 2 Table 15. Register 2 Bit0 Bit1 Bit2 Bit3 Register address Bit16 Bit17 Bit18 ... Bit19 Bit4 Bit20 Bit5 Bit6 Bit21 Bit22 PLL divider setting Bit7 Bit8 Bit9 Bit10 Bit11 N-Divider Value Bit12 Bit13 Bit14 Bit15 Bit23 Prescaler Select Bit24 RSV Bit25 RSV Bit28 FCO sel mode Bit29 Bit30 Cal accuracy Bit31 CAL Bit26 Bit27 VCO select Table 16. Register 2 Field Descriptions REGISTER 2 36 NAME RESET VALUE DESCRIPTION Bit0 ADDR_0 0 Bit1 ADDR_1 1 Bit2 ADDR_2 0 Bit3 ADDR_3 1 Bit4 ADDR_4 0 Bit5 NINT_0 0 Bit6 NINT_1 0 Bit7 NINT_2 0 Bit8 NINT_3 0 Bit9 NINT_4 0 Bit10 NINT_5 0 Bit11 NINT_6 0 Bit12 NINT_7 1 Bit13 NINT_8 0 Bit14 NINT_9 0 Bit15 NINT_10 0 Bit16 NINT_11 0 Bit17 NINT_12 0 Bit18 NINT_13 0 Bit19 NINT_14 0 Bit20 NINT_15 0 Submit Documentation Feedback Register address bits PLL N-divider division setting Copyright © 2010–2016, Texas Instruments Incorporated TRF372017 www.ti.com SLWS224E – AUGUST 2010 – REVISED JANUARY 2016 Table 16. Register 2 Field Descriptions (continued) REGISTER 2 NAME RESET VALUE DESCRIPTION Bit21 PLL_DIV_SEL0 1 Bit22 PLL_DIV_SEL1 0 Bit23 PRSC_SEL 1 Bit24 RSV 0 Bit25 RSV 0 Bit26 VCO_SEL_0 0 Bit27 VCO_SEL_1 1 Bit28 VCOSEL_MODE 0 Single VCO auto-calibration mode (1 = active) Bit29 CAL_ACC_0 0 Bit30 CAL_ACC_1 0 Error count during the cap array calibration Recommended programming [00] Bit31 EN_CAL 0 Select division ratio of divider in front of prescaler Set prescaler modulus (0 → 4/5; 1 → 8/9) Selects between the four integrated VCOs 00 = lowest frequency VCO; 11 = highest frequency VCO Execute a VCO frequency auto-calibration. Set to 1 to initiate a calibration. Resets automatically. PLL_DIV: Select division ratio of divider in front of prescaler. Table 17. Frequency Divider PLL DIV FREQUENCY DIVIDER 00 1 01 2 10 4 VCOSEL_MODE: When it is 1, the cap array calibration is run on the VCO selected through bits VCO_SEL. 7.5.1.1.3 Register 3 Table 18. Register 3 Bit0 Bit1 Bit2 Bit3 Register address Bit4 Bit5 Bit6 Bit16 Bit17 Bit20 Bit21 Bit22 Bit18 Bit19 Bit7 Bit8 Bit23 Bit24 Bit9 Bit10 Bit11 Bit12 Fractional N-Divider Value Bit25 Bit26 ... Bit27 Bit28 Bit13 Bit14 Bit15 Bit29 Bit30 RSV Bit31 RSV Table 19. Register 3 Field Descriptions REGISTER 3 NAME RESET VALUE Bit0 ADDR_0 1 Bit1 ADDR_1 1 Bit2 ADDR_2 0 Bit3 ADDR_3 1 Bit4 ADDR_4 0 Copyright © 2010–2016, Texas Instruments Incorporated DESCRIPTION Register address bits Submit Documentation Feedback 37 TRF372017 SLWS224E – AUGUST 2010 – REVISED JANUARY 2016 www.ti.com Table 19. Register 3 Field Descriptions (continued) REGISTER 3 NAME RESET VALUE Bit5 NFRAC 0 Bit6 NFRAC 0 Bit7 NFRAC 0 Bit8 NFRAC 0 Bit9 NFRAC 0 Bit10 NFRAC 0 Bit11 NFRAC 0 Bit12 NFRAC 0 Bit13 NFRAC 0 Bit14 NFRAC 0 Bit15 NFRAC 0 Bit16 NFRAC 0 Bit17 NFRAC 0 Bit18 NFRAC 0 Bit19 NFRAC 0 Bit20 NFRAC 0 Bit21 NFRAC 0 Bit22 NFRAC 0 Bit23 NFRAC 0 Bit24 NFRAC 0 Bit25 NFRAC 0 Bit26 NFRAC 0 Bit27 NFRAC 0 Bit28 NFRAC 0 Bit29 NFRAC 0 Bit30 RSV 0 Bit31 RSV 0 DESCRIPTION Fractional PLL N divider value 0 to 0.99999. 7.5.1.1.4 Register 4 Table 20. Register 4 Bit0 Bit16 PD DC off Bit1 Bit2 Bit3 Register address Bit4 Bit6 Bit7 Bit8 Bit9 Bit10 Bit11 Power-Down PLL blocks Bit17 EXT VCO Bit20 Bit21 Bit22 PLL Test Control Bit23 Bit24 Bit25 Bit26 Bit27 ΣΔ Mode order Bit18 Bit19 Bit5 PD PLL Bit12 Bit13 Bit14 Bit15 PD VCM Bit28 Bit29 Bit30 ΣΔ Mode controls Bit31 EN Fract mode Table 21. Register 4 Field Descriptions REGISTER 4 NAME 38 RESET VALUE DESCRIPTION Bit0 ADDR_0 0 Bit1 ADDR_1 0 Bit2 ADDR_2 1 Bit3 ADDR_3 1 Bit4 ADDR_4 0 Bit5 PWD_PLL 0 Power-down all PLL blocks (1 = off) Bit6 PWD_CP 0 When 1, charge pump is off Submit Documentation Feedback Register address bits Copyright © 2010–2016, Texas Instruments Incorporated TRF372017 www.ti.com SLWS224E – AUGUST 2010 – REVISED JANUARY 2016 Table 21. Register 4 Field Descriptions (continued) REGISTER 4 NAME RESET VALUE DESCRIPTION Bit7 PWD_VCO 0 When 1, VCO is off Bit8 PWD_VCOMUX 0 Power-down the 4 VCO mux block (1 = Off) Bit9 PWD_DIV124 0 Power-down programmable RF divider in PLL feedback path (1 = off) Bit10 PWD_PRESC 0 Power-down programmable prescaler (1 = off) Bit11 RSV 0 Bit12 PWD_OUT_BUFF 1 Power-down LO output buffer (1 = off). Bit13 PWD_LO_DIV 1 Power-down frequency divider in LO output chain 1 (1 = off) Bit14 PWD_TX_DIV 1 Power-down frequency divider in modulator chain (1 = off) Bit15 PWD_BB_VCM 1 Power-down baseband input DC common block (1 = off) Bit16 PWD_DC_OFF 1 Power-down baseband input DC offset control block (1 = off) Bit17 EN_EXTVCO 0 Enable external LO/VCO input buffer (1 = enabled) Bit18 EN_ISOURCE 0 Enable offset current at Charge Pump output (to be used in fractional mode only, 1 = on). Bit19 LD_ANA_PREC_0 0 Bit20 LD_ANA_PREC_1 0 Bit21 CP_TRISTATE_0 0 Bit22 CP_TRISTATE_1 0 Bit23 SPEEDUP 0 Speed up PLL and Tx blocks by bypassing bias stabilizer capacitors. Bit24 LD_DIG_PREC 0 Lock detector precision (increases sampling time if set to 1) Bit25 EN_DITH 1 Enable ΔΣ modulator dither (1=on) Bit26 MOD_ORD_0 0 Bit27 MOD_ORD_1 1 ΔΣ modulator order (1 through 4). Not used in integer mode. 1st order, B[27..26] = [00] 2nd order, B[27..26] = [01] 3rd order, B[27..26] = [10] 4th order, B[27..26] = [11] Bit28 DITH_SEL 0 Select dither mode for ΔΣ modulator (0 = const; 1 = pseudo-random) Bit29 DEL_SD_CLK_0 0 Bit30 DEL_SD_CLK_1 1 ΔΣ modulator clock delay. Not used in integer mode. Min delay = 00 Max delay = 11 Bit31 EN_FRAC 0 Enable fractional mode (1 = fractional enabled) Control precision of analog lock detector (1 1 = low; 0 0 = high). See Lock Detect section of Application Information for usage details. Set the charge pump output in Tristate mode. Normal, B[22..21] = [00] Down, B[22..21] = [01] Up, B[22..21] = [10] Tristate, B[22..21] = [11] 7.5.1.1.5 Register 5 Table 22. Register 5 Bit0 Bit1 Bit2 Bit3 Register address Bit16 Bit17 VCOMUX BIAS Bit18 Bit19 OUTBUF BIAS Bit4 Bit5 Bit6 Bit7 VCO_R Trim Bit20 Bit21 RSV Bit22 BIAS SEL Bit8 Bit9 PLL_R_Trim Bit23 Bit24 Bit25 VCO CAL REF Bit10 Bit11 Bit12 VCO Current Bit26 Bit27 VCOMUX AMPL Bit13 Bit28 Bit29 VCO Bias Voltage Bit14 Bit15 VCOBUF BIAS Bit30 RSV Bit31 EN_LD ISRC Table 23. Register 5 Field Descriptions REGISTER 5 NAME RESET VALUE DESCRIPTION Bit0 ADDR_0 1 Bit1 ADDR_1 0 Bit2 ADDR_2 1 Bit3 ADDR_3 1 Bit4 ADDR_4 0 Copyright © 2010–2016, Texas Instruments Incorporated Register address bits Submit Documentation Feedback 39 TRF372017 SLWS224E – AUGUST 2010 – REVISED JANUARY 2016 www.ti.com Table 23. Register 5 Field Descriptions (continued) REGISTER 5 NAME RESET VALUE DESCRIPTION Bit5 VCOBIAS_RTRIM_0 0 Bit6 VCOBIAS_RTRIM_1 0 Bit7 VCOBIAS_RTRIM_2 1 Bit8 PLLBIAS_RTRIM_0 0 Bit9 PLLBIAS_RTRIM_1 1 Bit10 VCO_BIAS_0 0 Bit11 VCO_BIAS_1 0 Bit12 VCO_BIAS_2 0 Bit13 VCO_BIAS_3 1 Bit14 VCOBUF_BIAS_0 0 Bit15 VCOBUF_BIAS_1 1 Bit16 VCOMUX_BIAS_0 0 Bit17 VCOMUX_BIAS_1 1 Bit18 BUFOUT_BIAS_0 0 Bit19 BUFOUT_BIAS_1 1 Bit20 RSV 0 Bit21 RSV 1 Bit22 VCO_CAL_IB 0 Bit23 VCO_CAL_REF_0 0 Bit24 VCO_CAL_REF_1 0 Bit25 VCO_CAL_REF_2 1 Bit26 VCO_AMPL_CTRL_0 0 Bit27 VCO_AMPL_CTRL_1 1 Bit28 VCO_VB_CTRL_0 0 Bit29 VCO_VB_CTRL _1 1 Bit30 RSV 0 Bit31 EN_LD_ISOURCE 1 VCO bias resistor trimming. Recommended programming [100]. PLL bias resistor trimming. Recommended programming [10]. VCO bias reference current. 300 µA, B[13..10] = [00 00] 600 µA, B[13..10] = [11 11] Bias current varies directly with reference current Recommended programming 400 µA, B[13..10] = [0101] with VCC_VCO2 = 3.3 V 600 µA, B[13..10] = [1111] with VCC_VCO2 = 5 V VCO buffer bias reference current. 300 µA, B[15..14] = [00] 600 µA, B[15..14] = [11] Bias current varies directly with reference current Recommended programming [10] VCO’s muxing buffer bias reference current. 300 µA, B[17..16] = [00] 600 µA, B[17..16] = [11] Bias current varies directly with reference current Recommended programming [11] PLL output buffer bias reference current. 300 µA, B[19..18] = [00] 600 µA, B[19..18] = [11] Bias current varies directly with reference current Select bias current type for VCO calibration circuitry 0 = PTAT; 1 = constant over temperature Recommended programming [0] VCO calibration reference voltage trimming. 0.9 V, B[25..23] = [000] 1.4 V, B[25..23] = [111] Recommended programming [010] Adjust the signal amplitude at the VCO mux input Recommended programming [11] VCO core bias voltage control 1.2 V, B[29..28] = [00] 1.35 V, B[29..28] = [01] 1.5 V, B[29..28] = [10] 1.65 V, B[29..28] = [11] Recommended programming [00] Enable monitoring of LD to turn on Isource when in frac-n mode (EN_FRAC=1). 0 = ISource set by EN_ISOURCE. 1 = ISource set by LD. Recommended programming [0] 7.5.1.1.6 Register 6 Table 24. Register 6 Bit0 Bit1 Bit2 Bit3 Register address Bit4 Bit5 Bit16 Bit17 Bit18 Bit19 BB DC OFFSET Bit20 Bit21 40 Submit Documentation Feedback Bit6 Bit7 Bit22 Bit23 VREF SEL Bit8 Bit9 Bit10 Bit11 BB DC OFFSET Bit24 Bit25 TXDIV SEL Bit26 Bit27 LODIV SEL Bit12 Bit13 Bit28 Bit29 TXDIV BIAS Bit14 Bit15 Bit30 Bit31 LODIV BIAS Copyright © 2010–2016, Texas Instruments Incorporated TRF372017 www.ti.com SLWS224E – AUGUST 2010 – REVISED JANUARY 2016 Table 25. Register 6 Field Descriptions REGISTER 6 NAME RESET VALUE Bit0 ADDR_0 0 Bit1 ADDR_1 1 Bit2 ADDR_2 1 Bit3 ADDR_3 1 Bit4 ADDR_4 0 Bit5 IOFF_0 0 Bit6 IOFF_1 0 Bit7 IOFF_2 0 Bit8 IOFF_3 0 Bit9 IOFF_4 0 Bit10 IOFF_5 0 Bit11 IOFF_6 0 Bit12 IOFF_7 1 Bit13 QOFF_0 0 Bit14 QOFF_1 0 Bit15 QOFF_2 0 Bit16 QOFF_3 0 Bit17 QOFF_4 0 Bit18 QOFF_5 0 Bit19 QOFF_6 0 Bit20 QOFF_7 1 Bit21 VREF_SEL_0 0 Bit22 VREF_SEL_1 0 Bit23 VREF_SEL_2 1 Bit24 TX_DIV_SEL_0 0 Bit25 TX_DIV_SEL_1 0 Bit26 LO_DIV_SEL_0 0 Bit27 LO_DIV_SEL_1 0 Bit28 TX_DIV_BIAS_0 0 Bit29 TX_DIV_BIAS_1 1 Bit30 LO_DIV_BIAS_0 0 Bit31 LO_DIV_BIAS_1 1 Copyright © 2010–2016, Texas Instruments Incorporated DESCRIPTION Register address bits Adjust Iref current used for defining I DC offset. Full range, 2 × Iref, B[12..5] = [1 1111 111] Mid scale, Iref B[12..5] = [1 0000 000] Adjust Iref current used for defining Q DC offset. Full range, 2 × Iref, B[20..13] = [1 1111 111] Mid scale, Iref B[20..13] = [1 0000 000] Adjust Vref in baseband common mode generation circuit. 0.65 V, B[23..21] = [000] 1 V, B[23..21] = [111] Modulator common mode is Vref + Vbe. Recommended programming [100] Adjust Tx path divider. Div1, [B25..24] = [00] Div2, [B25..24] = [01] Div4, [B25..24] = [10] Div8, [B25..24] = [11] Adjust LO path divider Div1, [B28..27] = [00] Div2, [B28..27] = [01] Div4, [B28..27] = [10] Div8, [B28..27] = [11] TX divider bias reference current 25 µA, [B29..28] = [00] 37.5 µA, [B29..28] = [01] 50 µA, [B29..28] = [10] 62.5 µA, [B29..28] = [11] Bias current varies directly with reference current LO divider bias reference current 25 µA, [B29..28] = [00] 37.5 µA, [B29..28] = [01] 50 µA, [B29..28] = [10] 62.5 µA, [B29..28] = [11] Bias current varies directly with reference current Submit Documentation Feedback 41 TRF372017 SLWS224E – AUGUST 2010 – REVISED JANUARY 2016 www.ti.com 7.5.1.1.7 Register 7 Table 26. Register 7 Bit0 Bit1 Bit2 Bit3 Register address Bit16 Bit17 Bit18 MUX CONTROL Bit19 ISRC SINK Bit4 Bit5 Bit6 Bit20 Bit21 Bit22 OFFSET CURRENT ADJUST Bit7 Bit8 Bit9 Bit10 VCO CAP ARRAY CONTROL Bit23 Bit24 LP PD TimeConst Bit25 VCM Bias Bit11 Bit12 Bit26 Bit27 Bit28 MIX LO VCM Bit13 RSV Bit14 VCO test mode Bit29 Bit30 DC OFF REF Bit15 CAL bypass Bit31 VCO BIAS SEL Table 27. Register 7 Field Descriptions REGISTER 7 42 NAME RESET VALUE DESCRIPTION Bit0 ADDR_0 1 Bit1 ADDR_1 1 Bit2 ADDR_2 1 Bit3 ADDR_3 1 Bit4 ADDR_4 0 Bit5 RSV 0 Bit6 RSV 0 Bit7 VCO_TRIM_0 0 Bit8 VCO_TRIM_1 0 Bit9 VCO_TRIM_2 0 Bit10 VCO_TRIM_3 0 Bit11 VCO_TRIM_4 0 Bit12 VCO_TRIM_5 1 Bit13 RSV 0 Bit14 VCO_TEST_MODE 0 Counter mode: measure max/min frequency of each VCO Bit15 CAL_BYPASS 0 Bypass of VCO auto-calibration. When 1, VCO_TRIM and VCO_SEL bits are used to select the VCO and the cap array setting Bit16 MUX_CTRL_0 1 Bit17 MUX_CTRL_1 0 Bit18 MUX_CTRL_2 0 Bit19 ISOURCE_SINK 0 Bit20 ISOURCE_TRIM_0 0 Bit21 ISOURCE_TRIM_1 0 Bit22 ISOURCE_TRIM_2 1 Bit23 PD_TC_0 0 Bit24 PD_TC_1 0 Bit25 IB_VCM_SEL 0 Bit26 RSV 0 Bit27 RSV 0 Bit28 RSV 1 Submit Documentation Feedback Register address bits VCO capacitor array control bits, used in manual cal mode Select signal for test output (pin 5, LD). [000] = Ground [001] = Lock detector [010] = NDIV counter output [011] = Ground [100] = RDIV counter output [101] = Ground [110] = A_counter output [111] = Logic high; Charge pump offset current polarity. Adjust isource bias current in frac-n mode. Time constant control for PWD_OUT_BUFF [00] = Minimum time constant [11] = Maximum time constant Select constant/ptat current for Common mode bias generation block 0 = PTAT 1 = const Copyright © 2010–2016, Texas Instruments Incorporated TRF372017 www.ti.com SLWS224E – AUGUST 2010 – REVISED JANUARY 2016 Table 27. Register 7 Field Descriptions (continued) REGISTER 7 NAME RESET VALUE DESCRIPTION Bit29 DCOFFSET_I_0 0 Bit30 DCOFFSET_I_1 1 Bit31 VCO_BIAS_SEL 0 Adjust BB input DC offset Iref 50 µA, B[27..26] = [00] 100 µA, B[27..26] = [01] 150 µA, B[27..26] = [10] 200 µA, B[27..26] = [11] Select VCO_BIAS trim settings stored in EEPROM 0 = Use EEPROM settings if parity check is 1; otherwise, use SPI settings 1 = Use SPI settings Recommended programming [1] 7.5.1.2 Readback Mode Register 0 functions as a Readback register. TRF372017 implements the capability to read-back the content of any serial programming interface register by initializing register 0. Each read-back is composed by two phases: writing followed by the actual reading of the internal data. This is shown in the timing diagram in Figure 2. During the writing phase, a command is sent to TRF372017 register 0 to set it in read-back mode and to specify which register is to be read. In the proper reading phase, at each rising clock edge, the internal data is transferred into the RDBK pin and can be read at the following falling edge (LSB first). The first clock after the LE goes high (end of writing cycle) is idle and the following 32 clocks pulses transfer the internal register content to the RDBK pin. 7.5.1.2.1 Readback From the Internal Registers Banks TRF372017 integrates 8 registers: Register 0 (000) to Register 7 (111). Registers 1 through 7 are used to set-up and control the TRF372017 functionalities, while register 0 is used for the readback function. The latter register must be programmed with a specific command that sets TRF372017 in read-back mode and specifies the register to be read: • Set B[31] to 1 to put TRF372017 in read-back mode. • Set B[30,28] equal to the address of the register to be read (000 to 111). • Set B27 to control the VCO frequency counter in VCO test mode. 7.5.1.2.1.1 Register 0 Write Table 28. Register 0 Write NAME ADDRESS BITS RESET VALUE DESCRIPTION B0 ADDR 0 B1 ADDR 0 B2 ADDR 0 B3 ADDR 1 B4 ADDR 0 Copyright © 2010–2016, Texas Instruments Incorporated Register 0 to be programmed to set TRF372017 in readback mode. Submit Documentation Feedback 43 TRF372017 SLWS224E – AUGUST 2010 – REVISED JANUARY 2016 www.ti.com Table 28. Register 0 Write (continued) NAME RESET VALUE DESCRIPTION B5 N/C 0 B6 N/C 0 B7 N/C 0 B8 N/C 0 B9 N/C 0 B10 N/C 0 B11 N/C 0 B12 N/C 0 B13 N/C 0 B14 N/C 0 B15 N/C 0 B16 N/C 0 B17 N/C 0 B18 N/C 0 DATA FIELD B19 N/C 0 B20 N/C 0 B21 N/C 0 B22 N/C 0 B23 N/C 0 B24 N/C 0 B25 N/C 0 B26 N/C 0 B27 COUNT_MODE_MUX_SEL 0 B28 RB_REG X B29 RB_REG X B30 RB_REG X B31 RB_ENABLE 1 Select Readback for VCO maximum frequency or minimum frequency. 0 = Max 1 = Min 3 LSB’s of the address for the register that is being read Reg 0, B[30..28] = [000] Reg 7, B[30..28] = [111] 1 ≥ Put the device in Readback Mode The contents of any register specified in RB_REG can be read back during the read cycle, including register 0. Bit0 Bit1 Bit2 Bit3 Register address Bit4 Bit5 CHIP_ID Bit13 Bit14 Bit15 Bit16 Bit17 Bit18 Bit19 Bit20 COUNT0-7/VCO_TRM Bit6 Bit7 Bit8 Bit9 NU Bit21 Bit22 Bit23 COUNT8-10/VCO_SEL Bit10 Bit11 Bit12 R_SAT_ERR Bit24 Bit25 Bit26 Bit27 Bit28 Bit29 Bit30 COUNT11-17 Bit31 COUNT_MODE-MUX-SEL REGISTER 0 NAME 44 RESET VALUE Bit0 ADDR_0 0 Bit1 ADDR_1 0 Bit2 ADDR_2 0 Bit3 ADDR_3 1 Bit4 ADDR_4 0 Bit5 CHIP_ID_0 1 Bit6 CHIP_ID_1 1 Bit7 NU x Submit Documentation Feedback DESCRIPTION Register address bits Copyright © 2010–2016, Texas Instruments Incorporated TRF372017 www.ti.com SLWS224E – AUGUST 2010 – REVISED JANUARY 2016 REGISTER 0 NAME RESET VALUE Bit8 NU x Bit9 NU x Bit10 NU x Bit11 NU x Bit12 R_SAT_ERR x Bit13 count_0/NU x Bit14 count_1/NU x Bit15 count_2/VCO_TRIM_0 x Bit16 count_3/VCO_TRIM_1 x Bit17 count_4/VCO_TRIM_2 x Bit18 count_5/VCO_TRIM_3 x Bit19 count_6/VCO_TRIM_4 x Bit20 count_7/VCO_TRIM_5 x Bit21 count_8/NU x Bit22 count_9/VCO_sel_0 x Bit23 count_10/VCO_sel_1 x Bit24 count x Bit25 count x Bit26 count x Bit27 count x Bit28 count x Bit29 count x Bit30 count x Bit31 COUNT_MODE_MUX_SEL x Copyright © 2010–2016, Texas Instruments Incorporated DESCRIPTION Error flag for calibration speed B[30..13] = VCO frequency counter high when COUNT_MODE_MUX_SEL = 0 and VCO_TEST_MODE = 1 B[30..13] = VCO frequency counter low when COUNT_MODE_MUX_SEL = 1 and VCO_TEST_MODE = 1 B[20..15] = Autocal results for VCO_TRIM, B[23..22] = Autocal results for VCO_SEL when VCO_TEST_MODE = 0 0 = Minimum frequency 1 = Maximum frequency Submit Documentation Feedback 45 TRF372017 SLWS224E – AUGUST 2010 – REVISED JANUARY 2016 www.ti.com 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The TRF372017 is suited for quadrature up-conversion applications such as wireless radio transmitters. 8.2 Typical Application +3.3 V FB-1K 1 mF 4.7 pF Loop Filter: values described in table R3 R4 C1 C3 C4 C2 REFIN +3.3 V 1 mF FB-1K 100 pF PS 100 pF LD Baseband interface BBQ_N described in application information BBQ_P PS RDBK VCC_DIG GND_DIG LD GND VCC_LO1 GND BBQ_N BBQ_P GND GND EXT_VCO VCC_VCO1 LO_OUT_P LO_OUT_N VCC_VCO2 GND VCC_LO2 GND BBI_N BBI_P GND GND +3.3 V EXT_VCO +3.3 V/+5.0 V FB-1K FB-1K 1 mF +3.3 V 4.7 pF 1 mF 4.7 pF FB-1K 100 pF BBI_N BBI_P 4.7 pF Baseband interface described in application information +3.3 V GND RSVD GND GND GND RFOUT GND VCC_D2S VCC_MIX GND GND GND +3.3V SCAN_EN CLK DATA LE GND REFIN GND VCC_PLL CP_OUT GND VTUNE GND 4.7 pF FB-1K 4.7 pF R2 22 pF LE DATA CLK RDBK 1.8 pF 1000 pF +3.3 V 1 mF 1.8 pF 1000 pF 1 mF NC 75 75 4.7 pF LO_OUT_P 22 pF LO_OUT_N RFOUT +5.0 V +5.0 V FB-1K 100 pF 46 Submit Documentation Feedback 4.7 pF 4.7 pF FB-1K 100 pF 4.7 pF Copyright © 2010–2016, Texas Instruments Incorporated TRF372017 www.ti.com SLWS224E – AUGUST 2010 – REVISED JANUARY 2016 Typical Application (continued) 8.2.1 Design Requirements Table 29 shows the design requirements for this application. Table 29. Quadrature Up-Converter Design Requirements for Wireless Transmitter Application PARAMETER REQUIREMENT (1) TRF372017 PERFORMANCE –5 to 0 dB –3.1 dB Gain Noise figure, NF +20 dBm +25 dBm 1dB compression (P1dB) >+10 dBm +11.5 dBm ACPR >70 dBc 75 dBc RF output frequency range 1500 to 2500 MHz 300 to 4300 MHz LO input frequency range 1000 to 3000 MHz 300 to 4800 MHz IF input frequency range LO phase noise (1) DC - 150 MHz DC - 1 GHz