TRF7970ARHBR

Product Folder Order Now Technical Documents Tools & Software Support & Community Reference Design TRF7970A ZHCS363L – AUGUST 2011 – REVISED MARCH 2017 TRF7970A 多协议全集成式 13.56MHz RFID 和近场通信 (NFC) 收发器 IC 1 器件概述 1.1 特性 1 • 支持近场通信 (NFC) 标准 NFCIP-1 (ISO/IEC 18092) 和 NFCIP‑2 (ISO/IEC 21481) • 完全集成了以下标准的协议处理：ISO/IEC 15693、 ISO/IEC 18000-3、ISO/IEC 14443 A 和 B 以及 FeliCa™ • 集成式编码器、解码器和数据组帧功能，用于 NFC 发起方运行模式以及有源和无源目标方运行模式， 适合所有三种比特率（106kbps、212kbps、 424kbps）以及卡仿真 • 借助带有可编程唤醒电平的射频场检测器，实现 NFC 无源应答器仿真 • 通过射频场检测器避免 NFC 物理碰撞 • 通过集成的状态机实现 ISO/IEC 14443 A 防撞（破 坏的字节）（应答器仿真或 NFC 无源目标） • 输入电压范围：2.7VDC 至 5.5VDC • 可编程输出功率：+20dBm (100mW)，+23dBm 1.2 • • • • 应用范围 移动器件（平板电脑、手机） 安全配对（ Bluetooth®， Wi-Fi®，其他配对无线网 络） 公共运输或者赛事票务 护照或者付费 (POS) 读取器系统 1.3 (200mW) • 从 1.8VDC 至 5.5 VDC 的可编程 I/O 电压电平 • 来自 13.56MHz 或者 27.12MHz 晶振或者振荡器的 可编程系统时钟频率输出 (RF，RF/2，RF/4) • 针对其它系统组件（微控制器 (MCU)，外设，指示 器）的集成电压稳压器输出，20mA（最大值） • 可编程调制深度 • 具有针对“读取漏洞”消除和邻近读取器系统或者周围 环境频带内噪声检测的具有接收信号强度指示器 (RSSI) 的双接收器架构 • 针对超低功耗系统设计的可编程功率模式（断电时 < 1µA） • 并行或 SPI 接口（带有 127 字节 FIFO） • 温度范围：-40°C 至 110°C • 32 引脚 QFN 封装 (5mm × 5mm) • • • • • 近程无线通信任务（固件升级） 产品识别或者认证 医疗设备或者消耗品 访问控制、数字门锁 电子业务卡共享 说明 TRF7970A 器件是一款用于 13.56MHz NFC/RFID 系统的集成式模拟前端 (AFE) 和多协议数据组帧器件， 支持所有的三种 NFC 工作模式：读/写器模式、对等模式和卡仿真模式，符合 ISO/IEC 14443 A 和 B、 Sony FeliCa、ISO/IEC 15693、NFCIP-1 (ISO/IEC 18092) 和 NFCIP-2 (ISO/IEC 21481) 等标准。该器件具 有内置的编程选项，因此适合于 NFC、接近和邻近识别系统的广泛 应用 。 通过在控制寄存器内选择所需的协议可对此器件进行配置。通过对所有控制寄存器进行直接存取，可根据需 要对不同的读取器参数进行微调。 TRF7970A 器件针对所有符合板载 ISO 协议的组帧和同步任务，支持高达 848kbps 的数据速率。 TRF7970A 器件还支持 NFC 论坛标签类型 1、2、3、4 和 5 的读写器模式。可通过使用该器件提供的直接 模式之一来实现其他标准甚至自定义协议。这些直接模式可让用户完全控制 AFE，并且还可以访问原始子载 波数据或者未组帧但已经是 ISO 格式的数据和相关（提取的）时钟信号。 接收器系统具有双输入接收器架构，可最大程度实现通信稳定。接收器还包括多种自动和手动增益控制选 项。在 RSSI 寄存器中可获取从应答器、周围信号源或者内部电平接收到的信号强度。 可使用 SPI 或并行接口进行 MCU 和 TRF7970A 器件间的通信。当使用内置的硬件编码器和解码器时，发 送和接收功能使用一个 127 字节的 FIFO 寄存器。对于直接发送或接收功能，由于编码器或解码器可被旁路 绕开，所以 MCU 可实时地处理数据。 TRF7970A 器件支持 2.7V 至 5.5V 的宽电源电压范围以及 MCU I/O 接口的 1.8V 至 5.5V 数据通信电平。 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. English Data Sheet: SLOS743 TRF7970A ZHCS363L – AUGUST 2011 – REVISED MARCH 2017 www.ti.com.cn 当使用 5V 电源时，发送器对于 50Ω 负载具有 100mW (+20dBm) 或 200mW (+23dBm) 等效值的可选输出 功率电平，并支持可选调制深度的 OOK 和 ASK 调制。 内置的可编程辅助稳压器为 MCU 和读取器系统内的其他外部电路提供高达 20mA 的电源。 通过具有可编程唤醒电平、八种可选电源模式以及超低功耗运行模式的集成射频场检测器，可以轻松开发可 靠、经济高效且电池寿命长的设计。 要评估 TRF7970A 多协议收发器 IC，可使用TRF7970AEVM、TRF7970ATB 或 DLP-7970ABP。 器件信息 器件型号 TRF7970ARHB 1.4 封装 封装尺寸 VQFN (32) 5mm x 5mm 功能方框图 图 1-1 显示了方框图。 VDD_I/O MUX RX_IN1 Phase and Amplitude Detector Gain RSSI (AUX) RF Level Detector RX_IN2 RSSI (External) Filter and AGC Digitizer ISO Protocol Handling Transmitter Analog Front End I/O_1 (Control Registers and Command Logic) I/O_3 Gain VDD_PA TX_OUT I/O_0 State Control Logic MCU Interface Bit Framing 127-Byte FIFO I/O_5 I/O_6 I/O_7 SYS_CLK DATA_CLK VIN Serial Conversion CRC and Parity VSS_PA I/O_4 IRQ Decoder Framing I/O_2 Level Shifter Phase and Amplitude Detector RSSI (Main) Logic VDD_A BAND_GAP EN EN2 ASK/OOK VSS_A Digital Control State Machine MOD VDD_RF Voltage Supply Regulator Systems (Supply Regulators and Reference Voltages) VSS_RF VDD_X OSC_IN OSC_OUT VSS Crystal or Oscillator Timing System VSS_D Copyright © 2017, Texas Instruments Incorporated 图 1-1. 方框图 2 器件概述 版权 © 2011–2017, Texas Instruments Incorporated TRF7970A www.ti.com.cn ZHCS363L – AUGUST 2011 – REVISED MARCH 2017 内容 1 器件概述 .................................................... 1 6 6.10 TRF7970A IC Communication Interface ............ 30 功能方框图 ............................................ 2 6.11 6.12 TRF7970A Initialization ............................. 48 Special Direct Mode for Improved MIFARE™ Compatibility ......................................... 49 6.13 NFC Modes.......................................... 49 6.14 Direct Commands from MCU to Reader ............ 51 6.15 Register Description ................................. 55 应用范围 .............................................. 1 1.3 修订历史记录............................................... 4 Device Characteristics .................................. 6 Related Products ..................................... 6 Terminal Configuration and Functions .............. 7 .......................................... 7 4.2 Signal Descriptions ................................... 7 Specifications ............................................ 9 5.1 Absolute Maximum Ratings .......................... 9 5.2 ESD Ratings .......................................... 9 5.3 Recommended Operating Conditions ................ 9 5.4 Electrical Characteristics ............................ 10 5.5 Thermal Resistance Characteristics ................ 11 5.6 Switching Characteristics ........................... 11 Detailed Description ................................... 12 6.1 Overview ............................................ 12 6.2 System Block Diagram .............................. 15 6.3 Power Supplies ...................................... 15 6.4 Receiver – Analog Section .......................... 21 6.5 Receiver – Digital Section ........................... 22 6.6 Oscillator Section ................................... 27 6.7 Transmitter – Analog Section ....................... 28 4.1 5 说明 ................................................... 1 1.2 3.1 4 Transmitter – Digital Section ........................ 29 Transmitter – External Power Amplifier and Subcarrier Detector ................................. 30 特性 ................................................... 1 1.4 2 3 6.8 6.9 1.1 Pin Diagram 版权 © 2011–2017, Texas Instruments Incorporated 7 Applications, Implementation, and Layout........ 75 7.1 8 9 TRF7970A Reader System Using SPI With SS Mode ................................................ 75 .............................. ...... 7.4 Reader Antenna Design Guidelines ................ 器件和文档支持 .......................................... 8.1 入门和下一步 ........................................ 8.2 器件命名规则 ........................................ 8.3 工具与软件 .......................................... 8.4 文档支持 ............................................. 8.5 社区资源 ............................................. 8.6 商标.................................................. 8.7 静电放电警告 ........................................ 8.8 Glossary ............................................. 机械、封装和可订购信息................................ 7.2 Layout Considerations 76 7.3 Impedance Matching TX_Out (Pin 5) to 50 Ω 76 内容 77 78 78 78 79 79 80 80 80 80 81 3 TRF7970A ZHCS363L – AUGUST 2011 – REVISED MARCH 2017 www.ti.com.cn 2 修订历史记录 注：之前版本的页码可能与当前版本有所不同。 Changes from April 18, 2014 to March 27, 2017 • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • 4 Page 通篇更正了 ISO/IEC 标准代号；例如，将 ISO14443 更改为 ISO/IEC 14443 ................................................ 1 更改了以下部分的内容：节 1.3 - 说明 ............................................................................................. 1 Added Section 3.1, Related Products ............................................................................................. 6 Moved TSTG from Section 5.2 to Section 5.1, Absolute Maximum Ratings ................................................... 9 Moved Section 5.2 and changed title from Handling Ratings to ESD Ratings ............................................... 9 Added VOL and VOH to Section 5.4, Electrical Characteristics ................................................................ 10 Changed the TYP value of the fD_CLKmax parameter from 8 to 4 MHz in Section 5.4, Electrical Characteristics ....... 10 Throughout document, removed support for application control of Automatic Gain Control (AGC) and Receiver Gain Adjust, because these features were designed for test functionality and not for production use .................. 12 Added NFC Type 5 tags to supported list in Section 6.1.1, RFID and NFC Operation – Reader and Writer ........... 12 Removed the paragraph that started "The desired system of operation (bit rate) is achieved by..." from Section 6.1.2, NFC Device Operation – Initiator ................................................................................ 13 Removed the paragraph that started "The desired system of operation (bit rate) is achieved by..." from Section 6.1.3, NFC Device Operation – Target ................................................................................. 13 Throughout document, changed "tag" emulation or emulator to "card" emulation or emulator ........................... 13 Added the sentence that starts "For interoperability purposes, TI recommends..." in the first bulleted list item in Section 6.1.3, NFC Device Operation – Target ................................................................................. 14 Changed POLLING to SENSF_REQ in the bulleted list item that starts "If the first command is a SENSF_REQ..." and deleted the sentence that started "The POLLING response is sent in..." in Section 6.1.3, NFC Device Operation – Target................................................................................................... 14 Updated the bulleted list item that starts "If the first command is ATR_REQ..." in Section 6.1.3, NFC Device Operation – Target ................................................................................................................. 14 Changed "coded as ISO14443" to "SENSB_REQ" in the bulleted list item that starts "If the first command is a SENSB_REQ..." in Section 6.1.3, NFC Device Operation – Target .......................................................... 14 Changed "FeliCa" to "peer-to-peer" in Section 6.1.3.1, Active Target, and Section 6.1.3.2, Passive Target ........... 14 Updated the paragraph that starts "The transmission of a response must occur after RF collision avoidance..." in Section 6.1.3.1, Active Target .................................................................................................... 14 Updated the paragraph that starts "The transmit system in passive target mode..." in Section 6.1.3.2, Passive Target ................................................................................................................................. 14 Updated the description in Section 6.1.3.3, Card Emulation .................................................................. 15 Added the sentence that starts "For applications in which the TRF7970A may be subjected..." in the second paragraph of 节 6.3, Power Supplies ............................................................................................. 15 Changed VDD_A to VDD_X in the last sentence that reads "The VDD_X output current should not exceed 20 mA." in the NOTE in Analog Supply Regulator: VDD_A ................................................................................... 16 Removed the paragraph that started "The RF power amplifier regulator..." from Digital Supply Regulator: VDD_X .... 16 Changed 250 mV to 400 mV in "...a "Delta Voltage" of 400 mV below VIN..." .............................................. 16 Added the paragraph that starts "As VDD_RF is increased, the system..." in 节 6.3.2, Supply Regulator Settings ..... 18 Removed the paragraphs that started "The main receiver also has..." and "By default, the AGC window comparator..." from 节 6.4.2, Receiver Gain and Filter Stages ............................................................... 21 Changed 表 6-5 to match 表 6-37 ................................................................................................. 22 Updated 节 6.5, Receiver – Digital Section, to clarify and remove duplicate content ...................................... 22 Updated the description in 节 6.5.1.2, External RSSI .......................................................................... 26 Removed "Equivalent Series Resistance" from 表 6-9, Minimum Crystal Recommendations ............................ 28 Removed mention of 3-wire SPI and replaced "IRQ" with "Slave Select" in the first paragraph of 节 6.10.1, General Introduction ................................................................................................................ 30 Updated the description of FIFO level interrupts in 节 6.10.1.4, FIFO Operation .......................................... 34 Added "but recommended" to "It is optional but recommended to read the FIFO Status register..." in 节 6.10.3, Reception of Air Interface Data .................................................................................................... 36 Changed the title of 节 6.10.4, Data Transmission From MCU to TRF7970A .............................................. 37 Removed the sentence that started "The choice of one of these modes over another..." from 节 6.10.5, Serial Interface Communication (SPI) .................................................................................................... 37 Updated the paragraph that starts "TI recommends resetting the FIFO after receiving data..." in 节 6.10.5.1, Serial Interface Mode With Slave Select (SS) ................................................................................... 42 Added the NOTE that starts "An additional direct mode..." in 节 6.10.6, Direct Mode ..................................... 43 修订历史记录 版权 © 2011–2017, Texas Instruments Incorporated TRF7970A www.ti.com • • • • • • • • • • • • • • • • • • • • • • ZHCS363L – AUGUST 2011 – REVISED MARCH 2017 Added 节 6.11, TRF7970A Initialization ......................................................................................... Changed the application report that is referenced in 节 6.12, Special Direct Mode for Improved MIFARE™ Compatibility ......................................................................................................................... Changed POLLING to SENSF_REQ and updated description in the list item that starts "If the first command is a SENSF_REQ..." ..................................................................................................................... Updated the description in the list item that starts "If the first command is ATR_REQ..." ................................. Corrected description of B1 Irq_col in 表 6-18, IRQ Status Register (0x0C) for NFC and Card Emulation Operation: changed from "(as defined in register 0x01)" to "(as defined in register 0x10)" .............................. Removed mention of collision avoidance commands from 节 6.13.2, Initiator .............................................. Added and updated comments in 表 6-19, Address and Command Word Bit Distribution ................................ Removed command code 0x15, Close Slot Sequence, from 表 6-19, Address and Command Word Bit Distribution .......................................................................................................................... Added the sentence that starts "This command should be sent after a Software Initialization command..." in 节 6.14.1.1, Idle (0x00) ................................................................................................................ Changed the description in 节 6.14.1.3, Initial RF Collision Avoidance (0x04) ............................................. Changed the description in 节 6.14.1.4, Response RF Collision Avoidance (0x05) ....................................... Changed the description in 节 6.14.1.5, Response RF Collision Avoidance (0x06, n = 0) ................................ Added "This is used by the ISO/IEC 15693 protocol" to 节 6.14.1.11, Transmit Next Time Slot (0x14) ................ Corrected description of B1 Irq_col in 表 6-43, IRQ Status Register (0x0C): changed from "(as defined in register 0x01)" to "(as defined in register 0x10)" ............................................................................... Changed the description of B5:B3 in 表 6-47 from "...Auxiliary RSSI represents the signal level at RX_IN2" to "...Auxiliary RSSI represents the signal level at RX_IN1" ...................................................................... Removed former Section 7.1, TRF7970A Reader System Using Parallel Microcontroller Interface ..................... Changed 图 7-1, Application Schematic – SPI With SS Mode MCU Interface ............................................. Updated the description in 节 7.1.2, Schematic ................................................................................. 添加了节 8.1“入门和后续步骤” ..................................................................................................... 添加了节 8.2“器件命名规则” ....................................................................................................... 添加了节 8.3“工具和软件” .......................................................................................................... 更新了节 8.4“文档支持” ............................................................................................................. 修订历史记录 Copyright © 2011–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TRF7970A 48 49 50 50 51 51 51 51 52 53 53 53 54 66 68 75 75 75 78 78 79 79 5 TRF7970A ZHCS363L – AUGUST 2011 – REVISED MARCH 2017 www.ti.com 3 Device Characteristics Table 3-1 lists the supported modes of operation for the TRF7970A device. Table 3-1. Supported Modes of Operation P2P INITIATOR OR READER/WRITER TECHNOLOGY BIT RATE (kbps) NFC-A and NFC-B (ISO/IEC 14443 A and B) (1) 3.1 CARD EMULATION P2P TARGET TECHNOLOGY BIT RATE (kbps) TECHNOLOGY BIT RATE (kbps) 106, 212, 424, 848 (1) NFC-A, NFC-B 106 NFC-A 106 NFC-F (JIS: X6319-4) 212, 424 N/A N/A NFC-F 212, 424 NFC-V (ISO/IEC 15693) 6.7, 26.7 N/A N/A N/A N/A 848 kbps applies to reader/writer mode only. Related Products For information about other devices in this family of products or related products, see the following links. Products for TI Wireless Connectivity Connect more with the industry’s broadest wireless connectivity portfolio. Products for NFC / RFID TI provides one of the industry’s most differentiated NFC and RFID product portfolios and is your solution to meet a broad range of NFC connectivity and RFID identification needs. Companion Products for TRF7970A Review products that are frequently purchased or used with this product. Reference Designs for TRF7970A The TI Designs Reference Design Library is a robust reference design library that spans analog, embedded processor, and connectivity. Created by TI experts to help you jump start your system design, all TI Designs include schematic or block diagrams, BOMs, and design files to speed your time to market. Search and download designs at ti.com/tidesigns. 6 Device Characteristics Copyright © 2011–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TRF7970A TRF7970A www.ti.com ZHCS363L – AUGUST 2011 – REVISED MARCH 2017 4 Terminal Configuration and Functions 4.1 Pin Diagram Figure 4-1 shows the pinout for the 32-pin RHB package. VDD_X OSC_IN OSC_OUT VSS_D EN SYS_CLK DATA_CLK EN2 32 31 30 29 28 27 26 25 VDD_A 1 24 I/O_7 VIN 2 23 I/O_6 VDD_RF 3 22 I/O_5 VDD_PA 4 21 I/O_4 TX_OUT 5 20 I/O_3 VSS_PA 6 19 I/O_2 VSS_RX 7 18 I/O_1 RX_IN1 8 17 I/O_0 Pad 11 12 13 14 RX_IN2 VSS BG ASK/OOK IRQ MOD 15 16 VDD_I/O 10 VSS_A 9 Figure 4-1. 32-Pin RHB Package (Top View) 4.2 Signal Descriptions Table 4-1 describes the signals. Table 4-1. Terminal Functions TERMINAL NAME NO. VDD_A 1 VIN VDD_RF TYPE (1) DESCRIPTION OUT Internal regulated supply (2.7 V to 3.4 V) for analog circuitry 2 SUP External supply input to chip (2.7 V to 5.5 V) 3 OUT Internal regulated supply (2.7 V to 5 V), normally connected to VDD_PA (pin 4) VDD_PA 4 INP Supply for PA; normally connected externally to VDD_RF (pin 3) TX_OUT 5 OUT RF output (selectable output power, 100 mW or 200 mW, with VDD = 5 V) VSS_PA 6 SUP Negative supply for PA; normally connected to circuit ground VSS_RX 7 SUP Negative supply for RX inputs; normally connected to circuit ground RX_IN1 8 INP Main RX input RX_IN2 9 INP Auxiliary RX input VSS 10 SUP Chip substrate ground BAND_GAP 11 OUT Bandgap voltage (VBG = 1.6 V); internal analog voltage reference ASK/OOK 12 BID (1) Selection between ASK and OOK modulation (0 = ASK, 1 = OOK) for direct mode 0 or 1. Can be configured as an output to provide the received analog signal output. SUP = Supply, INP = Input, BID = Bidirectional, OUT = Output Terminal Configuration and Functions Copyright © 2011–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TRF7970A 7 TRF7970A ZHCS363L – AUGUST 2011 – REVISED MARCH 2017 www.ti.com Table 4-1. Terminal Functions (continued) TERMINAL NAME IRQ NO. 13 TYPE (1) DESCRIPTION OUT Interrupt request INP External data modulation input for direct mode 0 or 1 OUT Subcarrier digital data output (see registers 0x1A and 0x1B) MOD 14 VSS_A 15 SUP Negative supply for internal analog circuits; connected to GND VDD_I/O 16 INP Supply for I/O communications (1.8 V to VIN) level shifter. VIN should be never exceeded. I/O_0 17 BID I/O pin for parallel communication I/O_1 18 BID I/O pin for parallel communication I/O_2 19 BID I/O_3 20 BID I/O_4 21 BID I/O_5 22 BID I/O pin for parallel communication TX enable (in special direct mode) I/O pin for parallel communication TX data (in special direct mode) I/O pin for parallel communication Slave select signal in SPI mode I/O pin for parallel communication Data clock output in direct mode 1 and special direct mode I/O pin for parallel communication I/O_6 23 BID MISO for serial communication (SPI) Serial bit data output in direct mode 1 or subcarrier signal in direct mode 0 I/O pin for parallel communication. I/O_7 24 BID EN2 25 INP Selection of power down mode. If EN2 is connected to VIN, then VDD_X is active during power down mode 2 (for example, to supply the MCU). DATA_CLK 26 INP Data clock input for MCU communication (parallel and serial) OUT If EN = 1 (EN2 = don't care) the system clock for MCU is configured. Depending on the crystal that is used, options are as follows (see register 0x09): 13.56-MHz crystal: Off, 3.39 MHz, 6.78 MHz, or 13.56 MHz 27.12-MHz crystal: Off, 6.78 MHz, 13.56 MHz, or 27.12 MHz SYS_CLK 27 MOSI for serial communication (SPI) If EN = 0 and EN2 = 1, then system clock is set to 60 kHz EN 28 INP Chip enable input (If EN = 0, then chip is in sleep or power-down mode). VSS_D 29 SUP Negative supply for internal digital circuits OSC_OUT 30 OUT Crystal or oscillator output OSC_IN 31 VDD_X Thermal Pad 8 INP Crystal or oscillator input OUT Crystal oscillator output 32 OUT Internally regulated supply (2.7 V to 3.4 V) for digital circuit and external devices (for example, an MCU) PAD SUP Chip substrate ground Terminal Configuration and Functions Copyright © 2011–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TRF7970A TRF7970A www.ti.com ZHCS363L – AUGUST 2011 – REVISED MARCH 2017 5 Specifications Absolute Maximum Ratings (1) 5.1 (2) over operating free-air temperature range (unless otherwise noted) VIN Input voltage range IIN Maximum current VIN TJ Maximum operating virtual junction temperature TSTG Storage temperature (1) (2) (3) 5.3 6 UNIT V 150 mA Any condition 140 °C Continuous operation, long-term reliability (3) 125 °C 150 °C –55 ESD Ratings V(ESD) (2) MAX Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions are not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to substrate ground terminal VSS. The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may result in reduced reliability or lifetime of the device. 5.2 (1) MIN –0.3 Electrostatic discharge VALUE UNIT Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) ±2000 V Charged-device model (CDM), per JEDEC specification JESD22-C101, all pins (2) ±500 V Machine model (MM) ±200 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ±2000 V may actually have higher performance. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±500 V may actually have higher performance. Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN TYP MAX UNIT VIN Operating input voltage 2.7 5 5.5 V TA Operating ambient temperature –40 25 110 °C TJ Operating virtual junction temperature –40 25 125 °C VIL Input voltage, logic low I/O lines, IRQ, SYS_CLK, DATA_CLK, EN, EN2, ASK/OOK, MOD VIH Input voltage threshold, logic high I/O lines, IRQ, SYS_CLK, DATA_CLK, EN, EN2, ASK/OOK, MOD 0.2 × VDD_I/O 0.8 × VDD_I/O V Specifications Copyright © 2011–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TRF7970A V 9 TRF7970A ZHCS363L – AUGUST 2011 – REVISED MARCH 2017 5.4 www.ti.com Electrical Characteristics TYP operating conditions are TA = 25°C, VIN = 5 V, full-power mode (unless otherwise noted) MIN and MAX operating conditions are over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 0.2 × UNIT VOL Low-level output voltage V VOH High-level output voltage IPD1 Supply current in power down mode 1 All building blocks disabled, including supply-voltage regulators; measured after 500-ms settling time (EN = 0, EN2 = 0) 0.5 5 µA IPD2 Supply current in power down mode 2 (sleep mode) The SYS_CLK generator and VDD_X remain active to support external circuitry; measured after 100-ms settling time (EN = 0, EN2 = 1) 120 200 µA ISTBY Supply current in stand-by mode Oscillator running, supply-voltage regulators in low-consumption mode (EN = 1, EN2 = x) 1.9 3.5 mA ION1 Supply current without antenna driver current Oscillator, regulators, RX and AGC active, TX is off 10.5 14 mA ION2 Supply current, TX (half power) Oscillator, regulators, RX and AGC and TX active, POUT = 100 mW 70 78 mA ION3 Supply current, TX (full power) Oscillator, regulators, RX and AGC and TX active, POUT = 200 mW 130 150 mA VPOR Power-on-reset voltage Input voltage at VIN 1.4 2 2.6 V VBG Bandgap voltage (pin 11) Internal analog reference voltage 1.5 1.6 1.7 V VDD_A Regulated output voltage for analog circuitry (pin 1) VIN = 5 V 3.1 3.4 3.8 V VDD_X Regulated supply for external circuitry Output voltage pin 32, VIN = 5 V 3.1 3.4 3.8 V IVDD_Xmax Maximum output current of VDD_X Output current pin 32, VIN = 5 V 20 mA RRFOUT Antenna driver output resistance RRFIN RX_IN1 and RX_IN2 input resistance VRF_INmax Maximum RF input voltage at RX_IN1 and RX_IN2 VRF_INmin VDD_I/O 0.8 × VDD_I/O (1) V Half-power mode, VIN = 2.7 V to 5.5 V 8 12 Full-power mode, VIN = 2.7 V to 5.5 V 4 6 10 20 4 VRF_INmax should not exceed VIN 3.5 Minimum RF input voltage at RX_IN1 and RX_IN2 (input sensitivity) (2) fSUBCARRIER = 424 kHz 1.4 2.5 fSUBCARRIER = 848 kHz 2.1 3 fSYS_CLK SYS_CLK frequency In power mode 2, EN = 0, EN2 = 1 60 120 fC Carrier frequency Defined by external crystal tCRYSTAL Crystal run-in time Time until oscillator stable bit is set (register 0x0F) (3) fD_CLKmax Maximum DATA_CLK frequency (4) Depends on capacitive load on the I/O lines, TI recommends 2 MHz (4) ROUT RSYS_CLK (1) (2) (3) (4) 10 25 kΩ Vpp 13.56 mVpp kHz MHz 3 2 Ω ms 4 10 MHz Output resistance I/O_0 to I/O_7 500 800 Ω Output resistance RSYS_CLK 200 400 Ω Antenna driver output resistance Measured with subcarrier signal at RX_IN1 or RX_IN2 and measured the digital output at MOD pin with register 0x1A bit 6 = 1. Depends on the crystal parameters and components TI recommends a DATA_CLK speed of 2 MHz. Higher data clock depends on the capacitive load. Maximum SPI clock speed should not exceed 10 MHz. This clock speed is acceptable only when external capacitive load is less than 30 pF. MISO driver has a typical output resistance of 400 Ω (12-ns time constant when 30-pF load used). Specifications Copyright © 2011–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TRF7970A TRF7970A www.ti.com 5.5 (1) (2) ZHCS363L – AUGUST 2011 – REVISED MARCH 2017 Thermal Resistance Characteristics PACKAGE θJC θJA (1) RHB (32 pin) 31°C/W 36.4°C/W POWER RATING (2) TA ≤ 25°C TA ≤ 85°C 2.7 W 1.1 W This data was taken using the JEDEC standard high-K test PCB. Power rating is determined with a junction temperature of 125°C. This is the temperature at which distortion starts to increase substantially. Thermal management of the final PCB should strive to keep the junction temperature at or below 125°C for best performance and long-term reliability. 5.6 Switching Characteristics TYP operating conditions are TA = 25°C, VIN = 5 V, full-power mode (unless otherwise noted) MIN and MAX operating conditions are over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX Depends on capacitive load on the I/O lines (1) 250 62.5 50 UNIT tLO/HI DATA_CLK time high or low, one half of DATA_CLK at 50% duty cycle tSTE,LEAD Slave select lead time, slave select low to clock 200 ns tSTE,LAG Slave select lag time, last clock to slave select high 200 ns tSTE,DIS Slave select disable time, slave select rising edge to next slave select falling edge tSU,SI ns 300 ns MOSI input data setup time 15 ns tHD,SI MOSI input data hold time 15 ns tSU,SO MISO input data setup time 15 ns tHD,SO MISO input data hold time 15 ns tVALID,SO MISO output data valid time (1) DATA_CLK edge to MISO valid, CL ≤ 30 pF 30 50 75 ns TI recommends a DATA_CLK speed of 2 MHz. Higher data clock depends on the capacitive load. Maximum SPI clock speed should not exceed 10 MHz. This clock speed is acceptable only when external capacitive load is less than 30 pF. MISO driver has a typical output resistance of 400 Ω (12-ns time constant when 30-pF load used). Specifications Copyright © 2011–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TRF7970A 11 TRF7970A ZHCS363L – AUGUST 2011 – REVISED MARCH 2017 www.ti.com 6 Detailed Description 6.1 6.1.1 Overview RFID and NFC Operation – Reader and Writer The TRF7970A is a high-performance 13.56-MHz HF RFID and NFC transceiver IC composed of an integrated analog front end (AFE) and a built-in data framing engine for ISO/IEC 15693, ISO/IEC 14443 A and B, and FeliCa. This includes data rates up to 848 kbps for ISO/IEC 14443 with all framing and synchronization tasks on board (in default mode). The TRF7970A also supports NFC tag type 1, 2, 3, 4, and 5 operations. This architecture lets the customer build a complete cost-effective yet high-performance multiprotocol 13.56-MHz RFID and NFC system together with a low-cost microcontroller. Other standards and even custom protocols can be implemented by using either of the direct modes that the device offers. These direct modes (0 and 1) allow the user to fully control the analog front end (AFE) and also gain access to the raw subcarrier data or the unframed but already ISO formatted data and the associated (extracted) clock signal. The receiver system has a dual input receiver architecture. The receivers also include various automatic and manual gain control options. The received input bandwidth can be selected to cover a broad range of input subcarrier signal options. The received signal strength from transponders, ambient sources, or internal levels is available through the RSSI register. The receiver output is selectable among a digitized subcarrier signal and any of the integrated subcarrier decoders. The selected subcarrier decoder delivers the data bit stream and the data clock as outputs. The TRF7970A also includes a receiver framing engine. This receiver framing engine performs the CRC or parity check, removes the EOF and SOF settings, and organizes the data in bytes for ISO/IEC 14443 A and B, ISO/IEC 15693, and FeliCa protocols. Framed data is then accessible to the microcontroller (MCU) through a 127-byte FIFO register. VDD VDD_X VDD VDD_I/O TX_OUT Matching TRF7970A RX_IN 1 RX_IN2 VSS Crystal 13.56 MHz MCU (MSP430 or ARM) Parallel or SPI VIN XIN Supply: 2.7 V to 5.5 V Figure 6-1. Application Block Diagram A parallel or serial interface (SPI) can be used for the communication between the MCU and the TRF7970A reader. When the built-in hardware encoders and decoders are used, transmit and receive functions use a 127-byte FIFO register. For direct transmit or receive functions, the encoders and decoders can be bypassed so that the MCU can process the data in real time. The TRF7970A supports data communication voltage levels from 1.8 V to 5.5 V for the MCU I/O interface. The transmitter has selectable output-power levels of 100 mW (+20 dBm) or 200 mW (+23 dBm) equivalent into a 50-Ω load when using a 5-V supply. 12 Detailed Description Copyright © 2011–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TRF7970A TRF7970A www.ti.com ZHCS363L – AUGUST 2011 – REVISED MARCH 2017 The transmitter supports OOK and ASK modulation with selectable modulation depth. The TRF7970A also includes a data transmission engine that comprises low-level encoding for ISO/IEC 15693, ISO/IEC 14443 A and B, and FeliCa. Included with the transmit data coding is the automatic generation of Start Of Frame (SOF), End Of Frame (EOF), Cyclic Redundancy Check (CRC), and parity bits. Several integrated voltage regulators ensure a proper power-supply noise rejection for the complete reader system. The built-in programmable auxiliary voltage regulator VDD_X (pin 32), is able to deliver up to 20 mA to supply a microcontroller and additional external circuits within the reader system. 6.1.2 NFC Device Operation – Initiator The transmitting system includes an RF level detector (programmable level) which is used for initial (or response) RF collision avoidance. The RF collision avoidance sequence is started by sending a direct command. If successful, the NFC initiator can send the data or commands, the MCU has loaded in the FIFO register. The coding of this data is done by hardware coders in ISO/IEC 14443 A and B, or FeliCa format. The coders also provide CRC and parity bits (if required) and automatically add preambles, SOF, EOF, and synchronization bytes as defined by selected protocol. The receiver system offers the same analog features (AGC, AM or PM, bandwidth selection, and so on) as described previously in RFID and NFC reader and writer description. The system comprises integrated decoders for passive targets (ISO/IEC 14443 A or ISO/IEC 14443 B tag or FeliCa) or active targets (ISO/IEC 14443 A or ISO/IEC 14443 B reader or FeliCa). For all this options, the system also supports framing including CRC and parity check and removal of SOF, EOF, and synchronization bytes as specified by the selected protocol. 6.1.3 NFC Device Operation – Target The activation of NFC target is done when a sufficient RF field level is detected on the antenna. The level needed for wake-up is selectable and is stored in a nonvolatile register. When the activation occurs, the system performs automatic power-up and waits for the first command to be received. Based on this command, the system knows if it should operate as passive or active target and at what bit rate. After activation, the receiver system offers the same analog features (for example, AGC, AM/PM, and bandwidth selection) as in the case of an RFID reader. When used as the NFC target, the chip is typically in a power down or standby mode. If EN2 = H, the chip keeps the supply system on. If EN2 = L and EN = L, the chip is in complete power down. To operate as NFC target or card emulator, the MCU must load a value different from zero (0) in the Target Detection Level register (B0-B2) to enable the RF measurement system (supplied by VEXT, so it can also operate during complete power down and consume only 3.5 µA). The RF measurement constantly monitors the RF signal on the antenna input. When the RF level on the antenna input exceeds the level defined in the in Target Detection Level register, the chip is automatically activated (EN is internally forced high). When the voltage supply system and the oscillator are started and are stable, osc_ok goes high (B6 of RSSI Level and Oscillator Status register) and IRQ is sent with bit B2 = 1 of IRQ register (field change). Bit B7 NFC Target Protocol in register directly displays the status of RF level detection (running constantly also during normal operation). This informs the MCU that the chip should start operation as NFC TARGET device. When the first command from the INITIATOR is received, another IRQ sent with B6 (RX start) set in the IRQ register. The MCU must set EN = H (confirm the power up) in the time between the two IRQs, because the internal power-up ends after the second IRQ. The type and coding of the first initiator (or reader in the case of a card emulator) command defines the communication protocol type that the target must use. Therefore, the communication protocol type is available in the NFC Target Protocol register immediately after receiving the first command. Detailed Description Copyright © 2011–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TRF7970A 13 TRF7970A ZHCS363L – AUGUST 2011 – REVISED MARCH 2017 www.ti.com.cn Based on the first command from the INITIATOR, the following actions are taken: • If the first command is SENS_REQ or ALL_REQ, the TARGET must enter the SDD protocol for 106kbps passive communication to begin; afterward, the baud rate can be changed to 212 kbps or 424 kbps, which is determined by the NFC initiator device. If bit B5 in the NFC Target Detection Level register is not set, the MCU handles the SDD and the command received is send to FIFO. For interoperability purposes, TI recommends allowing the MCU to handle the SDD process rather than use the TRF7970A Auto-SDD feature to ensure interoperability with other NFC devices. If the RF field is turned off (B7 in NFC Target Protocol register is low) at any time, the system sends an IRQ to the MCU with bit B2 (RF field change) in the IRQ register set high. This informs the MCU that the procedure was aborted and the system must be reset. The clock extractor is automatically activated in this mode. • If the command is SENS_REQ or ALL_REQ and the card emulation bit in ISO Control register is set, the system emulates an ISO/IEC 14443 A or ISO/IEC 14443 B tag. The procedure does not differ from the one previously described for the case of a passive target at 106 kbps. The clock extractor is automatically activated in this mode. • If the first command is a SENSF_REQ, the system becomes the TARGET in passive communication using 212 kbps or 424 kbps. The SDD is relatively simple and is handled by the MCU directly. • If the first command is ATR_REQ, the system operates as an active TARGET using the same communication speed and bit coding as used by the INITIATOR. Again, all of the replies are handled by the MCU. The MCU should handle the timing requirements for collision avoidance. This is done by using external RSSI to detect external RF fields before enabling RF on the TRF7970A. • If the first command is a SENSB_REQ request and the card emulation bit is set in the ISO Control register, the system enters ISO/IEC 14443 B emulation mode. The anticollision must be handled by the MCU, and the chip provides all physical level coding, decoding, and framing for this protocol. 6.1.3.1 Active Target If the first command received by the RF interface defines the system as an active target, then the receiver selects the appropriate data decoders (ISO/IEC 14443 A or ISO/IEC 14443 B reader or peer-to-peer) and framing option. Only the raw (decoded) data is forwarded to the MCU through the FIFO. SOF, EOF, preamble, sync bytes, CRC, and parity bytes are checked by the framer and discarded. The transmission of a response must occur after RF collision avoidance has been processed. The recommended method for RF collision avoidance is to use external RSSI to detect any external RF field. If successful, the NFC initiator can send the data that the MCU has loaded in the FIFO register. The coding of this data is done by hardware coders either in ISO/IEC 14443 A format (106-kbps system) or in peer-topeer format for (212-kbps and 424-kbps systems). The coders also provide CRC and parity bits (if required) and automatically add preambles, SOF, EOF, and synchronization bytes as defined by selected protocol. 6.1.3.2 Passive Target If the first command received by the RF interface defines the system as a passive target, then the receiver selects the appropriate data decoders (ISO/IEC 14443 A or ISO/IEC 14443 B reader or peer-to-peer) and framing option. Again, only the raw (decoded) data is forwarded to the MCU through the FIFO; SOF, EOF, preamble, sync bytes, CRC, and parity bytes are checked by the framer and discarded. The receiver works same as in the case of an active target. The transmit system in passive target mode differs from active target and operates similar to the standard tag. There is no RF collision avoidance sequence, and encoders are used to code the data for ISO/IEC 14443 A or ISO/IEC 14443 B tag (at 106 kbps, to start) or peer-to-peer (at 212 kbps, to start) format. The coding system adds all of the SOF, EOF, CRC, parity bits, and synchronization bytes that are required by protocol. The response is transmitted over-the-air with a method known as load modulation. 14 Detailed Description 版权 © 2011–2017, Texas Instruments Incorporated 提交文档反馈意见 产品主页链接: TRF7970A TRF7970A www.ti.com.cn 6.1.3.3 ZHCS363L – AUGUST 2011 – REVISED MARCH 2017 Card Emulation The chip can enter this mode by setting appropriate option bits. The chip can emulate ISO/IEC 14443 A and B card types. For ISO/IEC 14443 A and B, the emulation supports 106-kbps data rate to start. For ISO/IEC 14443 A, the anticollision algorithm can be performed using an internal state machine, which relieves the MCU of any real-time tasks; however, this method can present interoperability challenges with other NFC devices due to timing requirements. To ensure best interoperability, TI recommends allowing the MCU to manage the anticollision process, instead. The unique ID required for anticollision is provided by the MCU after wakeup of the system. 6.2 System Block Diagram 图 6-2 shows a block diagram of the TRF7970A. VDD_I/O MUX Phase and Amplitude Detector RX_IN1 Gain RSSI (AUX) RF Level Detector RSSI (External) RX_IN2 Filter and AGC Digitizer ISO Protocol Handling Transmitter Analog Front End I/O_1 (Control Registers and Command Logic) I/O_3 Gain MCU Interface VDD_PA TX_OUT I/O_0 State Control Logic Bit Framing 127-Byte FIFO I/O_5 I/O_6 I/O_7 SYS_CLK DATA_CLK VIN Serial Conversion CRC and Parity VSS_PA I/O_4 IRQ Decoder Framing I/O_2 Level Shifter Phase and Amplitude Detector RSSI (Main) Logic VDD_A BAND_GAP EN EN2 ASK/OOK VSS_A Digital Control State Machine MOD VDD_RF Voltage Supply Regulator Systems (Supply Regulators and Reference Voltages) VSS_RF VDD_X OSC_IN OSC_OUT VSS Crystal or Oscillator Timing System VSS_D Copyright © 2017, Texas Instruments Incorporated 图 6-2. System Block Diagram 6.3 Power Supplies The TRF7970A positive supply input VIN (pin 2) sources three internal regulators with output voltages VDD_RF, VDD_A and VDD_X. All regulators use external bypass capacitors for supply noise filtering and must be connected as indicated in reference schematics. These regulators provide a high power supply reject ratio (PSRR) as required for RFID reader systems. All regulators are supplied by VIN (pin 2). The regulators are not independent and have common control bits in register 0x0B for output voltage setting. The regulators can be configured to operate in either automatic or manual mode (register 0x0B, bit 7). The automatic regulator setting mode ensures an optimal compromise between PSRR and the highest possible supply voltage for RF output (to ensure maximum RF power output). The manual mode allows the user to manually configure the regulator settings. For applications in which the TRF7970A may be subjected to external noise, manually reducing the regulator settings can improve RF performance. Detailed Description 版权 © 2011–2017, Texas Instruments Incorporated 提交文档反馈意见 产品主页链接: TRF7970A 15 TRF7970A ZHCS363L – AUGUST 2011 – REVISED MARCH 2017 6.3.1 www.ti.com.cn Supply Arrangements Regulator Supply Input: VIN The positive supply at VIN (pin 2) has an input voltage range of 2.7 V to 5.5 V. VIN provides the supply input sources for three internal regulators with the output voltages VDD_RF, VDD_A, and VDD_X. External bypass capacitors for supply noise filtering must be used (per reference schematics). 注 VIN must be the highest voltage supplied to the TRF7970A. RF Power Amplifier Regulator: VDD_RF The VDD_RF (pin 3) regulator is supplying the RF power amplifier. The voltage regulator can be set for either 5-V or 3-V operation. External bypass capacitors for supply noise filtering must be used (per reference schematics). When configured for 5-V manual-operation, the VDD_RF output voltage can be set from 4.3 V to 5 V in 100-mV steps. In 3-V manual-operation, the output can be programmed from 2.7 V to 3.4 V in 100-mV steps. The maximum output current capability for 5-V operation is 150 mA and for 3-V operation is 100 mA. Analog Supply Regulator: VDD_A Regulator VDD_A (pin 1) supplies the analog circuits of the device. The output voltage setting depends on the input voltage and can be set for 5-V and 3-V operation. When configured for 5-V manual-operation, the output voltage is fixed at 3.4 V. External bypass capacitors for supply noise filtering must be used (per reference schematics). When configured for 3-V manual-operation, the VDD_A output can be set from 2.7 V to 3.4 V in 100-mV steps (see 表 6-2). 注 The configuration of VDD_A and VDD_X regulators are not independent from each other. The VDD_X output current should not exceed 20 mA. Digital Supply Regulator: VDD_X The digital supply regulator VDD_X (pin 32) provides the power for the internal digital building blocks and can also be used to supply external electronics within the reader system. When configured for 3-V operation, the output voltage can be set from 2.7 to 3.4 V in 100-mV steps. External bypass capacitors for supply noise filtering must be used (per reference schematics). 注 The configuration of the VDD_A and VDD_X regulators are not independent from each other. The VDD_X output current should not exceed 20 mA. By default, the regulators are set in automatic regulator setting mode. In this mode, the regulators are automatically set every time the system is activated by setting EN input High or each time the automatic regulator setting bit, B7 in register 0x0B is set to a 1. The action is started on the 0 to 1 transition. This means that, if the user wants to rerun the automatic setting from a state in which the automatic setting bit is already high, the automatic setting bit (B7 in register 0x0B) should be changed: 1-0-1. By default, the regulator setting algorithm sets the regulator outputs to a "Delta Voltage" of 400 mV below VIN, but not higher than 5 V for VDD_RF and 3.4 V for VDD_A and VDD_A. 16 Detailed Description 版权 © 2011–2017, Texas Instruments Incorporated 提交文档反馈意见 产品主页链接: TRF7970A TRF7970A www.ti.com.cn ZHCS363L – AUGUST 2011 – REVISED MARCH 2017 Power Amplifier Supply: VDD_PA The power amplifier of the TRF7970A is supplied through VDD_PA (pin 4). The positive supply pin for the RF power amplifier is externally connected to the regulator output VDD_RF (pin 3). I/O Level Shifter Supply: VDD_I/O The TRF7970A has a separate supply input VDD_I/O (pin 16) for the built-in I/O level shifter. The supported input voltage ranges from 1.8 V to VIN, not exceeding 5.5 V. Pin 16 is used to supply the I/O interface pins (I/O_0 to I/O_7), IRQ, SYS_CLK, and DATA_CLK pins of the reader. In typical applications, VDD_I/O is directly connected to VDD_X, while VDD_X also supplies the MCU. This ensures that the I/O signal levels of the MCU match the logic levels of the TRF7970A. Negative Supply Connections: VSS, VSS_TX, VSS_RX, VSS_A, VSS_PA The negative supply connections VSS_X of each functional block are all externally connected to GND. The substrate connection is VSS (pin 10), the analog negative supply is VSS_A (pin 15), the logic negative supply is VSS_D (pin 29), the RF output stage negative supply is VSS_PA (pin 6), and the negative supply for the RF receiver VSS_RX (pin 7). Detailed Description 版权 © 2011–2017, Texas Instruments Incorporated 提交文档反馈意见 产品主页链接: TRF7970A 17 TRF7970A ZHCS363L – AUGUST 2011 – REVISED MARCH 2017 6.3.2 www.ti.com.cn Supply Regulator Settings The input supply voltage mode of the reader needs to be selected. This is done in the Chip Status Control register (0x00). Bit 0 in register 0x00 selects between 5-V or 3-V input supply voltage. The default configuration is 5 V, which reflects an operating supply voltage range of 4.3 V to 5.5 V. If the supply voltage is below 4.3 V, the 3-V configuration should be used. As VDD_RF is increased, the system can become more susceptible to noise coupling on the RX lines. For minimum noise coupling, TI recommends using the value of 0x00. For improved range, higher VDD_RF voltages may be set, but complete system testing is required to determine the value which provides optimal performance. The various regulators can be configured to operate in automatic or manual mode. This is done in the Regulator and I/O Control register (0x0B), as shown in 表 6-1 and 表 6-2. 表 6-1. Supply Regulator Setting: 5-V System REGISTER ADDRESS (hex) OPTION BITS SETTING IN REGULATOR CONTROL REGISTER B7 (1) COMMENTS B6 B5 B4 B3 B2 B1 B0 1 x x x x x 0 0 Automatic regulator setting 400-mV difference 0B 0 x x x x 1 1 1 VDD_RF = 5 V, VDD_A = 3.4 V, VDD_X = 3.4 V 0B 0 x x x x 1 1 0 VDD_RF = 4.9 V, VDD_A = 3.4 V, VDD_X = 3.4 V 0B 0 x x x x 1 0 1 VDD_RF = 4.8 V, VDD_A = 3.4 V, VDD_X = 3.4 V 0B 0 x x x x 1 0 0 VDD_RF = 4.7 V, VDD_A = 3.4 V, VDD_X = 3.4 V 0B 0 x x x x 0 1 1 VDD_RF = 4.6 V, VDD_A = 3.4 V, VDD_X = 3.4 V 0B 0 x x x x 0 1 0 VDD_RF = 4.5 V, VDD_A = 3.4 V, VDD_X = 3.4 V 0B 0 x x x x 0 0 1 VDD_RF = 4.4 V, VDD_A = 3.4 V, VDD_X = 3.4 V 0B 0 x x x x 0 0 0 VDD_RF = 4.3 V, VDD_A = 3.4 V, VDD_X = 3.4 V Automatic Mode (default) 0B Manual Mode (1) x = Don't care 表 6-2. Supply Regulator Setting: 3-V System REGISTER ADDRESS (hex) OPTION BITS SETTING IN REGULATOR CONTROL REGISTER B7 (1) COMMENTS B6 B5 B4 B3 B2 B1 B0 1 x x x x x 0 0 Automatic regulator setting 400-mV difference 0B 0 x x x x 1 1 1 VDD_RF = 3.4 V, VDD_A = 3.4 V, VDD_X = 3.4 V 0B 0 x x x x 1 1 0 VDD_RF = 3.3 V, VDD_A = 3.3 V, VDD_X = 3.3 V 0B 0 x x x x 1 0 1 VDD_RF = 3.2 V, VDD_A = 3.2 V, VDD_X = 3.2 V 0B 0 x x x x 1 0 0 VDD_RF = 3.1 V, VDD_A = 3.1 V, VDD_X = 3.1 V 0B 0 x x x x 0 1 1 VDD_RF = 3.0 V, VDD_A = 3.0 V, VDD_X = 3.0 V 0B 0 x x x x 0 1 0 VDD_RF = 2.9 V, VDD_A = 2.9 V, VDD_X = 2.9 V 0B 0 x x x x 0 0 1 VDD_RF = 2.8 V, VDD_A = 2.8 V, VDD_X = 2.8 V 0B 0 x x x x 0 0 0 VDD_RF = 2.7 V, VDD_A = 2.7 V, VDD_X = 2.7 V Automatic Mode (default) 0B Manual Mode (1) x = Don't care The regulator configuration function adjusts the regulator outputs by default to 400 mV below VIN level, but not higher than 5 V for VDD_RF, 3.4 V for VDD_A and VDD_X. This ensures the highest possible supply voltage for the RF output stage while maintaining an adequate PSRR (power supply rejection ratio). 18 Detailed Description 版权 © 2011–2017, Texas Instruments Incorporated 提交文档反馈意见 产品主页链接: TRF7970A TRF7970A www.ti.com.cn 6.3.3 ZHCS363L – AUGUST 2011 – REVISED MARCH 2017 Power Modes The chip has several power states, which are controlled by two input pins (EN and EN2) and several bits in the chip status control register (0x00) (see 表 6-3 and 表 6-4). 表 6-3. 3.3-V Operation Power Modes (1) EN2 EN CHIP STATUS CONTROL REGISTER (0x00) REGULATOR CONTROL REGISTER (0x0B) TRANSMITTER RECEIVER SYS_CLK (13.56 MHz) SYS_CLK (60 kHz) VDD_X Power down 0 0 XX XX OFF OFF OFF OFF OFF