TS12A12511
SCDS248E – OCTOBER 2009 – REVISED SEPTEMBER 2022
TS12A12511 5-Ω Single-Channel SPDT Analog Switch
With Negative Signaling Capability
1 Features
3 Description
•
•
•
•
•
•
•
•
The TS12A12511 is a bidirectional, single-channel,
single-pole double-throw (SPDT) analog switch that
can pass signals with swings of 0 to 12 V or –6 V to 6
V. This switch conducts equally well in both directions
when it is on. The device also offers a low ON-state
resistance of 5 Ω (typical), which is matched to
within 1 Ω between channels. The maximum current
consumption is 93
MHz. The TS12A12511 exhibits break-before-make
switching action, preventing momentary shorting
when switching channels. This device is available
packaged in an 8-lead VSSOP, 8-lead SOT-23, and
a 8-pin WSON.
•
•
•
±2.7-V to ±6-V dual supply
2.7-V to 12-V single supply
5-Ω (typical) ON-state resistance
1.6-Ω (typical) ON-state resistance flatness
3.3-V, 5-V compatible digital control inputs
Rail-to-rail analog signal handling
Fast tON, tOFF times
Supports both digital and analog signal
applications
Tiny 8-lead SOT-23, 8-lead MSOP, and QFN-8
packages
Latch-up performance exceeds 100 mA per JESD
78, Class II
ESD performance tested per JESD 22
– ±2000-V Human Body Model
(A114-B, Class II)
– ±1000-V Charged-Device Model (C101)
2 Applications
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Automatic test equipment
Power routing
Communication systems
Data acquisition systems
Sample-and-hold systems
Relay replacement
Grid Infrastructure
Package Information(1)
PART NUMBER
TS12A12511
(1)
PACKAGE
BODY SIZE (NOM)
DCN (SOT-23, 8)
2.90 mm × 1.63 mm
DGK (VSSOP, 8)
3.00 mm × 3.00 mm
DRJ (WSON, 8)
4.00 mm × 4.00 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
SPDT
NC
COM
NO
IN
Simplified Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TS12A12511
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SCDS248E – OCTOBER 2009 – REVISED SEPTEMBER 2022
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................4
6.5 Electrical Characteristics: ±5-V Dual Supply...............5
6.6 Electrical Characteristics: 12-V Single Supply............ 6
6.7 Electrical Characteristics: 5-V Single Supply.............. 7
6.8 Typical Characteristics................................................ 8
7 Parameter Measurement Information.......................... 10
7.1 Test Circuits.............................................................. 10
8 Detailed Description......................................................14
8.1 Overview................................................................... 14
8.2 Functional Block Diagram......................................... 14
8.3 Feature Description...................................................14
8.4 Device Functional Modes..........................................14
9 Application and Implementation.................................. 15
9.1 Application Information............................................. 15
9.2 Typical Application.................................................... 15
10 Power Supply Recommendations..............................17
11 Layout........................................................................... 17
11.1 Layout Guidelines................................................... 17
11.2 Layout Example...................................................... 17
12 Device and Documentation Support..........................18
12.1 Receiving Notification of Documentation Updates..18
12.2 Support Resources................................................. 18
12.3 Trademarks............................................................. 18
12.4 Electrostatic Discharge Caution..............................18
12.5 Glossary..................................................................18
13 Mechanical, Packaging, and Orderable
Information.................................................................... 18
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (January 2019) to Revision E (September 2022)
Page
• Updated the numbering format for tables, figures, and cross-references throughout the document..................1
• Updated the Applications section....................................................................................................................... 1
• Updated the Leakage Current vs I/O Voltage (Switch ON) and Leakage Current vs I/O Voltage (Switch OFF)
figures................................................................................................................................................................. 8
Changes from Revision C (January 2015) to Revision D (January 2019)
Page
• Added Junction temperature to the Absolute Maximum Ratings table............................................................... 4
Changes from Revision B (April 2011) to Revision C (January 2015)
Page
• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device
Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information
section ............................................................................................................................................................... 1
Changes from Revision A (May 2010) to Revision B (April 2011)
Page
• Deleted preview status from DGK and DCN packages...................................................................................... 3
2
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5 Pin Configuration and Functions
COM
NC
GND
V+
1
8
2
7
3
6
5
4
COM
NC
GND
V+
NO
V–
IN
N.C.
Figure 5-1. DGK Package, 8-Pin VSSOP (Top View)
1
8
2
7
6
3
4
5
NO
V–
IN
N.C.
Figure 5-2. DCN Package, 8-Pin SOT-23 (Top View)
COM
1
8
NO
NC
2
7
V–
GND
3
6
IN
V+
4
5
N.C.
N.C. – Not internally connected NC – Normally closed NO – Normally open
The Exposed Thermal Pad must be electrically connected to V– or left floating.
Figure 5-3. DRJ Package, 8-Pin WSON (Top View)
Table 5-1. Pin Functions
PIN
NAME
NO.
TYPE(1)
DESCRIPTION
COM
1
I/O
Common. Can be an input or output.
GND
3
—
Ground (0 V) reference
IN
6
I
NC
2
I/O
Normally closed. Can be an input or output.
N.C.
5
—
No connect. Not internally connected.
NO
8
I/O
Normally open. Can be an input or output.
VCC
4
I
Most positive power supply
–VCC
7
I
Most negative power supply. This pin is only used in dual-supply applications and should be tied to
ground in single-supply applications.
Thermal pad
(1)
—
Logic control input
The Exposed Thermal Pad must be electrically connected to V– or left floating.
I = input, O = output
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6 Specifications
6.1 Absolute Maximum Ratings
TA = 25°C (unless otherwise noted).(1)
MIN
MAX
UNIT
VCC to -VCC
0
13
V
VCC to GND
–0.3
13
V
-VCC to GND
–6.5
0.3
V
VI/O
Analog inputs
IIN
Digital inputs
II/O
NC, NO, or COM
V
±30
mA
Peak current
NC, NO, or COM
±100
mA
Continuous current
NC, NO, or COM
±50
mA
TA
Operating temperature
TJ
Junction temperature
Tstg
Storage temperature
(1)
–VCC – 0.5 V CC + 0.5
–40
–65
85
°C
150
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Section 6.3 is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VCC
0
12
V
–VCC
–6
0
V
VI/O
–VCC
VCC
V
VIN
0
VCC
V
6.4 Thermal Information
TS12A12511
THERMAL METRIC(1)
DCN
DGK
DRJ
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
218.4
184.5
47.8
RθJC(top)
Junction-to-case (top) thermal resistance
89.9
71.0
48.6
RθJB
Junction-to-board thermal resistance
144.4
104.5
24.2
ψJT
Junction-to-top characterization parameter
7.8
11.3
1.2
ψJB
Junction-to-board characterization parameter
141.7
103.3
24.4
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
9.0
(1)
4
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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6.5 Electrical Characteristics: ±5-V Dual Supply
VCC = 5 V ± 10%, –VCC = –5 V ± 10%, TA = –40°C to 85°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA= 25°C
MIN
TYP
TA= –40°C to 85°C
MAX
MIN
TYP
MAX
UNIT
ANALOG SWITCH
Analog signal range
-VCC
VCC
V
8
Ω
RON
ON-state resistance
VNC = -4.5 V to +4.5 V
or VNO = –4.5 V to 4.5 V, ICOM = –10 mA;
see Figure 7-1
5
ΔRON
ON-state resistance
match between
channels
VNC = -4.5 V to +4.5 V
or VNO = -4.5 V to +4.5 V,
ICOM = –10 mA
1
1.2
1.6
Ω
RON(flat)
ON-state resistance
flatness
VNC = -3.3 V to +3.3 V
or VNO = -3.3 V to +3.3 V,
ICOM = –10 mA
1.6
2.2
2.2
Ω
5
LEAKAGE CURRENTS
INC(OFF),
INO(OFF)
OFF leakage current
VNC = -4.5 V to +4.5 V
or VNO = -4.5 V to +4.5 V
VCOM = -4.5 V to +4.5 V; see Figure 7-2
–1
±0.5
1
–50
50
nA
INC(ON),
INO(ON)
ON leakage current
VNC = -4.5 V to +4.5 V
or VNO = -4.5 V to +4.5 V
VCOM = open; see Figure 7-3
–1
±0.5
1
–50
50
nA
2.4
VCC
V
0
0.8
V
–1
1
μA
DIGITAL INPUTS
VINH
High-level input
voltage
VINL
Low-level input voltage
IINL, IINH
Input current
CIN
Control input
capacitance
VIN = VINL or VINH
0.005
2.5
pF
DYNAMIC(1)
tON
Turn-ON time
RL = 300 Ω, CL = 35 pF,
VCOM = 3.3 V; see Figure 7-5
80
95
115
ns
tOFF
Turn-OFF time
RL = 300 Ω, CL = 35 pF,
VCOM = 3.3 V
41
50
56
ns
tBBM
Break-before-make
time delay
RL = 300 Ω, CL = 35 pF,
VNC = VNO = 3.3 V; see Figure 7-6
36
QC
Charge injection
VNC = VNO = 0 V, RGEN = 0 Ω, CL = 1 nF;
see Figure 7-7
26
pC
OISO
OFF isolation
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 7-8
–70
dB
XTALK
Channel-to-channel
crosstalk
RL = 50 Ω, CL = 5 pF, f = 1 MHz,
see Figure 7-9
–70
dB
BW
Bandwidth –3 dB
RL = 50 Ω, CL = 5 pF; see Figure 7-10
93
MHz
THD
Total harmonic
distortion
RL = 600 Ω, CL = 15pF, VNO = 1VRMS,
f = 20 kHz; see Figure 7-11
0.004%
CNC(OFF),
CNO(OFF)
NC, NO
OFF capacitance
f = 1 MHz; see Figure 7-4
14
pF
CCOM(ON),
CNC(ON),
CNO(ON)
COM, NC, NO
ON capacitance
f = 1 MHz; see Figure 7-4
60
pF
18
ns
SUPPLY
ICC
(1)
Positive supply current
0.03
1
μA
Specified by design, not subject to production test.
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6.6 Electrical Characteristics: 12-V Single Supply
VCC = 12 V ± 10%, -VCC = 0 V, GND = 0 V, TA = –40°C to 85°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA= 25°C
MIN
TYP
TA= –40°C to 85°C
MAX
MIN
TYP
MAX
UNIT
ANALOG SWITCH
Analog signal range
0
Ron
ON-state resistance
VNC =0 V to 10.8 V or VNO = 0 V to
10.8 V,
ICOM = –10 mA, see Figure 7-1
5
ΔRon
ON-state resistance
match between
channels
VNC = 0 V to 10.8 V or VNO = 0 V to
10.8 V,
ICOM = –10 mA
1.6
Ron(flat)
ON-state resistance
flatness
VNC = 3.3 V to 7V or VNO = 3.3 V to
7 V,
ICOM = –10 mA
1.7
5
2.4
1.8
VCC
V
8
Ω
2.6
Ω
3.2
Ω
LEAKAGE CURRENTS
INC(OFF),
INO(OFF)
OFF leakage current
VNC = 0 V to 10.8 V or VNO = 0 V to
10.8 V,
VCOM = 0 V to 10.8 V; see Figure
7-2
–10
±0.5
10
–50
50
nA
INC(ON),
INO(ON)
ON leakage current
VNC = 0 V to 10.8V or VNO = 0 V to
10.8 V,
VCOM = open; see Figure 7-3
–10
±0.5
10
–50
50
nA
V
DIGITAL INPUTS
VINH
High-level input voltage
5
VCC
VINL
Low-level input voltage
0
0.8
V
IINL, IINH
Input current
–0.1
0.1
μA
CIN
Digital input capacitance
VIN = VINL or VINH
±0.005
2.7
pF
DYNAMIC (1)
tON
Turn-ON time
RL = 300 Ω, CL = 35 pF,
VCOM = 3.3 V; see Figure 7-5
56
85
110
ns
tOFF
Turn-OFF time
RL = 300 Ω, CL = 35 pF,
VCOM = 3.3 V; see Figure 7-5
25
30
31
ns
tBBM
Break-before-make
time delay
RL = 300 Ω, CL = 35 pF,
VNC = VNO = 3.3 V; see Figure 7-6
30
QC
Charge injection
RGEN = VNC = VNO = 0 V, RGEN = 0
Ω, CL = 1 nF;
see Figure 7-7
491
pC
OISO
OFF isolation
RL = 50 Ω, CL = 5 pF, f = 1 MHz,
see Figure 7-8
–70
dB
XTALK
Channel-to-channel
crosstalk
RL = 50 Ω, CL = 5 pF, f = 1 MHz,
see Figure 7-9
–70
dB
BW
Bandwidth –3 dB
RL = 50 Ω, CL = 5 pF, see Figure
7-10
200
MHz
THD
Total harmonic distortion
RL = 600 Ω, CL = 15pF, VNO = 1
VRMS, f = 20 kHz; see Figure 7-11
CNC(OFF),
CINO(OFF)
NC, NO
OFF capacitance
f = 1 MHz, see Figure 7-4
14
pF
CCOM(ON),
CNC(ON),
CNO(ON)
COM, NC, NO
ON capacitance
f = 1 MHz, see Figure 7-4
55
pF
19
ns
0.04%
SUPPLY
ICC
(1)
6
Positive supply current
0.07
1
μA
Specified by design, not subject to production test.
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6.7 Electrical Characteristics: 5-V Single Supply
VCC = 5 V ± 10%, -VCC = 0 V, GND = 0 V, TA = –40°C to 85°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA= 25°C
MIN
TYP
TA= –40°C to 85°C
MAX
MIN
TYP
MAX
UNIT
ANALOG SWITCH
Analog signal range
0
VCC
V
Ron
ON-state resistance
VNC =0 V to 4.5 V or VNO = 0 V to
4.5 V,
ICOM = –10 mA;
see Figure 7-1
8
10
12.5
Ω
ΔRon
ON-state resistance
match between
channels
VNC =0 V to 4.5 V or VNO = 0 V to
4.5 V,
ICOM = –10 mA
1
1.1
1.5
Ω
Ron(flat)
ON-state resistance
flatness
VNC =0 V to 4.5 V or VNO = 0 V to
4.5 V,
ICOM = –10 mA
1.3
2
Ω
1.3
LEAKAGE CURRENTS
INC(OFF),
INO(OFF)
OFF leakage current
VNC =0 V to 4.5 V or VNO = 0 V to
4.5 V,
VCOM = 0 V to 4.5 V; see Figure 7-2
–1
±0.5
1
–50
50
nA
INC(ON),
INO(ON)
ON leakage current
VNC = 0 V to 4.5V or VNO = 0 V to
4.5 V,
VCOM = open; see Figure 7-3
–1
±0.5
1
–50
50
nA
V
DIGITAL INPUTS
VINH
High-level input voltage
2.4
VCC
VINL
Low-level input voltage
0
0.8
V
IINL, IINH
Input current
–0.1
0.1
μA
CIN
Digital input capacitance
VIN = VINL or VINH
0.01
2.8
pF
DYNAMIC(1)
tON
Turn-ON time
RL = 300 Ω, CL = 35 pF,
VCOM = 3.3 V; see Figure 7-5
119
145
178
ns
tOFF
Turn-OFF time
RL = 300 Ω, CL = 35 pF,
VCOM = 3.3 V; see Figure 7-5
38
47
95.2
ns
tBBM
Break-before-make
time delay
RL = 300 Ω, CL = 35 pF,
VNC = VNO = 3.3 V; see Figure 7-6
79
QC
Charge injection
VGEN = VNC = VNO = 0 V, RGEN = 0
Ω, CL = 1 nF;
see Figure 7-7
65
pC
OISO
OFF isolation
RL = 50 Ω, CL = 5 pF, f = 1 MHz,
see Figure 7-8
–70
dB
XTALK
Channel-to-channel crosstalk
RL = 50 Ω, CL = 5 pF, f = 1 MHz,
see Figure 7-9
–70
dB
BW
Bandwidth –3 dB
RL = 50 Ω, see Figure 7-10
152
MHz
THD
Total harmonic distortion
RL = 600 Ω, CL = 15 pF, VNO = 1
VRMS, f = 20 kHz; see Figure 7-11
CNC(OFF),
CNO(OFF)
NC, NO
OFF capacitance
f = 1 MHz, see Figure 7-4
15
pF
CCOM(ON),
CNC(ON),
INO(ON)
COM, NC, NO
ON capacitance
f = 1 MHz, see Figure 7-4
55
pF
44
ns
0.04%
POWER REQUIREMENTS
ICC
(1)
Positive supply current
VIN = 0 V or VCC
0.02
1
μA
Specified by design, not subject to production test.
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6.8 Typical Characteristics
7.0
0.10
0.05
6.0
0.00
-0.05
ON-leakage Current (nA)
RON (Ohms)
5.0
4.0
3.0
2.0
-0.10
-0.15
-0.20
-0.25
VCC = 3 V, –VCC = –3 V
VCC = 3 V, - VCC = -3 V
VCC = 5 V, - VCC = -5 V
VCC = 6 V, - VCC = -6 V
1.0
-0.30
VCC = 5 V, –VCC = –5 V
VCC = 6 V, –VCC = –6 V
-0.35
-0.40
-6.0
0.0
-6
-5
-4
-3
-2
-1
0
1
2
3
4
5
-4.0
-2.0
6
0.0
2.0
4.0
6.0
Switch I/O Voltage (V)
VIO(V)
Figure 6-2. Leakage Current vs I/O Voltage (Switch ON)
Figure 6-1. RON vs VIO
3.00
0.05
0.00
2.50
-0.10
-0.15
-0.20
VCC = 3 V, –VCC = –3 V
-0.25
VCC = 5 V, –VCC = –5 V
Positive Supply Current (nA)
OFF-leakage Current (nA)
-0.05
2.00
VCC = 3 V, -VCC = -3 V
VCC = 5 V, -VCC = -5 V
VCC = 6 V, -VCC = -6 V
1.50
1.00
VCC = 6 V, –VCC = –6 V
-0.30
0.50
-0.35
-6.0
-4.0
-2.0
0.0
2.0
4.0
6.0
0.00
-40.00
Switch I/O Voltage (V)
Figure 6-3. Leakage Current vs I/O Voltage (Switch OFF)
25.00
85.00
Temperature (degrees C)
Figure 6-4. Positive Supply Current vs Temperature
7.0
0.00
-40.00
25.00
85.00
6.0
-0.50
4.0
-1.50
VCC = 3 V, - VCC = -3 V
VCC = 5 V, -VCC = -5 V
VCC = 6 V, -VCC = -6 V
VOUT (V)
Negative Supply Current (nA)
5.0
-1.00
3.0
2.0
-2.00
VCC = 3 V, -VCC = -3 V
VCC = 5 V, -VCC = -5 V
VCC = 6 V, -VCC = -6 V
1.0
-2.50
0.0
-1.0
-3.00
0.0
Temperature (Degrees C)
Figure 6-5. Negative Supply Current vs Temperature
8
0.5
1.0
1.5
2.0
2.5
3.0
3.5
Control Input Voltage (V)
Figure 6-6. Control Input (IN) Threshold Voltage
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6.8 Typical Characteristics (continued)
-5.00
0.0
-2.0
-15.00
-4.0
-25.00
Magnitude (dB)
Magnitude (dB)
-6.0
-8.0
-10.0
-12.0
-45.00
-55.00
-14.0
-16.0
-18.0
1.00E+6
-35.00
-65.00
10.00E+6
100.00E+6
-75.00
1.00E+6
1.00E+9
Frequency (Hz)
10.00E+6
Figure 6-7. Bandwidth Dual Supply (±5 V)
100.00E+6
1.00E+9
Frequency (Hz)
Figure 6-8. Off Isolation vs Frequency Dual Supply (±5 V)
0.050
-5.0
0.045
-15.0
0.040
0.035
0.030
-35.0
THD
Magnitude (dB)
-25.0
-45.0
12V_0V/NC-COM
12V_0V/NO-COM
5V_0V/NC-COM
5V_0V/NO-COM
5V_5V/NC-COM
5V_5V/NO-COM
0.025
0.020
0.015
-55.0
0.010
-65.0
0.005
-75.0
1.00E+6
0.000
10.00E+6
100.00E+6
10
1.00E+9
100
1000
10000
100000
Frequency
Frequency (Hz)
Figure 6-10. THD+N (%) vs Frequency
Figure 6-9. Crosstalk vs Frequency Dual Supply (±5 V)
600
500
400
Charge Injection (pC)
300
200
100
0
-100
-200
-300
-400
6V
5V
5.
5V
4V
4.
5V
3V
3.
5V
2V
2.
5V
1.
5V
1V
0V
0.
5V
-1
V
-0
.5
V
-2
V
-1
.5
V
-3
V
-2
.5
V
-4
V
-3
.5
V
5V
-5
V
-4
.5
V
-5
.
-6
V
-500
Bias Voltage
Figure 6-11. Charge Injection vs Bias Voltage
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7 Parameter Measurement Information
7.1 Test Circuits
Vcc
VNO NO
COM
+
VCOM
Channel ON
R on
VI
ICOM
IN
VCOM – VNO
I COM
VI = VIH or VIL
+
GND
–VCC
Figure 7-1. ON-State Resistance
Vcc
VNO NO
COM
+
VCOM
+
VI
OFF-State Leakage Current
Channel OFF
VI = VIH or VIL
IN
+
GND
–VCC
Figure 7-2. OFF-State Leakage Current (ICOM(OFF), INC(OFF))
Vcc
VNO NO
COM
+
VI
VCOM
ON-State Leakage Current
Channel ON
VI = VIH or VIL
IN
+
GND
–VCC
Figure 7-3. ON-State Leakage Current (ICOM(ON), INC(ON))
10
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VCC
VNO
NO
Capacitance
Meter
VBIAS = VCC, VIO, or GND and
VI = VIO or GND
COM
COM
VI
IN
Capacitance is measured at NO,
COM, and IN inputs during ON
and OFF conditions.
VBIAS
GND
–VCC
Figure 7-4. Capacitance (CCOM(OFF), CCOM(ON), CNC(OFF), CNC(ON))
Vcc
NO
VCOM
VI
VNO
TEST
RL
CL
VCOM
tON
50 Ω
35 pF
Vcc
tOFF
50 Ω
35 pF
Vcc
COM
CL(2)
RL
IN
Logic
Input(1)
VIO
Logic
Input
(VI)
GND
50%
50%
0
tON
–VCC
(1)
(2)
tOFF
Switch
Output
(VNO)
90%
90%
All input pulses are supplied by generators having the following characteristics: PRR≤ 10 MHz, Z O = 50 Ω, tr < 5 ns, t f < 5 ns.
C L includes probe and jig capacitance.
Figure 7-5. Turn-ON (tON) and Turn-OFF Time (tOFF)
Vcc
Logic
Input
(VI)
VNC or VNO
NC or NO
VCOM
VIO
50%
0
COM
NC or NO
CL(2)
VI
Logic
Input(1)
IN
(2)
Switch
Output
(VCOM)
90%
90%
tBBM
GND
–VCC
(1)
RL
VNC or VNO = Vcc /2
RL = 50 Ω
CL = 35 pF
All input pulses are supplied by generators having the following characteristics: PRR≤ 10 MHz, Z O = 50 Ω, tr < 5 ns, t f < 5 ns.
C L includes probe and jig capacitance.
Figure 7-6. Break-Before-Make Time Delay (tBBM)
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VCC
RGEN
VGEN
Logic
Input
(VI)
VIH
OFF
ON
OFF V
IL
NO
COM
+
VCOM
∆VCOM
VCOM
CL(1)
VI
VGEN = 0 to Vcc
IN
Logic
Input(2)
RGEN = 0
CL = 1 nF
QC = CL × ∆VCOM
VI = VIH or VIL
GND
–VCC
(1)
(2)
C L includes probe and jig capacitance.
All input pulses are supplied by generators having the following characteristics: PRR≤ 10 MHz, Z O = 50 Ω, tr < 5 ns, t f < 5 ns.
Figure 7-7. Charge Injection (QC)
Vcc
Network Analyzer
Channel OFF: NO to COM
50 W
VNO NO
VI = VIO or GND
COM
Source
Signal
VCOM
50 W
Network Analyzer Setup
VI
50 W
Source Power = 0 dBm
(632-mV P-P at 50-Wload)
IN
+
GND
DC Bias = 350 mV
–VCC
Figure 7-8. OFF Isolation (OISO)
Vcc
Network Analyzer
50 W
VNO1
Source
Signal
VNO2
NO1
NO2
COM2
50 W
VI
Channel ON: NO to COM
COM1
Network Analyzer Setup
50 W
Source Power = 0 dBm
(632 mV P-P at 50 Wload)
IN
+
DC Bias = 350 mV
GND
–VCC
Figure 7-9. Channel-to-Channel Crosstalk (XTALK)
12
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VCC
Network Analyzer
50 W
VNO
NO
Channel ON: NO to COM
COM
VCOM
VI = VIH or VIL
Source
Signal
Network Analyzer Setup
VI
50 W
IN
Source Power = 0 dBm
(632-mV P-P at 50-Wload)
+
GND
DC Bias = 350 mV
–VCC
Figure 7-10. Bandwidth (BW)
Channel ON: COM to NO
VSOURCE = Vcc P-P
VI = (VIO – Vcc/2) or −Vcc /2
RL = 600 Ω
fSOURCE = 20 Hz to 20 kHz
CL = 50 pF
Vcc /2
Audio Analyzer
NO
Source
Signal
COM
CL(1)
600
VI
IN
600
−Vcc /2
(1)
–VCC
C L includes probe and jig capacitance.
Figure 7-11. Total Harmonic Distortion
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8 Detailed Description
8.1 Overview
The TS12A12511 is a bidirectional, single channel, single-pole double-throw (SPDT) analog switch that can pass
signals with swings of 0 to 12 V or –6 V to 6 V. This switch conducts equally well in both directions when it is
on. It also offers a low ON-state resistance of 5 Ω (typical), which is matched to within 1 Ω between channels.
The maximum current consumption is < 1 μA and –3 dB bandwidth is > 93 MHz. The TS12A12511 exhibits
break-before-make switching action, preventing momentary shorting when switching channels. This device is
available in an 8-lead MSOP, 8-lead SOT-23, and 8-pin QFN package.
8.2 Functional Block Diagram
SPDT
NC
COM
NO
IN
8.3 Feature Description
The TS12A12511 can pass signals with swings of 0 to 12 V or –6 V to 6. The device is great for applications
where the AC signals do not have a common mode voltage since both the positive and negative swing of the
signal can be passed through the device with little distortion.
8.4 Device Functional Modes
Table 8-1. Truth Table
14
IN
NC TO COM, COM TO NC
L
On
Off
H
Off
On
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NO TO COM, COM TO NO
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
Analog signals that range over the entire supply voltage (VCC to GND) or (VCC to -VCC) can be passed with very
little change in ON-state resistance. The switches are bidirectional, so the NO, NC, and COM pins can be used
as either inputs or outputs.
9.2 Typical Application
12 V
0.1 F
0.1 F
VCC
SPST switch
System
Digital
Control
IN
Signal
Path
COM
NO
Device 1
12 V
0.1 F
NC
GND/-VCC
Device 2
12 V
0.1 F
3.3 V
Figure 9-1. Typical Application Schematic
9.2.1 Design Requirements
Pull the digitally controlled input select pin IN to VCC or GND to avoid unwanted switch states that could result if
the logic control pin is left floating.
9.2.2 Detailed Design Procedure
Select the appropriate supply voltage to cover the entire voltage swing of the signal passing through the switch
since the TS12A12511 input or output signal swing of the device is dependant of the supply voltage VCC and
-VCC.
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9.2.3 Application Curve
7.0
6.0
RON (Ohms)
5.0
4.0
3.0
2.0
VCC = 3 V, - VCC = -3 V
VCC = 5 V, - VCC = -5 V
VCC = 6 V, - VCC = -6 V
1.0
0.0
-6
-5
-4
-3
-2
-1
0
1
2
3
4
5
6
VIO(V)
Figure 9-2. RON vs VIO
16
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10 Power Supply Recommendations
Proper power-supply sequencing is recommended for all CMOS devices. Do not exceed the absolute maximum
ratings, because stresses beyond the listed ratings can cause permanent damage to the device. Always
sequence VCC and -VCC on first, followed by NO, NC, or COM.
Although it is not required, power-supply bypassing improves noise margin and prevents switching noise
propagation from the VCC supply to other components. A 0.1-μF capacitor, connected from VCC to GND, is
adequate for most applications.
11 Layout
11.1 Layout Guidelines
It is recommended to place a bypass capacitor as close to the supply pins, VCC and -VCC, as possible to help
smooth out lower frequency noise and provide better load regulation across the frequency spectrum. Minimize
trace lengths and vias on the signal paths to preserve signal integrity.
11.2 Layout Example
LEGEND
Polygonal Copper Pour
VIA to Power Plane
VIA to GND Plane
To System
Bypass Capacitor
To System
1
COM
NO
8
2
NC
-VCC
7
3
GND
IN
6
4
VCC
N.C.
5
-Vcc
To System
To System
Vcc
Bypass Capacitor
Figure 11-1. Layout Schematic
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12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
18
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PACKAGE OPTION ADDENDUM
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3-Jun-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TS12A12511DCNR
ACTIVE
SOT-23
DCN
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
NFHS
HFHA
Samples
TS12A12511DGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
2US
2UA
Samples
TS12A12511DRJR
ACTIVE
SON
DRJ
8
1000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ZVE
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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