TS12A4514D

TS12A4514,, TS12A4515 www.ti.com ................................................................................................................................................... SCDS193D – AUGUST 2006 – REVISED MARCH 2009 SPST CMOS ANALOG SWITCHES FEATURES 1 • • • 2-V to 12-V Single-Supply Operation Specified ON-State Resistance: – 15 Ω Max With 12-V Supply – 20 Ω Max With 5-V Supply – 50 Ω Max With 3.3-V Supply Specified Low OFF-Leakage Currents: – 1 nA at 25°C – 10 nA at 85°C • • • • • Specified Low ON-Leakage Currents: – 1 nA at 25°C – 10 nA at 85°C Low Charge Injection: 11.5 pC (12-V Supply) Fast Switching Speed: tON = 80 ns, tOFF = 50 ns (12-V Supply) Break-Before-Make Operation (tON > tOFF) TTL/CMOS-Logic Compatible With 5-V Supply DESCRIPTION/ORDERING INFORMATION The TS12A4514/TS12A4515 are single pole/single throw (SPST), low-voltage, single-supply CMOS analog switches, with very low switch ON-state resistance. The TS12A4514 is normally open (NO). The TS12A4515 is normally closed (NC). These CMOS switches can operate continuously with a single supply between 2 V and 12 V. Each switch can handle rail-to-rail analog signals. The OFF-leakage current maximum is only 1 nA at 25°C or 10 nA at 85°C. All digital inputs have 0.8-V to 2.4-V logic thresholds, ensuring TTL/CMOS-logic compatibility when using a 5-V supply. For pin-compatible parts for use with dual supplies, see the TS12A4516/TS12A4517. ORDERING INFORMATION TA PACKAGE PDIP – P Reel of 1500 TS12A4514D Reel of 2500 TS12A4514DR SOP (SOT-23) – DBV Reel of 3000 TS12A4514DBVR 9CJ_ PDIP – P Reel of 1000 TS12A4515P TS12A4515P Reel of 1500 TS12A4515D Reel of 2500 TS12A4515DR Reel of 3000 TS12A4515DBVR SOP (SOT-23) – DBV (3) TOP-SIDE MARKING (3) TS12A4514P SOIC – D (1) (2) ORDERABLE PART NUMBER Reel of 1000 SOIC – D –40°C to 85°C (1) (2) TS12A4514P YD514 YD515 9CK_ Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. DBV: The last character designates assembly/test Site 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006–2009, Texas Instruments Incorporated TS12A4514,, TS12A4515 SCDS193D – AUGUST 2006 – REVISED MARCH 2009 ................................................................................................................................................... www.ti.com PIN CONFIGURATIONS COM 1 8 NO N.C. 2 7 GND N.C. 3 6 IN V+ 4 5 N.C. INPUT LOW HIGH TS12A4514 SOT-23 PACKAGE (TOP VIEW) TS12A4515 D OR P PACKAGE (TOP VIEW) TS12A4514 D OR P PACKAGE (TOP VIEW) COM 1 8 NC N.C. 2 7 GND N.C. 3 6 IN V+ 4 5 N.C. SWITCH STATE TS12A4514 TS12A4515 OFF ON ON OFF COM 1 NO 2 GND 3 5 4 TS12A4515 SOT-23 PACKAGE (TOP VIEW) V+ IN COM 1 NC 2 GND 3 5 V+ 4 IN MARKNG INFORMATION (SOTs onl y) XX XX LOT SPECIFIC CODE AE = TS12A4514 AF = TS12A4515 N.C. – Not internally connected NO – Normally open NC – Normally closed Absolute Minimum and Maximum Ratings (1) (2) voltages referenced to GND MIN MAX V+ Supply voltage range (3) –0.3 13 V VNC VNO VCOM Analog voltage range (4) –0.3 V+ + 0.3 or ±20 mA V Continuous current into any terminal Peak current, NO or COM (pulsed at 1 ms, 10% duty cycle) ESD per method 3015.7 ±20 mA ±30 mA >2000 Continuous power dissipation (TA = 70°C) UNIT 8-pin plastic DIP (derate 9.09 mW/°C above 70°C) 727 8-pin SOIC (derate 5.88 mW/°C above 70°C) 471 5-pin SOT-23 (derate 7.1 mW/°C above 70°C) 571 V mW TA Operating temperature range –40 85 °C Tstg Storage temperature range –65 150 °C 300 °C Lead temperature (soldering, 10 s) (1) (2) (3) (4) 2 Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum All voltages are with respect to ground, unless otherwise specified. Voltages exceeding V+ or GND on any signal terminal are clamped by internal diodes. Limit forward-diode current to maximum current rating. Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated Product Folder Link(s): TS12A4514 TS12A4515 TS12A4514,, TS12A4515 www.ti.com ................................................................................................................................................... SCDS193D – AUGUST 2006 – REVISED MARCH 2009 Electrical Characteristics for 5-V Supply (1) V+ = 4.5 V to 5.5 V, VINH = 2.4 V, VINL = 0.8 V, TA = –40°C to 85°C (unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS MIN TYP (2) TA MAX UNIT Analog Switch Analog signal range VCOM, VNO, VNC ON-state resistance ron ON-state resistance flatness ron(flat) 0 V+ = 4.5 V, VCOM = 3.5 V, ICOM = 1 mA 25°C VCOM = 1 V, 2 V, 3 V, ICOM = 1 mA 25°C V+ 9.5 Full 15 20 1 3 Full 4 NO, NC OFF leakage current (3) INO(OFF), INC(OFF) V+ = 5.5 V, VCOM = 1 V, VNO or VNC = 4.5 V 25°C 1 Full 10 COM OFF leakage current (3) ICOM(OFF) V+ = 5.5 V, VCOM = 1 V, VNO or VNC = 4.5 V 25°C 1 Full 10 COM ON leakage current (3) ICOM(ON) V+ = 5.5 V, VCOM = 4.5 V, VNO or VNC = 4.5 V 25°C 1 Full 10 V Ω Ω nA nA nA Digital Control Input (IN) Input logic high VIH Full 2.4 V+ V Input logic low VIL Full 0 0.8 V 0.01 µA Input leakage current IIH, IIL VIN = V+, 0 V Full Turn-on time tON see Figure 2 Turn-off time tOFF see Figure 2 Charge injection (4) QC CL = 1 nF, VNO = 0 V, RS = 0 Ω, See Figure 1 25°C –3 pC NO, NC OFF capacitance CNO(OFF), CNC(OFF) f = 1 MHz, See Figure 4 25°C 7.5 pF COM OFF capacitance CCOM(OFF) f = 1 MHz, See Figure 4 25°C 7.5 pF COM ON capacitance CCOM(ON) f = 1 MHz, See Figure 4 25°C 19 pF VIN = V+, 0 V 25°C 1.5 pF 25°C 475 MHz Dynamic Digital input capacitance CI 25°C 32 Full 100 125 25°C 25 Full 50 60 ns ns Bandwidth BW RL = 50 Ω, CL = 15 pF, VNO = 1 VRMS, f = 100 kHz OFF isolation OISO RL = 50 Ω, CL = 15 pF, VNO = 1 VRMS, f = 100 kHz 25°C –94 dB Total harmonic distortion THD RL = 50 Ω, CL = 15 pF, VNO = 1 VRMS, f = 100 kHz 25°C 0.08 % Supply V+ supply current (1) (2) (3) (4) I+ VIN = 0 V or V+ 25°C 0.05 Full 0.1 µA The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum. Typical values are at TA = 25°C. Leakage parameters are 100% tested at maximum-rated hot operating temperature, and are ensured by correlation at 25°C. Specified by design, not production tested Copyright © 2006–2009, Texas Instruments Incorporated Product Folder Link(s): TS12A4514 TS12A4515 Submit Documentation Feedback 3 TS12A4514,, TS12A4515 SCDS193D – AUGUST 2006 – REVISED MARCH 2009 ................................................................................................................................................... www.ti.com Electrical Characteristics for 12-V Supply (1) V+ = 11.4 V to 12.6 V, VINH = 5 V, VINL = 0.8 V, TA = –40°C to 85°C (unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS TA MIN TYP (2) MAX UNIT Analog Switch Analog signal range VCOM, VNO, VNC ON-state resistance ron ON-state resistance flatness ron(flat) 0 V+ = 11.4 V, VCOM = 10 V, ICOM = 1 mA 25°C V+ = 11.4 V, VCOM = 2 V, 5 V, 10 V, ICOM = 1 mA 25°C V+ 6.5 Full 10 15 1.5 V Ω 3 Full 4 NO, NC OFF leakage current (3) INO(OFF), INC(OFF) V+ = 12.6 V, VCOM = 1 V, VNO or VNC = 10 V 25°C 1 Full 10 COM OFF leakage current (3) ICOM(OFF) V+ = 12.6 V, VCOM = 1 V, VNO or VNC = 10 V 25°C 1 Full 10 COM ON leakage current (3) ICOM(ON) V+ = 12.6 V, VCOM = 10 V, VNO or VNC = 10 V 25°C 1 Full 10 Ω nA nA nA Digital Control Input (IN) Input logic high Input logic low Input leakage current VIH VIL Full 5 Full 0 V+ Full V 0.8 V 0.01 µA IIH, IIL VIN = V+, 0 V Turn-on time tON See Figure 2 Turn-off time tOFF See Figure 2 Charge injection (4) QC CL = 1 nF, VNO = 0 V, RS = 0 Ω, See Figure 1 25°C –11.5 pC NO, NC OFF capacitance CNO(OFF) CNC(OFF) f = 1 MHz, See Figure 4 25°C 7.5 pF COM OFF capacitance CCOM(OFF) f = 1 MHz, See Figure 4 25°C 7.5 pF COM ON capacitance CCOM(ON) f = 1 MHz, See Figure 4 25°C 21.5 pF VIN = V+, 0 V 25°C 1.5 pF 25°C 520 MHz Dynamic Digital input capacitance CI 25°C 22 Full 25°C 75 80 20 Full 45 50 ns ns Bandwidth BW RL = 50 Ω, CL = 15 pF, VNO = 1 VRMS, f = 100 kHz OFF isolation OISO RL = 50 Ω, CL = 15 pF, VNO = 1 VRMS, f = 100 kHz 25°C –95 dB Total harmonic distortion THD RL = 50 Ω, CL = 15 pF, VNO = 1 VRMS, f = 100 kHz 25°C 0.07 % Supply V+ supply current (1) (2) (3) (4) 4 I+ VIN = 0 V or V+ 25°C 0.05 Full 0.2 µA The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum. Typical values are at TA = 25°C. Leakage parameters are 100% tested at maximum-rated hot operating temperature, and are ensured by correlation at 25°C. Specified by design, not production tested Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated Product Folder Link(s): TS12A4514 TS12A4515 TS12A4514,, TS12A4515 www.ti.com ................................................................................................................................................... SCDS193D – AUGUST 2006 – REVISED MARCH 2009 Electrical Characteristics for 3-V Supply (1) V+ = 3 V to 3.6 V, TA = –40°C to 85°C (unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS MIN TYP (2) TA MAX UNIT Analog Switch Analog signal range VCOM, VNO, VNC 0 V+ ON-state resistance ron V+ = 3 V, VCOM = 1.5 V, INO = 1 mA, 25°C ON-state resistance flatness V+ = 3 V, VCOM = 1 V, 1.5 V, 2 V, ICOM = 1 mA 25°C ron(flat) NO, NC OFF leakage current (3) INO(OFF), INC(OFF) V+ = 3.6 V, VCOM = 1 V, VNO or VNC = 3 V 25°C 1 Full 10 COM OFF leakage current (3) ICOM(OFF) V+ = 3.6 V, VCOM = 1 V, VNO or VNC = 3 V 25°C 1 Full 10 COM ON leakage current (3) ICOM(ON) V+ = 3.6 V, VCOM = 3 V, VNO or VNC = 3 V 25°C 1 Full 10 18.5 Full 40 50 1 V Ω 3 Full 4 Ω nA nA nA Digital Control Input (IN) Input logic high Input logic low Input leakage current VIH VIL IIH, IIL VIN = V+, 0 V Turn-on time (4) tON See Figure 2 Turn-off time (4) tOFF See Figure 2 Full 2.4 Full 0 V+ Full V 0.8 V 0.01 µA Dynamic Charge injection (4) 25°C 63 Full 120 175 25°C 33 Full 80 120 ns ns QC CL = 1 nF, See Figure 1 25°C –1.5 pC NO, NC OFF capacitance CNO(OFF), CNC(OFF) f = 1 MHz, See Figure 4 25°C 7.5 pF COM OFF capacitance CCOM(OFF) f = 1 MHz, See Figure 4 25°C 7.5 pF COM ON capacitance CCOM(ON) f = 1 MHz, See Figure 4 25°C 17 pF VIN = V+, 0 V 25°C 1.5 pF 25°C 460 MHz Digital input capacitance CI Bandwidth BW RL = 50 Ω, CL = 15 pF, VNO = 1 VRMS, f = 100 kHz OFF isolation OISO RL = 50 Ω, CL = 15 pF, VNO = 1 VRMS, f = 100 kHz 25°C –94 dB Total harmonic distortion THD RL = 50 Ω, CL = 15 pF, VNO = 1 VRMS, f = 100 kHz 25°C 0.15 % Supply V+ supply current (1) (2) (3) (4) I+ VIN = 0 V or V+ 25°C 0.03 Full 0.05 µA The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum. Typical values are at TA = 25°C. Leakage parameters are 100% tested at maximum-rated hot operating temperature, and are ensured by correlation at 25°C. Specified by design, not production tested Copyright © 2006–2009, Texas Instruments Incorporated Product Folder Link(s): TS12A4514 TS12A4515 Submit Documentation Feedback 5 TS12A4514,, TS12A4515 SCDS193D – AUGUST 2006 – REVISED MARCH 2009 ................................................................................................................................................... www.ti.com PIN DESCRIPTION (1) PIN NO. TS12A4514 (1) 6 TS12A4515 D, P SOT-23 NAME D, P SOT-23 DESCRIPTION 1 1 1 1 COM Common 2, 3, 5 – 2, 3, 5 – N.C. No connect (not internally connected) 4 5 4 5 V+ Power supply 6 4 6 4 IN Digital control to connect COM to NO or NC 7 3 7 3 GND Digital ground 8 2 – – NO Normally open – – 8 2 NC Normally closed NO, NC, and COM pins are identical and interchangeable. Any may be considered as an input or an output; signals pass in both directions. Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated Product Folder Link(s): TS12A4514 TS12A4515 TS12A4514,, TS12A4515 www.ti.com ................................................................................................................................................... SCDS193D – AUGUST 2006 – REVISED MARCH 2009 APPLICATION INFORMATION Power-Supply Considerations The TS12A4514/TS12A4515 construction is typical of most CMOS analog switches, except that they have only two supply pins: V+ and GND. V+ and GND drive the internal CMOS switches and set their analog voltage limits. Reverse ESD-protection diodes are internally connected between each analog-signal pin and both V+ and GND. One of these diodes conducts if any analog signal exceeds V+ or GND. Virtually all the analog leakage current comes from the ESD diodes to V+ or GND. Although the ESD diodes on a given signal pin are identical and, therefore, fairly well balanced, they are reverse biased differently. Each is biased by either V+ or GND and the analog signal. This means their leakages will vary as the signal varies. The difference in the two diode leakages to the V+ and GND pins constitutes the analog-signal-path leakage current. All analog leakage current flows between each pin and one of the supply terminals, not to the other switch terminal. This is why both sides of a given switch can show leakage currents of the same or opposite polarity. There is no connection between the analog-signal paths and V+ or GND. V+ and GND also power the internal logic and logic-level translators. The logic-level translators convert the logic levels to switched V+ and GND signals to drive the analog signal gates. Logic-Level Thresholds The logic-level thresholds are CMOS/TTL compatible when V+ is 5 V. As V+ is raised, the level threshold increases slightly. When V+ reaches 12 V, the level threshold is about 3 V – above the TTL-specified high-level minimum of 2.8 V, but still compatible with CMOS outputs. CAUTION: If the user is using the TS12A4514 or TS12A4515 with a V+ supply of 3 V, then the control input (IN) voltage should not exceed V+, otherwise the output levels can exceed 3 V and violate the absolute maximum rating, potentially damaging the device. High-Frequency Performance In 50-Ω systems, signal response is reasonably flat up to 250 MHz (see Typical Operating Characteristics). Above 20 MHz, the on response has several minor peaks that are highly layout dependent. The problem is not in turning the switch on; it is turning it off. The OFF-state switch acts like a capacitor and passes higher frequencies with less attenuation. At 10 MHz, OFF isolation is about –45 dB in 50-Ω systems, decreasing (approximately 20 dB per decade) as frequency increases. Higher circuit impedances also make OFF isolation decrease. OFF isolation is about 3 dB above that of a bare IC socket, and is due entirely to capacitive coupling. Test Circuits/Timing Diagrams V+ V+ NO VNO or VNC = 0 V TS12A4514 TS12A4515 VIN IN COM V+ VIN 0V TS12A4514 VOUT GND ∆VOUT CL 1000 pF 50 Ω TS12A4515 VOUT ∆VOUT is the measured voltage due to charge transfer error Q when the channel turns off. Q = DVOUT x CL Figure 1. Charge Injection Copyright © 2006–2009, Texas Instruments Incorporated Product Folder Link(s): TS12A4514 TS12A4515 Submit Documentation Feedback 7 TS12A4514,, TS12A4515 SCDS193D – AUGUST 2006 – REVISED MARCH 2009 ................................................................................................................................................... www.ti.com V+ V+ V+ NO 0V VNO TS12A4514 VIN IN 50% VIN VNOPEAK COM 90% 90% VOUT VOUT GND 50 Ω 35 pF 300 Ω 0V tOFF tON V+ V+ V+ 0V VNO NC TS12A4515 VIN VNOPEAK COM IN 50% VIN GND 50 Ω 90% VOUT VOUT 35 pF 300 Ω 90% 0V tON tOFF Figure 2. Switching Times V+ V+ 10 nF V+ NO TS12A4514 TS12A4515 VIN VOUT 50 Ω 50 Ω MEAS REF COM IN GND 50 Ω 50 Ω Measurements are standardized against short at socket terminals. OFF isolation is measured between COM and OFF terminals on each switch. ON loss is measured between COM and ON terminals on each switch. Signal direction through switch is reversed; worst values are recorded. OFF Isolation = 20log VOUT VIN ON Loss = 20log VOUT VIN Figure 3. OFF Isolation and ON Loss V+ V+ As Required NO or NC TS12A4514 TS12A4515 IN COM GND 1-MHz Capacitance Analyzer Figure 4. NO, NC, and COM Capacitance 8 Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated Product Folder Link(s): TS12A4514 TS12A4515 PACKAGE OPTION ADDENDUM www.ti.com 18-Aug-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) TS12A4514D ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 YD514 Samples TS12A4514DBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 9CJE Samples TS12A4514DR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 YD514 Samples TS12A4514P ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 TS12A4514P Samples TS12A4515D ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 YD515 Samples TS12A4515DBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 9CKE Samples TS12A4515DR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 YD515 Samples TS12A4515DRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 YD515 Samples TS12A4515P ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 TS12A4515P Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of