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TS3A4751
SCDS227F – JULY 2006 – REVISED MARCH 2015
TS3A4751 0.9-Ω Low-voltage, single-supply, 4-channel spst analog switch
1 Features
3 Description
•
The TS3A4751 device is a bidirectional, 4-channel,
normally open (NO) single-pole single-throw (SPST)
analog switch that operates from a single 1.6-V to
3.6-V supply. This device has fast switching speeds,
handles rail-to-rail analog signals, and consumes very
low quiescent power.
1
•
•
•
•
•
•
•
•
Low ON-State Resistance (RON)
– 0.9 Ω Max (3-V Supply)
– 1.5 Ω Max (1.8-V Supply)
RON Flatness: 0.4 Ω Max (3-V)
RON Channel Matching
– 0.05 Ω Max (3-V Supply)
– 0.15 Ω Max (1.8-V Supply)
1.6-V to 3.6-V Single-Supply Operation
1.8-V CMOS Logic Compatible (3-V Supply)
High Current-Handling Capacity (100 mA
Continuous)
Fast Switching: tON = 5 ns, tOFF = 4 ns
Supports Both Digital and Analog Applications
ESD Protection Exceeds JESD-22
– ±4000-V Human Body Model (A114-A)
– 300-V Machine Model (A115-A)
– ±1000-V Charged-Device Model (C101)
2 Applications
•
•
•
•
•
•
•
•
•
Power Routing
Battery-Powered Systems
Audio and Video Signal Routing
Low-Voltage Data-Acquisition Systems
Communications Circuits
PCMCIA Cards
Cellular Phones
Modems
Hard Drives
The digital input is 1.8-V CMOS compatible when
using a 3-V supply.
The TS3A4751 device has four normally open (NO)
switches. The TS3A4751 is available in a 14-pin thin
shrink small-outline package (TSSOP) and in spacesaving 14-pin VQFN (RGY) and micro X2QFN (RUC)
packages.
Device Information(1)
PART NUMBER
TS3A4751
PACKAGE
BODY SIZE (NOM)
TSSOP (14)
5.00 mm × 4.40 mm
VQFN (14)
3.50 mm × 3.50 mm
X2QFN (14)
2.00 mm × 2.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
SPST
NO1
COM1
IN1
SPST
NO2
COM2
IN2
SPST
NO3
COM3
IN3
SPST
NO4
COM4
IN4
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TS3A4751
SCDS227F – JULY 2006 – REVISED MARCH 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
7
1
1
1
2
3
4
Absolute Maximum Ratings ...................................... 4
ESD Ratings.............................................................. 4
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 5
Electrical Characteristics for 1.8-V Supply................ 6
Electrical Characteristics for 3-V Supply .................. 7
Typical Characteristics ............................................ 10
Detailed Description ............................................ 13
7.1 Overview ................................................................. 13
7.2 Functional Block Diagram ....................................... 13
7.3 Feature Description................................................. 13
7.4 Device Functional Modes........................................ 13
8
Application and Implementation ........................ 14
8.1 Application Information............................................ 14
8.2 Typical Application .................................................. 14
9 Power Supply Recommendations...................... 16
10 Layout................................................................... 16
10.1 Layout Guidelines ................................................. 16
10.2 Layout Example .................................................... 16
11 Device and Documentation Support ................. 17
11.1
11.2
11.3
11.4
11.5
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
17
17
17
17
17
12 Mechanical, Packaging, and Orderable
Information ........................................................... 17
4 Revision History
Changes from Revision E (January 2015) to Revision F
•
Changed Supply Voltage from: 3.3 V to: 3.6 V in the Recommended Operating Conditions ............................................... 5
Changes from Revision D (July 2008) to Revision E
•
2
Page
Page
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
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SCDS227F – JULY 2006 – REVISED MARCH 2015
5 Pin Configuration and Functions
PW PACKAGE
(TOP VIEW)
NO1 1
14
VCC
COM1 2
13
IN1
NO2 3
12
IN4
11 NO4
COM2 4
IN2 5
10
COM4
IN3 6
9
COM3
GND 7
8
NO3
COM2
IN2
IN3
4
5
6
COM1
NO2
2
3
7
GND
8
NO3
9
11
10
IN1
NO4
14
COM4
COM3
Exposed
Center
Pad
12
VCC
1
13
5
IN2
IN3
GND
NO1
6
4
NO2
COM2
7
2
1
NO3
IN4
COM4
COM3
10
9
IN4
NO4
11
IN1
13
Exposed
Center
Pad
3
NO1
RGY PACKAGE
(BOTTOM VIEW)
8
14
COM1
VCC
12
RGY PACKAGE
(TOP VIEW)
If the exposed center pad is used, it must be connected as a
secondary ground or left electrically open.
NO1
COM1
NO2
COM2
IN2
3
4
5
11
10
9
8
NO4
COM4
COM3
NO3
GND
12
7
IN4
13
5
IN1
IN2
IN3
COM2
6
3
IN3
14
4
6
VCC
NO2
14
2
GND
COM1
7
1
13
NO1
IN1
VCC
2
NO3
8
RUC PACKAGE
(BOTTOM VIEW)
1
COM4
COM3
9
NO4
11
10
IN4
12
RUC PACKAGE
(TOP VIEW)
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SCDS227F – JULY 2006 – REVISED MARCH 2015
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Pin Functions
PIN
NO.
NAME
I/O
DESCRIPTION
1
NO1
I/O
Normally open signal path
2
COM1
I/O
Common signal path
3
NO2
I/O
Normally open signal path
4
COM2
I/O
Common signal path
5
IN2
I
Logic control input
6
IN3
I
Logic control input
7
GND
—
Ground
8
NO3
I/O
Normally open signal path
9
COM3
I/O
Common signal path
10
COM4
I/O
Common signal path
11
NO4
I/O
Normally open signal path
12
IN4
I
Logic control input
13
IN1
I
Logic control input
14
VCC
I
Positive supply voltage
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
(2)
VCC
Supply voltage referenced to GND
VNO
VCOM
VIN
Analog and digital voltage
INO
ICOM
On-state switch current
ICC
IGND
Continuous current through VCC or GND
V
Peak current pulsed at 1 ms, 10% duty cycle
TA
Operating temperature
TJ
Junction temperature
Tstg
Storage temperature
(1)
(2)
VNO, VCOM = 0 to VCC
MIN
MAX
UNIT
–0.3
4
V
–0.3
VCC + 0.3
V
–100
100
mA
±100
mA
±200
mA
85
°C
150
°C
150
°C
COM, VI/O
–40
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Signals on COM or NO exceeding VCC or GND are clamped by internal diodes. Limit forward diode current to maximum current rating.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
4
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±4000
Charged-device model (CDM), per JEDEC specification JESD22-C101
or ANSI/ESDA/JEDEC JS-002 (2)
±1000
Machine Model
±300
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VCC
Supply Voltage
VNO
VCOM
VIN
Analog and digital voltage range
MIN
MAX
UNIT
1.65
3.6
V
0
VCC
V
6.4 Thermal Information
TS3A4751
THERMAL METRIC
(1)
PW
RGY
RUC
UNIT
14 PINS
RθJA
Junction-to-ambient thermal resistance
132.3
68.5
196.4
RθJC(top)
Junction-to-case (top) thermal resistance
60.6
83.1
73.9
RθJB
Junction-to-board thermal resistance
74.2
44.6
130.7
ψJT
Junction-to-top characterization parameter
11.2
7.8
2.1
ψJB
Junction-to-board characterization parameter
73.6
44.7
130.6
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
24.6
N/A
(1)
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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SCDS227F – JULY 2006 – REVISED MARCH 2015
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6.5 Electrical Characteristics for 1.8-V Supply
VCC = 1.65 V to 1.95 V, TA = –40°C to 85°C, VIH = 1 V, VIL = 0.4 V (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
TA
(2)
MIN
TYP (3)
MAX
UNIT
VCC
V
ANALOG SWITCH
VCOM, VNO
Analog signal range
0
Ron
ON-state resistance
VCC = 1.8 V, ICOM = –10 mA,
VNO = 0.9 V
25°C
1
ΔRon
ON-state resistance match
between channels (4)
VCC = 1.8 V, ICOM = –10 mA,
VNO = 0.9 V
25°C
Ron(flat)
ON-state resistance
flatness (5)
VCC = 1.8 V, ICOM = –10 mA,
0 ≤ VNO ≤ VCC
25°C
INO(OFF)
NO
OFF leakage current (6)
VCC = 1.95 V, VCOM = 0.15 V, 1.65 V,
VNO = 1.8 V, 0.15 V
25°C
–1
Full
–10
ICOM(OFF)
COM
OFF leakage current (6)
VCC = 1.95 V, VCOM = 0.15 V, 1.65 V,
VNO = 1.65 V, 0.15 V
25°C
–1
Full
–10
ICOM(ON)
COM
ON leakage current (6)
VCC = 1.95 V, VCOM = 0.15 V, 1.65 V,
VNO = 0.15 V, 1.65 V, or floating
25°C
–1
Full
–3
tON
Turn-on time
VNO = 1.5 V, RL = 50 Ω,
CL = 35 pF, See Figure 1
25°C
tOFF
Turn-off time
VNO = 1.5 V, RL = 50 Ω,
CL = 35 pF, See Figure 1
25°C
QC
Charge injection
VGEN = 0, RGEN = 0, CL = 1 nF,
See Figure 5
25°C
3.2
pC
CNO(OFF)
NO OFF capacitance
f = 1 MHz, See Figure 2
25°C
23
pF
CCOM(OFF)
COM OFF capacitance
f = 1 MHz, See Figure 2
25°C
20
pF
CCOM(ON)
COM ON capacitance
f = 1 MHz, See Figure 2
25°C
43
pF
BW
Bandwidth
RL = 50 Ω, Switch ON
25°C
123
MHz
OISO
OFF isolation (7)
RL = 50 Ω, CL = 5 pF,
See Figure 3
f = 1 MHz
XTALK
Crosstalk
RL = 50 Ω, CL = 5 pF,
See Figure 3
f = 10 MHz
THD
Total harmonic distortion
f = 20 Hz to 20 kHz, VCOM
= 2 VP-P
RL = 32 Ω
Full
1.5
2
0.09
Full
0.15
0.25
0.7
Full
0.9
1.5
0.5
1
10
0.5
1
10
0.01
1
3
Ω
Ω
Ω
nA
nA
nA
DYNAMIC
6
Full
20
5
Full
f = 10 MHz
f = 100 MHz
RL = 600 Ω
18
10
12
–61
25°C
ns
dB
–36
–95
25°C
ns
dB
–73
0.14%
25°C
0.013%
DIGITAL CONTROL INPUTS (IN1–IN4)
VIH
Input logic high
Full
VIL
Input logic low
Full
IIN
Input leakage current
VI = 0 or VCC
1
25°C
Full
V
0.4
0.1
–10
5
10
V
nA
SUPPLY
VCC
ICC
(1)
(2)
(3)
(4)
(5)
(6)
(7)
6
Power-supply range
Positive-supply current
1.6
VI = 0 or VCC
3.6
25°C
0.05
Full
0.5
V
μA
The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum.
Parts are tested at 85°C and specified by design and correlation over the full temperature range.
Typical values are at TA = 25°C.
Δron = ron(max) – ron(min)
Flatness is defined as the difference between the maximum and minimum value of ron as measured over the specified analog signal
ranges.
Leakage parameters are 100% tested at the maximum-rated hot operating temperature and specified by correlation at TA = 25°C.
OFF isolation = 20log10 (VCOM/VNO), VCOM = output, VNO = input to OFF switch
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6.6 Electrical Characteristics for 3-V Supply
VCC = 2.7 V to 3.6 V, TA = –40°C to 85°C, VIH = 1.4 V, VIL = 0.5 V (unless otherwise noted). (1)
PARAMETER
TEST CONDITIONS
TA
(2)
MIN
TYP (3)
MAX
UNIT
VCC
V
ANALOG SWITCH
VCOM, VNO
Analog signal range
0
Ron
ON-state resistance
VCC = 2.7 V, ICOM = –100 mA,
VNO = 1.5 V
25°C
0.7
ΔRon
ON-state resistance match
between channels (4)
VCC = 2.7 V, ICOM = –100 mA,
VNO = 1.5 V
25°C
Ron(flat)
ON-state resistance
flatness (5)
VCC = 2.7 V, ICOM = –100 mA,
VNO = 1 V, 1.5 V, 2 V
25°C
INO(OFF)
NO
OFF leakage current (6)
VCC = 3.6 V, VCOM = 0.3 V, 3 V,
VNO = 3 V, 0.3 V
25°C
–2
Full
–18
ICOM(OFF)
COM
OFF leakage current (6)
VCC = 3.6 V, VCOM = 0.3 V, 3 V,
VNO = 3 V, 0.3 V
25°C
–2
Full
–18
ICOM(ON)
COM
ON leakage current (6)
VCC = 3.6 V, VCOM = 0.3 V, 3 V,
VNO = 0.3 V, 3 V, or floating
25°C
–2.5
tON
Turn-on time
VNO = 1.5 V, RL = 50 Ω,
CL = 35 pF, See Figure 1
25°C
tOFF
Turn-off time
VNO = 1.5 V, RL = 50 Ω,
CL = 35 pF, See Figure 1
25°C
QC
Charge injection
VGEN = 0, RGEN = 0, CL = 1 nF,
See Figure 5
25°C
3
pC
CNO(OFF)
NO OFF capacitance
f = 1 MHz, See Figure 2
25°C
23
pF
CCOM(OFF)
COM OFF capacitance
f = 1 MHz, See Figure 2
25°C
20
pF
CCOM(ON)
COM ON capacitance
f = 1 MHz, See Figure 2
25°C
43
pF
BW
Bandwidth
RL = 50 Ω, Switch ON
25°C
125
MHz
OISO
OFF isolation (7)
RL = 50 Ω, CL = 5 pF,
See Figure 3
f = 10 MHz
XTALK
Crosstalk
RL = 50 Ω, CL = 5 pF,
See Figure 3
f = 10 MHz
THD
Total harmonic distortion
f = 20 Hz to 20 kHz,
VCOM = 2 VP-P
RL = 32 Ω
Full
1.1
0.03
Full
0.05
0.15
0.23
Full
Full
0.9
0.4
0.5
1
2
18
1
2
18
0.01
–5
2.5
5
Ω
Ω
Ω
nA
nA
nA
DYNAMIC
5
Full
15
4
Full
f = 1 MHz
f = 1 MHz
RL = 600 Ω
14
9
10
–40
25°C
ns
dB
–62
–73
25°C
ns
dB
–95
0.04%
25°C
0.003%
DIGITAL CONTROL INPUTS (IN1–IN4)
VIH
Input logic high
Full
VIL
Input logic low
Full
IIN
Input leakage current
VI = 0 or VCC
1.4
25°C
Full
V
0.5
0.5
–20
1
20
V
nA
SUPPLY
VCC
ICC
(1)
(2)
(3)
(4)
(5)
(6)
(7)
Power-supply range
Positive-supply current
1.6
VCC = 3.6 V, VIN = 0 or VCC
3.6
25°C
0.075
Full
0.75
V
μA
The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum.
Parts are tested at 85°C and specified by design and correlation over the full temperature range.
Typical values are at VCC = 3 V, TA = 25°C.
Δron = ron(max) – ron(min)
Flatness is defined as the difference between the maximum and minimum value of ron as measured over the specified analog signal
ranges.
Leakage parameters are 100% tested at the maximum-rated hot operating temperature and specified by correlation at TA = 25°C.
OFF isolation = 20log10 (VCOM/VNO), VCOM = output, VNO = input to OFF switch
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VCC
VCC
IN
NO
tR < 5 ns
tF < 5 ns
VIH + 0.5 V
VNO
IN
VCOM
COM
VNO
VCOM
35 pF
50W
50%
50%
0
90%
90%
0
a
GND
tON
tOFF
Figure 1. Switching Times
VCC
VCC
NO
1-MHz
Capacitance
Analyzer
As
Required
IN
COM
GND
Figure 2. NO and COM Capacitance
VCC
0.1 µF
Network
Analyzer
VCC
VI
50Ω
50Ω
Meas
Ref
NO
(1)
VO
VCC
IN
COM
GND
Measurements are standardized against
short at socket terminals. OFF isolation is
measured between COM and OFF terminals
on each switch. Bandwidth is measured between
COM and ON terminals on each switch. Signal
direction through switch is reversed; worst
values are recorded.
50W50Ω
OFF isolation = 20 log VO/VI
(1)
Add 50-Ω termination for
OFF isolation
Figure 3. OFF Isolation, Bandwidth, and Crosstalk
8
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Channel ON: COM to NO
VSOURCE = VCC P-P
VI = VCC
fSOURCE = 20 Hz to 20 kHz
CL = 50 pF
RL = 600Ω
VCC
Audio Analyzer
NO
Signal
Source
600Ω
COM
CL(A)
IN
600Ω
-VCC
A.
CL includes probe and jig capacitance.
Figure 4. Total Harmonic Distortion (THD)
VCC
VCC
RGEN
NO
VGEN
VI
IN
a
VI
VO
COM
GND
CL
1000 pF
V+
0
VO
ΔVO
Figure 5. Charge Injection (QC)
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6.7 Typical Characteristics
1.6
1.6
1.4
1.4
1.2
1.2
V+ = 1.8 V
R on (Ω)
R on (Ω)
1.0
0.8
0.6
V+ = 2.7 V
1.0
0.8
–40°C
0.6
0.4
0.4
0.2
0.2
0.0
0.0
0.5
1.0
1.5
85°C
25°C
2.0
2.5
3.0
0.0
0.0
0.5
VCOM (V)
25°C
0.5
0.4
0.3
–40°C
0.2
0.1
0.0
0.0
INC/COM (pA)
R on (Ω)
1000.00
100.00
1.00
0.5
1.0
1.5
VCOM (V)
2.0
2.5
−40°C
25 85
TA (°C)
Figure 9. ION and IOFF vs Temperature
(VCC = 3.6 V)
3.0
30
°C
7
V+ = 3 V
6
tON/tOFF (ns)
25
QC (pC)
°C
8
35
20
15
V+ = 1.8 V
10
5
5
tON
4
3
tOFF
2
1
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0
1.6
2.0
VCOM (V)
Figure 10. QC vs VCOM
10
COM (ON)
10.00
Figure 8. Ron vs VCOM (VCC = 2.7 V)
0
0.0
2.0
NC/NO (OFF)
85°C
0.7
0.6
1.5
VCOM (V)
Figure 7. Ron vs VCOM (VCC = 1.8 V)
Figure 6. Ron vs VCOM
1.0
0.9
0.8
1.0
2.4
2.8
3.2
3.6
4.0
V+ (V)
Figure 11. tON and tOFF vs Supply Voltage
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Typical Characteristics (continued)
7
1000.000
tON = 1.8 V
855C
100.000
5
255C
10.000
ICC (nA)
tON/tOFF (ns)
6
4
3
tOFF = 1.8 V
tON = 3 V
tOFF = 3 V
2
1.000
–405C
0.100
0.010
1
0.001
0.0
0
−40°C
25°C
TA (°C)
85°C
0.5
1.0
1.5
2.0
2.5
3.0
3.5
V+ (V)
Figure 13. ICC vs VCC
Figure 12. tON and tOFF vs Temperature
0
0
−2
−10
−20
Attenuation (dB)
Gain (dB)
−4
−6
−8
−10
−12
−40
−50
−60
−70
−80
−14
0.1
−30
−90
1
10
Frequency (MHz)
100
1000
0.1
Figure 14. Gain vs Frequency
(VCC = 3 V)
1
10
Frequency (MHz)
100
1000
Figure 15. OFF Isolation vs Frequency
(VCC = 3 V)
0.042
0.0040
0.0036
0.041
0.0032
0.0028
THD (%)
THD (%)
0.040
0.039
0.038
0.0024
0.0020
0.0016
0.0012
0.0008
0.037
0.0004
0.036
0
10
100
1K
Frequency (kHz)
10K
100K
Figure 16. Total Harmonic Distortion vs Frequency
(RL = 32 Ω)
0.0000
0
10
100
1K
Frequency (kHz)
10K
100K
Figure 17. Total Harmonic Distortion vs Frequency
(RL = 600 Ω)
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Typical Characteristics (continued)
0
Attenuation (dB)
−20
−40
−60
−80
−100
−120
0
0.1
1
10
Frequency (MHz)
100
1000
Figure 18. Crosstalk vs Frequency (VCC = 3 V)
12
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7 Detailed Description
7.1 Overview
The TS3A4751 is a bidirectional, 4-channel, normally open (NO) single-pole single-throw (SPST) analog switch
that operates from a single 1.6-V to 3.6-V supply. This device has fast switching speeds, handles rail-to-rail
analog signals, and consumes very low quiescent power.
The digital input is 1.8-V CMOS compatible when using a 3-V supply.
The TS3A4751 has four normally open (NO) switches. The TS3A4751 is available in a 14-pin thin shrink smalloutline package (TSSOP) and in space-saving 14-pin VQFN (RGY) and micro X2QFN (RUC) packages.
7.2 Functional Block Diagram
SPST
NO1
COM1
IN1
SPST
NO2
COM2
IN2
SPST
NO3
COM3
IN3
SPST
NO4
COM4
IN4
7.3 Feature Description
This device has fast switching speeds, handles rail-to-rail analog signals, and consumes very low quiescent
power.
The digital input is 1.8-V TTL/CMOS compatible when using a 3-V supply.
7.4 Device Functional Modes
Table 1. Function Table
IN
NO TO COM,
COM TO NO
L
OFF
H
ON
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 Logic Inputs
The TS3A4751 logic inputs can be driven up to 3.6 V, regardless of the supply voltage. For example, with a 1.8V supply, IN may be driven low to GND and high to 3.6 V. Driving IN rail to rail minimizes power consumption.
8.1.2 Analog Signal Levels
Analog signals that range over the entire supply voltage (VCC to GND) can be passed with very little change in
Ron (see Typical Characteristics). The switches are bidirectional, so NO and COM can be used as either inputs
or outputs.
8.2 Typical Application
3.3 V
0.1 µF
0.1 µF
System
Controller
Switch
Control
Logic
VCC
SPST switch
IN1
IN2
IN3
IN4
Device 1
NO1
3.3 V
0.1 µF
COM1
COM2
Signal
Path
NO2
Device 1
3.3 V
0.1 µF
COM3
COM4
Device 1
NO3
3.3 V
0.1 µF
Device 1
NO4
GND
3.3 V
0.1 µF
Figure 19. Typical Application Diagram
14
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Typical Application (continued)
8.2.1 Design Requirements
Ensure that all of the signals passing through the switch are with in the specified ranges to ensure proper
performance.
8.2.2 Detailed Design Procedure
The TS3A4751 and can be properly operated without any external components. However, it is recommended
that unused pins should be connected to ground through a 50-Ω resistor to prevent signal reflections back into
the device. It is also recommneded that the digital control pins (INX) be pulled up to VCC or down to GND to
avoid undesired switch positions that could result from the floating pin.
8.2.3 Application Curve
1.6
1.4
1.2
V+ = 1.8 V
R on (Ω)
1.0
0.8
0.6
V+ = 2.7 V
0.4
0.2
0.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
VCOM (V)
Figure 20. Ron vs VCOM
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9 Power Supply Recommendations
Proper power-supply sequencing is recommended for all CMOS devices. Do not exceed the absolute maximum
ratings because stresses beyond the listed ratings can cause permanent damage to the devices. Always
sequence VCC on first, followed by NO or COM.
Although it is not required, power-supply bypassing improves noise margin and prevents switching noise
propagation from the VCC supply to other components. A 0.1-μF capacitor, connected from VCC to GND, is
adequate for most applications.
10 Layout
10.1 Layout Guidelines
High-speed switches require proper layout and design procedures for optimum performance.
Reduce stray inductance and capacitance by keeping traces short and wide.
Ensure that bypass capacitors are as close to the device as possible.
Use large ground planes where possible.
10.2 Layout Example
Figure 21. Layout Schematic
16
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11 Device and Documentation Support
11.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TS3A4751PWR
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
YC751
TS3A4751PWRG4
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
YC751
TS3A4751RGYR
ACTIVE
VQFN
RGY
14
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
YC751
TS3A4751RUCR
ACTIVE
QFN
RUC
14
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
3MO
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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