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TS3A5017
SCDS188G – JANUARY 2005 – REVISED JANUARY 2019
TS3A5017 Dual SP4T Analog Switch / Multiplexer / Demultiplexer
1 Features
3 Description
•
•
•
•
•
•
•
The TS3A5017 device is a dual single-pole
quadruple-throw (4:1) analog switch that is designed
to operate from 2.3 V to 3.6 V. This device can
handle both digital and analog signals, and signals up
to V+ can be transmitted in either direction.
1
•
Isolation in the Powered-Down Mode, V+ = 0
Low ON-State Resistance
Low Charge Injection
Excellent ON-State Resistance Matching
Low Total Harmonic Distortion (THD)
2.3-V to 3.6-V Single-Supply Operation
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Performance Tested Per JESD 22
– 1500-V Human-Body Model
(A114-B, Class II)
– 1000-V Charged-Device Model (C101)
PART NUMBER
TS3A5017
PACKAGE
BODY SIZE (NOM)
SOIC (16)
9.90 mm × 3.90 mm
SSOP (16)
4.90 mm × 3.90 mm
TSSOP (16)
5.00 mm × 4.40 mm
TVSOP (16)
4.40 mm × 3.60 mm
UQFN (16)
2.50 mm × 1.80 mm
VQFN (16)
4.00 mm × 3.50 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
•
•
•
•
Device Information(1)
Sample-and-Hold Circuits
Battery-Powered Equipment
Audio and Video Signal Routing
Communication Circuits
Block Diagram
EN
IN1
IN2
D
S1
S2
S3
S4
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TS3A5017
SCDS188G – JANUARY 2005 – REVISED JANUARY 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
4
4
4
4
5
6
7
7
8
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics for 3.3-V Supply................
Electrical Characteristics for 2.5-V Supply................
Switching Characteristics for 3.3-V supply................
Switching Characteristics for 2.5-V supply................
Typical Characteristics ..............................................
Parameter Measurement Information ................ 10
Detailed Description ............................................ 14
8.1 Overview ................................................................. 14
8.2 Functional Block Diagram ....................................... 14
8.3 Feature Description................................................. 14
8.4 Device Functional Modes........................................ 15
9
Application and Implementation ........................ 16
9.1 Application Information............................................ 16
9.2 Typical Application ................................................. 16
10 Power Supply Recommendations ..................... 17
11 Layout................................................................... 17
11.1 Layout Guidelines ................................................. 17
11.2 Layout Example .................................................... 18
12 Device and Documentation Support ................. 19
12.1
12.2
12.3
12.4
12.5
Device Support......................................................
Documentation Support ........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
19
20
20
20
20
13 Mechanical, Packaging, and Orderable
Information ........................................................... 21
4 Revision History
Changes from Revision F (October 2018) to Revision G
Page
•
Changed Feature From: 2000-V Human-Body Model To: 1500-V Human-Body Model ....................................................... 1
•
Changed the HBM value From: ±2000 V To: ±1500 V in the ESD Ratings........................................................................... 4
Changes from Revision E (April 2015) to Revision F
•
Page
Changed the XTALK MAX value From:–49 dB To – 69 dB in the Electrical Characteristics for 3.3-V Supply......................... 6
Changes from Revision D (December 2008) to Revision E
Page
•
Added Applications, Device Information table, Pin Functions table, ESD Ratings table, Thermal Information table,
Typical Characteristics, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
•
Deleted Ordering Information table. ....................................................................................................................................... 1
2
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SCDS188G – JANUARY 2005 – REVISED JANUARY 2019
5 Pin Configuration and Functions
D, DBQ, DGV, and PW Package
16-Pin SOIC, SSOP, TVSOP and TSSOP
(Top View)
Logic
Control
Logic
Control
RGY Package
16-Pin VQFN
(Top View)
16 V+
1EN
V+
1
16
1EN
1
IN2
2
15 2EN
1S4
3
14 IN1
IN2
2
15
2EN
1S3
4
13 2S4
1S4
3
14
IN1
1S2
5
12 2S3
13
2S4
12
2S3
1S1
6
1D
7
GND
11 2S2
10 2S1
8
9
Exposed
Center
Pad
1S3
4
1S2
5
1S1
6
11
2S2
1D
7
10
2S1
2D
8
9
GND
2D
If exposed center pad is used, it must be
connected as a secondary ground or left
electrically open.
IN2
1EN
V+
2EN
RSV Package
16-Pin UQFN
(Top View)
16
15
13
14
11
IN1
2S4
1S2
3
10
2S3
1S1
4
9
2S2
5
6
7
2D
2S1
12
2
1D
1
1S3
GND
1S4
8
Pin Functions
PIN
NAME
SOIC, SSOP, TVSOP,
TSSOP, VQFN NO.
UQFN NO.
TYPE
DESCRIPTION
1D
7
5
I/O
1EN
1
15
I
Common path for switch 1
1S1
6
4
I/O
Switch 1 channel 1
1S2
5
3
I/O
Switch 1 channel 2
1S3
4
2
I/O
Switch 1 channel 3
1S4
3
1
I/O
Switch 1 channel 4
2D
9
7
I/O
Common path for switch 2
2EN
15
13
I
2S1
10
8
I/O
Switch 2 channel 1
2S2
11
9
I/O
Switch 2 channel 2
2S3
12
10
I/O
Switch 2 channel 3
2S4
13
11
I/O
Switch 2 channel 4
GND
8
6
–
Ground
IN1
14
12
I
Switch 1 input select
IN2
2
16
I
Switch 2 input select
V+
16
14
–
Supply voltage
Active-low enable for switch 1
Active-low enable for switch 2
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2)
Supply voltage (3)
V+
VS, VD Analog voltage
(3) (4)
MIN
MAX
UNIT
–0.5
4.6
V
–0.5
4.6
V
ISK,
IDK
Analog port clamp current
VS, VD < 0
–50
IS, ID
ON-state switch current
VS, VD = 0 to 7 V
–128
128
VI
Digital input voltage
–0.5
4.6
IIK
Digital input clamp current (3) (4)
I+
Continuous current through V+
IGND
Continuous current through GND
–100
Tstg
Storage temperature
–65
(1)
(2)
(3)
(4)
VI < 0
mA
mA
V
–50
mA
100
mA
mA
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum.
All voltages are with respect to ground, unless otherwise specified.
The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±1500
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VI/O
Switch input/output voltage range
V+
Supply voltage range
VI
Control input voltage range
TA
Operating Temperature Range
MIN
MAX
UNIT
0
3.6
V
2.3
3.6
V
0
3.6
V
–40
85
°C
6.4 Thermal Information
TS3A5018
THERMAL METRIC
RθJA
(1)
4
(1)
Junction-to-ambient thermal resistance
D (SOIC)
DBQ
(SSOP)
DGV
(TVSOP)
PW
(TSSOP)
RGY
(VQFN)
RSV (UQFN)
16 PINS
16 PINS
16 PINS
16 PINS
16 PINS
16 PINS
73
82
120
108
91.6
184
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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6.5 Electrical Characteristics for 3.3-V Supply
V+ = 2.7 V to 3.6 V, TA = –40°C to 85°C (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
TA
V+
MIN
TYP MAX
0
V+
UNIT
Analog Switch
VD, VS
Analog signal
range
ron
ON-state
resistance
0 ≤ VS ≤ V+,
ID = –32 mA,
Switch ON,
see Figure 12
Δron
ON-state
resistance
match
between
channels
VS = 2.1 V,
ID = –32 mA,
Switch ON,
see Figure 12
ron(flat)
ON-state
resistance
flatness
0 ≤ VS ≤ V+,
ID = –32 mA,
Switch ON,
see Figure 12
IS(OFF)
ISPWR(OFF)
ID(OFF)
IDPWR(OFF)
S
OFF leakage
current
D
OFF leakage
current
25°C
Full
11
3V
14
25°C
VS = 1 V, VD = 3 V,
or
VS = 3 V, VD = 1 V,
Full
1
3V
7
3V
25°C
Switch OFF,
see Figure 13
VS = 0 to 3.6 V,
VD = 3.6 V to 0,
Full
25°C
Full
VS = 1 V, VD = 3 V,
or
VS = 3 V, VD = 1 V,
0V
25°C
Switch OFF,
see Figure 13
VD = 0 to 3.6 V,
VS = 3.6 V to 0,
Full
25°C
Full
IS(ON)
S
ON leakage
current
VS = 1 V, VD = Open,
or
VS = 3 V, VD = Open,
Switch ON,
see Figure 14
ID(ON)
D
ON leakage
current
VD = 1 V, VS = Open,
or
VD = 3 V, VS = Open,
Switch ON,
see Figure 14
0V
25°C
Full
–1
3.6 V
1
0.05
0.1
μA
5
0.2
0.5
1
0.05
0.1
–5
μA
5
–0.2
–0.1
3.6 V
0.5
–0.2
–1
Ω
0.1
0.2
–5
–0.1
25°C
Full
–0.2
–0.1
3.6 V
0.05
Ω
9
10
–0.1
3.6 V
Ω
2
3
25°C
Full
12
V
0.2
0.05
–0.2
μA
0.1
0.2
μA
Digital Control Inputs (IN1, IN2, EN) (2)
VIH
Input logic high
Full
2
V+
V
VIL
Input logic low
Full
0
0.8
V
Input leakage
current
VI = V+ or 0
25°C
–1
Charge injection
VGEN = 0, RGEN = 0,
CL = 0.1 nF,
See Figure 21
25°C
3.3 V
5
pC
CS(OFF)
S
OFF
capacitance
VS = V+ or GND,
Switch OFF,
See Figure 15
25°C
3.3 V
4.5
pF
CD(OFF)
D
OFF
capacitance
VD = V+ or GND,
Switch OFF,
See Figure 15
25°C
3.3 V
19
pF
CS(ON)
S
VS = V+ or GND,
ON capacitance Switch ON,
See Figure 15
25°C
3.3 V
25
pF
CD(ON)
D
VD = V+ or GND,
ON capacitance Switch ON,
See Figure 15
25°C
3.3 V
25
pF
Digital input
capacitance
VI = V+ or GND,
See Figure 15
25°C
3.3 V
2
pF
BW
Bandwidth
RL = 50 Ω,
Switch ON,
See Figure 17
25°C
3.3 V
165
MHz
OISO
OFF isolation
RL = 50 Ω,
f = 1 MHz,
See Figure 18
25°C
3.3 V
–69
dB
IIH, IIL
QC
CI
(1)
(2)
Full
3.6 V
0.05
–1
1
1
μA
The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum
All unused digital inputs of the device must be held at V+ or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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Electrical Characteristics for 3.3-V Supply (continued)
V+ = 2.7 V to 3.6 V, TA = –40°C to 85°C (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
TA
V+
MIN
TYP MAX
UNIT
XTALK
Crosstalk
RL = 50 Ω,
f = 1 MHz,
See Figure 19
25°C
3.3 V
–-69
dB
XTALK(ADJ)
Crosstalk
adjacent
RL = 50 Ω,
f = 1 MHz,
See Figure 20
25°C
3.3 V
–74
dB
Total harmonic
distortion
RL = 600 Ω,
CL = 50 pF,
f = 20 Hz to 20 kHz,
see Figure 22
25°C
3.3 V
0.21%
Positive supply
current
VI = V+ or GND,
Switch ON or OFF
THD
Supply
I+
25°C
2.5
3.6 V
Full
7
10
μA
6.6 Electrical Characteristics for 2.5-V Supply
V+ = 2.3 V to 2.7 V, TA = –40°C to 85°C (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
TA
V+
MIN
TYP MAX
0
V+
UNIT
Analog Switch
VD, VS
Analog signal
range
ON-state
resistance
0 ≤ VS ≤ V+,
ID = –24 mA,
Switch ON,
see Figure 12
Δron
ON-state
resistance match
between channels
VS = 1.6 V,
ID = –24 mA,
Switch ON,
see Figure 12
ron(flat)
ON-state
resistance flatness
0 ≤ VS ≤ V+,
ID = –24 mA,
Switch ON,
see Figure 12
ron
IS(OFF)
ISPWR(OFF)
ID(OFF)
IDPWR(OFF)
S
OFF leakage
current
D
OFF leakage
current
VS = 0.5 V, VD = 2.2 V,
or
VS = 2.2 V, VD = 0.5 V,
VS = 0 to 2.7 V,
VD = 2.7 V to 0,
25°C
Full
Full
25°C
Full
Full
25°C
Full
VS = 0.5 V, VD = 2.2 V,
or
VS = 2.2 V, VD = 0.5V,
VD = 0 to 2.7 V,
VS = 2.7 V to 0,
1
2.3 V
0V
Full
25°C
Full
IS(ON)
S
ON leakage
current
VS = 0.5 V, VD = Open,
or
VS = 2.2 V, VD = Open,
Switch ON,
see Figure 14
ID(ON)
D
ON leakage
current
VD = 0.5 V, VS = Open,
or
VD = 2.2 V, VS = Open,
Switch ON,
see Figure 14
0V
25°C
Full
25°C
Full
–1
1
0.05
0.1
Ω
μA
5
0.2
0.5
1
0.05
0.1
–5
μA
5
–0.2
–0.1
2.7 V
0.5
–0.2
–1
Ω
0.1
0.2
–5
–0.1
2.7 V
0.05
–0.2
–0.1
2.7 V
18
20
–0.1
25°C
Switch OFF,
see Figure 13
16
Ω
2
3
2.3 V
2.7 V
22
24
25°C
25°C
Switch OFF,
see Figure 13
20.5
2.3 V
V
0.2
0.05
μA
0.1
μA
–0.2
0.2
1.7
V+
V
0.7
V
Digital Control Inputs (IN1, IN2, EN) (2)
(1)
(2)
6
VIH
Input logic high
Full
VIL
Input logic low
Full
0
IIH, IIL
Input leakage
current
VI = V+ or 0
25°C
–1
QC
Charge injection
VGEN = 0, RGEN = 0,
CL = 0.1 nF,
See Figure 21
25°C
2.5 V
CS(OFF)
S
OFF capacitance
VS = V+ or GND,
Switch OFF,
See Figure 15
25°C
2.5 V
Full
2.7 V
0.05
–1
1
1
μA
pC
4.5
pF
The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum
All unused digital inputs of the device must be held at V+ or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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Electrical Characteristics for 2.5-V Supply (continued)
V+ = 2.3 V to 2.7 V, TA = –40°C to 85°C (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
TA
V+
MIN
TYP MAX
UNIT
CD(OFF)
D
OFF capacitance
VD = V+ or GND,
Switch OFF,
See Figure 15
25°C
2.5 V
18.5
pF
CS(ON)
S
ON capacitance
VS = V+ or GND,
Switch ON,
See Figure 15
25°C
2.5 V
24
pF
CD(ON)
D
ON capacitance
VD = V+ or GND,
Switch ON,
See Figure 15
25°C
2.5 V
24
pF
Digital input
capacitance
VI = V+ or GND,
See Figure 15
25°C
2.5 V
2
pF
BW
Bandwidth
RL = 50 Ω,
Switch ON,
See Figure 17
25°C
2.5 V
165
MHz
OISO
OFF isolation
RL = 50 Ω,
f = 1 MHz,
See Figure 18
25°C
2.5 V
–69
dB
XTALK
Crosstalk
RL = 50 Ω,
f = 1 MHz,
See Figure 19
25°C
2.5 V
–69
dB
Crosstalk adjacent
RL = 50 Ω,
f = 1 MHz,
See Figure 20
25°C
2.5 V
–74
dB
Total harmonic
distortion
RL = 600 Ω,
CL = 50 pF,
f = 20 Hz to 20 kHz,
see Figure 22
25°C
2.5 V
0.29%
Positive supply
current
VI = V+ or GND,
Switch ON or OFF
CI
XTALK(ADJ)
THD
Supply
I+
25°C
Full
2.5
2.7 V
7
10
μA
6.7 Switching Characteristics for 3.3-V supply
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
tON
Turnon time
VD = 2 V,
RL = 300 Ω,
CL = 35 pF,
see Figure 16
tOFF
Turnoff time
VD =2 V,
RL = 300 Ω,
CL = 35 pF,
see Figure 16
TA
V+
MIN
TYP
MAX
25°C
3.3 V
1
5
9.5
Full
3 V to
3.6 V
1
25°C
3.3 V
0.5
Full
3 V to
3.6 V
0.5
TA
V+
MIN
TYP
MAX
25°C
2.5 V
1.5
5
8
Full
2.3 V to
2.7 V
10.5
1.5
UNIT
ns
3.5
4.5
ns
6.8 Switching Characteristics for 2.5-V supply
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
tON
Turnon time
VCOM = 2 V,
RL = 300 Ω,
CL = 35 pF,
see Figure 16
tOFF
Turnoff time
VCOM =2 V,
RL = 300 Ω,
CL = 35 pF,
see Figure 16
1
25°C
2.5 V
0.3
Full
2.3 V to
2.7 V
0.3
10
2
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ns
4.5
6
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UNIT
ns
7
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6.9 Typical Characteristics
18
12
TA = 25°C
16
10
V+ = 2.5 V
14
85°C
rON (Ω)
12
8
rON (Ω)
10
8
6
25°C
6
4
V+ = 3.3 V
4
–40°C
2
2
0
0
1
3
2
0
0.0
4
0.5
1.0
VCOM (V)
Figure 1. ron vs VCOM
1.5
2.0
VCOM (V)
INC(ON)
Leakage Current (nA)
14
rON (Ω)
12
85°C
10
25°C
6
4
2
0
0.0
–40°C
ICOM(ON)
30
INO(ON)
20
10
INO(OFF)
0
0.5
1.0
1.5
2.0
2.5
3.0
–40
Figure 3. ron vs VCOM (V+ = 2.5 V)
25
TA (°C)
85
Figure 4. Leakage Current vs Temperature (V+ = 3.6 V)
9
4.5
4.0
8
V+ = 3.3 V
3.0
6
2.5
tON /tOFF (ns)
3.5
7
V+ = 2.5 V
2.0
1.5
4
3
2
0.5
1
0.5
1.0
2.0
1.5
VCOM (V)
2.5
3.0
3.5
tON
5
1.0
0.0
0.0
ICOM(OFF)
INC(OFF)
VCOM (V)
Charge Injection (pC)
3.5
40
16
0
2.0
tOFF
2.5
3.0
3.5
4.0
V+ (V)
Figure 5. Charge Injection (QC) vs VCOM
8
3.0
Figure 2. ron vs VCOM (V+ = 3.3 V)
18
8
2.5
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Figure 6. tON and tOFF vs Supply Voltage
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Typical Characteristics (continued)
2.0
Logic-Level Threshold (nA)
1.8
1.6
VIH
1.4
VIL
1.2
1.0
0.8
0.6
0.4
0.2
0.0
2.0
2.2 2.4
2.6
2.8
3.0 3.2 3.4
V+ (V)
3.6
3.8
4.0
Figure 7. Logic-Level Threshold vs V+
Figure 8. Bandwidth (Gain vs Frequency) (V+ = 3.3 V)
0.35
THD (%)
0.30
0.25
0.20
0.15
0.10
10
100
1000
Frequency (Hz)
10 K
100 K
Figure 10. Total Harmonic Distortion vs Frequency
(µA)
Figure 9. OFF Isolation and Crosstalk vs Frequency
(V+ = 3.3 V)
(°C)
Figure 11. Power-Supply Current vs Temperature
(V+ = 3.6 V)
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7 Parameter Measurement Information
Channel ON
V – VS2-S4 or Vs1
ron = D
Ω
ID
VI = VIH or VIL
Figure 12. ON-State Resistance (ron)
OFF-State Leakage Current
Channel OFF
VI = VIH or VIL
VS1 or VS2-S4 = 0 to V+
and
VD = V+ to 0
Figure 13. OFF-State Leakage Current (ID(OFF), IS(OFF))
ON-State Leakage Current
Channel ON
VI = VIH or VIL
Figure 14. ON-State Leakage Current (ID(ON), IS(ON))
10
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Parameter Measurement Information (continued)
VBIAS = V+ to GND
VI = VIH or VIL
Capacitance is measured at S1,
S2-S4, D, and IN inputs during
ON and OFF conditions.
Figure 15. Capacitance (CI, CD(OFF), CD(ON), CS(OFF), CS(ON))
CL
300 Ω
35 pF
300 Ω
35 pF
(C)
(B)
V+
(B)
0
(A)
tOFF
A.
All
input
pulses
are
supplied
PRR ≤ 10 MHz, ZO = 50 Ω, tr < 5 ns, tf < 5 ns.
B.
CL includes probe and jig capacitance.
C.
See Electrical Characteristics for VD.
by
generators
having
the
following
characteristics:
Figure 16. Turnon (tON) and Turnoff Time (tOFF)
Channel ON: S1 to D
VI = V+ or GND
50 Ω
Network Analyzer Setup
Source Power = 0 dBm
(632-mV P-P at 50-Ω load)
50 Ω
DC Bias = 350 mV
Figure 17. Bandwidth (BW)
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Parameter Measurement Information (continued)
Channel OFF: S to D
VI = V+ or GND
50 Ω
50 Ω
Network Analyzer Setup
Source Power = 0 dBm
(632-mV P-P at 50-Ω load)
50 Ω
DC Bias = 350 mV
Figure 18. OFF Isolation (OISO)
Channel ON: S1 to D
Channel OFF: S2-S4 to D
VI = V+ or GND
50 Ω
VS2-S4
Network Analyzer Setup
50 Ω
50 Ω
Source Power = 0 dBm
(632-mV P-P at 50-Ω load)
DC Bias = 350 mV
Figure 19. Crosstalk (XTALK)
50 Ω
V1S
Channel ON: S1 to D
1S1
1D
V2S 2S1
50 Ω
Network Analyzer Setup
2D
Source Power = 0 dBm
(632-mV P-P at 50-Ω load)
50 Ω
DC Bias = 350 mV
Figure 20. Adjacent Crosstalk (XTALK)
12
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Parameter Measurement Information (continued)
VIH
VIL
Δ VD
VGEN = 0 to V+
RGEN = 0
CL = 0.1 nF
QC = CL X Δ VD
VI = VIH or VIL
A.
All
input
pulses
are
supplied
PRR ≤ 10 MHz, ZO = 50 Ω, tr < 5 ns, tf < 5 ns.
B.
CL includes probe and jig capacitance.
by
generators
having
the
following
characteristics:
Figure 21. Charge Injection (QC)
10 µF
10 µF
600 Ω
(A)
600 Ω
600 Ω
A.
CL includes probe and jig capacitance.
Figure 22. Total Harmonic Distortion (THD)
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8 Detailed Description
8.1 Overview
The TS3A5017 is a dual Single-Pole-4-Throw (SP4T) solid-state analog switch. The TS3A5017, like all analog
switches, is bidirectional. Each D pin connects to its four respective S pins, with the switch connection dependent
on the status of EN, IN2, and IN1. See Table 1 for the switch configuration truth table.
8.2 Functional Block Diagram
EN
IN1
IN2
D
S1
S2
S3
S4
Figure 23. Functional Block Diagram (Each Switch)
8.3 Feature Description
Isolation in powered-down mode allows signals to be present at the inputs while the switch is powered off without
causing damage to the device. The low ON-state resistance and low charge injection give the TS3A5017 better
performance at higher speeds.
14
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8.4 Device Functional Modes
Table 1. Function Table
IN1
D TO S,
S TO D
L
L
D = S1
L
H
D = S2
L
H
L
D = S3
L
H
H
D = S4
H
X
X
OFF
EN
IN2
L
L
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TS3A5018 can be used in a variety of customer systems. The TS3A5018 can be used anywhere multiple
analog or digital signals must be selected to pass across a single line.
9.2 Typical Application
3.3 V
V+
C or System
Logic
EN
S1
IN1
S2
IN2
S3
D
S4
To/From
System
GND
Figure 24. System Schematic for TS3A5017
9.2.1 Design Requirements
In this particular application, V+ was 3.3 V, although V+ is allowed to be any voltage specified in Recommended
Operating Conditions. A decoupling capacitor is recommended on the V+ pin. See Power Supply
Recommendations for more details.
9.2.2 Detailed Design Procedure
In this application, EN, IN1, and IN2 are, by default, pulled low to GND. Choose these resistor sizes based on
the current driving strength of the GPIO, the desired power consumption, and the switching frequency (if
applicable). If the GPIO is open-drain, use pullup resistors instead.
16
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Typical Application (continued)
9.2.3 Application Curve
5.0
4.5
tON /tOFF (ns)
4.0
tON
3.5
3.0
2.5
2.0
tOFF
1.5
1.0
0.5
0.0
–40
25
85
TA (°C)
Figure 25. tON and tOFF vs Temperature (V+ = 3.3 V)
10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions.
Each VCC terminal should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, a 0.1-μF bypass capacitor is recommended. If there are multiple pins labeled VCC, then a 0.01-μF or
0.022-μF capacitor is recommended for each VCC because the VCC pins will be tied together internally. For
devices with dual-supply pins operating at different voltages, for example VCC and VDD, a 0.1-µF bypass
capacitor is recommended for each supply pin. It is acceptable to parallel multiple bypass capacitors to reject
different frequencies of noise. 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor
should be installed as close to the power terminal as possible for best results.
11 Layout
11.1 Layout Guidelines
Reflections and matching are closely related to loop antenna theory, but different enough to warrant their own
discussion. When a PCB trace turns a corner at a 90° angle, a reflection can occur. This is primarily due to the
change of width of the trace. At the apex of the turn, the trace width is increased to 1.414 times its width. This
upsets the transmission line characteristics, especially the distributed capacitance and self–inductance of the
trace — resulting in the reflection. It is a given that not all PCB traces can be straight, and so they will have to
turn corners. Below figure shows progressively better techniques of rounding corners. Only the last example
maintains constant trace width and minimizes reflections.
Unused switch I/Os, such as NO, NC, and COM, can be left floating or tied to GND. However, the IN1, IN2, and
EN pins must be driven high or low. Due to partial transistor turnon when control inputs are at threshold levels,
floating control inputs can cause increased ICC or unknown switch selection states. See Implications of Slow or
Floating CMOS Inputs, SCBA004 for more details.
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11.2 Layout Example
BETTER
BEST
2W
WORST
1W min.
W
Figure 26. Trace Example
18
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Device Nomenclature
Table 2. Parameter Description
SYMBOL
VCOM
DESCRIPTION
Voltage at COM
VNC
Voltage at NC
VNO
Voltage at NO
ron
Δron
ron(flat)
Resistance between COM and NC or NO ports when the channel is ON
Difference of ron between channels in a specific device
Difference between the maximum and minimum value of ron in a channel over the specified range of conditions
INC(OFF)
Leakage current measured at the NC port, with the corresponding channel (NC to COM) in the OFF state
INC(ON)
Leakage current measured at the NC port, with the corresponding channel (NC to COM) in the ON state and the output
(COM) open
INO(OFF)
Leakage current measured at the NO port, with the corresponding channel (NO to COM) in the OFF state
INO(ON)
Leakage current measured at the NO port, with the corresponding channel (NO to COM) in the ON state and the output
(COM) open
ICOM(OFF)
Leakage current measured at the COM port, with the corresponding channel (COM to NC or NO) in the OFF state
ICOM(ON)
Leakage current measured at the COM port, with the corresponding channel (COM to NC or NO) in the ON state and the
output (NC or NO) open
VIH
Minimum input voltage for logic high for the control input (IN, EN)
VIL
Maximum input voltage for logic low for the control input (IN, EN)
VI
Voltage at the control input (IN, EN)
IIH, IIL
Leakage current measured at the control input (IN, EN)
tON
Turnon time for the switch. This parameter is measured under the specified range of conditions and by the propagation
delay between the digital control (IN) signal and analog output NC or NO) signal when the switch is turning ON.
tOFF
Turnoff time for the switch. This parameter is measured under the specified range of conditions and by the propagation
delay between the digital control (IN) signal and analog output (NC or NO) signal when the switch is turning OFF.
QC
Charge injection is a measurement of unwanted signal coupling from the control (IN) input to the analog (NC or NO)
output. This is measured in coulomb (C) and measured by the total charge induced due to switching of the control input.
Charge injection, QC = CL × ΔVCOM, CL is the load capacitance and ΔVCOM is the change in analog output voltage.
CNC(OFF)
Capacitance at the NC port when the corresponding channel (NC to COM) is OFF
CNC(ON)
Capacitance at the NC port when the corresponding channel (NC to COM) is ON
CNO(OFF)
Capacitance at the NC port when the corresponding channel (NO to COM) is OFF
CNO(ON)
Capacitance at the NC port when the corresponding channel (NO to COM) is ON
CCOM(OFF)
Capacitance at the COM port when the corresponding channel (COM to NC) is OFF
CCOM(ON)
Capacitance at the COM port when the corresponding channel (COM to NC) is ON
CI
Capacitance of control input (IN, EN)
OISO
OFF isolation of the switch is a measurement of OFF-state switch impedance. This is measured in dB in a specific
frequency, with the corresponding channel (NC to COM) in the OFF state.
XTALK
Crosstalk is a measurement of unwanted signal coupling from an ON channel to an OFF channel (NC1 to NO1). Adjacent
crosstalk is a measure of unwanted signal coupling from an ON channel to an adjacent ON channel (NC1 to NC2) .This is
measured in a specific frequency and in dB.
BW
Bandwidth of the switch. This is the frequency in which the gain of an ON channel is –3 dB below the DC gain.
THD
Total harmonic distortion describes the signal distortion caused by the analog switch. This is defined as the ratio of root
mean square (RMS) value of the second, third, and higher harmonic to the absolute magnitude of the fundamental
harmonic.
I+
Static power-supply current with the control (IN) pin at V+ or GND
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12.2 Documentation Support
12.2.1 Related Documentation
•
Implications of Slow or Floating CMOS Inputs, SCBA004
12.3 Trademarks
All trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
20
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13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TS3A5017D
ACTIVE
SOIC
D
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TS3A5017
Samples
TS3A5017DBQR
ACTIVE
SSOP
DBQ
16
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
YA017
Samples
TS3A5017DGVR
ACTIVE
TVSOP
DGV
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
YA017
Samples
TS3A5017DR
ACTIVE
SOIC
D
16
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TS3A5017
Samples
TS3A5017PW
ACTIVE
TSSOP
PW
16
90
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
YA017
Samples
TS3A5017PWR
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
YA017
Samples
TS3A5017PWRG4
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
YA017
Samples
TS3A5017RGYR
ACTIVE
VQFN
RGY
16
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
YA017
Samples
TS3A5017RGYRG4
ACTIVE
VQFN
RGY
16
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
YA017
Samples
TS3A5017RSVR
ACTIVE
UQFN
RSV
16
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
ZVL
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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