TS3DDR32611
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SCDS347A – AUGUST 2013 – REVISED SEPTEMBER 2013
1A Peak Sink/Source PCDDR3 Termination Regulator with Integrated Isolation Switch and
Low Power Mode Operation
Check for Samples: TS3DDR32611
FEATURES
DESCRIPTION
•
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The TS3DDR32611 is a sink/source double data rate
type III (PCDDR3) termination regulator with a 1%
accuracy buffered reference output. It has built-in
termination SPST switches that can be disconnected
when the memory system undergoes lower speed
operation without the need of voltage termination.
Turning off these switches enables significant power
saving on the memory system. The switches on-state
resistance has a typical value of only 1.75Ω which
helps retain signal integrity on the signal lines.
1
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•
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VDD Range – 3.0V to 3.6V
RON 1.75Ω typical
Channel Count – 26
VDDQ – Input Voltage 1.2V to 3.5V
VTT – VDDQ/2 typical with 1A sink/source
capability
VREF – VDDQ/2±1% × VDDQ
Switch Time – (TON/OFF) 100ns Max
IDD Supply Current
– High Speed Mode (IDD,HS) 220 µA Max
– Low Speed Mode (IDD,LS) 220 µA Max
– Power Down Mode (IDD,PD) 5 µA Max
Special Features
– 1.8-V Compatible Control Inputs (VTT_EN,
ODT_EN)
– High current Sinking/Sourcing Capability:
1A Max
48-Ball ZQC Package (4mm x 4mm, 0.5mm
pitch)
The TS3DDR32611 is powered from a 3.3V supply.
The VDDQ pin takes 1.2V to 1.8V input while the
output voltage at VTT pin is tracking 1/2 × VDDQ. The
regulator’s VTT output is capable of sinking/sourcing
up to 1A current, while the VREF pin output is
1/2VDDQ±1%
×
VDDQ
with
5mA
current
sinking/sourcing capability. The TS3DDR32611 has 4
modes of operation: high speed, low speed, VREF
mode and power down mode, depending on the
control signals VTT_EN and ODT_EN. These
different modes of operation provide flexibility to
establish a memory system’s performance and power
consumption.
APPLICATIONS
•
Double Data Rate type 3 (PCDDR3) termination
and regulation in mobile devices
The TS3DDR32611 is situated within a small 48 balls
BGA package with only 4mm x 4mm in size, which
makes it a perfect candidate to be used in mobile
applications.
SWITCH DIAGRAM
TS3DDR32611
VLDOIN
VDDQ
VREF
VTT
Regulator
VTT
VTTSNS
VTT_EN
OBT_EN
3.3V
Supply
VDD
GND
PGND
RESET_N
CKE1
CKE0
CH25
CH24
CH23
CH22
CH21
CH19
CH20
CH18
CH17
CH15
CH16
CH14
CH13
CH12
CH11
CH10
CH9
CH7
CH8
CH6
CH5
CH3
CH4
CH2
CH1
CH0
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
TS3DDR32611
SCDS347A – AUGUST 2013 – REVISED SEPTEMBER 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DIE SIZE: 4.0 mm × 4.0 mm
BUMP PITCH: 0.5 mm
7
6
5
4
G
CH5
CH9
CH13
CH17
F
CH3
CH7
CH11
E
CH1
GND
GND
3
1
2
3
4
G
VDDQ
VDD
CH22
CH17
VLDO
IN
F
VLDO
IN
CH23
CH21
VTT
VTT
E
VTT
VTT
NC
VTT
SNS
D
VTT
SNS
NC
PGND
C
PGND
CH24
VTT
EN
B
VTT
EN
CH24
CH25
ODT
EN
A
ODT
EN
CH25
2
1
CH22
VDD
VDDQ
CH15
CH21
CH23
GND
GND
D
CH0
GND
GND
GND
C
CH2
GND
GND
GND
B
CH4
CH8
CH12
CH16
GND
VTT
REF
5
6
7
CH13
CH9
CH5
CH15
CH11
CH7
CH3
GND
GND
GND
GND
CH1
GND
GND
GND
GND
CH0
GND
GND
GND
CH2
CH20
CH16
CH12
CH8
CH4
CH19
CH18
CH14
CH10
CH6
Switch I/O
GND
LDO Power
VTT
REF
LDO I/O
A
CH6
CH10
CH14
CH18
CH20
CH19
Control
NC
TS3DDR32611 Pin Mapping (1)
(1)
7
6
5
4
3
2
1
G
CH5
CH9
CH13
CH17
CH22
VDD
VDDQ
F
CH3
CH7
CH11
CH15
CH21
CH23
VLODIN
E
CH1
GND
GND
GND
GND
VTT
VTT
D
CH0
GND
GND
GND
GND
NC
VTTSNS
C
CH2
GND
GND
GND
VREF
PGND
B
CH4
CH8
CH12
CH16
CH20
CH24
VTT_EN
A
CH6
CH10
CH14
CH18
CH19
CH25
ODT_EN
The NC must be floating, and cannot be connected to anything.
PIN FUNCTIONS
PIN
NO.
NAME
TYPE
C4, C5, C6, D3, D4, D5,
GND
D6, E3, E4, E5, E6
E1, E2
—
Signal Ground
VTT
O
Power output for VTT LDO, need to connect 10-μF or greater MLCC for stability
C1
PGND
—
Power GND for VTT LDO
D1
VTTSNS
I
VTT LDO voltage sense input
F1
VLDOIN
I
Power supply input for VTT/ VTTREF
C2
VREF
O
VREF buffered reference output. Need to connect 0.22-μF or greater MLCC for stability.
B1
VTT_EN
I
Enable signal for VTT and VREF output
A1
ODT_EN
I
Enable signal for Switch
G1
VDDQ
I
VDDQ input, reference input for VREF
G2
VDD
I
Device power supply input 3.3 V typical
D7, E7, C7, F7, B7, G7,
A7, F6, B6, G6, A6, F5,
B5, G5, A5, F4, B4, G4,
A4, A3, B3, F3, G3, F2,
B2, A2
D2
2
DESCRIPTION
CH0-CH25
I/O
Switch input or output
NC
—
Not connected, must be floating and cannot be connected to any signal
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SCDS347A – AUGUST 2013 – REVISED SEPTEMBER 2013
FUNCTION TABLE
STATE
Power Down mode
(1)
(2)
VTT_EN (1)
ODT_EN (1)
VTT
VREF
SWITCH
(2)
L
L
OFF(Discharge)
OFF(Discharge)
Disabled
Low Speed mode
H
L
ON
ON
Disabled
High Speed mode
H
H
ON
ON
Enabled
The VTT_EN and ODT_EN pins has 6MΩ weak pull-down resistor to GND to make its default value to be LOW.
For VTT_EN= L and ODE_EN= H, the TS3DDR32611 will also stays in the power down mode. However, there will be an increased
leakage current of up to max 25µA depending on the voltage level of ODT_EN and is thus not a recommended setting to use.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
(2)
MIN
MAX
VDD
Supply voltage range (3)
–0.3
5.5
V
VCTRL
Control input (VTT_EN, ODT_EN) voltage range (3)
–0.3
5.5
V
VDDQ
VDDQ input voltage range (3)
–0.3
3.6
V
(3)
UNIT
VLDOIN
VLDOIN input voltage range
–0.3
3.6
V
VTT, VREF
VTT, VREF output voltage range (3)
–0.3
3.6
V
VTTSNS
VTTSNS input voltage range (3)
–0.3
3.6
V
(3)
–0.3
0.3
V
2
kV
500
V
PGND
PGND input voltage range
HBM
Electrostatic discharge QSS 009-105 (JESD22-A114A)
CDM
Electrostatic discharge QSS 009-147 (JESD22-C101B.01)
TJ
Junction temperature
–40
125
°C
TA
Operating free-air temperature
–55
150
°C
(1)
(2)
(3)
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum.
All voltages are with respect to GND, unless otherwise specified.
PACKAGE THERMAL IMPEDANCE (1)
θJA
(1)
(2)
Package thermal impedance
ZQC package
TYP
UNIT
101 (2)
°C/W
The package thermal impedance is calculated in accordance with JESD 51-7.
69.2°C/W With 4 Central GND vias when layout.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
(1)
VDD
Supply voltage range
VCTRL
Control input (VTT_EN, ODT_EN) voltage range (1)
VDDQ
VDDQ input voltage range (1)
(1)
MIN
MAX
UNIT
3.0
3.6
V
0
3.6
V
1.2
1.5
V
VLDOIN
VLDOIN input voltage range
VTT+0.4
1.5
V
VTT, VREF
VTT, VREF output voltage range (1)
0
0.75
V
VTTSNS
VTTSNS input voltage range (1)
0
0.75
V
(1)
–0.1
0.1
V
–40
85
°C
PGND
PGND input voltage range
TA
Operating free-air temperature
(1)
All voltages are with respect to GND, unless otherwise specified.
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ELECTRICAL CHARACTERISTICS
TA = –40°C to 85°C, Typical values are at VDD = 3.3V, TA = 25°C, (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
IVDD(HS)
VDD supply current in high
speed mode (1)
VDD = 3.3V
No load, VTT_EN=ODT_EN= 1.8V,
VDDQ=1.5 V
150
220
µA
IVDD(LS)
VDD supply current in low
speed mode (1)
VDD = 3.3V
No load, VTT_EN=1.8V,
ODT_EN= 0V, VDDQ=1.5V
150
220
µA
IVDD(PD)
VDD supply current in power
down mode (1)
VDD = 3.3V
No load, VTT_EN=0V,ODT_EN= 0V,
VDDQ=1.5V
1
5
µA
IVLDOIN
VLDOIN supply current in high or
low speed mode
VDD = 3.3V
No load, VTT_EN=H, ODT_EN= H or
L, VDDQ=1.5V
1
5
µA
IVLDOIN(PD)
VLDOIN supply current in power
down mode
VDD = 3.3V
No load, VTT_EN=L, ODT_EN=H or
L, VDDQ=1.5V
1
5
µA
VTT OUTPUT
VTT
Output voltage
Output voltage tolerance to
1/2VDDQ
VTTTOL
VDDQ/2
VDDQ = 1.25V,
1.35V, 1.5V
V
|IVTT|< 60 mA
-20
±15
20
|IVTT|< 550 mA
-35
±25
35
|IVTT|< 1 A
-60
±35
60
mV
IVTT(SRC)
Source current limit
VDDQ = 1.5 V
VTT=VTTSNS=0.6 V
1000
mA
IVTT(SINK)
Sink current limit
VDDQ = 1.5 V
VTT=VTTSNS=0.9 V
1000
mA
Max Source or Sink current
capability
VDDQ = 1.5 V
VTT=VTTSNS=0 V
1.5
A
VTT Discharge current
VDDQ = 0 V
VTT_EN=L, ODT_EN=H or L,
VTT = 0.5 V, TA=25°C
10
mA
VTTSNS Input Bias current
VTTSNS=VREF
No load, VTT_EN=H, ODT_EN= H
0.1
µA
IVTT(max)
IVTT(DIS)
IVTTSNS(BIAS)
–0.1
VREF OUTPUT
VREF
Output voltage
VREFTOL
Output voltage tolerance to
1/2VDDQ
VDDQ = 1.25V,
1.35V, 1.5V
|IVREF|< 5 mA
IVREF(SRC)
Source current limit
VDDQ = 1.5V
VREF=0 V
10
mA
IVREF(SINK)
Sink current limit
VDDQ = 0V
VREF=1.5 V
10
mA
VREF Discharge current
VDDQ = 0V
VTT_EN=L,ODT_EN=H or L,
VREF=0.5 V, TA = 25°C
VDDQ input current
VDDQ = 1.5V
VVREF(DIS)
VDDQ/2
V
1.0%*VDD
-1.0%*VDDQ
mV
Q
2
mA
40
µA
VDDQ INPUT
IVDDQ
30
ISOLATION SWITCH
RON
RON,
FLAT
ΔRON
ON-state resistance
VDD = 3.3V
VI/O = 0.75 V, |IVTT|= 18 mA
1.75
4
Ω
ON-state resistance flatness
VDD = 3.3V
VI/O = 0 V to 0.75 V, |IVTT|= 18 mA
0.2
0.4
Ω
ON-state resistance match
between channels
VDD = 3.3V
VI/O = 0.75 V, |IVTT|= 18 mA
0.2
Ω
DIGITAL CONTROL INPUTS (VTT_EN, ODT_EN)
VIH
Input logic high
VDD = 3.0 V to 3.6 V
VIL
Input logic low
VDD = 3.0 V to 3.6 V
VLHYST
Hysteresis voltage
ILK
Input leak current
1.3
V
0.6
V
1
µA
0.5
–1
V
OVER-TEMPERATURE PROTECTION
TOTP
(1)
4
Over temperature protection
Shutdown temperature
Hysteresis
150
30
°C
For ODT_EN and VTT_EN, If the VIH is less than 1.8V but more than Max VIH, or VIL is more than 0V but less than Max VIL, it will cause
the IVDD has the max 25µA increase based on the voltage at ODT_EN and VTT_EN.
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SCDS347A – AUGUST 2013 – REVISED SEPTEMBER 2013
DYNAMIC CHARACTERISTICS
TA = –40°C to 85°C, Typical values are at VCC = 3.3V, TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
tON /OFF
Switching time between low
speed and high speed mode
RL = 50Ω, CL = 5pF
VDD = 3.0 V to 3.6 V
100
ns
tRAMP(VTT)
VTT ramp time
CVTT= 20 µF
VDD = 3.0V to 3.6V,
IVTT=0
50
µs
tRAMP(VREF)
VREF ramp time
CVREF= 220 nF
VDD = 3.0V to 3.6V,
IVREF =0
30
µs
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0.78
0.71
0.77
0.7
0.76
0.69
VTT Voltage (V)
VTT Voltage (V)
TYPICAL CHARACTERISTICS
0.75
0.74
0.73
0.68
0.67
0.66
0.72
0.65
0.71
0.64
0.7
±1000
0
±500
500
0.63
±1000
1000
VTT Current (mA)
500
1000
VTT Current (mA)
C001
Figure 1. VTT Load Regulation (0.75V)
C002
Figure 2. VTT Load Regulation (0.675V)
0.66
0.760
0.65
0.758
0.756
VREF Voltage (V)
0.64
VTT Voltage (V)
0
±500
0.63
0.62
0.61
0.6
0.754
0.752
0.750
0.748
0.746
0.744
0.59
0.742
0.58
±1000
0.740
0
±500
500
1000
VTT Current (mA)
±5
±3
±1
1
3
VREF Current (mA)
C003
Figure 3. VTT Load Regulation (0.625V)
5
C004
Figure 4. VREF Load Regulation (0.75V)
0.635
0.685
0.683
0.630
0.679
VREF Voltage (V)
VREF Voltage (V)
0.681
0.677
0.675
0.673
0.671
0.625
0.620
0.669
0.667
0.665
0.615
±5
±3
±1
1
3
VREF Current (mA)
±5
±3
±1
1
3
VREF Current (mA)
C005
Figure 5. VREF Load Regulation (0.675V)
6
5
5
C006
Figure 6. VREF Load Regulation (0.625V)
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TYPICAL CHARACTERISTICS (continued)
Figure 7. Start-up Waveform for VTT (Power-down to High
Speed)
Figure 8. Start-up Waveform for VREF (Power-down to High
Speed)
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REVISION HISTORY
Changes from Original (August 2013) to Revision A
•
8
Page
Added TYPICAL CHARACTERISTICS section. ................................................................................................................... 6
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PACKAGE OPTION ADDENDUM
www.ti.com
17-Nov-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TS3DDR32611ZQCR
OBSOLETE
BGA
MICROSTAR
JUNIOR
ZQC
48
TBD
Call TI
Call TI
XSL2611
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
