TS3DV621
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SCDS330C – JANUARY 2012 – REVISED MAY 2013
12-Channel 1:2 MUX/DEMUX Switch with Integrated 4-Channel Sideband Signal Switching
for DVI/HDMI and DisplayPort (DP) Applications
Check for Samples: TS3DV621
FEATURES
APPLICATIONS
•
•
•
•
1
•
•
•
•
•
•
•
•
•
•
Switch Type: 2:1 or 1:2
Data Rate Compatibility
– HDMI v1.4
– DVI 1.0
– DisplayPort 1.1a
Bandwidth (-3dB) – 2.2 GHz
RON – 8 Ω
CON – 5.6 pF
VCC Range – 3.0V–3.6 V
I/O Voltage Range – 0–5 V
Bit-to-Bit Skew – 6 ps Typical
Propagation Delay – 40 ps Typical
Special Features
– Dedicated Enable Logic Supports Hi-Z
Mode
– IOFF Protection Prevents Current Leakage in
Powered Down State (VCC = 0 V)
ESD Performance
– 2kV Human Body Model (A114B, Class II)
– 1kV Charged Device Model (C101)
42-pin QFN Package (9 x 3.5 mm, 0.5 mm
Pitch)
DVI/HDMI/DisplayPort Signal Switching
General Purpose TMDS/LVDS Signal Switching
spacer
DESCRIPTION
The TS3DV621 is a 1:2 or 2:1 bi-directional
multiplexer/demultiplexer with a integrated 4 sideband control channel (DDC, AUX, CEC, or HPD)
signal switcher. Operating from a 3 to 3.6V supply,
the TS3DV621 offers low and flat ON-state resistance
as well as low I/O capacitance, which allows the
TS3DV621 to achieve a typical bandwidth of 2.2
GHz. The device provides the high bandwidth
necessary for HDMI, DVI, and DisplayPort
applications. The TS3DV621 expands the high-speed
physical link interface from a single HDMI port to two
HDMI ports (A or B port) or vise-versa. It can also be
used for DisplayPort (DP) source/sink applications.
The integrated side-band control channels allow 5V
signals to pass through, making the TS3DV621
suitable for HDMI applications.
The most common application for the TS3DV621 is
the sink application. In this case, there are two
possible sources (DVD, set-top box, or game
console) that are routed to one receiver. The
unselected port is in the high-impedance mode, such
that the receiver receives information from only one
source. HDCP encryption is passed through the
switch for the receiver to decode.
ORDERING INFORMATION
For package and ordering information, see the Package Option Addendum at the end of this document.
Primary HDMI Source
Sideband
Channel
Graphic
Display
Processor
Secondary Source
DDC & CEC or
Aux & HPD
Channel
Video Imaging
HDMI Receiver
Processor
Primary Source
DDC & CEC or
Aux & HPD
TS3DV621
Secondary HDMI or
DisplayPort Source
Data
Figure 1. Multiplexing Dual Video Input Source (HDMI/DisplayPort)
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012–2013, Texas Instruments Incorporated
TS3DV621
SCDS330C – JANUARY 2012 – REVISED MAY 2013
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PIN FUNCTIONS
VCC
D0+B
D0+A
D0–B
D0–A
42
41
40
39
PIN
38
1
DESCRIPTION
NO.
VCC
1,17, 30
Power
Supply Voltage
GND
PowerPad
Ground
Ground
EN
8
I
Enable Input
SEL1
9
I
Select Input 1
SEL2
10
I
Select Input 2
D0+A
41
I/O
Port A, Lane 0, +ve signal
D0+
2
37
D1+B
D0–
3
36
D1–A
D1+
4
35
D1–B
D0-A
39
I/O
Port A, Lane 0, -ve signal
D1–
5
34
D2+A
D1+A
38
I/O
Port A, Lane 1, +ve signal
D2+
6
33
D2+B
D1-A
36
I/O
Port A, Lane 1, -ve signal
D2–
7
32
D2–A
D2+A
34
I/O
Port A, Lane 2, +ve signal
EN
8
31
D2–B
D2-A
32
I/O
Port A, Lane 2, -ve signal
GND
SEL1
9
30
VCC
D3+A
29
I/O
Port A, Lane 3, +ve signal
SEL2
10
29
D3+A
D3-A
27
I/O
Port A, Lane 3, -ve signal
42
I/O
Port B, Lane 0, +ve signal
D3+
11
28
D3+B
D0+B
D3–
12
27
D3–A
D0-B
40
I/O
Port B, Lane 0, -ve signal
D3–B
D1+B
37
I/O
Port B, Lane 1, +ve signal
35
I/O
Port B, Lane 1, -ve signal
13
AUX–
14
25
AUX+A
D1-B
HPD
15
24
AUX+B
D2+B
33
I/O
Port B, Lane 2, +ve signal
D2-B
31
I/O
Port B, Lane 2, -ve signal
D3+B
28
I/O
Port B, Lane 3, +ve signal
21
26
D3-B
26
I/O
Port B, Lane 3, -ve signal
HPDA
AUX+
D0+
2
I/O
Common Port, Lane 0, +ve signal
D0–
3
I/O
Common Port, Lane 0, -ve signal
D1+
4
I/O
Common Port, Lane 1, +ve signal
D1–
5
I/O
Common Port, Lane 1, -ve signal
D2+
6
I/O
Common Port, Lane 2, +ve signal
D2–
7
I/O
Common Port, Lane 2, -ve signal
D3+
11
I/O
Common Port, Lane 3, +ve signal
D3-
12
I/O
Common Port, Lane 3, -ve signal
AUX+A
25
I/O
+ve AUX Channel for Port A
AUX-A
23
I/O
-ve AUX Channel for Port A
HPDA
21
I/O
Port A HPD
CECA
19
I/O
Port A CEC
AUX+B
24
I/O
+ve AUX Channel for Port B
AUX-B
22
I/O
-ve AUX Channel for Port B
HPDB
20
I/O
Port B HPD
CECB
18
I/O
Port B CEC
AUX+
13
I/O
+ve AUX Channel for Common Port
AUX–
14
I/O
-ve AUX Channel for Common Port
HPD
15
I/O
HPD for Common Port
CEC
16
I/O
CEC for Common Port
23
HPDB
CECB
20
22
19
17
18
VCC
16
CECA
CEC
2
D1+A
I/O TYPE
NAME
AUX–A
AUX–B
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LOGIC DIAGRAM
D0+
D0+A
D0–
D0–A
D1+
D1+A
D1–
D1–A
D2+
D2+A
D2–
D3+
D2–A
D3+A
D3–
D3–A
D0+B
D0–B
D1+B
D1–B
D2+B
D2–B
D3+B
D3–B
AUX+
AUX+A
AUX–
AUX–A
HPD
HPDA
CEC
CECA
AUX+B
AUX–B
HPDB
CECB
EN
Control Logic
SEL1
SEL2
Table 1. FUNCTION TABLE
(1)
EN
SEL1
SEL2
L
X
X
FUNCTION
H
L (1)
L (1)
Output port A = Input
Output Port B = High Impedance
H
H (1)
H (1)
Output Port A = High Impedance
Output Port B = Input
All I/O = High Impedance
Tie SEL1 and SEL2 together for easy output control
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APPLICATION EXAMPLES
HDMI
Transmitter 1
D0+A
D0-A
D1+A
D1-A
D2+A
D2-A
D3+A
D3-A
DDC CLK _A
DDC DATA _A
CEC_A
HPD_A
TS3DV621
HDMI Switch
HDMI
Transmitter 1
D0+B
D0-B
D1+B
D1-B
D2+B
D2-B
D3+B
D3-B
DDC CLK _B
DDC DATA _B
CEC_B
HPD_B
D0+
D0D1+
D1D2+
D2D3+
D3DDC CLK
DDC DATA
CEC
HPD
Display
HDMI
HDMI Scalar/
(DLP, LCD, TV,
Receiver
Video Decoder
PDP, HDTV)
Figure 2. Dual HDMI Source Application
D0+
D0D1+
D1D2+
D2D3+
D3AUX/DDC
AUX/DDC
Cab_Detect
HPD
Dual Mode
DisplayPort
Source
TS3DV621
D0+
D0D1+
D1D2+
D2D3+
D3AUX+
AUXCab_Detect
HPD
Dual Mode
DisplayPort
Connector
DP/HDMI
Switch
D0+
D0D1+
D1D2+
D2D3+
D3DDC_CLK
DDC_DATA
HDMI
Connector
HPD
Figure 3. Dual-Mode DisplayPort Application
4
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ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VCC
Supply voltage range
-0.5
4.6
V
VI/O
Analog voltage range (2) (3) (4)
All I/O
–0.5
7
V
VIN
Digital input voltage range (2) (3)
SEL1, SEL2
–0.5
7
II/OK
Analog port diode current
VI/O < 0
IIK
Digital input clamp current
VIN < 0
II/O
On-state switch current (5)
All I/O
IDD
IGND
Continuous current through VDD or GND
θJA
Package thermal impedance
Tstg
Storage temperature range
(1)
(2)
(3)
(4)
(5)
(6)
(6)
V
–50
mA
–50
mA
–128
128
mA
–100
100
mA
31.8
°C/W
150
°C
RUA package
–65
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to ground, unless otherwise specified.
The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
VI and VO are used to denote specific conditions for VI/O.
II and IO are used to denote specific conditions for II/O.
The package thermal impedance is calculated in accordance with JESD 51-7
RECOMMENDED OPERATING CONDITIONS (1)
MIN
MAX
UNIT
VCC
Supply voltage
3
3.6
V
VIH
High-level control input voltage
SEL1, SEL2
2
5.5
V
VIL
Low-level control input voltage
SEL1, SEL2
0
0.8
V
VIN
Input voltage
SEL1, SEL2
0
5.5
V
VI/O
Input/Output voltage
0
5.5
V
TA
Operating free-air temperature
–40
85
°C
(1)
All unused control inputs of the device must be held at VDD or GND to ensure proper device operation. Refer to the TI application
report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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ELECTRICAL CHARACTERISTICS
TEST CONDITIONS (1)
PARAMETER
MIN TYP (2)
VIK
Digital input clamp voltage
SEL1,SEL2
VCC = 3.6 V, IIN = -18 mA
– 1. 2
RON
On-state resistance
All I/O
VCC = 3 V, 1.5 V ≤ VI/O ≤ VCC, II/O = –40 mA
RON(flat) (3)
On-state resistance flatness
All I/O
VCC = 3 V, VI/O = 1.5 V and VCC,
II/O = –40mA
1.5
ΔRON (4)
On-state resistance match
between channels
All I/O
VCC = 3 V, 1.5 V ≤ VI/O ≤ VCC, II/O = –40mA
0.4
IIH
Digital input high leakage
current
SEL1,SEL2
IIL
Digital input low leakage
current
IOFF
CIN
UNIT
V
8
Ω
12
Ω
1
Ω
VCC = 3.6 V , VIN = VDD
±1
µA
SEL1,SEL2
VCC = 3.6 V, VIN = GND
±1
µA
Leakage under power off
conditions
All outputs
VCC = 0 V, VI/O = 0 to 3.6 V, VIN = 0 to 5.5V
±1
µA
Digital input capacitance
SEL1,SEL2
f = 1 MHz, VIN = 0 V
3.2
pF
2
pF
pF
2.6
COFF
Switch OFF capacitance
All I/O
f = 1 MHz, VI/O = 0 V, Output is open,
Switch is OFF
CON
Switch ON capacitance
All I/O
f = 1 MHz, VI/O = 0 V, Output is open,
Switch is ON
5.6
ICC
VCC supply current
VCC = 3.6 V, II/O = 0, VIN = VDD or GND
300
(1)
(2)
(3)
(4)
MAX
– 0. 8
400
µA
VI, VO, II, and IO refer to I/O pins, VIN refers to the control inputs
All typical values are at VCC = 3.3V (unless otherwise noted), TA = 25°C
RON(FLAT) is the difference of RON in a given channel at specified voltages.
ΔRON is the difference of RON from center port to any other ports.
SWITCHING CHARACTERISTICS
Over recommended operation free-air temperature range, VCC = 3.3 V ± 0.3 V, RL = 200 Ω, CL = 4 pF (unless otherwise
noted) (see and )
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd (2)
All I/O input side
All I/O output side
tPZH, tPZL
SEL1, SEL2
All I/O
2
7
ns
tPHZ, tPLZ
SEL1, SEL2
All I/O
2
5
ns
All I/O input side
All I/O output side
6
30
ps
6
30
ps
tsk(o)
(3)
MIN TYP (1) MAX
40
tsk(p) (4)
(1)
(2)
(3)
(4)
UNIT
ps
All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C.
The propagation delay is the calculated RC time constant of the typical ON-State resistance of the switch and the specified load
capacitance when driven by an ideal voltage source (zero output impedance).
Output skew between center port and any other channel.
Skew between opposite transitions of the same output |tPHL – tPLH|
DYNAMIC CHARACTERISTICS
Over recommended operation free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted)
PARAMETER
6
TYP (1)
UNIT
XTALK
RL = 50 Ω, f = 250 MHz (Figure 11)
–43
OIRR
RL = 50 Ω, f = 250 MHz (Figure 12)
–42
dB
RL = 50 Ω, Switch ON (Figure 10)
2.2
GHz
BW
(1)
TEST CONDITIONS
dB
All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C.
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OPERATING CHARACTERISTICS
0
0
-20
-2
Attenuation - dB
Attenuation - dB
-40
-4
-6
-60
-80
-8
-100
-10
-120
-12
1.00E+05 1.00E+06 1.00E+07 1.00E+08 1.00E+09 1.00E+10
f - Frequency - Hz
Figure 4. Gain vs Frequency
-140
1.00E+05 1.00E+06 1.00E+07 1.00E+08 1.00E+09 1.00E+10
f - Frequency - Hz
Figure 5. Off Isolation vs Frequency
9.0
0
8.8
-20
8.6
8.4
RON - W
Attenuation - dB
-40
-60
-80
8.2
8.0
-100
7.8
-120
7.6
-140
1.00E+05 1.00E+06 1.00E+07 1.00E+08 1.00E+09 1.00E+10
f - Frequency - Hz
Figure 6. Crosstalk vs Frequency
7.4
1.4
1.9
2.9
2.4
VI - Input Voltage - V
Figure 7. RON vs VIN
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PARAMETER MEASUREMENT INFORMATION
Enable and Disable Times
VDD
Input Generator
VIN
50 Ω
50 Ω
VG1
TEST CIRCUIT
DUT
2 × VDD
Input Generator
S1
RL
VO
VI
GND
50 Ω
CL
(see Note A)
50 Ω
VG2
RL
TEST
VDD
S1
RL
Vin
CL
V∆
t PLZ/t PZL
3.3 V ± 0.3 V
2 × VDD
200 Ω
GND
4 pF
0.3 V
t PHZ/t PZH
3.3 V ± 0.3 V
GND
200 Ω
VDD
4 pF
0.3 V
VSEL
VO
3.33 V
Output Control
(VIN)
1.65 V
1.65 V
0V
Output
Waveform 1
S1 at 2 x VCC
(see Note B)
t PZL
t PLZ
VOH
VDC/2
VOL + 0.3 V
t PZH
VO
Open
Output
Waveform 2
S1 at GND
(see Note B)
VOL
t PHZ
VCC/2
VOH - 0.3 V
VOH
VOL
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics:PRR ≤10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
Figure 8. Test Circuit and Voltage Waveforms
8
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PARAMETER MEASUREMENT INFORMATION (continued)
Skew
VDD
Input Generator
VSEL
50 Ω
50 Ω
VG1
TEST CIRCUIT
DUT
2 × VDD
Input Generator
50 Ω
t sk(o)
t sk(p)
RL
S1
RL
Vin
CL
3.3 V ± 0.3 V
Open
200 Ω
VCC or GND
4 pF
3.3 V ± 0.3V
Open
200 Ω
VCC or GND
4 pF
VCC
3.5 V
2.5 V
1.5 V
Data In at
Ax or Ay
t PLHx
t PHLx
VOH
(VOH + VOL)/2
VOL
Data Out at
XB 1 or XB 2
t sk(o)
VO
CL
(see Note A)
50 Ω
TEST
VO
Open
GND
VG2
VI
S1
RL
VO
VI
Input
t sk(o)
VOH
(VOH + VOL)/2
VOL
Data Out at
YB 1 or YB 2
t PLHy
3.5 V
2.5 V
1.5 V
t PHLy
t PLH
VOH
(VOH + VOL)/2
VOL
Output
t sk(o) = t PLHy − tPLHx or t PHLy − tPHLx
VOLTAGE WAVEFORMS
OUTPUT SKEW (t sk(o))
t PHL
t sk(p) = t PHL − tPLH
VOLTAGE WAVEFORMS
PULSE SKEW [t sk(p)]
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
Figure 9. Test Circuit and Voltage Waveforms
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PARAMETER MEASUREMENT INFORMATION (continued)
EXT TRIGGER
BIAS
VBIAS
Network Analyzer
(HP8753ES)
P1
P2
VCC
AX
BX
DUT
SEL
VSEL
Figure 10. Test Circuit for Frequency Response (BW)
Frequency response is measured at the output of the ON channel. For example, when VSEL = 0 and A0 is the
input, the output is measured at B0. All unused analog I/O ports are left open.
HP8753ES Setup
Average = 4
RBW = 3 kHz
VBIAS = 0.35 V
ST = 2 s
P1 = 0 dBM
10
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PARAMETER MEASUREMENT INFORMATION (continued)
EXT TRIGGER
BIAS
VBIAS
Network Analyzer
(HP8753ES)
P1
P2
VCC
A0
BX
RL = 50 W
A1
BX
BX
BX
A2
BX
RL = 50 W
A3
BX
BX
SEL
BX
VSEL
A. CL includes probe and jig capacitance.
B. A 50 W termination resistor is needed to match the loading of the network analyzer.
Figure 11. Test Circuit for Crosstalk (XTALK)
Crosstalk is measured at the output of the nonadjacent ON channel. For example, when VSEL = 0 and A1 is the
input, the output is measured at A3. All unused analog input (A) ports are connected to GND, and output (B)
ports are left open.
HP8753ES Setup
Average = 4
RBW = 3 kHz
VBIAS = 0.35 V
ST = 2 s
P1 = 0 dBM
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PARAMETER MEASUREMENT INFORMATION (continued)
EXT TRIGGER
BIAS
VBIAS
Network Analyzer
(HP8753ES)
P1
P2
VDD
A0
0B1
RL = 50 W
A1
1B1
DUT
0B2
1BX2
SEL
VSEL
A. CL includes probe and jig capacitance.
B. A 50 W termination resistor is needed to match the loading of the network analyzer.
Figure 12. Test Circuit for OFF Isolation (OIRR)
OFF isolation is measured at the output of the OFF channel. For example, when VSEL = GND and A1 is the input,
the output is measured at 1B2. All unused analog input (A) ports are connected to ground, and output (B) ports
are left open.
HP8753ES Setup
Average = 4
RBW = 3 kHz
VBIAS = 0.35 V
ST = 2 s
P1 = 0 dBM
12
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SCDS330C – JANUARY 2012 – REVISED MAY 2013
REVISION HISTORY
Changes from Original (January 2012) to Revision A
Page
•
Changed CON value in FEATURES from 5.6 pF to 4 pF. ..................................................................................................... 1
•
Deleted LEVEL-SHIFTING REQUIREMENT FOR DUAL-MODE DP/HDMI APPLICATION section from document. ......... 4
•
Added CON TYP value to the ELECTRICAL CHARACTERISTICS table. ............................................................................. 6
Changes from Revision A (February 2012) to Revision B
Page
•
Changed CON value from 4 pF to 5.6 pF. ............................................................................................................................. 1
•
Changed CON TYP value to the ELECTRICAL CHARACTERISTICS table. ........................................................................ 6
Changes from Revision B (May 2012) to Revision C
•
Page
Updated APPLICATIONS. .................................................................................................................................................... 1
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Product Folder Links :TS3DV621
13
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TS3DV621RUAR
ACTIVE
WQFN
RUA
42
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
SD621
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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