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TS3USB221A
SCDS277A – NOVEMBER 2008 – REVISED FEBRUARY 2015
TS3USB221A ESD Protected, High-Speed USB 2.0 (480-Mbps) 1:2 Multiplexer and
Demultiplexer Switch With Single Enable
1 Features
3 Description
•
•
•
•
•
•
•
•
•
•
The TS3USB221A device is a high-bandwidth switch
specially designed for the switching of high-speed
USB 2.0 signals in handset and consumer
applications, such as cell phones, digital cameras,
and notebooks with hubs or controllers with limited
USB I/Os. The wide bandwidth (900 MHz) of this
switch allows signals to pass with minimum edge and
phase distortion. The device multiplexes differential
outputs from a USB host device to one of two
corresponding outputs. The switch is bidirectional and
offers little or no attenuation of the high-speed signals
at the outputs. The device also has a low power
mode that will reduce the power consumtion to 1 μA
for portible applications with a battery or limited
power budget. The device is designed for low bit-tobit skew and high channel-to-channel noise isolation,
and is compatible with various standards, such as
high-speed USB 2.0 (480 Mbps).
1
•
•
VCC Operation at 2.5 V to 3.3 V
VI/O Accepts Signals Up to 5.5 V
1.8-V Compatible Control-Pin Inputs
Low-Power Mode When OE Is Disabled (1 μA)
RON = 6 Ω Maximum
ΔRON = 0.2 Ω Typical
Cio(on) = 6 pF Typical
Low Power Consumption (30 μA Maximum)
High Bandwidth (900 MHz Typical)
Latch-Up Performance Exceeds 100 mA
Per JESD 78, Class II
ESD Performance Tested Per JESD 22
– 7000-V Human-Body Model
(A114-B, Class II)
– 1000-V Charged-Device Model (C101)
ESD Performance I/O to GND
– 12-kV Human-Body Model
The TS3USB221A device integrates ESD protection
cells on all pins, is available in a tiny μQFN package
(2 mm × 1.5 mm) and is characterized over the free
air temperature range from –40°C to 85°C.
2 Applications
•
•
•
•
•
Routes Signals for USB 1.0, 1.1, and 2.0
Mobile Phones
Cameras
Notebooks
USB I/O expansion
Device Information(1)
PART NUMBER
TS3USB221A
PACKAGE
UQFN
BODY SIZE (NOM)
1.50 mm × 2.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
4 Simplified Schematic
D+
1D+
D−
1D−
2D+
2D−
S
OE
EN is the internal enable signal applied to the switch.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TS3USB221A
SCDS277A – NOVEMBER 2008 – REVISED FEBRUARY 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Simplified Schematic.............................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
1
2
3
4
7.1
7.2
7.3
7.4
7.5
7.6
4
4
4
4
5
11 Power Supply Recommendations ..................... 16
12 Layout................................................................... 16
5
13 Device and Documentation Support ................. 18
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics ..........................................
Dynamic Electrical Characteristics, VCC = 3.3 V
±10% ..........................................................................
7.7 Dynamic Electrical Characteristics, VCC = 2.5 V
±10% ..........................................................................
7.8 Switching Characteristics, VCC = 3.3 V ±10%...........
7.9 Switching Characteristics, VCC = 2.5 V ±10%...........
7.10 Typical Characteristics ............................................
6
6
6
7
8
9
Parameter Measurement Information .................. 8
Detailed Description ............................................ 12
9.1
9.2
9.1
9.2
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
12
12
13
13
10 Application and Implementation........................ 14
10.1 Application Information.......................................... 14
10.2 Typical Application ................................................ 14
12.1 Layout Guidelines ................................................. 16
12.2 Layout Example .................................................... 17
13.1 Trademarks ........................................................... 18
13.2 Electrostatic Discharge Caution ............................ 18
13.3 Glossary ................................................................ 18
14 Mechanical, Packaging, and Orderable
Information ........................................................... 18
5 Revision History
Changes from Original (November 2008) to Revision A
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................ 1
•
Deleted the Ordering Information table from the data sheet. See the Mechanical, Packaging, and Orderable
Information section for the ordering information..................................................................................................................... 1
•
Update the document to the new TI data sheet standard ..................................................................................................... 1
2
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SCDS277A – NOVEMBER 2008 – REVISED FEBRUARY 2015
6 Pin Configuration and Functions
10-Pin µQFN
RSE Package
(Top View)
VCC
1D+
1
1D–
10
9
S
2
8
D+
2D+
3
7
D–
2D–
4
6
OE
1
1D+
5
GND
10-Pin µQFN
RSE Package
(Bottom View)
VCC
10
S
9
D+
8
2
1D–
D–
7
3
2D+
OE
6
4
2D–
5
GND
Pin Functions
PIN
NAME
DESCRIPTION
NO.
I/O
1D+
1
I/O
1D–
2
I/O
2D+
3
I/O
2D–
4
I/O
GND
5
-
Ground
OE
6
I
Bus-switch enable
D+
8
I/O
Common USB port
D—
7
I/O
S
9
I
Select input
VCC
10
-
Supply voltage
USB port 1
USB port 2
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7 Specifications
7.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC
Control input voltage, VS, V OE
Switch I/O voltage, VI/O
(2) (3)
(2) (3) (4)
Control input clamp current, IIK
VIN < 0
I/O port clamp current, II/OK
VI/O < 0
ON-state switch current, II/O
MIN
MAX
UNIT
–0.5
4.6
V
–0.5
7
V
–0.5
7
V
–50
mA
(5)
Continuous current through VCC or GND
Tstg
(1)
(2)
(3)
(4)
(5)
Storage temperature range
–65
–50
mA
±120
mA
±100
mA
150
°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to ground, unless otherwise specified.
The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
VI and VO are used to denote specific conditions for VI/O.
II and IO are used to denote specific conditions for II/O.
7.2 ESD Ratings
VALUE
Human-body model (HBM), per
ANSI/ESDA/JEDEC JS-001 (1)
V(ESD)
Electrostatic discharge
All pins except I/O to
GND
±7000
I/O to GND
±12000
Charged-device model (CDM), per JEDEC
All pins
specification JESD22-C101 (2)
(1)
(2)
UNIT
V
±1000
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions.
7.3 Recommended Operating Conditions
VCC
MIN
MAX
2.3
3.6
VCC = 2.3 V to 2.7 V
0.46 × VCC
VCC
VCC = 2.7 V to 3.6 V
0.46 × VCC
VCC
VCC = 2.3 V to 2.7 V
0
0.25 × VCC
VCC = 2.7 V to 3.6 V
0
0.25 × VCC
0
5.5
V
–40
85
°C
Supply voltage
High-level control input voltage
VS, V OE
Low-level control input voltage
VI/O
Data input/output voltage
TA
Operating free-air temperature
UNIT
V
V
V
7.4 Thermal Information
THERMAL METRIC (1)
RSE
10 PINS
RθJA
Junction-to-ambient thermal resistance
179.7
RθJC(top)
Junction-to-case (top) thermal resistance
107.9
RθJB
Junction-to-board thermal resistance
100.7
ψJT
Junction-to-top characterization parameter
ψJB
Junction-to-board characterization parameter
(1)
4
UNIT
°C/W
7.1
100.0
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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7.5 Electrical Characteristics (1)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP (2)
MAX
UNIT
–1.8
V
VIK
Input-Source Clamp Voltage
VCC = 3.6 V, 2.7 V, II = –18 mA
IIN
Input leakage current, control
inputs
VCC = 3.6 V, 2.7 V, 0 V, VIN = 0 V to 3.6 V
±1
μA
Off-state leakage current
VCC = 3.6 V, 2.7 V, VO = 0 V to 5.25 V, VI = 0 V,
VIN = VCC or GND, Switch OFF
±1
μA
Power-off leakage current
VCC = 0 V
ICC
Supply Current
VCC = 3.6 V, 2.7 V, VIN = VCC or GND,
II/O = 0 V, Switch ON or OFF
30
μA
ICC
Supply Current (low power
mode)
VCC = 3.6 V, 2.7 V, VIN = VCC or GND,
Switch disabled, OE in high state
1
μA
Supply-current change, control
inputs
One input at 1.8 V,
Other inputs at VCC
or GND
Cin
Input capacitance, control
inputs
VCC = 3.3 V, 2.5 V, VIN = VCC or 0 V
1.5
2.5
pF
Cio(OFF)
OFF capacitance
VCC = 3.3 V, 2.5 V, VI/O = VCC or 0 V, Switch OFF
3.5
5
pF
Cio(ON)
ON capacitance
VCC = 3.3 V, 2.5 V, VI/O = VCC or 0 V, Switch ON
6
7.5
pF
3
6
VI = 2.4 V, IO = –15 mA
3.4
6
VI = 0 V, IO = 30 mA
0.2
VI = 1.7, IO = –15 mA
0.2
IOZ
(3)
I(OFF)
ΔICC
(4)
(5)
RON
ON-state resistance
VCC = 3 V, 2.3 V
ΔRON
ON-state resistance match
between channels
VCC = 3 V, 2.3 V
RON(flat)
ON-state resistance flatness
VCC = 3 V, 2.3 V
(1)
(2)
(3)
(4)
(5)
VI/O = 0 V to 5.25 V
±2
VI/O = 0 V to 3.6 V
±2
VI/O = 0 V to 2.7 V
±1
VCC = 3.6 V
20
VCC = 2.7 V
0.5
VI = 0 V, IO = 30 mA
VI = 0 V, IO = 30 mA
1
VI = 1.7, IO = –15 mA
1
μA
μA
Ω
Ω
Ω
VIN and IIN refer to control inputs. VI, VO, II, and IO refer to data pins.
All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C.
For I/O ports, the parameter IOZ includes the input leakage current.
This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
Measured by the voltage drop between the A and B terminals at the indicated current through the switch. ON-state resistance is
determined by the lower of the voltages of the two (A or B) terminals.
7.6 Dynamic Electrical Characteristics, VCC = 3.3 V ±10%
over operating range, TA = –40°C to 85°C, VCC = 3.3 V ±10%, GND = 0 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
XTALK
Crosstalk
RL = 50 , f = 250 MHz
–40
OIRR
OFF isolation
RL = 50 , f = 250 MHz
–41
dB
BW
Bandwidth (–3 dB)
RL = 50
0.9
GHz
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7.7 Dynamic Electrical Characteristics, VCC = 2.5 V ±10%
over operating range, TA = –40°C to 85°C, VCC = 2.5 V ±10%, GND = 0 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
XTALK
Crosstalk
RL = 50 , f = 250 MHz
–39
OIRR
OFF isolation
RL = 50 , f = 250 MHz
-40
dB
dB
BW
Bandwidth (3 dB)
RL = 50
0.9
GHz
7.8 Switching Characteristics, VCC = 3.3 V ±10%
over operating range, TA = –40°C to 85°C, VCC = 3.3 V ±10%, GND = 0 V
PARAMETER
tpd
Propagation delay
MIN
(2) (3)
Line enable time
tOFF
Line disable time
tSK(O)
Output skew between center port to any other port (2)
(1)
(2)
(3)
MAX
0.25
tON
tSK(P)
TYP (1)
ns
S to D, nD
30
OE to D, nD
17
S to D, nD
12
OE to D, nD
10
Skew between opposite transitions of the same output (tPHL– tPLH)
(2)
UNIT
ns
ns
0.1
0.2
ns
0.1
0.2
ns
For Max or Min conditions, use the appropriate value specified under Electrical Characteristics for the applicable device type.
Specified by design
The bus switch contributes no propagational delay other than the RC delay of the on resistance of the switch and the load capacitance.
The time constant for the switch alone is of the order of 0.25 ns for 10-pF load. Since this time constant is much smaller than the rise/fall
times of typical driving signals, it adds very little propagational delay to the system. Propagational delay of the bus switch, when used in
a system, is determined by the driving circuit on the driving side of the switch and its interactions with the load on the driven side.
7.9 Switching Characteristics, VCC = 2.5 V ±10%
over operating range, TA = –40°C to 85°C, VCC = 2.5 V ±10%, GND = 0 V
PARAMETER
tpd
Propagation delay
MIN
(2) (3)
TYP (1)
MAX
0.25
UNIT
ns
S to D, nD
50
OE to D, nD
32
S to D, nD
23
OE to D, nD
12
tON
Line enable time
tOFF
Line disable time
tSK(O)
Output skew between center port to any other port (2)
0.1
0.2
ns
tSK(P)
Skew between opposite transitions of the same output (tPHL– tPLH) (2)
0.1
0.2
ns
(1)
(2)
(3)
6
ns
ns
For Max or Min conditions, use the appropriate value specified under Electrical Characteristics for the applicable device type.
Specified by design
The bus switch contributes no propagational delay other than the RC delay of the on resistance of the switch and the load capacitance.
The time constant for the switch alone is of the order of 0.25 ns for 10-pF load. Since this time constant is much smaller than the rise/fall
times of typical driving signals, it adds very little propagational delay to the system. Propagational delay of the bus switch, when used in
a system, is determined by the driving circuit on the driving side of the switch and its interactions with the load on the driven side.
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7.10 Typical Characteristics
0
0
–1
–20
Attenuation (dB)
Gain (dB)
–2
–3
–4
–40
–60
–80
–5
–100
–6
–120
–7
100.0E+3
100.0E+3
1.0E+6
10.0E+6
100.0E+6
1.0E+9
1.0E+6
100.0E+6
1.0E+9
10.0E+9
Frequency (Hz)
Frequency (Hz)
Figure 2. OFF Isolation vs Frequency
Figure 1. Gain vs Frequency
0
3.5
–20
3.4
3.3
–40
VCC = 3 V
ron (Ω)
Attenuation (dB)
10.0E+6
10.0E+9
–60
3.2
VCC = 2.3 V
3.1
–80
3.0
–100
2.9
–120
100.0E+3
2.8
1.0E+6
10.0E+6
100.0E+6
1.0E+9
10.0E+9
0.0
0.5
1.0
1.5
3.0
3.5
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7
Frequency (Hz)
2.0
2.5
VIN (V)
Figure 3. Crosstalk vs Frequency
Figure 4. ron vs VIN (IOUT = –15 mA)
3.5
3.4
3.3
ron (Ω)
VCC = 3 V
3.2
VCC = 2.3 V
3.1
3.0
2.9
2.8
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
VIN (V)
Figure 5. rON vs VIN (IOUT = 30 mA)
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8 Parameter Measurement Information
VCC
1D or 2D VOUT1 or VOUT2
VIN
RL
CL
VCOM
tON
500 Ω
50 pF
V+
tOFF
500 Ω
50 pF
V+
D
CL(2)
1D or 2D
VCTRL
TEST
RL
S
CL(2)
Logic
Input(1)
RL
GND
1.8 V
Logic
Input
(VI)
50%
50%
0
tON
tOFF
Switch
Output
(VOUT1 or VOUT2)
(1)
(2)
90%
90%
VOH
VOL
All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr < 5 ns, tf < 5 ns.
CL includes probe and jig capacitance.
Figure 6. Turn-On (tON) and Turn-Off Time (tOFF)
VCC
Network Analyzer
Channel OFF: 1D to D
50 W
VOUT1 1D
VCTRL = VCC or GND
D
Source
Signal
50 W
VIN
2D
Network Analyzer Setup
Source Power = 0 dBm
(632-mV P-P at 50-W load)
VCTRL S
50 W
+
GND
DC Bias = 350 mV
Figure 7. OFF Isolation (OISO)
8
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Parameter Measurement Information (continued)
VCC
Network Analyzer
Channel ON: 1D to D
50 W
VOUT1 1D
Channel OFF: 2D to D
VIN
Source
Signal
VCTRL = VCC or GND
VOUT2 2D
50 W
Network Analyzer Setup
50 W
VCTRL S
+
Source Power = 0 dBm
(632-mV P-P at 50-W load)
GND
DC Bias = 350 mV
Figure 8. Crosstalk (XTALK)
VCC
Network Analyzer
50 W
VOUT1
1D
Channel ON: 1D to D
D
Source
Signal
VIN
VCTRL = VCC or GND
2D
Network Analyzer Setup
50 W
VCTRL
+
Source Power = 0 dBm
(632-mV P-P at 50-W load)
S
GND
DC Bias = 350 mV
Figure 9. Bandwidth (BW)
400 mV
Figure 10. Propagation Delay
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Parameter Measurement Information (continued)
800 mV
50%
50%
Input
400 mV
tPLH
tPHL
VOH
50%
Output
VOL
tSK(P) = | tPHL – tPLH |
PULSE SKEW tSK(P)
800 mV
50%
50%
Input
400 mV
tPLH1
tPHL1
VOH
50%
50%
Output 1
VOL
tSK(O)
tSK(O)
VOH
50%
50%
Output 2
tPLH2
VOL
tPHL2
tSK(O) = | tPLH1 – tPLH2 | or | tPHL1 – tPHL2 |
OUTPUT SKEW tSK(P)
Figure 11. Skew Test
VCC
VOUT1 1D
+
D
VIN
Channel ON
VOUT2 2D
r on +
VCTRL
IIN
S
VIN * VOUT2 or VOUT1
W
IIN
VCTRL = VIH or VIL
+
GND
Figure 12. ON-State Resistance (ron)
10
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Parameter Measurement Information (continued)
VCC
VOUT1 1D
VIN
D
+
VOUT2 2D
VCTRL
+
S
OFF-State Leakage Current
Channel OFF
VCTRL = VIH or VIL
+
GND
Figure 13. OFF-State Leakage Current
VCC
VOUT1 1D
Capacitance
Meter
VBIAS
VBIAS = VCC or GND
VOUT2 2D
VCTRL = VCC or GND
VIN D
Capacitance is measured at 1D,
2D, D, and S inputs during ON
and OFF conditions.
VCTRL S
GND
Figure 14. Capacitance
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9 Detailed Description
9.1 Overview
The TS3USB221A device is a 2-channel SPDT switch specially designed for the switching of high-speed USB
2.0 signals in handset and consumer applications, such as cell phones, digital cameras, and notebooks with
hubs or controllers with limited USB I/Os. The wide bandwidth (900 MHz) of this switch allows signals to pass
with minimum edge and phase distortion. The device multiplexes differential outputs from a USB host device to
one of two corresponding outputs. The switch is bidirectional and offers little or no attenuation of the high-speed
signals at the outputs. The device also has a low power mode that will reduce the power consumption to 1 μA for
portible applications with a battery or limited power budget.
The device is designed for low bit-to-bit skew and high channel-to-channel noise isolation, and is compatible with
various standards, such as high-speed USB 2.0 (480 Mbps).
The TS3USB221A device integrates ESD protection cells on all pins, is available in a tiny μQFN package (2 mm
× 1.5 mm) and is characterized over the free air temperature range from –40°C to 85°C.
9.2 Functional Block Diagram
D+
1D+
D−
1D−
2D+
2D−
S
OE
A
B
VCC
Charge
Pump
EN (see Note A)
A.
EN is the internal enable signal applied to the switch.
Figure 15. Simplified Schematic of Each FET Switch (SW)
12
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9.1 Feature Description
9.1.1 Low Power Mode
The TS3USB221A has a low power mode that reduces the power consumption to 1 μA while the devices is not
in use. To put the device in low power mode and disable the switch, the bus-switch enable pin OE must be
supplied with a logic "High" signal.
9.2 Device Functional Modes
Table 1. Truth Table
S
OE
FUNCTION
X
H
Disconnect
L
L
D = 1D
H
L
D = 2D
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
There are many USB applications in which the USB hubs or controllers have a limited number of USB I/Os. The
TS3USB221A solution can effectively expand the limited USB I/Os by switching between multiple USB buses in
order to interface them to a single USB hub or controller.
10.2 Typical Application
3.3 V
0.1 μF
0.1 μF
VCC
System
Controller
Switch
Control Logic
USB
Controller
TS3USB221A
2-channel
SPDT
S
OE
1D+
1DD+
USB Port 1
D2D+
2D-
USB Port 2
GND
Figure 16. Application Schematic
14
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Typical Application (continued)
10.2.1 Design Requirements
Design requirements of the USB 1.0,1.1, and 2.0 standards should be followed.
It is recommended that the digital control pins S and OE be pulled up to VCC or down to GND to avoid undesired
switch positions that could result from the floating pin.
10.2.2 Detailed Design Procedure
The TS3USB221A can be properly operated without any external components. However, it is recommended that
unused pins should be connected to ground through a 50-Ω resistor to prevent signal reflections back into the
device.
0.5
0.5
0.4
0.4
0.3
0.3
Differential Signal (V)
Differential Signal (V)
10.2.3 Application Curves
0.2
0.1
0.0
–0.1
–0.2
0.2
0.1
0.0
–0.1
–0.2
–0.3
–0.3
–0.4
–0.4
–0.5
–0.5
0.0
0.2
0.4
0.5
0.8
1.0
1.2
1.4
1.6
1.8
2.0
0.0
0.2
0.4
0.5
–9
0.8
1.0
1.2
1.4
1.6
1.8
2.0
–9
Time (X 10 ) (s)
Time (X 10 ) (s)
Figure 17. Eye Pattern: 480-Mbps USB Signal With No
Switch (Through Path)
Figure 18. Eye Pattern: 480-Mbps USB Signal With Switch
NC Path
0.5
0.4
Differential Signal (V)
0.3
0.2
0.1
0.0
–0.1
–0.2
–0.3
–0.4
–0.5
0.0
0.2
0.4
0.5
0.8
1.0
1.2
1.4
1.6
1.8
2.0
–9
Time (X 10 ) (s)
Figure 19. Eye Pattern: 480-Mbps USB Signal With Switch NO Path
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11 Power Supply Recommendations
Power to the device is supplied through the VCC pin and should follow the USB 1.0, 1.1, and 2.0 standards. A
bypass capacitor is recommended to be placed as close to the supply pin VCC to help smooth out lower
frequency noise to provide better load regulation across the frequency spectrum.
12 Layout
12.1 Layout Guidelines
Place supply bypass capacitors as close to VCC pin as possible and avoid placing the bypass caps near the
D+/D- traces.
The high speed D+/D- traces should always be matched lengths and must be no more than 4 inches; otherwise,
the eye diagram performance may be degraded. A high-speed USB connection is made through a shielded,
twisted pair cable with a differential characteristic impedance. In layout, the impedance of D+ and D- traces
should match the cable characteristic differential impedance for optimal performance.
Route the high-speed USB signals using a minimum of vias and corners which will reduce signal reflections and
impedance changes. When a via must be used, increase the clearance size around it to minimize its
capacitance. Each via introduces discontinuities in the signal’s transmission line and increases the chance of
picking up interference from the other layers of the board. Be careful when designing test points on twisted pair
lines; through-hole pins are not recommended.
When it becomes necessary to turn 90°, use two 45° turns or an arc instead of making a single 90° turn. This
reduces reflections on the signal traces by minimizing impedance discontinuities.
Do not route USB traces under or near crystals, oscillators, clock signal generators, switching regulators,
mounting holes, magnetic devices or IC’s that use or duplicate clock signals.
Avoid stubs on the high-speed USB signals because they cause signal reflections. If a stub is unavoidable, then
the stub should be less than 200 mm.
Route all high-speed USB signal traces over continuous planes (VCC or GND), with no interruptions.
Avoid crossing over anti-etch, commonly found with plane splits.
Due to high frequencies associated with the USB, a printed circuit board with at least four layers is
recommended; two signal layers separated by a ground and power layer as shown in Figure 20.
Signal 1
GND Plane
Power Plane
Signal 2
Figure 20. Four-Layer Board Stack-Up
The majority of signal traces should run on a single layer, preferably Signal 1. Immediately next to this layer
should be the GND plane, which is solid with no cuts. Avoid running signal traces across a split in the ground or
power plane. When running across split planes is unavoidable, sufficient decoupling must be used. Minimizing
the number of signal vias reduces EMI by reducing inductance at high frequencies.
16
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12.2 Layout Example
LEGEND
VIA to Power Plane
Polygonal Copper Pour
VIA to GND Plane
Bypass Capacitor
V+
To Microcontroller
10
1 1D+
VCC
S
9
2 1D-
D+
8
3 2D+
D-
7
USB Port 1
To USB Host
USB Port 2
4 2D-
OE 6
GND
5
To Microcontroller
Figure 21. Package Layout Diagram
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13 Device and Documentation Support
13.1 Trademarks
All trademarks are the property of their respective owners.
13.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
(3)
Device Marking
(4/5)
(6)
TS3USB221ARSER
ACTIVE
UQFN
RSE
10
3000
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
(LH7, LHR, LHV)
TS3USB221ARSERG4
ACTIVE
UQFN
RSE
10
3000
RoHS & Green
Level-1-260C-UNLIM
-40 to 85
(LH7, LHR, LHV)
NIPDAU
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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