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TS3USB30E
SCDS255F – DECEMBER 2008 – REVISED AUGUST 2015
TS3USB30E ESD-Protected, High-Speed USB 2.0 (480-Mbps)
1:2 Multiplexer/Demultiplexer Switch With Single Enable
1 Features
3 Description
•
•
•
•
The TS3USB30E is a high-bandwidth 1:2 switch
specially designed for the switching of high-speed
USB 2.0 signals in handset and consumer
applications, such as cell phones, digital cameras,
and notebooks with hubs or controllers with limited
USB I/Os. The wide bandwidth (900 MHz) of this
switch allows signals to pass with minimum edge and
phase distortion. The device multiplexes differential
outputs from a USB host device to one of two
corresponding outputs, or from two different hosts to
one corresponding output. The switch is bidirectional
and offers little or no attenuation of the high-speed
signals at the outputs. It is designed for low bit-to-bit
skew and high channel-to-channel noise isolation,
and is compatible with various standards, such as
high-speed USB 2.0 (480 Mbps).
1
•
•
•
•
•
•
•
•
•
VCC Operation at 3 V to 4.3 V
D+/D– Pins Tolerate up to 5.25 V
1.8-V Compatible Control-Pin Inputs
IOFF Supports Partial Power-Down-Mode
Operation
RON = 10 Ω Maximum
ΔRON = 0.35 Ω Typical
Cio(ON) = 7.5 pF Typical
Low Power Consumption (1 μA Maximum)
–3-dB Bandwidth = 900 MHz Typical
Latch-Up Performance Exceeds
100 mA Per JESD 78, Class II (1)
ESD Performance Tested Per JESD 22
– 8000-V Human-Body Model
(A114-B, Class II)
– 1000-V Charged-Device Model (C101)
ESD Performance I/O Port to GND (2)
– 15000-V Human-Body Model
Packaged in 10-pin UQFN (1.4 mm × 1.8 mm)
The TS3USB30E integrates ESD protection cells on
all pins, is available in a tiny UQFN package (1.8 mm
× 1.4 mm) or a VSSOP package, and is
characterized over the free-air temperature range of
–40°C to 85°C.
Device Information(1)
PART NUMBER
2 Applications
•
•
•
•
•
(1)
(2)
TS3USB30E
Routes Signals for USB 1.0, 1.1, and 2.0
Multi-Purpose Signal Switching
Portable Electronics
Industrial
Consumer Products
PACKAGE
BODY SIZE (NOM)
VSSOP (10)
3.00 mm × 3.00 mm
UQFN (10)
1.80 mm × 1.40 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Except OE and S inputs
High-voltage HBM is performed in addition to the standard
HBM testing (A114-B, Class II) and applies to I/O ports tested
with respect to GND only.
Functional Block Diagram
D1+
D+
D2+
D1–
D–
D2–
S
OE
Control
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TS3USB30E
SCDS255F – DECEMBER 2008 – REVISED AUGUST 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
4
4
4
5
5
6
6
7
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions ......................
Thermal Information ..................................................
Electrical Characteristics ..........................................
Dynamic Electrical Characteristics............................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 8
Detailed Description ............................................ 12
8.1 Overview ................................................................. 12
8.2 Functional Block Diagram ....................................... 12
8.3 Feature Description................................................. 12
8.4 Device Functional Modes........................................ 12
9
Application and Implementation ........................ 13
9.1 Application Information............................................ 13
9.2 Typical Application ................................................. 13
10 Power Supply Recommendations ..................... 15
11 Layout................................................................... 15
11.1 Layout Guidelines ................................................. 15
11.2 Layout Example .................................................... 16
12 Device and Documentation Support ................. 17
12.1
12.2
12.3
12.4
12.5
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
17
17
17
17
17
13 Mechanical, Packaging, and Orderable
Information ........................................................... 17
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (August 2012) to Revision F
Page
•
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
•
Changed package type in Description from DGS to VSSOP ................................................................................................ 1
2
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SCDS255F – DECEMBER 2008 – REVISED AUGUST 2015
5 Pin Configuration and Functions
10
GND
VCC
9
D+
OE
8
5
D–
VCC
9
4
S
10
3
2
D2+
D1+
1
D2+
S
8
1
2
7
6
D2–
6
OE
D1+
D2–
7
RSW PACKAGE
10-PIN UQFN
BOTTOM VIEW
D1–
D1–
RSW PACKAGE
10-PIN UQFN
TOP VIEW
DGS PACKAGE
10-PIN VSSOP
TOP VIEW
3
D+
4
GND
5
D–
Pin Functions
PIN
NAME
I/O
DESCRIPTION
UQFN
VSSOP
D1+
1
2
I/O
D1–
7
8
I/O
D+
3
4
I/O
D-
5
6
I/O
D2+
2
3
I/O
D2–
6
7
I/O
OE
8
9
I
Bus-switch enable
S
10
1
I
Select input
GND
4
5
—
Ground
VCC
9
10
—
Voltage supply
USB signal path port 1
Common USB signal path
USB signal path port 2
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (see
VCC
(1) (2)
)
Supply voltage
VIN
Control input voltage
(3)
(4)
MIN
MAX
UNIT
–0.5
7
V
V
–0.5
7
D+, D– when VCC > 0
–0.5
VCC + 0.3
D+, D– when VCC = 0
–0.5
5.25
VI/O
Signal path I/O voltage (3)
IIK
Control input clamp current
VIN < 0
–50
mA
II/OK
I/O port clamp current
VI/O < 0
–50
mA
II/O
ON-state switch current (5)
±64
mA
±100
mA
150
°C
Continuous current through VCC or GND
Tstg
(1)
(2)
(3)
(4)
(5)
Storage temperature
–65
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions . Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to ground, unless otherwise specified.
The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
VI and VO are used to denote specific conditions for VI/O.
II and IO are used to denote specific conditions for II/O.
6.2 ESD Ratings
VALUE
V(ESD)
Electrostatic discharge
Human body model (HBM),
per ANSI/ESDA/JEDEC JS-001 (1)
All pins
8000
I/O port to GND
15000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
(1)
(2)
UNIT
V
1000
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
See
VCC
(1)
.
VIH
High-level control input voltage
VIL
Low-level control input voltage
VI/O
Data input/output voltage
TA
Operating free-air temperature
(1)
4
MIN
MAX
3
4.3
VCC = 3 V to 3.6 V
1.3
VCC
VCC = 4.3 V
1.7
VCC
VCC = 3 V to 3.6 V
0
0.5
VCC = 4.3 V
0
0.7
0
VCC
V
–40
85
°C
Supply voltage
UNIT
V
V
V
All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to Implications of Slow or
Floating CMOS Inputs (SCBA004).
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6.4 Thermal Information
TS3USB30E
THERMAL METRIC (1)
DGS (VSSOP)
RSW (UQFN)
10 PINS
10 PINS
UNIT
203.1
114.5
°C/W
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
88.7
64.7
°C/W
RθJB
Junction-to-board thermal resistance
123.0
21.0
°C/W
ψJT
Junction-to-top characterization parameter
21.2
1.9
°C/W
ψJB
Junction-to-board characterization parameter
121.6
21.0
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953).
6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
VIK
Control input clamp voltage
VCC = 3 V, II = –18 mA
IIN
Control inputs
IOZ
MIN TYP (2)
MAX
UNIT
–1.2
V
VCC = 4.3 V, 0 V, VIN = 0 to 4.3 V
±1
μA
D+ and D– OFF-state leakage current (3)
VCC = 4.3 V, VO = 0 to 3.6 V, VI = 0,
Switch OFF
±1
μA
IOFF
Powered off leakage current
VCC = 0 V, VO = 0 to 4.3 V, VI = 0,
VIN = VCC or GND
±2
μA
ICC
Supply current
VCC = 4.3 V, II/O = 0,
Switch ON or OFF
1
μA
Control inputs
VCC = 4.3 V, VIN = 2.6 V
10
μA
Cin
Control inputs digital input capacitance
VCC = 0 V,
VIN = VCC or GND
1
pF
Cio(OFF)
OFF-state input capacitance
VCC = 3.3 V, VI/O = 3.3 V or 0,
Switch OFF
2
pF
Cio(ON)
ON-state input capacitance
VCC = 3.3 V, VI/O = 3.3 V or 0,
Switch ON
7.5
pF
ΔICC
(4)
RON
ON-state resistance
ΔRON
ron(flat)
(1)
(2)
(3)
(4)
(5)
(5)
10
Ω
VCC = 3 V, VI = 0.4, IO = –8 mA
6
ON-state resistance match between channels
VCC = 3 V, VI = 0.4, IO = –8 mA
0.35
Ω
ON-state resistance flatness
VCC = 3 V, VI = 0 V or 1 V, IO = –8 mA
2
Ω
VIN and IIN refer to control inputs. VI, VO, II, and IO refer to data pins.
All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C.
For I/O ports, the parameter IOZ includes the input leakage current.
This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
Measured by the voltage drop between the A and B terminals at the indicated current through the switch. ON-state resistance is
determined by the lower of the voltages of the two (A or B) terminals.
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6.6 Dynamic Electrical Characteristics
over operating range, TA = –40°C to 85°C, VCC = 3.3 V ± 10%, GND = 0 V
PARAMETER
TYP (1)
TEST CONDITIONS
UNIT
XTALK
Crosstalk
RL = 50 Ω, f = 240 MHz, See Figure 6
–54
OISO
OFF isolation
RL = 50 Ω, f = 240 MHz, See Figure 5
–40
dB
BW
Bandwidth (–3 dB)
RL = 50 Ω, CL = 5 pF, See Figure 7
900
MHz
(1)
dB
For Max or Min conditions, use the appropriate value specified under Electrical Characteristics for the applicable device type.
6.7 Switching Characteristics
over operating range, TA = –40°C to 85°C, VCC = 3.3 V ± 10%, GND = 0 V
PARAMETER
TEST CONDITIONS
RL = 50 Ω, CL = 5 pF,
See Figure 8
TYP (1)
MAX
UNIT
tpd
Propagation delay (2)
tON
Line enable time, SEL to D, nD
RL = 50 Ω, CL = 5 pF,
See Figure 4
30
ns
tOFF
Line disable time, SEL to D, nD
RL = 50 Ω, CL = 5 pF,
See Figure 4
25
ns
tON
Line enable time, OE to D, nD
RL = 50 Ω, CL = 5 pF,
See Figure 4
30
ns
tOFF
Line disable time, OE to D, nD
RL = 50 Ω, CL = 5 pF,
See Figure 4
25
ns
tSK(O)
Output skew between center port to any other port (2)
RL = 50 Ω, CL = 5 pF,
See Figure 9
50
ps
tSK(P)
Skew between opposite transitions of the same output
(tPHL – tPLH) (2)
RL = 50 Ω, CL = 5 pF,
See Figure 9
20
ps
tJ
Total jitter (2)
RL = 50 Ω, CL = 5 pF,
tR = tF = 500 ps at 480 Mbps
(PRBS = 215 – 1)
20
ps
(1)
(2)
(3)
6
(3)
MIN
0.25
ns
For Max or Min conditions, use the appropriate value specified under Electrical Characteristics for the applicable device type.
Specified by design
The bus switch contributes no propagational delay other than the RC delay of the on resistance of the switch and the load capacitance.
The time constant for the switch alone is of the order of 0.25 ns for 10-pF load. Since this time constant is much smaller than the rise/fall
times of typical driving signals, it adds very little propagational delay to the system. Propagational delay of the bus switch, when used in
a system, is determined by the driving circuit on the driving side of the switch and its interactions with the load on the driven side.
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6.8 Typical Characteristics
0
0
–10
–2
–20
Attenuation (dB)
Gain (dB)
–4
–6
–8
–30
–40
–50
–60
–10
–70
–12
–14
100.0E+3
–80
–90
1.0E+6
10.0E+6
100.0E+6
1.0E+9
10.0E+9
100.0E+3
1.0E+6
Frequency (Hz)
10.0E+6
100.0E+6
1.0E+9
10.0E+9
Frequency (Hz)
Figure 1. Gain vs Frequency
Figure 2. OFF Isolation
0
Attenuation (dB)
–20
–40
–60
–80
–100
–120
100.0E+3
1.0E+6
10.0E+6
100.0E+6
Frequency (Hz)
1.0E+9
10.0E+9
Figure 3. Crosstalk
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7 Parameter Measurement Information
VCC
1D or 2D VOUT1
VIN
TEST
RL
CL
VIN
tON
50 Ω
5 pF
VCC
tOFF
50 Ω
5 pF
VCC
D
1D or 2D VOUT2
CL(2)
RL
S
OE
VSEL(1)
1.8 V
Logic
RL
Input
(VSEL or V OE)
CL(2)
GND
50%
50%
0
tON
VOE(1)
Switch
Output
(VOUT1 or V OUT2)
tOFF
90%
90%
VOH
VOL
(1)
All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr < 5 ns,
tf < 5 ns.
(2)
CL includes probe and jig capacitance.
Figure 4. Turn-On (tON) and Turn-Off Time (tOFF)
VCC
Network Analyzer
Channel OFF: 1D to D
50 Ω
VOUT1 1D
VSEL = VCC
VIN
D
Source
Signal
50 Ω
2D
Network Analyzer Setup
Source Power = 0 dBm
(632-mV P-P at 50- Ω load)
VSEL S
50 Ω
+
GND
DC Bias = 350 mV
Figure 5. OFF Isolation (OISO)
VCC
Network Analyzer
Channel ON: 1D to D
50 Ω
VOUT1 1D
Channel OFF: 2D to D
VIN
Source
Signal
VSEL = VCC
VOUT2 2D
50 Ω
50 Ω
Network Analyzer Setup
VSEL S
+
GND
Source Power = 0 dBm
(632-mV P-P at 50- Ω load)
DC Bias = 350 mV
Figure 6. Crosstalk (XTALK)
8
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Parameter Measurement Information (continued)
VCC
Network Analyzer
50 Ω
VOUT1
1D
Channel ON: 1D to D
D
Source
Signal
VIN
VCTRL = GND
2D
Network Analyzer Setup
50 Ω
VSEL
Source Power = 0 dBm
(632-mV P-P at 50-Ω load)
S
GND
GND
DC Bias = 350 mV
Figure 7. Bandwidth (BW)
400 mV
Figure 8. Propagation Delay
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Parameter Measurement Information (continued)
VOH
VOL
Pulse Skew tSK(P)
VOH
VOL
VOH
VOL
Output Skew tSK(P)
Figure 9. Skew Test
10
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Parameter Measurement Information (continued)
VCC
VOUT1 1D
D
+
VIN
Channel ON
VOUT2 2D
r on
VSEL
IIN
S
VIN
VOUT2 or VOUT1
IIN
VSEL = VIH or VIL
+
GND
Figure 10. ON-State Resistance (RON)
VCC
VOUT1 1D
D
+
VOUT2 2D
VSEL
VIN
+
S
OFF-State Leakage Current
Channel OFF
VSEL = VIH or VIL
+
GND
Figure 11. OFF-State Leakage Current
VCC
VOUT1 1D
Capacitance
Meter
VBIAS
VBIAS = VCC or GND
VOUT2 2D
VSEL = VCC or GND
VIN D
Capacitance is measured at 1D,
2D, D, and S inputs during ON
and OFF conditions.
VSEL S
GND
Figure 12. Capacitance
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8 Detailed Description
8.1 Overview
The TS3USB30E is a high-bandwidth switch specially designed for the switching and isolating of high-speed
USB 2.0 signals in systems with limited USB I/Os. The wide bandwidth (900 MHz) of this switch allows signals to
pass with minimum edge and phase distortion. The device multiplexes differential outputs from a USB host
device to one of two corresponding outputs or from two different hosts to one corresponding output. The switch is
bidirectional and offers little or no attenuation of the high-speed signals at the outputs. It is designed for low bitto-bit skew and high channel-to-channel noise isolation, and is compatible with various standards, such as highspeed USB 2.0 (480 Mbps).
8.2 Functional Block Diagram
D1+
D+
D2+
D1–
D–
D2–
S
OE
Control
8.3 Feature Description
The TS3USB30E has a bus-switch enable pin OE that can place the signal paths in high impedance. This allows
the user to isolate the bus when it is not in use and consume less current.
8.4 Device Functional Modes
The device functional modes are shown in Table 1.
Table 1. Truth Table
12
S
OE
FUNCTION
X
H
Disconnect
L
L
D = D1
H
L
D = D2
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
There are many USB applications in which the USB hubs or controllers have a limited number of USB I/Os. The
TS3USB30E solution can effectively expand the limited USB I/Os by switching between multiple USB buses in
order to interface them to a single USB hub or controller. TS3USB221E can also be used to connect a single
controller to two USB connectors or controllers.
9.2 Typical Application
VCC
TS3USB30E
1D+
USB2.0
Controller
D+
1D–
Set Top Box
(STB) CPU
or DSP
Processor
USB
Connector
D–
2D+
DVR or
Mass Storage
Controller
2D–
Control
S
OE
Figure 13. Application Diagram
9.2.1 Design Requirements
Design requirements of the USB 1.0, 1.1, and 2.0 standards should be followed. TI recommends that the digital
control pins S and OE be pulled up to VCC or down to GND to avoid undesired switch positions that could result
from the floating pin.
9.2.2 Detailed Design Procedure
The TS3USB30E can be properly operated without any external components. However, it is recommended that
unused pins be connected to ground through a 50-Ω resistor to prevent signal reflections back into the device.
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Typical Application (continued)
0.5
0.5
0.4
0.4
0.3
0.3
Differential Signal (V)
Differential Signal (V)
9.2.3 Application Curves
0.2
0.1
0.0
–0.1
–0.2
0.2
0.1
0.0
–0.1
–0.2
–0.3
–0.3
–0.4
–0.4
–0.5
–0.5
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
0.0
2.0
0.2
0.4
0.6
–9
0.8
1.0
1.2
1.4
1.6
1.8
2.0
–9
Time (x 10 ) (s)
Time (x 10 ) (s)
Figure 14. Eye Pattern: 480-Mbps USB Signal With No
Switch (Through Path)
Figure 15. Eye Pattern: 480-Mbps USB Signal With Switch
NC Path
0.5
0.4
Differential Signal (V)
0.3
0.2
0.1
0.0
–0.1
–0.2
–0.3
–0.4
–0.5
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
–9
Time (x 10 ) (s)
Figure 16. Eye Pattern: 480-Mbps USB Signal With Switch NO Path
14
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SCDS255F – DECEMBER 2008 – REVISED AUGUST 2015
10 Power Supply Recommendations
Power to the device is supplied through the VCC pin and should follow the USB 1.0, 1.1, and 2.0 standards. TI
recommends placing a bypass capacitor as close as possible to the supply pin VCC to help smooth out lower
frequency noise to provide better load regulation across the frequency spectrum.
11 Layout
11.1 Layout Guidelines
Place supply bypass capacitors as close to VCC pin as possible and avoid placing the bypass caps near the D+
and D– traces.
The high-speed D+ and D– traces should always be of equal length and must be no more than 4 inches;
otherwise, the eye diagram performance may be degraded. A high-speed USB connection is made through a
shielded, twisted pair cable with a differential characteristic impedance. In layout, the impedance of D+ and D–
traces should match the cable characteristic differential impedance for optimal performance.
Route the high-speed USB signals using a minimum of vias and corners which will reduce signal reflections and
impedance changes. When a via must be used, increase the clearance size around it to minimize its
capacitance. Each via introduces discontinuities in the transmission line of the signal and increases the chance
of picking up interference from the other layers of the board. Be careful when designing test points on twisted
pair lines; through-hole pins are not recommended.
When it becomes necessary to turn 90°, use two 45° turns or an arc instead of making a single 90° turn. This
reduces reflections on the signal traces by minimizing impedance discontinuities.
Do not route USB traces under or near crystals, oscillators, clock signal generators, switching regulators,
mounting holes, magnetic devices, or IC’s that use or duplicate clock signals.
Avoid stubs on the high-speed USB signals because they cause signal reflections. If a stub is unavoidable, then
the stub should be less than 200 mm.
Route all high-speed USB signal traces over continuous planes (VCC or GND), with no interruptions.
Avoid crossing over anti-etch, commonly found with plane splits.
Due to high frequencies associated with the USB, a printed circuit board with at least four layers is
recommended: two signal layers separated by a ground layer and a power layer. The majority of signal traces
should run on a single layer, preferably Signal 1. Immediately next to this layer should be the GND plane, which
is solid with no cuts. Avoid running signal traces across a split in the ground or power plane. When running
across split planes is unavoidable, sufficient decoupling must be used. Minimizing the number of signal vias
reduces EMI by reducing inductance at high frequencies. For more information on layout guidelines, see High
Speed Layout Guidelines (SCAA082) and USB 2.0 Board Design and Layout Guidelines (SPRAAR7).
Submit Documentation Feedback
Copyright © 2008–2015, Texas Instruments Incorporated
Product Folder Links: TS3USB30E
15
TS3USB30E
SCDS255F – DECEMBER 2008 – REVISED AUGUST 2015
www.ti.com
11.2 Layout Example
To Device 2
VCC
To Device 1
= VIA to GND Plane
0603 Cap
OE
To System
D2-
D1-
To System
D-
VCC
GND
S
D+
To System
D2+
D1+
To System
To Device 2
To Device 1
Figure 17. Layout Recommendation
16
Submit Documentation Feedback
Copyright © 2008–2015, Texas Instruments Incorporated
Product Folder Links: TS3USB30E
TS3USB30E
www.ti.com
SCDS255F – DECEMBER 2008 – REVISED AUGUST 2015
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
• Implications of Slow or Floating CMOS Inputs, SCBA004
• High Speed Layout Guidelines, SCAA082
• USB 2.0 Board Design and Layout Guidelines, SPRAAR7
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Submit Documentation Feedback
Copyright © 2008–2015, Texas Instruments Incorporated
Product Folder Links: TS3USB30E
17
PACKAGE OPTION ADDENDUM
www.ti.com
25-Oct-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TS3USB30EDGSR
ACTIVE
VSSOP
DGS
10
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
(L6Q ~ L6R)
TS3USB30ERSWR
ACTIVE
UQFN
RSW
10
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
(LY7 ~ LYO ~ LYV)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
25-Oct-2016
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Oct-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TS3USB30EDGSR
VSSOP
DGS
10
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
TS3USB30ERSWR
UQFN
RSW
10
3000
180.0
9.5
1.6
2.0
0.8
4.0
8.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Oct-2018
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TS3USB30EDGSR
TS3USB30ERSWR
VSSOP
DGS
10
2500
358.0
335.0
35.0
UQFN
RSW
10
3000
189.0
185.0
36.0
Pack Materials-Page 2
PACKAGE OUTLINE
DGS0010A
VSSOP - 1.1 mm max height
SCALE 3.200
SMALL OUTLINE PACKAGE
C
5.05
TYP
4.75
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
10
1
3.1
2.9
NOTE 3
8X 0.5
2X
2
5
6
B
10X
3.1
2.9
NOTE 4
SEE DETAIL A
0.27
0.17
0.1
C A
1.1 MAX
B
0.23
TYP
0.13
0.25
GAGE PLANE
0 -8
0.15
0.05
0.7
0.4
DETAIL A
TYPICAL
4221984/A 05/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187, variation BA.
www.ti.com
EXAMPLE BOARD LAYOUT
DGS0010A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
10X (0.3)
10X (1.45)
(R0.05)
TYP
SYMM
1
10
SYMM
8X (0.5)
6
5
(4.4)
LAND PATTERN EXAMPLE
SCALE:10X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4221984/A 05/2015
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DGS0010A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
10X (1.45)
10X (0.3)
SYMM
1
(R0.05) TYP
10
SYMM
8X (0.5)
6
5
(4.4)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
4221984/A 05/2015
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
RSW0010A
UQFN - 0.55 mm max height
SCALE 7.000
PLASTIC QUAD FLATPACK - NO LEAD
1.45
1.35
B
A
PIN 1 INDEX AREA
1.85
1.75
0.55
0.45
NOTE 3
C
SEATING PLANE
0.05
0.00
0.05 C
2X 0.8
(0.13) TYP
SYMM
3
5
9X
0.45
0.35
2
6
SYMM
6X 0.4
7
1
10X
10
0.55
0.45
8
0.25
0.15
0.07
0.05
C A B
PIN 1 ID
4224897/A 03/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This package complies to JEDEC MO-288 variation UDEE, except minimum package height.
www.ti.com
EXAMPLE BOARD LAYOUT
RSW0010A
UQFN - 0.55 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
SYMM
8
10
10X (0.2)
SEE SOLDER MASK
DETAIL
(0.7)
1
7
SYMM
6X (0.4)
6
2
(1.6)
(R0.05) TYP
9X (0.6)
3
5
(1.2)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 30X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
OPENING
SOLDER MASK DEFINED
SOLDER MASK DETAILS
4224897/A 03/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RSW0010A
UQFN - 0.55 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
SYMM
8
10
10X (0.2)
(0.7)
1
7
SYMM
6X (0.4)
6
2
(1.6)
(R0.05) TYP
9X (0.6)
3
5
(1.2)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 30X
4224897/A 03/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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