TS3V340DR

  
   
   
 
   


  
 SCDS172A - JULY 2004 − REVISED DECEMBER 2004 D Low Differential Gain and Phase D D D D 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC EN S1D S2D DD S1C S2C DC RGY PACKAGE (TOP VIEW) S1A S2A DA S1B S2B DB VCC D D 1 1 16 15 EN 14 S1D 2 3 13 S2D 12 DD 4 5 6 7 8 GND description/ordering information 9 11 S1C 10 S2C DC D IN S1A S2A DA S1B S2B DB GND IN D D D D, DBQ, DGV, OR PW PACKAGE (TOP VIEW) (DG = 0.2%, DP = 0.1° Typ) Wide Bandwidth (BW = 500 MHz Typ) Low Crosstalk (XTALK = −80 dB Typ) Bidirectional Data Flow, With Near-Zero Propagation Delay Low and Flat ON-State Resistance (ron = 3 Ω Typ, ron(flat) = 1 Ω Typ) VCC Operating Range From 3 V to 3.6 V Ioff Supports Partial-Power-Down Mode Operation Data and Control Inputs Provide Undershoot Clamp Diode Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Performance Tested Per JESD 22 − 2000-V Human-Body Model (A114-B, Class II) − 1000-V Charged-Device Model (C101) Suitable for Both RGB and Composite Video Switching The TI video switch TS3V340 is a 4-bit 1-of-2 multiplexer/demultiplexer with a single switch-enable (EN) input. When EN is low, the switch is enabled, and the D port is connected to the S port. When EN is high, the switch is disabled, and the high-impedance state exists between the D and S ports. The select (IN) input controls the data path of the multiplexer/demultiplexer. Low differential gain and phase makes this switch ideal for composite and RGB video applications. The device has a wide bandwidth and low crosstalk, making it suitable for high-frequency applications as well. ORDERING INFORMATION QFN − RGY SOIC − D −40°C −40 C to 85 85°C C ORDERABLE PART NUMBER PACKAGE† TA SSOP (QSOP) − DBQ TSSOP − PW TVSOP − DGV Tape and reel TS3V340RGYR Tube TS3V340D Tape and reel TS3V340DR Tape and reel TS3V340DBQR Tube TS3V340PW Tape and reel TS3V340PWR Tape and reel TS3V340DGVR TOP-SIDE MARKING TF340 TS3V340 TF340 TF340 TF340 † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2004, Texas Instruments Incorporated  

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 SCDS172A - JULY 2004 − REVISED DECEMBER 2004 description/ordering information (continued) This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging current will not backflow through the device when it is powered down. This switch maintains isolation during power off. To ensure the high-impedance state during power up or power down, EN should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. FUNCTION TABLE INPUTS EN IN INPUT/OUTPUT D FUNCTION L L S1 D port = S1 port L H S2 D port = S2 port H X Z Disconnect PIN DESCRIPTION PIN NAME 2 DESCRIPTION S1, S2 Analog video I/Os D Analog video I/Os IN Select input EN Switch-enable input POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
  
   
   
 
   


  
 SCDS172A - JULY 2004 − REVISED DECEMBER 2004 PARAMETER DEFINITIONS DESCRIPTION PARAMETER RON Resistance between the D and S ports, with the switch in the ON state IOZ IOS VIN Output leakage current measured at the D and S ports, with the switch in the OFF state VEN CIN Voltage at EN Short-circuit current measured at the I/O pins Voltage at IN Capacitance at the control (EN, IN) inputs COFF Capacitance at the analog I/O port when the switch is OFF CON Capacitance at the analog I/O port when the switch is ON VIH VIL Minimum input voltage for logic high for the control (EN, IN) inputs VIK VI I/O and control (EN, IN) inputs diode clamp voltage VO IIH Voltage applied to the D or S pins when D or S is the switch output IIL II Input low leakage current of the control (EN, IN) inputs IO Ioff Current into the D or S pins when D or S is the switch output Maximum input voltage for logic low for the control (EN, IN) inputs Voltage applied to the D or S pins when D or S is the switch input Input high leakage current of the control (EN, IN) inputs Current into the D or S pins when D or S is the switch input Output leakage current measured at the D or S ports, with VCC = 0 tpds Propagation delay measured between S1x and S2x under the specified conditions, measured from 50% of the digital input to 90% of the analog output BW Frequency response of the switch in the ON state, measured at −3 dB XTALK Unwanted signal coupled from channel to channel. Measured in −dB. XTALK = 20 log VO/VI. This is a nonadjacent crosstalk. OIRR OFF isolation is the resistance (measured in −dB) between the input and output with the switch OFF. DG Magnitude variation between analog input and output pins when the switch is ON and the DC offset of composite video signal varies at the analog input pin. In NTSC standard, the frequency of the video signal is 3.58 MHz, and DC offset is from 0 to 0.714 V. DP Phase variation between analog input and output pins when the switch is ON and the DC offset of composite video signal varies at the analog input pin. In NTSC standard, the frequency of the video signal is 3.58 MHz, and DC offset is from 0 to 0.714 V. ICC ICCD Static power-supply current ∆ICC Increase in supply current for each control input that is at the specified voltage level, rather than VCC or GND Variation of ICC for a change in frequency in the control (EN, IN) inputs POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 
  
   
   
 
   


  
 SCDS172A - JULY 2004 − REVISED DECEMBER 2004 functional diagram (positive logic) 2 4 S1A DA 3 S2A DB 7 5 S1B 6 S2B 9 11 DC 10 DD 12 14 13 IN 1 15 EN 4 Control Logic POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 S1C S2C S1D S2D 
  
   
   
 
   


  
 SCDS172A - JULY 2004 − REVISED DECEMBER 2004 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V Control input voltage range, VIN (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Switch I/O voltage range, VI/O (see Notes 1, 2, and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Control input clamp current, IIK (VIN < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA I/O port clamp current, II/OK (VI/O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA ON-state switch current, II/O (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±128 mA Continuous current through VCC or GND terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance, θJA (see Note 5): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W (see Note 5): DBQ package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90°C/W (see Note 5): DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W (see Note 5): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W (see Note 6): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltages are with respect to ground, unless otherwise specified. 2. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 3. VI and VO are used to denote specific conditions for VI/O. 4. II and IO are used to denote specific conditions for II/O. 5. The package thermal impedance is calculated in accordance with JESD 51-7. 6. The package thermal impedance is calculated in accordance with JESD 51-5. recommended operating conditions (see Note 7) MIN MAX UNIT VCC VIH Supply voltage 3 3.6 V High-level control input voltage (EN, IN) 2 5.5 V VIL VO Low-level control input voltage (EN, IN) 0 0.8 V Analog I/O voltage 0 5.5 V TA Operating free-air temperature −40 85 °C NOTE 7: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 
  
   
   
 
   


  
 SCDS172A - JULY 2004 − REVISED DECEMBER 2004 electrical characteristics over recommended VCC = 3.3 V
0.3 V (unless otherwise noted)† PARAMETER VIK IIH EN, IN IIL IOZ§ IOS¶ EN, IN Ioff ICC EN, IN ICCD CIN free-air TEST CONDITIONS EN, IN ∆ICC operating EN, IN temperature range, TYP‡ MIN MAX UNIT VCC = 3 V, VCC = 3.6 V, IIN = −18 mA VIN and VEN = 5.5 V −1.8 V ±1 µA VCC = 3.6 V, VCC = 3.6 V, VIN and VEN = GND VO = 0 to 5.5 V, ±1 µA ±1 µA VCC = 3.6 V, VCC = 0, VO = 0.5 VCC, VO = 0 to 5.5 V, VCC = 3.6 V, VCC = 3.6 V, II/O = 0, One input at 3 V, VCC = 3.6 V, D and S ports open, VEN = GND, VIN input switching 50% duty cycle VIN or VEN = 5.5 V, 3.3 V or 0, f = 1 MHz VI = 5.5 V, 3.3 V, or 0, f = 1 MHz, Outputs open, Switch OFF VI = 5.5 V, 3.3 V, or 0, f = 1 MHz, Outputs open, Switch ON VCC = 3 V VI = 1 V, VI = 2 V, IO = 13 mA IO = 26 mA VI = 0, VI = 0, Switch OFF Switch ON 50 VI = 0 Switch ON or OFF 0.7 Other inputs at VCC or GND S port CON ron# µA 1.5 mA 30 D port COFF mA 1 µA 0.35 mA/ MHz 2.5 3.5 pF 5.5 7 3.5 5 10.5 14 3 6 3 6 pF pF Ω VCC = 3.3 V, VI = 0 to VCC, IO = 26 mA 1 Ω † VI, VO, II, and IO refer to I/O pins. ‡ All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C. § For I/O ports, the parameter IOZ includes the input leakage current. ¶ The IOS test is applicable to only one ON channel at a time. The duration of this test is less than 1 s. # Measured by the voltage drop between the D and S terminals at the indicated current through the switch. ON-state resistance is determined by the lower of the voltages of the two (D or S) terminals. || ron(flat) is the difference of ron in a given channel at specified voltages. ron(flat)|| switching characteristics over recommended operating free-air temperature range, VCC = 3.3 V
0.3 V, RL = 75 Ω, CL = 20 pF (unless otherwise noted) (see Figures 6 and 7) PARAMETER FROM (INPUT) TO (OUTPUT) tpd(s) IN tON tOFF TYP MAX D 2 5 ns IN or EN S 4 7 ns IN or EN S 2 7 ns dynamic characteristics over recommended VCC = 3.3 V
0.3 V (unless otherwise noted) PARAMETER DG k DPk BW XTALK OIRR operating free-air temperature TYP‡ TEST CONDITIONS UNIT range, UNIT RL = 150 Ω, f = 3.58 MHz, See Figure 7 0.2 % RL = 150 Ω, f = 3.58 MHz, See Figure 7 0.1 ° RL = 150 Ω, See Figure 8 500 MHz RL = 150 Ω, f = 10 MHz, RIN = 10 Ω, −80 dB RL = 150 Ω, f = 10 MHz, See Figure 10 −60 dB See Figure 9 ‡ All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C. k D and D are expressed in absolute magnitude. G P 6 MIN POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
  
   
   
 
   


  
 SCDS172A - JULY 2004 − REVISED DECEMBER 2004 0 0 Phase −10 −1 −2 −20 −3 −30 −4 Y −40 Phase (Deg) Gain (dB) Gain J −5 −50 −60 −6 1 10 100 700 Frequency (MHz) Gain −3 dB at 627 MHz Phase at −3-dB Frequency, −47 Deg Y J Figure 1. Gain/Phase vs Frequency 0 0.09 Differental Gain 0.08 −0.04 0.07 −0.06 0.06 −0.08 0.05 J Differental Phase −0.1 0.04 Y −0.12 0.03 −0.14 0.02 −0.16 0.01 −0.18 0 −0.2 −0.01 0 Y J Differential Phase (Deg) Differential Gain (%) −0.02 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 VBIAS (V) Differential Gain at 0.714 V, −0.11% Differential Phase at 0.714 V, 0.0466 Deg Figure 2. Differential Gain/Phase vs VBIAS POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 
  
   
   
 
   


  
 0 160 −10 140 −20 120 −30 100 Phase J −40 80 −50 60 Y −60 40 OFF Isolation 20 −70 −80 Phase (Deg) OFF Isolation (dB) SCDS172A - JULY 2004 − REVISED DECEMBER 2004 1 10 100 0 700 Frequency (MHz) Y J OFF Isolation at 10 MHz, −56 dB Phase at 10 MHz, 90 Deg 0 180 −10 160 −20 140 −30 120 100 −40 Phase J −50 80 −60 60 Y Crosstalk −70 40 −80 20 −90 0 1 10 100 Frequency (MHz) Y J Crosstalk at 10 MHz, −63 dB Phase at 10 MHz, 90 Deg Figure 4. Crosstalk vs Frequency 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 700 Phase (Deg) Crosstalk (dB) Figure 3. OFF Isolation vs Frequency 
  
   
   
 
   


  
 5 20 4 16 VO 3 12 2 8 rON 1 ON-State Resistance (Ω) Output Voltage (V) SCDS172A - JULY 2004 − REVISED DECEMBER 2004 4 0 0 0 1 2 3 4 5 Input Voltage (V) Figure 5. Output Voltage/ON-State Resistance vs Input Voltage POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 
  
   
   
 
   


  
 SCDS172A - JULY 2004 − REVISED DECEMBER 2004 PARAMETER MEASUREMENT INFORMATION VCC Input Generator VIN 50 Ω IN 50 Ω VG1 TEST CIRCUIT S1x DUT VS1 VO Dx S2x EN CL (see Note A) VS2 TEST VCC RL CL VS1 VS2 tpds 3.3 V ± 0.3 V 3.3 V ± 0.3 V 75 75 20 pF 20 pF GND VCC VCC GND Output Control (VIN) Analog Output Waveform (VO) RL VCC 50% 50% 0V 90% 90% VOH 0V VOLTAGE WAVEFORMS tpd(s) TIMES NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. C. The outputs are measured one at a time, with one transition per measurement. Figure 6. Test Circuit and Voltage Waveforms 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
  
   
   
 
   


  
 SCDS172A - JULY 2004 − REVISED DECEMBER 2004 PARAMETER MEASUREMENT INFORMATION VCC Input Generator VIN 50 Ω 50 Ω VG1 TEST CIRCUIT IN or EN S1X CL (see Note A) RL DUT DX S2X VI VCC 3.3 V ± 0.3 V TEST tON/tOFF CL (see Note A) RL CL VI 75 W 20 pF VCC RL VCC Output Control (VIN) 50% 50% 0V tON Analog Output Waveform (VO) VO tOFF 90% 90% VOH 0V VOLTAGE WAVEFORMS tON AND tOFF TIMES NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. C. The outputs are measured one at a time, with one transition per measurement. Figure 7. Test Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 
  
   
   
 
   


  
 SCDS172A - JULY 2004 − REVISED DECEMBER 2004 PARAMETER MEASUREMENT INFORMATION EXT TRIGGER VBIAS BIAS Network Analyzer (HP8753ES) Sawtooth Waveform Generator P1 P2 VCC S1A DA RL = 150 Ω IN DUT VIN EN VEN NOTE: For additional information on measurement method, refer to the TI application report, Measuring Differential Gain and Phase, literature number SLOA040. Figure 8. Test Circuit for Differential Gain/Phase Measurement Differential gain and phase is measured at the output of the ON channel. For example, when VIN = 0, VEN = 0, and DA is the input, the output is measured at S1A. HP8753ES setup Average = 20 RBW = 300 Hz ST = 1.381 s P1 = −7 dBM CW frequency = 3.58 MHz sawtooth waveform generator setup VBIAS = 0 to 1 V Frequency = 0.905 Hz 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
  
   
   
 
   


  
 SCDS172A - JULY 2004 − REVISED DECEMBER 2004 PARAMETER MEASUREMENT INFORMATION EXT TRIGGER BIAS VBIAS Network Analyzer (HP8753ES) P1 P2 VCC S1A DA RL = 150 Ω IN DUT VIN EN VEN Figure 9. Test Circuit for Frequency Response (BW) The frequency response is measured at the output of the ON channel. For example, when VIN = 0, VEN = 0, and DA is the input, the output is measured at S1A. All unused analog I/O ports are left open. HP8753ES setup Average = 4 RBW = 3 kHz VBIAS = 0.35 V ST = 2 s P1 = 0 dBM POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 
  
   
   
 
   


  
 SCDS172A - JULY 2004 − REVISED DECEMBER 2004 PARAMETER MEASUREMENT INFORMATION EXT TRIGGER BIAS VBIAS Network Analyzer (HP8753ES) P1 P2 VCC DA S1A RL = 150 Ω IN 50 Ω† VIN EN DUT VEN DB S1B RIN = 10 Ω RL = 150 Ω † A 50-Ω termination resistor is needed for the network analyzer. Figure 10. Test Circuit for Crosstalk (XTALK) The crosstalk is measured at the output of the nonadjacent ON channel. For example, when VIN = 0, VEN = 0, and DA is the input, the output is measured at S1B. All unused analog input (D) ports and output (S) ports are connected to GND through 10-Ω and 50-Ω pulldown resistors, respectively. HP8753ES setup Average = 4 RBW = 3 kHz VBIAS = 0.35 V ST = 2 s P1 = 0 dBM 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
  
   
   
 
   


  
 SCDS172A - JULY 2004 − REVISED DECEMBER 2004 PARAMETER MEASUREMENT INFORMATION EXT TRIGGER BIAS VBIAS Network Analyzer (HP8753ES) P1 P2 VCC S1A DA RL = 150 Ω IN DUT VIN S2A EN RL = 150 Ω 50 Ω† VEN † A 50-Ω termination resistor is needed for the network analyzer. Figure 11. Test Circuit for OFF Isolation (OIRR) The OFF isolation is measured at the output of the OFF channel. For example, when VIN = VCC, VEN = 0, and DA is the input, the output is measured at S1A. All unused analog input (D) ports are left open, and output (S) ports are connected to GND through 50-Ω pulldown resistors. HP8753ES setup Average = 4 RBW = 3 kHz VBIAS = 0.35 V ST = 2 s P1 = 0 dBM POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) TS3V340D ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TS3V340 Samples TS3V340DBQR ACTIVE SSOP DBQ 16 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 TF340 Samples TS3V340DGVR ACTIVE TVSOP DGV 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TF340 Samples TS3V340DR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TS3V340 Samples TS3V340PW ACTIVE TSSOP PW 16 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TF340 Samples TS3V340PWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TF340 Samples TS3V340RGYR ACTIVE VQFN RGY 16 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 TF340 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of