TSB43AA82APGE

TSB43AA82A TSB43AA82AI www.ti.com SLLA205 – MAY 2006 (iSphynx II) 1394 Integrated PHY and Link-Layer Controller for SBP-2 Products and DPP Products FEATURES • • • • • • • • IEEE 1394a-2000 Compliant Single 3.3-V Supply Internal 1.8-V Circuit to Reduce Power Consumption Integrated 400-Mbps Two-Port Physical Layer (PHY) Internal Voltage Regulator IEEE 1394 Related Functions: – Automated Read Response for ConfigROM Register Access – Automated Single Retry Protocol and Split Transaction Control SBP-2 Related Functions: – Supports Four Initiators by Automated Transactions and More Can Be Supported Through Firmware. – Automated Management ORB Fetching – Automated Linked Command ORB Fetching – Automated PageTable Fetching – Automated Status Block Transmit Ability to Support Direct Print Protocol (DPP) Mode • Data Transfers: – Auto Address Increment of Direct/Indirect Addressing on Data Transfer (Packetizer) – Automated Header Insert/Strip for DMA Data Transfers – 8-/16-Bit Asynchronous and Synchronous DMA I/F With Handshake and Burst Mode – Supports ATAPI (Ultra-DMA) Mode and SCSI Mode – 8-/16-Bit Data/Address Multiplex Microcontroller and 8-/16-Bit Separated Data/Address Bus – Three FIFO Configurations That Support High Performance for the DMA and for Command Exchanges • Asynchronous Command FIFO: 1512 Bytes • Config ROM/LOG FIFO: 504 Bytes • DMA FIFO: 4728 Bytes DESCRIPTION The TSB43AA82A is a high performance 1394 integrated PHY and link layer controller. It is compliant with the IEEE 1394-1995 and IEEE 1394a-2000 specifications and supports asynchronous transfers. TSB43AA82A has a generic 16-/8-bit host bus interface. It supports parallel or multiplexed connections to the microcontroller (MCU) at rates up to 40 MHz. The TSB43AA82A offers large data transfers with three mutually independent FIFOs: 1) the asynchronous command FIFO with 1512 Bytes, 2) the DMA FIFO with 4728 bytes and 3) the Config ROM/LOG FIFO with 504 bytes. The features of the TSB43AA82A support the serial bus protocol 2 (SBP-2). It handles up to four initiators with the SBP-2 transaction/timer manager. This SBP-2 transaction engine supports fully automated operation request block (ORB) fetches and fully automated memory page table fetches for both read and write transactions. Automated responses to other node requests are provided; this includes responding to another node’s read request to the Config ROM and issuing ack_busy_X for a single retry. Various control registers enable the user to program IEEE 1394 asynchronous transaction settings. The user can program the number of retries and the split transaction time-out value by setting the time limit register in the CFR. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006, Texas Instruments Incorporated TSB43AA82A TSB43AA82AI www.ti.com SLLA205 – MAY 2006 The TSB43AA82A also supports the direct print protocol (DPP). The asynchronous receive FIFO (ARF) in the TSB43AA82A is large enough to satisfy the connection register area, the DRF receiving FIFO can be used as the segment data unit (SDU) register to fulfill the large data transfer. This document is not intended to serve as a tutorial on IEEE 1394; users are referred to IEEE Std 1394-1995 and IEEE 1394a-2000 . (1) NOTE: This product is for high-volume CE applications only. For a complete datasheet or more information contact support@ti.com. (1) 2 IEEE Std 1394-1995, IEEE Standard for a High Performance Serial Bus IEEE Std 1394a–2000, IEEE Standard for a High Performance Serial Bus – Amendment 1 Submit Documentation Feedback PACKAGE OPTION ADDENDUM www.ti.com 13-Jul-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) (3) Device Marking Samples (4/5) (6) TSB43AA82APGE ACTIVE LQFP PGE 144 60 RoHS & Green NIPDAU Level-2-260C-1 YEAR 0 to 70 TSB43AA82A (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of