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TSC2007-Q1
SBAS545A – SEPTEMBER 2011 – REVISED DECEMBER 2016
TSC2007-Q1 1.2-V to 3.6-V, 12-Bit, Nanopower, 4-Wire
Micro Touch-Screen Controller With I2C Interface
1 Features
2 Applications
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
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Qualified for Automotive Applications
AEC-Q100 Test Guidance With the Following:
– Device Temperature Grade 3: –40°C to 85°C
Ambient Operating Temperature Range
– Device HBM ESD Classification Level 3B
– Device CDM ESD Classification Level C6
4-Wire Touch-Screen Interface
Single 1.2-V to 3.6-V Supply or Reference
Ratiometric Conversion
Effective Throughput Rate:
– Up to 20 kHz (8-Bit) or 10 kHz (12-Bit)
Preprocessing to Reduce Bus Activity
I2C Interface Supports:
– Standard, Fast, and High-Speed Modes
Simple, Command-Based User Interface:
– TSC2003-Q1 Compatible
– 8-Bit or 12-Bit Resolution
On-Chip Temperature Measurement
Touch Pressure Measurement
Internal Detection of Screen Touch
For Pen Touch Detect or Data Available Interrupt
Auto Power-Down Control
Low Power:
– 32.24 μA at 1.2 V, Fast Mode, 8.2 kHzEqualization Rate
– 39.31 μA at 1.8 V, Fast Mode, 8.2 kHzEqualization Rate
– 53.32 μA at 2.7 V, Fast Mode, 8.2 kHzEqualization Rate
Enhanced ESD Protection:
– ±25-kV Air-Gap Discharge
– ±15-kV Contact Discharge
– 5-mm × 4.4-mm 16-Pin TSSOP Package
NOTE: U.S. Patent NO. 6246394; other patents pending.
Automotive Infotainment Displays
Automotive Navigation Systems
Industrial User Interfaces
Multiscreen Touch Control Systems
3 Description
The TSC2007-Q1 device is a very low-power touch
screen controller designed to work with powersensitive, automotive touch-screen displays. It
contains a complete, ultra-low power, 12-bit, analogto-digital (A-D) resistive touch screen converter,
including drivers and the control logic to measure
touch pressure.
In addition to these standard features, the
TSC2007‑Q1 offers preprocessing of the touch
screen measurements to reduce bus loading, thus
reducing the consumption of host processor
resources that can then be redirected to more critical
functions.
The TSC2007-Q1 supports an I2C serial bus and data
transmission protocol in all three defined modes:
standard,
fast,
and
high-speed.
It
offers
programmable resolution of 8 bits or 12 bits to
accommodate different screen sizes and performance
needs.
The TSC2007-Q1 is available in a 16-pin TSSOP
package. The TSC2007-Q1 is characterized for the
–40°C to 85°C industrial temperature range.
Device Information(1)
PART NUMBER
TSC2007-Q1
PACKAGE
BODY SIZE (NOM)
TSSOP (16)
5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Functional Block Diagram
VDD/REF
PENIRQ
X+
XY+
Y-
Touch
Screen
Drivers
Interface
Mux
SAR
ADC
TEMP
AUX
Internal
Clock
Preprocessing
1
I2C
Serial
Interface
and
Control
SCL
SDA
A[0:1]
GND
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TSC2007-Q1
SBAS545A – SEPTEMBER 2011 – REVISED DECEMBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
Absolute Maximum Ratings ...................................... 4
ESD Ratings.............................................................. 4
Recommended Operating Conditions....................... 4
Thermal Information .................................................. 4
Electrical Characteristics........................................... 5
Timing Requirements: Standard Mode
(SCL = 100 kHz) ........................................................ 6
6.7 Timing Requirements: Fast Mode (SCL = 400 kHz). 7
6.8 Timing Requirements: High-Speed Mode
(SCL = 1.7 MHz) ........................................................ 7
6.9 Timing Requirements: High-Speed Mode
(SCL = 3.4 MHz) ........................................................ 8
6.10 Typical Characteristics ............................................ 9
7
Detailed Description ............................................ 12
7.1 Overview ................................................................. 12
7.2
7.3
7.4
7.5
8
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Programming...........................................................
12
12
19
19
Application and Implementation ........................ 29
8.1 Application Information............................................ 29
8.2 Typical Application .................................................. 29
9 Power Supply Recommendations...................... 33
10 Layout................................................................... 33
10.1 Layout Guidelines ................................................. 33
10.2 Layout Example .................................................... 34
11 Device and Documentation Support ................. 35
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Device Support......................................................
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
35
35
35
35
35
35
35
12 Mechanical, Packaging, and Orderable
Information ........................................................... 35
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (September 2011) to Revision A
Page
•
Added Device Information table, Specifications section, ESD Ratings table, Recommended Operating Conditions
table, Detailed Description section, Application and Implementation section, Power Supply Recommendations
section, Layout Guidelines section, Layout Example section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
•
Deleted Ordering Information table; see Package Option Addendum at the end of the data sheet ...................................... 1
•
Changed ESD Ratings information and added the AEC-Q100 Automotive bullets to Features ............................................ 1
•
Added Automotive Infotainment Displays and Automotive Navigation Systems bullets to Applications................................ 1
•
Deleted Digital Buffered PENIRQ bullet from Features.......................................................................................................... 1
•
Deleted On-Chip, Programmable PENIRQ Pull-Up bullet from Features ............................................................................. 1
•
Deleted Lead temperature parameters from Absolute Maximum Ratings table .................................................................... 1
•
Moved Power-supply voltage parameters from Electrical Characteristics table to the Recommended Operating
Conditions table ..................................................................................................................................................................... 1
•
Added IEC discharge information........................................................................................................................................... 4
•
Added Thermal Information table ........................................................................................................................................... 4
•
Changed RθJA values for PW (TSSOP) From: 86 To: 101.7 .................................................................................................. 4
•
Changed tOF to tF in Timing Requirements tables .................................................................................................................. 6
•
Changed text in Reference mode to clarify singled-ended operation .................................................................................. 15
•
Changed Figure 24 caption text from PINTDAV to PENIRQ ............................................................................................... 18
•
Added subsections to Throughput Rate and I2C Bus Traffic section to clarify 8-bit and 12-bit operation........................... 26
2
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SBAS545A – SEPTEMBER 2011 – REVISED DECEMBER 2016
5 Pin Configuration and Functions
PW package
16-Pin TSSOP
Top View
VDD/REF
1
16
AUX
X+
2
15
NC
Y+
3
14
A0
X–
4
13
A1
Y–
5
12
SCL
GND
6
11
SDA
NC
7
10
PENIRQ
NC
8
9
NC
Not to scale
Pin Functions
PIN
NAME
NO.
I/O
A/D
DESCRIPTION
A0
14
Input
Digital
Address input bit 0
A1
13
Input
Digital
Address input bit 1
AUX
16
Input
Analog
Auxiliary channel input
GND
6
—
—
Ground
7, 8, 9, 15
—
—
No connection
PENIRQ
10
Output
Digital
Data available interrupt output. A delayed (process delay) pen touch detect. Pin polarity
with active low.
SCL
12
Input and
Output
Digital
Serial clock. This pin is normally an input, but acts as an output when the device stretches
the clock to delay a bus transfer.
SDA
11
Input and
Output
Digital
Serial data I/O
VDD/REF
1
Input
—
X+
2
Input
Analog
X+ channel input
X–
4
Input
Analog
X– channel input
Y+
3
Input
Analog
Y+ channel input
Y–
5
Input
Analog
Y– channel input
NC
Supply voltage and external reference input
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TSC2007-Q1
SBAS545A – SEPTEMBER 2011 – REVISED DECEMBER 2016
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted). (1)
MIN
MAX
X+, Y+, AUX to GND
–0.4
VDD + 0.1
X–, Y– to GND
–0.4
VDD + 0.1
VDD/REF pin to GND
–0.3
5
V
–0.3
VDD + 0.3
V
Digital output voltage to GND
–0.3
VDD + 0.3
V
Power dissipation
(TJ(MAX) – TA) / RθJA
Analog input voltage
Voltage
Digital input voltage to GND
Operating free-air temperature, TA
–40
Junction temperature, TJ
Storage temperature, Tstg
(1)
–65
UNIT
V
85
°C
150
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
Human-body model (HBM), per AEC Q100-002 (1)
V(ESD)
(1)
(2)
Electrostatic discharge
UNIT
±8000
Charged-device model (CDM), per AEC Q100-011
±1000
IEC 61000-4-2 contact discharge (2)
Pins 2, 3, 4, and 5
±15000
IEC 61000-4-2 air-gap discharge (2)
Pins 2, 3, 4, and 5
±25000
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
Test method based on IEC standard 61000-4-2. Contact Texas Instruments for test details.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VDD
Power-supply voltage
VDD
MIN
MAX
1.2
3.6
UNIT
V
6.4 Thermal Information
TSC2007-Q1
THERMAL METRIC (1)
PW (TSSOP)
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
101.7
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
35.2
°C/W
RθJB
Junction-to-board thermal resistance
47.7
°C/W
ψJT
Junction-to-top characterization parameter
2.4
°C/W
ψJB
Junction-to-board characterization parameter
47
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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SBAS545A – SEPTEMBER 2011 – REVISED DECEMBER 2016
6.5 Electrical Characteristics
TA = –40°C to 85°C, VDD = 1.2 V to 3.6 V (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AUXILIARY ANALOG INPUT
Input voltage range
0
Input capacitance
VDD
V
12
Input leakage current
–1
pF
1
µA
12
Bits
A-D CONVERTER
Resolution
Programmable: 8 bits or 12 bits
No missing codes
12-bit resolution
11
Bits
±1.5
LSB (1)
VDD = 1.8 V
–1.2
LSB
VDD = 3 V
–3.1
LSB
VDD = 1.8 V
0.7
LSB
VDD = 3 V
0.1
LSB
TA = 25°C, VDD = 1.8 V, command 1011 set 0000
51
kΩ
TA = 25°C, VDD = 1.8 V, command 1011 set 0001
90
kΩ
Y+, X+
6
Ω
Y–, X–
5
Integral linearity
Offset error
Gain error
TOUCH SENSORS
PENIRQ pullup resistor, RIRQ
Switch ON‑resistance
Switch drivers drive current (2) (3)
100-ms duration
Ω
50
mA
INTERNAL TEMPERATURE SENSOR
Temperature range
–40
Differential method (4)
Resolution
TEMP1 (5)
Differential method (4)
Accuracy
TEMP1 (5)
85
°C
VDD = 3 V
1.94
°C/LSB
VDD = 1.6 V
1.04
°C/LSB
VDD = 3 V
0.35
°C/LSB
VDD = 1.6 V
0.19
°C/LSB
VDD = 3 V
±2
°C/LSB
VDD = 1.6 V
±2
°C/LSB
VDD = 3 V
±3
°C/LSB
VDD = 1.6 V
±3
°C/LSB
VDD = 1.2 V
3.19
MHz
VDD = 1.8 V
3.66
MHz
VDD = 2.7 V
3.78
MHz
VDD = 3.6 V
3.82
MHz
VDD = 1.2 V
1.6
MHz
VDD = 1.8 V
1.83
MHz
VDD = 2.7 V
1.88
MHz
VDD = 3.6 V
1.91
MHz
0.0056
%/°C
0.012
%/°C
INTERNAL OSCILLATOR
8-Bit
Internal clock frequency, fCCLK
12-Bit
Frequency drift
(1)
(2)
(3)
(4)
(5)
VDD = 1.6 V
VDD = 3 V
LSB means Least Significant Bit. With VDD/REF pin = 1.6 V, one LSB is 391 µV.
Not production tested. Specified by design.
Exceeding 50-mA source current may result in device degradation.
Difference between TEMP1 and TEMP2 measurement; no calibration necessary.
Temperature drift is –2.1 mV/°C.
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Electrical Characteristics (continued)
TA = –40°C to 85°C, VDD = 1.2 V to 3.6 V (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL INPUT AND OUTPUT
Logic family
CMOS
1.2 V ≤ VDD < 1.6 V
0.7 × VDD
VDD + 0.3
V
1.6 V ≤ VDD ≤ 3.6 V
0.7 × VDD
VDD + 0.3
V
1.2 V ≤ VDD < 1.6 V
–0.3
0.2 × VDD
V
1.6 V ≤ VDD ≤ 3.6 V
–0.3
0.3 × VDD
V
IIL
SCL and SDA pins
–1
1
µA
CIN (2)
SCL and SDA pins
10
pF
VOH
IOH = 2 TTL loads
VDD – 0.2
VDD
V
VOL
IOL = 2 TTL loads
0
0.2
V
ILEAK
Floating output
–1
1
µA
COUT (2)
Floating output
10
pF
190
µA
VIH
VIL
Logic level
Data format
Straight binary
POWER-SUPPLY REQUIREMENTS
VDD = 1.2 V, 32.56k eq rate
128
VDD = 1.2 V, 8.2k eq rate
Quiescent supply current
(VDD with sensor off)
Power down supply current
12-bit Fast mode
(clock = 400 kHz)
PD[1:0] = 0,0
32.24
VDD = 1.8 V, 34.42k eq rate
165
VDD = 1.8 V, 8.2k eq rate
39.31
VDD = 2.7 V, 34.79k eq rate
226.2
VDD = 2.7 V, 8.2k eq rate
53.32
Not addressed, SCL = SDA = 1
0
µA
240
µA
µA
335
µA
µA
0.8
µA
POWER-ON AND OFF SLOPE REQUIREMENTS (2)
VDD off ramp
TA = –40°C to 85°C
VDD off time
VDD on ramp
2
kV/s
TA = –40°C to 85°C, VDD = 0 V
1.2
TA = –20°C to 85°C, VDD = 0 V
0.3
s
s
TA = –40°C to 85°C
12
kV/s
6.6 Timing Requirements: Standard Mode (SCL = 100 kHz)
TA = –40°C to 85°C, VDD = 1.6 V (unless otherwise noted).
MIN
fSCL
SCL clock frequency
tBUF
Bus free time between a STOP and START condition
tHD,
STA
Hold time (repeated) START condition
tLOW
Low period of SCL clock
tHIGH
High period of the SCL clock
tSU,
STA
Setup time for a repeated START condition
tHD,
DAT
Data hold time
tSU,
DAT
Data setup time
tF
Fall time for both SDA and
SCL signals
tSU,
Setup time for STOP condition
Effective throughput
Equivalent rate = effective
throughput × 7
6
kHz
µs
4
µs
4.7
µs
4
µs
4.7
µs
3.45
µs
ns
Cb = total bus capacitance
1000
ns
Receiving
Cb = total bus capacitance
300
ns
Transmitting
Cb = total bus capacitance
250
4
Capacitive load for each bus line
Cycle time
UNIT
100
250
tR
STO
MAX
4.7
0
Rise time for both SDA and SCL signals
(receiving)
Cb
NOM
0
ns
µs
Cb = total capacitance of one bus line in pF
400
pF
8 bits
40 SCL + 127 CCLK, VDD = 1.8 V
434.7
12 bits
49 SCL + 148 CCLK, VDD = 1.8 V
570.9
8 bits
VDD = 1.8 V
2.3
kSPS
12 bits
VDD = 1.8 V
1.75
kSPS
8 bits
VDD = 1.8 V
16.1
kHz
12 bits
VDD = 1.8 V
12.26
kHz
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µs
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SBAS545A – SEPTEMBER 2011 – REVISED DECEMBER 2016
6.7 Timing Requirements: Fast Mode (SCL = 400 kHz)
All specifications typical at –40°C to 85°C, VDD = 1.6 V (unless otherwise noted).
MIN
NOM
UNIT
400
kHz
SCL clock frequency
tBUF
Bus free time between a STOP and START condition
1.3
µs
Hold time (repeated) START condition
0.6
µs
tLOW
Low period of SCL clock
1.3
µs
tHIGH
High period of the SCL clock
0.6
µs
tSU,
STA
Setup time for a repeated START condition
0.6
DAT
Data hold time
DAT
Data setup time
tHD,
tHD,
tSU,
STA
0
MAX
fSCL
tR
tF
Fall time for both SDA and
SCL signals
STO
Cb
Equivalent rate = effective
throughput × 7
ns
20 + 0.1 × Cb
300
ns
Receiving
Cb = total bus capacitance
20 + 0.1 × Cb
300
ns
Transmitting
Cb = total bus capacitance
20 + 0.1 × Cb
250
0.6
Capacitive load for each bus line
Effective throughput
µs
Cb = total bus capacitance
Setup time for STOP condition
Cycle time
0.9
100
Rise time for both SDA and SCL signals
(receiving)
tSU,
µs
0
ns
µs
Cb = total capacitance of one bus line in pF
400
pF
8 bits
40 SCL + 127 CCLK, VDD = 1.8 V
134.7
12 bits
49 SCL + 148 CCLK, VDD = 1.8 V
203.4
µs
µs
8 bits
VDD = 1.8 V
7.42
kSPS
12 bits
VDD = 1.8 V
4.92
kSPS
8 bits
VDD = 1.8 V
51.97
kHz
12 bits
VDD = 1.8 V
34.42
kHz
6.8 Timing Requirements: High-Speed Mode (SCL = 1.7 MHz)
All specifications typical at –40°C to 85°C, VDD = 1.6 V (unless otherwise noted).
MIN
NOM
UNIT
1.7
MHz
SCL clock frequency
tHD,
Hold time (repeated) START condition
160
ns
tLOW
Low period of SCL clock
320
ns
tHIGH
High period of the SCL clock
120
ns
tSU,
STA
Setup time for a repeated START condition
160
ns
tHD,
DAT
Data hold time
0
tSU,
DAT
Data setup time
10
STA
0
MAX
fSCL
150
ns
ns
tR
Rise time for a signal
(receiving)
SCL
Cb = total bus capacitance
20
80
ns
SDA
Cb = total bus capacitance
20
160
ns
tF
Fall time for a signal
(receiving)
SCL
Cb = total bus capacitance
20
80
ns
SDA
Cb = total bus capacitance
20
160
ns
tF
Fall time for both SDA and SCL signals
(transmitting)
Cb = total bus capacitance
20
160
ns
400
pF
tSU,
Cb
STO
Setup time for STOP condition
160
Capacitive load for each bus line
Cycle time
Effective throughput
Equivalent rate = effective
throughput × 7
ns
Cb = total capacitance of one bus line in pF
8 bits
40 SCL + 127 CCLK, VDD = 1.8 V
58.2
12 bits
49 SCL + 148 CCLK, VDD = 1.8 V
109.7
µs
8 bits
VDD = 1.8 V
17.17
kSPS
12 bits
VDD = 1.8 V
9.12
kSPS
8 bits
VDD = 1.8 V
120.22
kHz
12 bits
VDD = 1.8 V
63.81
kHz
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6.9 Timing Requirements: High-Speed Mode (SCL = 3.4 MHz)
All specifications typical at –40°C to 85°C, VDD = 1.6 V (unless otherwise noted).
MIN
fSCL
tHD,
SCL clock frequency
NOM
0
MAX
UNIT
3.4
MHz
Hold time (repeated) START condition
160
ns
tLOW
Low period of SCL clock
160
ns
tHIGH
High period of the SCL clock
60
ns
tSU,
STA
Setup time for a repeated START condition
DAT
Data hold time
0
DAT
Data setup time
10
tHD,
tSU,
STA
160
ns
70
ns
ns
Rise time for a signal
(receiving)
SCL
Cb = total bus capacitance
10
40
ns
SDA
Cb = total bus capacitance
10
80
ns
tF
Fall time for a signal
(receiving)
SCL
Cb = total bus capacitance
10
40
ns
SDA
Cb = total bus capacitance
10
80
ns
tF
Fall time for both SDA and SCL signals
(transmitting)
Cb = total bus capacitance
10
80
ns
100
pF
tR
tSU,
Cb
STO
Setup time for STOP condition
160
Capacitive load for each bus line
Cycle time
Effective throughput
Equivalent rate = effective
throughput × 7
ns
Cb = total capacitance of one bus line in pF
8 bits
40 SCL + 127 CCLK, VDD = 1.8 V
46.5
12 bits
49 SCL + 148 CCLK, VDD = 1.8 V
95.3
µs
µs
8 bits
VDD = 1.8 V
21.52
kSPS
12 bits
VDD = 1.8 V
10.49
kSPS
8 bits
VDD = 1.8 V
150.65
kHz
12 bits
VDD = 1.8 V
73.46
kHz
SDA
tSU, STA
tSU, DAT
tHD, DAT
tLOW
SCL
tBUF
tHD, STA
tSU, STO
tHIGH
tHD, STA
tR
START
CONDITION
tF
REPEATED
START
CONDITION
STOP
CONDITION
START
CONDITION
Figure 1. Detailed I/O Timing
8
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6.10 Typical Characteristics
At TA = –40°C to 85°C, VDD = 1.2 V to 3.6 V, PD1 = PD0 = 0, Fast mode, 12-bit mode, non-continuous AUX measurement,
and MAV filter enabled (see MAV Filter section), unless otherwise noted.
350
High-Speed Mode = 3.4MHz
300
80
VDD = 3.0V
VDD = 3.6V
Supply Current (mA)
Power-Down Supply Current (nA)
100
60
40
VDD = 1.6V
20
250
Fast Mode = 400kHz
200
150
100
Standard Mode = 100kHz
50
0
0
-40
-20
0
20
40
60
80
100
-40
-20
Temperature (°C)
20
40
60
80
100
Temperature (°C)
Figure 2. Power-Down Supply Current vs Temperature
Figure 3. Supply Current vs Temperature
600
300
High-Speed Mode = 3.4MHz
250
Supply Current (mA)
500
Supply Current (mA)
0
400
Fast Mode = 400kHz
300
200
Standard Mode = 100kHz
100
TA = +25°C
I2C Speed = 400kHz
PD1 = PD0 = 0
X, Y, Z Conversion at 200SSPS
200
with MAV
150
MAV Bypassed
100
Touch Sensor Modeled By:
2kW for X-Plane
2kW for Y-Plane
1kW for Z (Touch Resistance)
50
0
0
1.2
1.6
2.0
2.4
2.8
3.2
3.6
1.2
1.6
2.0
VDD (V)
2.4
2.8
3.2
3.6
VDD (V)
Figure 4. Supply Current vs
Supply Voltage (AUX Conversion)
Figure 5. Supply Current vs Supply Voltage
250
70
200
High-Speed Mode = 3.4MHz
50
Supply Current (mA)
Supply Current (mA)
60
40
30
20
Fast Mode = 400kHz
10
150
High-Speed Mode = 3.4MHz
100
Standard Mode = 100kHz
50
Fast Mode = 400kHz
Standard Mode = 100kHz
0
0
-40
-20
0
20
40
Temperature (°C)
60
80
100
Figure 6. Supply Current (Part Not Addressed) vs
Temperature
1.2
1.6
2.0
2.4
VDD (V)
2.8
3.2
3.6
Figure 7. Supply Current (Part Not Addressed) vs
Supply Voltage
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Typical Characteristics (continued)
At TA = –40°C to 85°C, VDD = 1.2 V to 3.6 V, PD1 = PD0 = 0, Fast mode, 12-bit mode, non-continuous AUX measurement,
and MAV filter enabled (see MAV Filter section), unless otherwise noted.
6
6
VDD = 1.8V
VDD = 1.8V
4
Delta from +25°C (LSB)
Delta from +25°C (LSB)
4
2
0
-2
2
0
-2
-4
-4
-6
-6
-40
-20
0
20
40
Temperature (°C)
60
80
100
-40
Figure 8. Change in Gain vs Temperature
-20
0
20
40
Temperature (°C)
80
100
Figure 9. Change in Gain vs Temperature
6
11
X+, Y+: VDD = 3.0V to Pin
X-, Y-: Pin to GND
10
Y+
Y5
9
8
RON (W)
RON (W)
60
7
Y-
X+
4
X-
6
Y+
3
5
X-
4
X+
2
3
1.2
1.6
2.0
2.4
2.8
3.6
3.2
-40
-20
0
VDD (V)
Figure 10. Switch ON-Resistance vs Supply Voltage
7
X+, Y+: VDD = 1.8V to Pin
X-, Y-: Pin to GND
60
80
100
Figure 11. Switch ON-Resistance vs Temperature
Y+
6
RON (W)
40
850
800
Y-
TEMP Diode Voltage (mV)
8
20
Temperature (°C)
X+
5
X4
3
TEMP2
Measurement Includes
A/D Converter Offset
and Gain Errors
TEMP1
137.5mV
94.2mV
750
700
650
600
550
500
450
2
-40
10
VDD = 1.8V
400
-20
0
20
40
60
80
100
-40
-20
0
20
40
60
80
100
Temperature (°C)
Temperature (°C)
Figure 12. Switch ON-Resistance vs Temperature
Figure 13. TEMP Diode Voltage vs Temperature
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Typical Characteristics (continued)
At TA = –40°C to 85°C, VDD = 1.2 V to 3.6 V, PD1 = PD0 = 0, Fast mode, 12-bit mode, non-continuous AUX measurement,
and MAV filter enabled (see MAV Filter section), unless otherwise noted.
704
Measurement Includes
A/D Converter Offset
and Gain Errors
586
TEMP2 Diode Voltage (mV)
TEMP1 Diode Voltage (mV)
588
584
582
580
578
576
VDD = VREF
574
1.2
1.6
2.0
2.4
VDD (V)
2.8
3.2
696
694
692
VDD = VREF
1.2
3.30
3.20
3.10
3.00
2.90
2.80
VDD = 1.2V
2.70
0
20
40
Temperature (°C)
60
80
2.0
2.4
VDD (V)
2.8
3.2
3.6
3.70
3.65
3.60
100
VDD = 1.8V
-40
Figure 16. Internal Oscillator Clock Frequency vs
Temperature
Internal Oscillator Clock Frequency (MHz)
1.6
Figure 15. TEMP2 Diode Voltage vs Supply Voltage
Internal Oscillator Clock Frequency (MHz)
Internal Oscillator Clock Frequency (MHz)
698
3.6
3.40
-20
700
690
Figure 14. TEMP1 Diode Voltage vs Supply Voltage
-40
Measurement Includes
A/D Converter Offset
and Gain Errors
702
-20
0
20
40
Temperature (°C)
60
80
100
Figure 17. Internal Oscillator Clock Frequency vs
Temperature
3.90
3.85
3.80
3.75
VDD = 3.0V
3.70
-40
-20
0
20
40
Temperature (°C)
60
80
100
Figure 18. Internal Oscillator Clock Frequency vs Temperature
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7 Detailed Description
7.1 Overview
The TSC2007-Q1 is an analog interface circuit for a human interface touch screen devices. All peripheral
functions are controlled through the command byte and onboard state machines. The TSC2007-Q1 features
include:
• Very low-power touch screen controller
• Very small onboard footprint
• Relieves host from tedious routine tasks by preprocessing, thus saving resources for more critical tasks
• Ability to work on very low supply voltage
• Minimal connection interface allows easy isolation and reduces the number of dedicated I/O pins required
• Miniature, yet complete; requires no external supporting components
• Enhanced electrostatic discharge (ESD) protection
The TSC2007-Q1 consists of the following blocks (see Functional Block Diagram):
• Touch Screen Sensor Interface
• Auxiliary Input (AUX)
• Temperature Sensor
• Acquisition Activity Preprocessing
• Internal Conversion Clock
• I2C Interface
Communication with the TSC2007-Q1 is done through an I2C serial interface. The TSC2007-Q1 is an I2C slave
device; therefore, data are shifted into or out of the TSC2007-Q1 under control of the host microprocessor, which
also provides the serial data clock.
Control of the TSC2007-Q1 and its functions is accomplished by writing to the command register of an internal
state machine. A simple command protocol compatible with I2C is used to address this register.
7.2 Functional Block Diagram
VDD/REF
X+
XY+
Y-
Touch
Screen
Drivers
Interface
Mux
SAR
ADC
TEMP
Preprocessing
PENIRQ
AUX
I2C
Serial
Interface
and
Control
SCL
SDA
A[0:1]
Internal
Clock
GND
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7.3 Feature Description
7.3.1 Touch Screen Operation
A resistive touch screen operates by applying a voltage across a resistor network and measuring the change in
resistance at a given point on the matrix where the screen is touched by an input (stylus, pen, or finger). The
change in the resistance ratio marks the location on the touch screen.
The TSC2007-Q1 supports resistive 4-wire configurations, as shown in Figure 35. The circuit determines location
in two coordinate pair dimensions, although a third dimension can be added for measuring pressure.
12
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Feature Description (continued)
7.3.2 Internal Temperature Sensor
In some applications, such as battery recharging, an ambient temperature measurement is required. The
temperature measurement technique used in the TSC2007-Q1 relies on the characteristics of a semiconductor
junction operating at a fixed current level. The forward diode voltage (VBE) has a well-defined characteristic
versus temperature. The ambient temperature can be predicted in applications by knowing the 25°C value of the
VBE voltage and then monitoring the delta of that voltage as the temperature changes.
The TSC2007-Q1 offers two modes of temperature measurement. The first mode requires calibration at a known
temperature, but only requires a single reading to predict the ambient temperature. The TEMP1 diode, shown in
Figure 19, is used during this measurement cycle. This voltage is typically 580 mV at 25°C with a 10-µA current.
The absolute value of this diode voltage can vary by a few millivolts; the temperature coefficient (TC) of this
voltage is very consistent at –2.1 mV/°C. During the final test of the end product, the diode voltage would be
stored at a known room temperature, in system memory, for calibration purposes by the user. The result is an
equivalent temperature measurement resolution of 0.35°C/LSB (1 LSB = 732 µV with VREF = 3 V).
VDD
TEMP2
TEMP1
+IN
Converter
-IN
GND
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Figure 19. Functional Block Diagram of Temperature Measurement Mode
The second mode does not require a test temperature calibration, but uses a two-measurement (differential)
method to eliminate the need for absolute temperature calibration and for achieving 2°C/LSB accuracy. This
mode requires a second conversion of the voltage across the TEMP2 diode with a resistance 91 times larger
than the TEMP1 diode. The voltage difference between the first (TEMP1) and second (TEMP2) conversion is
represented by:
kT
'V
u In(N)
q
where
•
•
•
•
N = the resistance ratio = 91.
k = Boltzmann's constant = 1.3807 × 10–23 J/K (joules per kelvins).
q = the electron charge = 1.6022 × 10–19 C (coulombs).
T = the temperature in kelvins (K).
(1)
This method can provide a much improved absolute temperature measurement, but a lower resolution of
1.6°C/LSB. Equation 2 solves for T:
q u 'V
T
k u In(N)
where
•
ΔV = VBE (TEMP2) – VBE(TEMP1) (in mV)
(2)
∴ T = 2.573 × ΔV (in K)
or T = 2.573 × ΔV – 273 (in °C)
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Feature Description (continued)
Temperature 1 and temperature 2 measurements have the same timing as the other data acquisition cycles
shown in Figure 32 and Figure 33.
7.3.3 Analog-to-Digital Converter
Figure 20 shows the analog inputs of the TSC2007-Q1. The analog inputs (X, Y, and Z touch panel coordinates,
chip temperature and auxiliary inputs) are provided through a multiplexer to the Successive Approximation
Register (SAR) A-D converter. The A-D architecture is based on capacitive redistribution architecture, which
inherently includes a sample-and-hold function.
VDD/REF
50kW
RIRQ
PENIRQ
90kW
Pen Touch
X+
TEMP2
TEMP1
Control
Logic
MAV
C3-C0
GND
X-
VDD
Y+
+IN
Y-
+REF
Converter
-IN
-REF
GND
AUX
GND
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Figure 20. Analog Input Section (Simplified Diagram)
A unique configuration of low ON-resistance switches allows an unselected A-D converter input channel to
provide power and an accompanying pin to provide ground for driving the touch panel. By maintaining a
differential input to the converter and a differential reference input architecture, it is possible to negate errors
caused by the driver switch ON-resistance.
14
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Feature Description (continued)
7.3.3.1 Reference
The TSC2007-Q1 uses an external voltage reference that is applied to the VDD/REF pin. The upper reference
voltage range is the same as the supply voltage range, which allows for simple, 1.2-V to 3.6-V, single-supply
operation of the chip.
7.3.3.2 Reference Mode
There is a critical item regarding the reference when making measurements while the switch drivers are on. For
this discussion, it is useful to consider the basic operation of the TSC2007-Q1 (see Figure 34). The application
used in the following example shows the device being used to digitize a resistive touch screen. If the touch
screen controller uses a single-ended reference mode, as shown in Figure 21, a measurement of the current Y
position of the pointing device is made by connecting the X+ input to the A-D converter, turning on the Y+ and Y–
drivers, and digitizing the voltage on X+. For this measurement, the resistance in the X+ lead does not affect the
conversion; it does affect the settling time, but the resistance is usually small enough that this timing is not a
concern. However, because the resistance between Y+ and Y– is fairly low, the ON-resistance of the Y drivers
does make a small difference. Under the situation outlined so far, it would not be possible to achieve a 0-V input
or a full-scale input regardless of where the pointing device is on the touch screen because some voltage is lost
across the internal switches. In addition, the internal switch resistance is unlikely to track the resistance of the
touch screen, providing an additional source of error. Therefore, the TSC2007-Q1 does not support single-ended
reference mode.
VDD/REF
Y+
X+
+IN
+REF
Converter
-IN
-REF
Y-
GND
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Figure 21. Simplified Diagram of Single-Ended Reference
This situation is resolved, as shown in Figure 22, by using the differential mode; the +REF and –REF inputs are
connected directly to Y+ and Y–, respectively. This mode makes the A-D converter ratiometric. The result of the
conversion is always a percentage of the external reference, regardless of how it changes in relation to the ONresistance of the internal switches.
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Feature Description (continued)
VDD/REF
Y+
X+
+IN
+REF
Converter
-IN
-REF
Y-
GND
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Figure 22. Simplified Diagram of Differential Reference
(Both Y Switches Enabled, X+ is Analog Input)
7.3.3.3 Touch Screen Settling
In some applications, external capacitors may be required across the touch screen to filter noise picked up by the
touch screen (noise generated by the LCD panel or back-light circuitry). These capacitors provide a low-pass
filter to reduce the noise, but they also cause a settling time requirement when the panel is touched. The settling
time typically shows up as a gain error. The problem is that the input or reference has not settled to its final
steady-state value before the A-D converter samples the inputs and provides the digital output. Additionally, the
reference voltage may continue to change during the measurement cycle.
To resolve these settling-time problems, the TSC2007-Q1 can be commanded to turn on the drivers only without
performing a conversion (see Table 4). Time can then be allowed, before the command is issued, to perform a
conversion. Generally, the time it takes to communicate the conversion command over the I2C bus is adequate
for the touch screen to settle.
7.3.3.4 Variable Resolution
The TSC2007-Q1 provides either 8-bit or 12-bit resolution for the A-D converter. Lower resolution is often
practical for measuring slow changing signals such as touch pressure. Performing the conversions at lower
resolution reduces the amount of time it takes for the A-D converter to complete its conversion process, which
also lowers power consumption.
7.3.3.5 8-Bit Conversion
The TSC2007-Q1 provides an 8-bit conversion mode (M = 1) that can be used when faster throughput is
required, and the digital result is not as critical (for example, measuring pressure). By switching to the 8-bit
mode, a conversion result can be read by transferring only one data byte. The internal clock runs twice as fast at
4 MHz.
The faster clock shortens each conversion by four bits and reduces data transfer time, which results in fewer
clock cycles and provides lower power consumption.
7.3.3.6 Conversion Clock and Conversion Time
The TSC2007-Q1 contains an internal clock, which drives the state machines inside the device that perform the
many functions of the part. This clock is divided down to provide a clock that runs the A-D converter. The
frequency of this clock is 4-MHz clock for 8-bit mode, and a 2-MHz clock for the 12-bit mode.
7.3.3.7 Data Format
The TSC2007-Q1 output data are in straight binary format as shown in Figure 23. This figure shows the ideal
output code for the given input voltage and does not include the effects of offset, gain, or noise.
16
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Feature Description (continued)
FS = Full-Scale Voltage = VREF(1)
1LSB = VREF(1)/4096
1LSB
11...111
Output Code
11...110
11...101
00...010
00...001
00...000
0V
Input Voltage
(2)
FS - 1LSB
(V)
(1)
Reference voltage at converter: +REF – (–REF). See Figure 20.
(2)
Input voltage at converter, after multiplexer: +IN – (–IN). See Figure 20.
Figure 23. Ideal Input Voltages and Output Codes
7.3.3.8 Touch Detect
The PENIRQ pin can be used as an interrupt to the host. RIRQ is an internal pullup resistor with a programmable
value of either 50 kΩ (default) or 90 kΩ. Write command 1011 (setup command) followed by data 0001 sets the
pullup to 90 kΩ.
NOTE
The first three bits must be 0s and the select bit is the last bit. To change the pullup back
to 50 kΩ, issue write command 1011 followed by data 0000.
An example for the Y-position measurement is detailed in Figure 24. The PENIRQ output is pulled high by an
internal pullup. While in power-down mode with PD0 = 0, the Y– driver is on and connected to GND, and the
PENIRQ output is connected to the X+ input. When the panel is touched, the X+ input is pulled to ground
through the touch screen, and the PENIRQ output goes low because of the current path through the panel to
GND, initiating an interrupt to the processor. During the measurement cycle for X, Y, and Z position, the X+ input
is disconnected from the PENIRQ pulldown transistor to eliminate any pullup resistor leakage current from
flowing through the touch screen, thus causing no errors.
In addition to the measurement cycles for X, Y, and Z position, commands that activate the X-drivers, Y-drivers,
and Y+ and X-drivers without performing a measurement also disconnect the X+ input from the PENIRQ
pulldown transistor, and disable the pen-interrupt output function, regardless of the value of the PD0 bit. Under
these conditions, the PENIRQ output is forced low. Furthermore, if the last command byte written to the
TSC2007-Q1 contains PD0 = 1, the pen-interrupt output function is disabled and cannot detect when the panel is
touched. To re-enable the pen-interrupt output function under these circumstances, a command byte must be
written to the TSC2007-Q1 with PD0 = 0.
When the bus master sends the address byte with the R/W bit = 0, and the TSC2007-Q1 sends an acknowledge,
the pen-interrupt function is disabled. If the command that follows the address byte contains PD0 = 0, then the
pen-interrupt function is enabled at the end of a conversion. This action is approximately 100 µs (12-bit mode) or
50 µs (8-bit mode) after the TSC2007-Q1 receives a STOP or START condition, following the receipt of a
command byte (see Figure 30 and Figure 29 for further details about when the conversion cycle begins).
In both cases previously listed, TI recommends that whenever the host writes to the TSC2007-Q1, the master
processor masks the interrupt associated to PENIRQ. This masking prevents false triggering of interrupts when
the PENIRQ line is disabled in the cases previously listed.
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Feature Description (continued)
Connect to
Analog Supply
VDD/REF
PENIRQ
VDD
RIRQ
Pen Touch
Control
Logic
TEMP1
High when
the X+ or Y+
driver is on.
X+
TEMP2
Y+
Sense
GND
Y-
ON
High when the X+ or Y+
driver is on, or when any
sensor connection/shortcircuit tests are activated.
Vias go to system analog ground plane.
GND
GND
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Figure 24. Example of a Pen-Touch Induced Interrupt Through the PENIRQ Pin
7.3.3.9 Preprocessing
The TSC2007-Q1 has a combined MAV filter (median value filter and averaging filter).
7.3.3.9.1 MAV Filter
If the acquired signal source is noisy because of the digital switching circuit, it may necessary to evaluate the
data without noise. In this case, the median value filter operation helps remove the noise. The array of seven
converted results is sorted first. The middle three values are then averaged to produce the output value of the
MAV filter.
The MAV filter is applied to all measurements for all analog inputs including the touch screen inputs, temperature
measurements TEMP1 and TEMP2, and auxiliary input AUX. To shorten the conversion time, the MAV filter may
be bypassed through the setup command; see Table 4 and Table 5.
7 measurements input
into temporary array
7
7 Acquired
Data
Sort by
descending order
Averaging output
from window of 3
7
3
Figure 25. MAV Filter Operation (Patent Pending)
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7.4 Device Functional Modes
7.4.1 Power-On Reset (POR)
During TSC2007-Q1 power up, an internal power-on reset (POR) is automatically implemented. The POR brings
the TSC to the default working condition, and checks the A0 and A1 pins for the two LSBs of the I2C address.
The TSC2007-Q1 senses the power-up curve to decide whether or not to implement a POR.
It is required to follow the power-on and power-off slope and interval requirements, as provided in Electrical
Characteristics, to ensure a proper POR of the TSC2007-Q1. Review Important Considerations to Assure a Safe
POR to ensure a safe POR.
tVDD_ON_RAMP
tVDD_OFF_RAMP
1.2V to 3.6V
0.9V
VDD
0.3V
0V
tVDD_OFF
Figure 26. Power-On Reset Timing
Table 1. Timing Requirements for Figure 26
PARAMETER
TEST CONDITIONS
VDD off ramp
MIN
TA = –40°C to 85°C
VDD off time
VDD on ramp
MAX
2
UNIT
kV/s
TA = –40°C to 85°C, VDD = 0 V
1.2
TA = –20°C to 85°C, VDD = 0 V
0.3
s
s
TA = –40°C to 85°C
12
kV/s
VDD Off Time for Valid POR (s)
1.4
1.2
1.0
Recommended VDD Off Time
for TA = -40°C to +85°C
0.8
0.6
0.4
0.2
0
Typical VDD Off Time for Various Temperatures
-40
-20
0
20
40
Temperature (°C)
60
80
100
Figure 27. VDD Off Time vs Temperature
7.5 Programming
7.5.1 I2C Interface
The TSC2007-Q1 supports the I2C serial bus and data transmission protocol in all three defined modes:
standard, fast, and high-speed. A device that sends data onto the bus is defined as a transmitter, and a device
receiving data as a receiver. The device that controls the message is called a master. The devices that are
controlled by the master are slaves. The bus must be controlled by a master device that generates the serial
clock (SCL), controls the bus access, and generates the START and STOP conditions. The TSC2007-Q1
operates as a slave on the I2C bus. Connections to the bus are made through the open-drain I/O lines, SDA, and
SCL.
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Programming (continued)
The following bus protocol has been defined (see Figure 28):
• Data transfer may be initiated only when the bus is not busy.
• During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data
line while the clock line is HIGH are interpreted as control signals.
Accordingly, the following bus conditions have been defined:
Bus Not Busy Both data and clock lines remain HIGH.
Start Data Transfer A change in the state of the data line, from HIGH to LOW, while the clock is HIGH, defines
a START condition.
Stop Data Transfer A change in the state of the data line, from LOW to HIGH, while the clock line is HIGH,
defines the STOP condition.
Data Valid
The state of the data line represents valid data, when, after a START condition, the data line is
stable for the duration of the HIGH period of the clock signal. There is one clock pulse per bit of
data.
Each data transfer is initiated with a START condition and terminated with a STOP condition.
The number of data bytes transferred between START and STOP conditions is not limited
and is determined by the master device. The information is transferred byte-wise and each
receiver acknowledges with a ninth-bit.
Within the I2C bus specifications, a standard mode (100-kHz clock rate), a fast mode (400kHz clock rate), and a high-speed mode (1.7-MHz or 3.4-MHz clock rate) are each defined.
The TSC2007-Q1 works in all three modes.
Acknowledge Each receiving device, when addressed, is obliged to generate an acknowledge after the
reception of each byte. The master device must generate an extra clock pulse that is associated
with this acknowledge bit.
A device that acknowledges must pull down the SDA line during the acknowledge clock
pulse in such a way that the SDA line is stable LOW during the HIGH period of the
acknowledge clock pulse. Of course, setup and hold times must be taken into account. A
master must signal an end of data to the slave by not generating an acknowledge bit on the
last byte that has been clocked out of the slave. In this case, the slave must leave the data
line HIGH to enable the master to generate the STOP condition.
Figure 28 details how data transfer is accomplished on the I2C bus. Depending upon the state of the R/W bit, two
types of data transfer are possible:
1. Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is the
slave address. Next follows a number of data bytes. The slave returns an acknowledge bit after the slave
address and each received byte.
2. Data transfer from a slave transmitter to a master receiver. The first byte, the slave address, is
transmitted by the master. The slave then returns an acknowledge bit. Next, a number of data bytes are
transmitted by the slave to the master. The master returns an acknowledge bit after all received bytes other
than the last byte. At the end of the last received byte, a not-acknowledge is returned.
The master device generates all of the serial clock pulses and the START and STOP conditions. A transfer ends
with a STOP condition or a repeated START condition. Because a repeated START condition is also the
beginning of the next serial transfer, the bus is not released.
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Programming (continued)
The TSC2007-Q1 may operate in the following two modes:
1. Slave Receiver Mode: Serial data and clock are received through SDA and SCL. After each byte is
received, an acknowledge bit is transmitted. START and STOP conditions are recognized as the beginning
and end of a serial transfer. Address recognition is performed by hardware after reception of the slave
address and direction bit.
2. Slave Transmitter Mode: The first byte (the slave address) is received and handled as in the slave receiver
mode. However, in this mode, the direction bit indicates that the transfer direction is reversed. Serial data are
transmitted on SDA by the TSC2007-Q1 while the serial clock is input on SCL. START and STOP conditions
are recognized as the beginning and end of a serial transfer.
7.5.1.1 I2C Fast or Standard Mode (F/S Mode)
In I2C Fast or Standard (F/S) mode, serial data transfer must meet the timing shown in the Specifications section.
In the serial transfer format of F/S mode, the master signals the beginning of a transmission to a slave with a
START condition (S), which is a high-to-low transition on the SDA input while SCL is high. When the master has
finished communicating with the slave, the master issues a STOP condition (P), which is a low-to-high transition
on SDA while SCL is high, as shown in Figure 28. The bus is free for another transmission after a STOP
condition has occurred. Figure 28 shows the complete F/S mode transfer on the I2C, 2-wire serial interface. The
address byte, control byte, and data byte are transmitted between the START and STOP conditions. The SDA
state is only allowed to change while SCL is low, except for the START and STOP conditions. Data are
transmitted in 8-bit words. Nine clock cycles are required to transfer the data into or out of the device (8-bit word
plus acknowledge bit).
SDA
MSB
Slave Address
R/W
Direction Bit
Acknowledgement
Signal from Receiver
Acknowledgement
Signal from Receiver
1
SCL
2
6
7
8
9
1
ACK
START
Condition
2
3-8
8
9
ACK
Repeated If More Bytes Are Transferred
STOP Condition
or Repeated
START Condition
Figure 28. Complete Fast-Mode or Standard-Mode Transfer
7.5.1.2 I2C High-Speed Mode (HS Mode)
The TSC2007-Q1 can operate with high-speed I2C masters. To do so, the pullup resistor on SCL must be
changed to an active pullup, as recommended in the I2C specification.
Serial data transfer format in High-Speed (HS) mode meets the Fast or Standard (F/S) mode I2C bus
specification. HS mode can only commence after the following conditions (all of which are in F/S mode) exist:
1. START condition (S)
2. 8-bit master code (00001xxx)
3. Not-acknowledge bit (N)
Figure 29 shows this sequence in more detail. HS-mode master codes are reserved 8-bit codes used only for
triggering HS mode, and are not to be used for slave addressing or any other purpose. The master code
indicates to other devices that an HS-mode transfer is about to begin and the connected devices must meet the
HS-mode specification. Because no device is allowed to acknowledge the master code, the master code is
followed by a not-acknowledge bit (N).
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Programming (continued)
After the not-acknowledge bit (N) and SCL have been pulled up to a HIGH level, the master switches to HS
mode and enables the current-source pullup circuit for SCL (at time tH shown in Figure 29). Because other
devices can delay the serial transfer before tH by stretching the LOW period of SCL, the master enables the
current-source pullup circuit when all devices have released SCL, and SCL has reached a HIGH level, thus
speeding up the last part of the rise time of the SCL.
The master then sends a repeated START condition (Sr) followed by a 7-bit slave address with a R/W bit
address, and receives an acknowledge bit (A) from the selected slave. After a repeated START (Sr) condition
and after each acknowledge bit (A) or not-acknowledge bit (N), the master disables its current-source pullup
circuit. This disabling enables other devices, such as the TSC2007-Q1, to delay the serial transfer (until the
converted data are stored in the TSC internal shift register) by stretching the LOW period of SCL. The master reenables its current-source pullup circuit again when all devices have released SCL, and SCL reaches a HIGH
level, which speeds up the last part of the SCL signal rise time.
Data transfer continues in HS mode after the next repeated START (Sr), and only switches back to F/S mode
after a STOP condition (P). To reduce the overhead of the master code, it is possible for the master to link a
number of HS-mode transfers, separated by repeated START conditions (Sr).
8-Bit Master Code 00001xxx
S
N
tH
SDA
SCL
1
2 to 5
6
7
8
9
Fast or Standard Mode
R/W
7-Bit Slave Address
Sr
A
n x (8-Bit DATA
+
A/N)
Sr P
SDA
SCL
1
2 to 5
6
7
8
9
1
2 to 5
6
7
8
9
If P then
Fast or Standard Mode
High-Speed Mode
= Current Source Pull-Up
tH
= Resistor Pull-Up
A = Acknowledge (SDA LOW)
N = Not Acknowledge (SDA HIGH)
S = START Condition
P = STOP Condition
Sr = Repeated START Condition
If Sr (dotted lines)
then High-Speed Mode
tFS
Figure 29. Complete High-Speed Mode Transfer
7.5.2 Digital Interface
7.5.2.1 Address Byte
The TSC2007-Q1 has a 7-bit slave address word. The first five bits (MSBs) of the slave address are factorypreset to comply with the I2C standard for A-D converters and are always set at 10010. The logic state of the
address input pins (A1–A0) determines the two LSBs of the device address to activate communication.
Therefore, a maximum of four devices with the same preset code can be connected on the same bus at one
time.
The A1–A0 address inputs are read whenever an address byte is received, and must be connected to the supply
pin (VDD/REF) or the ground pin (GND). The slave address is latched into the TSC2007-Q1 on the falling edge
of SCL after the R/W bit has been received by the slave.
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Programming (continued)
The last bit of the address byte (R/W) defines the operation to be performed. When set to a 1, a read operation is
selected; when set to a zero, a write operation is selected. Following the START condition, the TSC2007-Q1
monitors the SDA bus, checking the device type identifier being transmitted. Upon receiving the 10010 code, the
appropriate device select bits, and the R/W bit, the slave device outputs an acknowledge signal on the SDA line.
Table 2. I2C Slave Address Byte
MSB
D7
D6
D5
D4
D3
D2
D1
LSB
D0
1
0
0
1
0
A1
A0
R/W
Bit D0: R/W
1: I2C master read from TSC (I2C read addressing).
0: I2C master write to TSC (I2C write addressing).
7.5.2.2 Command Byte
Table 3. Command Byte Definition (Excluding the Setup Command) (1)
BIT
D7–D4
NAME
C3–C0
DESCRIPTION
Converter function select bits: These bits select the input to be converted and the converter function to be
executed, activate the drivers, and configure the PENIRQ pullup resistor (RIRQ). Table 4 lists the possible
converter functions.
All Converter Function Select bits as detailed in Table 4, except for the setup command (1011).
Power-down bits: These two bits select the power-down mode that the TSC2007-Q1 enters after the current
command completes, as shown in Table 3.
It is recommended to set PD0 = 0 in each command byte to get the lowest power consumption possible. If
multiple X, Y, and Z position measurements are done one right after another (such as when averaging),
PD0 = 1 leaves the touch screen drivers on at the end of each conversion cycle.
00: Power down between cycles. PENIRQ enabled.
01: A-D converter on. PENIRQ disabled.
10: A-D converter off. PENIRQ enabled.
11: A-D converter on. PENIRQ disabled.
D3–D2
PD1–PD0
D1
M
Mode bit
0: 12-bit (Lower speed referred to as the 2-MHz clock).
1: 8-bit (Higher speed referred to as the 4-MHz clock).
D0
X
Do not care.
(1)
The command byte definition for the setup command is shown in Table 5.
When the TSC2007-Q1 powers up, the power-down bits must be written to ensure that the device is placed into
the mode that achieves the lowest power. Therefore, immediately after power up, send a command byte that sets
PD1 = PD0 = 0, so that the device is in the lowest power mode, powering down between conversions.
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Table 4. Converter Function Select
(1)
C3
C2
C1
C0
FUNCTION
0
0
0
0
Measure TEMP0
0
0
0
1
Reserved
0
0
1
0
Measure AUX
0
0
1
1
Reserved
0
1
0
0
Measure TEMP1
0
1
0
1
Reserved
0
1
1
0
0
1
1
1
0
0
1
0
1
0
INPUT TO A-D
CONVERTER
X-DRIVERS Y-DRIVERS
ACK
REFERENCE
MODE
TEMP0
OFF
OFF
Y
Single-Ended
—
OFF
OFF
N
Single-Ended
AUX
OFF
OFF
Y
Single-Ended
—
OFF
OFF
N
Single-Ended
TEMP1
OFF
OFF
Y
Single-Ended
—
OFF
OFF
N
Single-Ended
Reserved
—
OFF
OFF
N
Single-Ended
1
Reserved
—
OFF
OFF
N
Single-Ended
0
Activate X-drivers
—
ON
OFF
Y
Differential
0
1
Activate Y-drivers
—
OFF
ON
Y
Differential
1
0
Activate Y+, X-drivers
—
X– ON
Y+ ON
Y
Differential
(1)
1
0
1
1
Setup command
—
OFF
OFF
N
—
1
1
0
0
Measure X position
Y+
ON
OFF
Y
Differential
1
1
0
1
Measure Y position
X+
OFF
ON
Y
Differential
1
1
1
0
Measure Z1 position
X+
X– ON
Y+ ON
Y
Differential
1
1
1
1
Measure Z2 position
Y–
X– ON
Y+ ON
Y
Differential
The setup command has an additional four bits of data. These data are static; that is, they are not changed by other commands, except
for the power-on reset. The default value for these bits after power-on reset is 0000. Table 5 shows the definition of these data bits.
Table 5. Command Byte Definition for the Setup Command
BIT
NAME
D7–D4
C3–C0
DESCRIPTION
D3–D2
PD1–PD0
D1
Filter control
0: Use the onboard MAV filter (default).
1: Bypass the onboard MAV filter.
D0
RIRQ select
PENIRQ pullup resistor (RIRQ) select
0: RIRQ = 50 kΩ (default).
1: RIRQ = 90 kΩ.
Setup command; must write 1011.
Reserved; must write 00.
7.5.2.3 Start a Converter Function or Write Cycle
A conversion or write cycle begins when the master issues the address byte containing the slave address of the
TSC2007-Q1, with the eighth bit equal to a 0 (R/W = 0), as shown in Table 2. Once the eighth bit has been
received, and the address matches the A1–A0 address input pin setting, the TSC2007-Q1 issues an
acknowledge.
When the master receives the acknowledge bit from the TSC2007-Q1, the master writes the command byte to
the slave (see Table 3). After the command byte is received by the slave, the slave issues another acknowledge
bit. The master then ends the write cycle by issuing a repeated START or a STOP condition, as shown in
Figure 30.
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SCL
Address Byte
1
SDA
0
0
1
0
Command Byte
A1
A0
R/W
0
0
C3
C2
C1
C0 PD1 PD0
TSC2007
ACK
M
X
TSC2007
ACK
Acquisition
START
0
Conversion
STOP or
Repeated START
Figure 30. Complete I2C Serial Write Transmission
If the master sends additional command bytes after the initial byte, but before sending a STOP or repeated
START condition, the TSC2007-Q1 does not acknowledge those bytes.
The input multiplexer channel for the A-D converter is selected when bits C3 through C0 are clocked in. If the
selected channel is an X, Y, or Z position measurement, the appropriate drivers turn on once the acquisition
period begins.
When R/W = 0, the input sample acquisition period starts on the falling edge of SCL when the C0 bit of the
command byte has been latched, and ends when a STOP or repeated START condition has been issued. A-D
conversion starts immediately after the acquisition period. The multiplexer inputs to the A-D converter are
disabled once the conversion period starts. However, if an X, Y, or Z position is being measured, the respective
touch screen drivers remain on during the conversion period. A complete write cycle is shown in Figure 30.
7.5.2.4 Read a Conversion or Read Cycle
For best performance, the I2C bus must remain in an idle state while an A-D conversion is taking place. This
idling prevents digital clock noise from affecting the bit decisions being made by the TSC2007-Q1. The master
must wait for at least 10 µs before attempting to read data from the TSC2007-Q1 to realize this best
performance. However, the master does not need to wait for a completed conversion before beginning a read
from the slave, if full 12-bit performance is not necessary.
Data access begins with the master issuing a START condition followed by the address byte (see Table 2) with
R/W = 1.
When the eighth bit has been received and the address matches, the slave issues an acknowledge. The first
byte of serial data then follows (D11–D4, MSB first).
After the first byte has been sent by the slave, it releases the SDA line for the master to issue an acknowledge.
The slave responds with the second byte of serial data upon receiving the acknowledge from the master (D3–D0,
followed by four 0 bits). The second byte is followed by a NOT acknowledge bit (ACK = 1) from the master to
indicate that the last data byte has been received. If the master somehow acknowledges the second data byte,
invalid data are returned (FFh). This condition applies to both 12-bit and 8-bit modes. See Figure 31 for a
complete I2C read transmission.
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SCL
Address Byte
1
SDA
0
0
1
0
Data Byte 2
Data Byte 1
A1 A0 R/W
1
START
0
D11 D10
D9 D8 D7 D6 D5 D4
TSC2007
ACK
0
D3 D2 D1 D0
MASTER
ACK
0
0
0
0
1
MASTER STOP or
NACK
Repeated
START
Figure 31. Complete I2C Serial Read Transmission
7.5.2.5 Throughput Rate and I2C Bus Traffic
Although the internal A-D converter has a sample rate of up to 200 kSPS, the throughput presented at the bus is
much lower. The rate is reduced because preprocessing manages the redundant work of filtering out noise. The
throughput is further limited by the I2C bus bandwidth. The effective throughput is approximately 20 kSPS at 8-bit
resolution, or 10 kSPS at 12-bit resolution. This preprocessing saves a large portion of the I2C bandwidth for the
system to use on other devices.
Each sample and conversion takes 19 CCLK cycles (12-bit), or 16 CCLK cycles (8-bit). For a typical internal 4MHz OSC clock, the frequency actually ranges from 3.66 MHz to 3.82 MHz. For VDD = 1.2 V, the frequency
reduces to 3.19 MHz, which gives a 3.19 MHz / 16 = 199 kSPS raw A-D converter sample rate.
7.5.2.5.1 12-Bit Operation
For 12-bit operation, sending the conversion result across the I2C bus takes 49 bus clocks (SCL clock). Each
write cycle takes 20 I2C cycles (START, STOP, address byte, 2 ACKs, and command byte). Each read cycle
takes 29 I2C cycles (START, STOP, address byte, 3 ACKs, and data bytes 1 and 2). Seven sample-and-convert
operations take 19 × 7 internal clocks to complete. The MAV filter loop requires 19 internal clocks. For VDD = 1.2
V, the complete processed data cycle time calculations are shown in Table 6. Because the first acquisition cycle
overlaps with the I/O cycle, four CCLKs must be deducted from the total CCLK cycles. For 12-bit mode, (19 × 7 +
19) – 4 = 148 CCLKs plus I/O are required.
7.5.2.5.2 8-Bit Operation
For 8-bit operation, sending the conversion result across the I2C bus takes 40 bus clocks (SCL clock). Each write
cycle takes 20 I2C cycles (START, STOP, address byte, 2 ACKs, and command byte). Each read cycle takes 20
I2C cycles (START, STOP, address byte, 2 ACKs, and data byte 1). Seven sample-and-convert operations takes
16×7 internal clocks to complete. The MAV filter loop requires 19 internal clocks. For VDD = 1.2 V, the complete
processed data cycle time calculations are shown in Table 6. Because the first acquisition cycle overlaps with the
I/O cycle, four CCLKs must be deducted from the total CCLK cycles. For 8-bit mode, (16 × 7 + 19) – 4 = 127
CCLKs plus I/O are required.
Table 6. Measurement Cycle Time Calculations
STANDARD MODE: 100 kHz (Period = 10 µs)
8-Bit
40 × 10 µs + 127 × 313 ns = 439.8 µs (2.27 kSPS through the I2C bus)
12-Bit
49 × 10 µs + 148 × 625 ns = 582.5 µs (1.72 kSPS through the I2C bus)
FAST MODE: 400 kHz (Period = 2.5 µs)
8-Bit
40 × 2.5 µs + 127 × 313 ns = 139.8 µs (7.15 kSPS through the I2C bus)
12-Bit
49 × 2.5 µs + 148 × 625 ns = 215 µs (4.65 kSPS through the I2C bus)
HIGH-SPEED MODE: 1.7 MHz (Period = 588 ns)
8-Bit
40 × 588 ns + 127 × 313 ns = 63.3 µs (15.79 kSPS through the I2C bus)
12-Bit
49 × 588 ns + 148 × 625 ns = 121.3 µs (8.24 kSPS through the I2C bus)
HIGH-SPEED MODE: 3.4 MHz (Period = 294 ns)
26
8-Bit
40 × 294 ns + 127 × 313 ns = 51.6 µs (19.39 kSPS through the I2C bus)
12-Bit
49 × 294 ns + 148 × 625 ns = 106.9 µs (9.35 kSPS through the I2C bus)
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As an example, use VDD = 1.2 V and 12-bit mode with the Fast-mode I2C clock (fSCL = 400 kHz). The equivalent
TSC throughput is at least seven times faster than the effective throughput across the bus (4.65 k × 7 = 32.55
kSPS). The supply current to the TSC for this rate and configuration is 128 µA. To achieve an equivalent sample
throughput of 8.2 kSPS using the device without preprocessing, the TSC2007-Q1 consumes only (8.2 or 32.55)
× 128 µA = 32.24 µA.
Table 7. Effective and Equivalent Throughput Rates
SUPPLY
VOLTAGE
I2C BUS
SPEED (fSCL)
RESOLUTION
TSC
CONVERSION
CYCLE TIME (µs)
EFFECTIVE
THROUGHPUT
(kSPS)
EQUIVALENT
THROUGHPUT
(kSPS)
SCL
CYCLES
CCLK
CYCLES
fCCLK
(kHz)
CCLK
PERIODS
(ns)
8-bit
433.6
2.31
16.14
40
127
3780
264.6
12-bit
568.7
1.76
12.31
49
148
1880
531.9
8-bit
133.6
7.49
52.4
40
127
3780
264.6
12-bit
201.2
4.97
34.79
49
148
1880
531.9
8-bit
57.1
17.5
122.53
40
127
3780
264.6
12-bit
107.5
9.3
65.09
49
148
1880
531.9
8-bit
45.4
22.04
154.31
40
127
3780
264.6
12-bit
93.1
10.74
75.16
49
148
1880
531.9
8-bit
434.7
2.3
16.1
40
127
3660
273.2
12-bit
570.9
1.75
12.26
49
148
1830
546.4
8-bit
134.7
7.42
51.97
40
127
3660
273.2
12-bit
203.4
4.92
34.42
49
148
1830
546.4
8-bit
58.2
17.17
120.22
40
127
3660
273.2
12-bit
109.7
9.12
63.81
49
148
1830
546.4
3.4 MHz
High-Speed
8-bit
46.5
21.52
150.65
40
127
3660
273.2
12-bit
95.3
10.49
73.46
49
148
1830
546.4
100 kHz
Standard
8-bit
439.8
2.27
15.92
40
127
3190
313.5
12-bit
582.5
1.72
12.02
49
148
1600
625
8-bit
139.8
7.15
50.07
40
127
3190
313.5
100 kHz
Standard
400 kHz
Fast
2.7 V
1.7 MHz
High-Speed
3.4 MHz
High-Speed
100 kHz
Standard
400 kHz
Fast
1.8 V
1.7 MHz
High-Speed
400 kHz
Fast
1.2 V
1.7 MHz
High-Speed
3.4 MHz
High-Speed
12-bit
215
4.65
32.56
49
148
1600
625
8-bit
63.3
15.79
110.51
40
127
3190
313.5
12-bit
121.3
8.24
57.7
49
148
1600
625
8-bit
51.6
19.39
135.72
40
127
3190
313.5
12-bit
106.9
9.35
65.47
49
148
1600
625
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I2C Write
I2C Read
Clock Stretched
SCL
CCLK
Address Byte
1
SDA
0
0
1
0
Command Byte
A1
R/W
A0 0
0
C3 C2
C1 C0 PD1 PD0
Address Byte
M
TSC2007
ACK
X
0
0
1
0
1
A1
0
START
D11 D10
0
D9
D8
D7
D6
D5
TSC2007
ACK
TSC2007
ACK
Acquisition 1
6 SCLs
Data Byte 2
Data Byte 1
R/W
1
A0
Conversion 1
15 CCLKs
STOP or
REPEATED START (
Acquisition 2
4 CCLKs
Conversion 7
15 CCLKs
Conversion 2
15 CCLKs
0
D4
D3
D2
D1
D0
0
0
0
1
MASTER
NACK
MASTER
ACK
MAV Filter
19 CCLKs
0
STOP or
REPEATED START
)
148 CCLKs (Filter is Enabled, 12-Bit Mode)
Figure 32. Data Acquisition Cycle (Filter Enabled)
I2C Write
I2C Read
Clock Stretched
SCL
CCLK
Address Byte
SDA
1
0
0
1
0
Command Byte
A1
R/W
A0 0
Address Byte
Data Byte 2
Data Byte 1
R/W
0
C3 C2
TSC2007
ACK
START
C1
C0 PD1 PD0
M
X
0
1
0
0
1
0
TSC2007
ACK
A0
1
0
D11 D10
D9
D8
TSC2007
ACK
Acquisition 1
6 SCLs
STOP or
REPEATED START (
A1
Conversion 1
15 CCLKs
D7
D6
D5
D4
0
D3
MASTER
ACK
D2
D1
D0
0
0
0
0
1
MASTER
NACK
STOP or
REPEATED START
)
15 CCLKs (Filter is Disabled, 12-Bit Mode)
Figure 33. Data Acquisition Cycle (Filter Disabled)
28
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TSC2007-Q1 is designed for use in automotive touch-screen displays. It supports resistive 4-wire touch
screens that can be used in the head unit for infotainment and navigation displays. The auxiliary input can be
used for external temperature sensing, ambient light monitoring for back-lighting control, or for current
monitoring.
8.2 Typical Application
A typical application of the TSC2007-Q1 is shown in Figure 34.
1.8VDC
1mF
0.1mF
1.2kW
X+
VDD/REF
GND
PENIRQ
1.2kW
Host
Processor
GPIO
Y+
A1
AUX
Auxiliary Input
GND
Y-
Touch
Screen
SDA
SDA
SCL
SCL
A0
TSC2007-Q1
X-
GND
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Figure 34. Typical Circuit Configuration
8.2.1 Design Requirements
The system-level requirements for this design include:
•
•
Normal 4-wire resistive touch screen
To achieve the best SNR, select the highest operating voltage of the TSC2007-Q1 device that is compatible
with the system.
8.2.2 Detailed Design Procedure
8.2.2.1 4-Wire Touch Screen Coordinate Pair Measurement
A 4-wire touch screen is typically constructed as shown in Figure 35. It consists of two transparent resistive
layers separated by insulating spacers.
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Typical Application (continued)
Conductive Bar
Transparent Conductor (ITO)
Bottom Side
Y+
X+
Silver
Ink
Transparent
Conductor (ITO)
Top Side
XY-
ITO = Indium Tin Oxide
Insulating Material (Glass)
Figure 35. 4-Wire Touch Screen Construction
The 4-wire touch screen panel works by applying a voltage across the vertical or horizontal resistive network.
The A-D converter converts the voltage measured at the point where the panel is touched. A measurement of the
Y position of the pointing device is made by connecting the X+ input to a data converter chip, turning on the Y+
and Y– drivers, and digitizing the voltage seen at the X+ input. The voltage measured is determined by the
voltage divider developed at the point of touch. For this measurement, the horizontal panel resistance in the X+
lead does not affect the conversion because of the high input impedance of the A-D converter.
Voltage is then applied to the other axis, and the A-D converter converts the voltage representing the X position
on the screen. This process provides the X and Y coordinates to the associated processor.
Measuring touch pressure (Z) can also be done with the TSC2007-Q1. To determine pen or finger touch, the
pressure of the touch must be determined. Generally, it is not necessary to have very high performance for this
test; therefore, 8-bit resolution mode may be sufficient (however, data sheet calculations are shown using the
12-bit resolution mode). There are several different ways of performing this measurement. The TSC2007-Q1
supports two methods. The first method requires knowing the X-plate resistance, the measurement of the X
position, and two additional cross panel measurements (Z2 and Z1) of the touch screen (see Figure 36).
Equation 3 calculates the touch resistance:
R TOUCH
RX
plate
u
XPosition § Z 2
¨
4096 © Z1
·
1¸
¹
(3)
The second method requires knowing both the X-plate and Y-plate resistance, measurement of X position and Y
position, and Z1. Equation 4 also calculates the touch resistance:
R X plate u XPosition § 4096 ·
Y
§
·
R TOUCH
1¸ R Y plate u ¨ 1 Position ¸
¨
4096
Z
4096
©
¹
© 1
¹
(4)
30
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Typical Application (continued)
Measure X-Position
X+
Y+
Touch
X-Position
Y-
X-
Measure Z1-Position
Y+
X+
Touch
Z1-Position
X-
Y-
Y+
X+
Touch
Z2-Position
X-
YMeasure Z2-Position
Figure 36. Pressure Measurement
When the touch panel is pressed or touched and the drivers to the panel are turned on, the voltage across the
touch panel often overshoots and then slowly settles down (decays) to a stable DC value. This effect is a result
of mechanical bouncing caused by vibration of the top layer sheet of the touch panel when the panel is pressed.
This settling time must be accounted for, or else the converted value is incorrect. Therefore, a delay must be
introduced between the time the driver for a particular measurement is turned on, and the time a measurement is
made.
In some applications, external capacitors may be required across the touch screen for filtering noise picked up by
the touch screen (noise generated by the LCD panel or back-light circuitry). The value of these capacitors
provides a low-pass filter to reduce the noise, but creates an additional settling time requirement when the panel
is touched. The settling time typically shows up as gain error.
To solve this problem, the TSC2007-Q1 can be commanded to turn on the drivers only, without performing a
conversion. Time can then be allowed to perform a conversion before the command is issued.
The TSC2007-Q1 touch screen interface can measure position (X, Y) and pressure (Z).
8.2.2.2 Touch-Panel Driving Power
On a resistive touch-screen system, the driving current of the touch panel, provided by the TSC device through
the analog interface, has the highest impact on the power consumption in the touch screen system. This touchpanel power consumption is decided by the resistance of the touch panel and the TSC power-supply (VDD)
voltage. Figure 37 shows this relationship. The touch screen is driven by the TSC from the VDD supply and the
resistance of the panel determines the peak drive current.
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Typical Application (continued)
Figure 37 only shows the ideal TSC driving condition where the internal resistance of the TSC is ignored
because the resistance is small (5 to 6 Ω) compared to the resistance of the touch panel (hundreds to thousands
of Ω). Therefore the actual power consumption may be less than that shown in Figure 37.
A
•
•
•
user can reduce power consumption in three ways:
Using touch screens with higher resistance
Using a low-power supply (VDD) to the TSC
Reducing the driver on-time or the on-off ratio of the driver
Touch panels with higher resistance are likely to cause more noise and longer settling time which limits the
options for users.
The TSC2007-Q1 device is designed with a power supply (VDD) range from 1.2 V to 3.6 V.
8.2.3 Application Curve
Touch-Panel Peak Drive Current (mA)
18
VDD = 1.6 VDC
VDD = 2.5 VDC
VDD = 3 VDC
VDD = 3.6 VDC
16
14
12
10
8
6
4
2
0
200
400
600
800 1000 1200 1400 1600 1800 2000
Panel Resistance (Ω)
Figure 37. Touch-Panel Power Consumption
32
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9 Power Supply Recommendations
This device is designed to operate from an input voltage supply of 1.2 V to 3.6 V. Power to the TSC2007-Q1
device must be clean and well bypassed. Add a 0.1-µF ceramic capacitor between VDD/REF and GND.
10 Layout
10.1 Layout Guidelines
The following layout suggestions may allow optimum performance from the TSC2007-Q1. Keep in mind that
many portable applications have conflicting requirements for power, cost, size, and weight. In general, most
portable devices have fairly clean power and grounds because most of the internal components are very low
power. This situation would mean less bypassing for the converter power and less concern regarding grounding.
However, each situation is unique and the following suggestions must be reviewed carefully.
For optimum performance, take care of the physical layout of the TSC2007-Q1 circuitry. The basic SAR
architecture is sensitive to glitches or sudden changes on the power supply, reference, ground connections, and
digital inputs that occur immediately before latching the output of the analog comparator. Therefore, during any
single conversion for an n-bit SAR converter, there are n windows in which large external transient voltages can
easily affect the conversion result. Such glitches might originate from switching power supplies, nearby digital
logic, and high power devices. The degree of error in the digital output depends on the reference voltage, layout,
and the exact timing of the external event. The error can change if the external event changes in time with
respect to the SCL input.
With this consideration in mind, power to the TSC2007-Q1 must be clean and well bypassed. A 0.1-µF ceramic
bypass capacitor must be placed as close to the device as possible. In addition, a 1-µF to 10-µF capacitor may
also be required if the impedance of the connection between VDD/REF and the power supply is high.
A bypass capacitor is generally not required on the VDD/REF pin because the internal reference is buffered by
an internal op amp. If an external reference voltage originates from an op amp, make sure that it can drive any
bypass capacitor that is used without oscillation.
The TSC2007-Q1 architecture offers no inherent rejection of noise or voltage variation with regard to using an
external reference input, which is of particular concern when the reference input is tied to the power supply. Any
noise and ripple from the supply appears directly in the digital results. While high-frequency noise can be filtered
out, voltage variation because of line frequency (50 Hz or 60 Hz) can be difficult to remove. Some package
options have pins labeled as VOID. Avoid any active trace going under any pin marked as VOID unless it is
shielded by a ground or power plane.
The GND pin must be connected to a clean ground point. In many cases, this point is the analog ground. Avoid
connections that are too near the grounding point of a microcontroller or digital signal processor. If required, run
a ground trace directly from the converter to the power-supply entry or battery connection point. The ideal layout
includes an analog ground plane dedicated to the converter and associated analog circuitry.
In the specific case of use with a resistive touch screen, take care with the connection between the converter and
the touch screen. Resistive touch screens have fairly low resistance; therefore, the interconnection must be as
short and robust as possible. Loose connections can be a source of error when the contact resistance changes
with flexing or vibrations.
As indicated previously, noise can be a major source of error in touch-screen applications (for example,
applications that require a back-lit LCD panel). This electromagnetic interference (EMI) noise can be coupled
through the LCD panel to the touch screen and cause flickering of the converted A-D converter data. Several
things can be done to reduce this error, such as using a touch screen with a bottom-side metal layer connected
to ground, which couples the majority of noise to ground. Additionally, filtering capacitors, from Y+, Y–, X+, and
X– to ground, can also help. However, the use of these capacitors increases screen settling time and requires a
longer time for panel voltages to stabilize. The resistor value varies depending on the touch screen sensor used.
The PENIRQ pullup resistor (RIRQ) may be adequate for most of sensors.
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10.2 Layout Example
Power Supply
Input
Legend
Via to ground plane
Copper trace/pour
Bypass caps must be
placed close to the
VDD/REF pin
Auxiliary input
To touch screen
{
VDD/REF
AUX
X+
NC
Y+
A0
Connect to
VDD or GND
VDD
X-
TSC2007-Q1
A1
SCL
Y-
SCL
GND
SDA
NC
/PENIRQ
NC
NC
SDA
To GPIO
Figure 38. Example Layout for TSC2007-Q1
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Developmental Support
For developmental support, see the following:
TSC2003-Q1 Automotive I2C Touch Screen Controller
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
Important Considerations to Assure a Safe POR (SBAA161)
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TSC2007IPWRQ1
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
TS2007I
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
