TSU6721YFF
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SCDS345 – JUNE 2013
MCPC Compatible USB Port Multimedia Switch
Supports USB, UART, Audio, ID, MIC, and Load Switch
Check for Samples: TSU6721YFF
FEATURES
•
1
•
•
•
•
Switch Matrix
– USB and UART Switch support USB 2.0 HS
– Audio Switch with Negative Signal
Capability
– ID Bypass Switch
– VBUS to MIC Switch
– DP to MIC Switch to Support MCPC
Load Switch
– 100 mΩ Load Switch
– OTG Support
– 28 V VBUS Rating with Over-voltage
Protection
– Programmable Overcurrent
Limiter/Protection
Charger Detection
– USB BCDv1.2 compliant
– VBUS Detection
– Data Contact Detection
– Primary and Secondary Detection
Compatible Accessories
– USB Chargers (DCP, CDP)
– Apple Charger
– USB Data Port
– Audio Headset with MIC and Remote
– Docking Support
– Factory Cable
•
•
Additional Features
– I2C Interface with Host Processor
– Switches Controlled by Automatic
Detection or Manual Control
– Interrupts Generated for Plug/Unplug
– Decoupling FET Switch to VBUS Added to
Reduce Degradation on MIC Line
– Support Control Signals used In
Manufacturing (JIG, BOOT)
ESD Performance Tested Per JESD 22
– 4000-V Human-Body Model (A114-B, Class
II)
– 1500-V Charged-Device Model (C101)
IEC ESD Performance
– ±8 kV Contact Discharge (IEC 61000-4-2) for
VBUS/DP/DM/ID to GND
APPLICATIONS
•
•
•
•
•
Cell Phones and Smart Phones
Tablet PCs
Digital Cameras and Camcorders
GPS Navigation Systems
Micro USB Interface with USB/UART/AUDIO
APPLICATION DIAGRAM
BATTERY
CHG IC
IEC ESD
VBAT
USB
inside
DP_HT
DM_HT
UART/USB
VBUS
DP
TxD
RxD
TSU6721
Negative signal
capability for cap-free
Amp or Codec
MIC
S_R
AUDIO
DM
ID
S_L
MIC
outside
VBUS
DP_CON
DM_CON
ID_CON
ID Bypass
Switch
JIG
BOOT
INTB
ISET
IDBP
I2C_SDA
I2C_SCL
MIC to VBUS
or DP (MCPC
Spec)
Support
USB CONNECTOR
USB2.0 High
Speed
OUT
I2C
Control
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
TSU6721YFF
SCDS345 – JUNE 2013
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
For package and ordering information, see the Package Option Addendum at the end of this document.
DESCRIPTION
TSU6721 is a high performance USB port multimedia switch featuring automatic switching and accessory
detection. The device connects a common USB port to pass audio, USB data, charging, On The Go (OTG) and
factory mode signals. The audio path has negative signal capability includes left (mono/stereo), right (stereo) as
well as microphone signals. Furthermore, TSU6721 is compatible with the MCPC specification.
TSU6721 features impedance detection which supports the detection of various accessories that are attached
through DP, DM and ID pins of the USB connector. The switch is controlled by automatic switching or manually
through I2C.
TSU6721 has an integrated low resistive Load Switch that is used to isolate the charger from the external
connector. OverVoltage Protection and programmable OverCurrent Limiter/Protection are additional features
included to the Load Switch.
The charger detection satisfies USB charger specification v1.2. In addition to DCP, CDP and SDP, the device
also detects Apple Chargers.
Power for this device is supplied through VBAT of the system or through VBUS when attached. TSU6721
supports factory mode testing when a USB/UART JIG cable is used in development and manufacturing.
2
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SCDS345 – JUNE 2013
BLOCK DIAGRAM
VDDIO
I2C
Interface
SCL
Switch
Ctrl
SDA
Switches
Load
Switch
Sense &
Ctrl.
I2C Interface
&
Hardware
Control
INTB
JIG
OUT
State Machine
DP_HT
DM_HT
TxD
BOOT
ISET
RxD
S_L
S_R
MIC
Buffers and/or
Comparators
IDBP
VBUS
DP
DM
ID
Charger
Detection
Sources
And
Comp’s
Accessory
ID
Detection
ADC
TSU6721 SWITCH
MATRIX
PMIC
OUT
VBUS
USB
DM_HT
DP_HT
DM
Micro
USB
DP
UART
TxD
RxD
ID
S_L
AUDIO
S_R
MIC
IDBP
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PIN OUT
TOP VIEW
BOTTOM VIEW
1
2
3
4
5
A
INTB
VDDIO
ISET
OUT
VBUS
B
DP_
HT
SDA
S_L
MIC
C
DM_
HT
SCL
NC
D
VBAT
IDBP
E
RxD
TxD
5
4
3
2
1
A
VBUS
OUT
ISET
VDDIO
INTB
DM
B
DM
MIC
S_L
SDA
DP_
HT
S_R
DP
C
DP
S_R
NC
SCL
DM_
HT
GND
GND
ID
D
ID
GND
GND
IDBP
VBAT
BOOT
JIG
GND
E
GND
JIG
BOOT
TxD
RxD
PIN FUNCTIONS
4
BALL NO.
PIN NAME
TYPE
DESCRIPTION
D1
VBAT
–
3.0 – 4.4V Battery supply voltage
A2
VDDIO
–
1.8 ~ 3.3V Logic Supply
A5
VBUS
I
USB connector VBUS
A4
OUT
O
Phone charger output
E5, D3, D4
GND
–
Ground
B1
DP_HT
I/O
USB data plus
C1
DM_HT
I/O
USB data minus
D2
IDBP
I/O
USB ID data
E1
RxD
I/O
UART receive data
E2
TxD
I/O
UART transmit data
C3
NC
–
Not connected internally
B4
MIC
I/O
Microphone signal
C4
S_R
I/O
Stereo headset right sound
B3
S_L
I/O
Mono or stereo headset left sound
C2
SCL
I
I2C clock
B2
SDA
I/O
I2C data
C5
DP
I/O
Common USB connector plus I/O port
B5
DM
I/O
Common USB connector minus I/O port
D5
ID
I/O
Common USB connector ID I/O port
A1
INTB
O
Interrupt signal when peripheral is plugged/unplugged. Push-pull output
A3
ISET
O
High current charger detected. Open-drain output
E4
JIG
O
GPIO factory output. Open-drain output
E3
BOOT
O
GPIO factory output. Push-pull output
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ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VBUS
Supply voltage from USB connector
–0.5
28
V
VBAT
Supply voltage from battery
–0.5
6
V
VDDIO
Logic supply voltage
–0.5
4.6
V
VBUS_OUT
Phone charger output
–0.5
7
V
DP
DP Connector voltage
–0.5
VBAT+0.5
V
DM
DM Connector voltage
–0.5
VBAT+0.5
V
ID
ID Connector voltage
–0.5
VBAT+0.5
V
IDBP
ID Host Side voltage
V
VAUDIO
VMIC
Switch I/O voltage range
VUSB/VUART
–0.5
VBAT+0.5
Audio Switch (S_L, S_R)
–1.5
VBAT+0.5
Mic Switch (MIC)
–0.5
VBAT+0.5
USB/UART Switch
V
–0.5
VBAT+0.5
VJIG & VISET
JIG and ISET voltage
–0.5
VBAT+0.5
V
VLOGIC_O
Voltage applied to logic output (SCL, SDA, INTB, BOOT)
–0.5
VDDIO
V
IBUS
IBUS_OUT
Peak input current on VBUS pin (12.5% duty cycle)
2.0
Peak input current on VBUS pin (3% duty cycle, 4ms on-time)
2.5
Peak input current on VBUS pin (12.5% duty cycle)
2.0
Peak input current on VBUS pin (3% duty cycle, 4ms on-time)
2.5
A
A
IISET & IJIG
ISET and JIG pins peak current
50
mA
IK
Analog port diode current
–50
50
mA
ISW-DC
ON-state continuous switch current
–60
60
mA
ISW-_ PEAK
ON-state peak switch current
–150
150
mA
IIK
Digital logic input clamp
current
–50
mA
ILOGIC_O
Continuous current through logic output (SCL, SDA, INTB, BOOT)
50
mA
IGND
Continuous current through GND
100
mA
Tstg
Storage temperature range
150
°C
VDDIO < 0
–50
–65
THERMAL IMPEDANCE RATINGS
θJA
Package thermal
impedance
YFP package
VALUE
UNIT
98.8
°C/W
SUMMARY OF TYPICAL CHARACTERISTICS
AMBIENT TEMPERATURE = 25°C
Number of channels
ON-state resistance (ron)
ON-state resistance match (Δron)
USB/UART PATH
AUDIO PATH
MIC PATH
2
1
1
6 Ω / 7 Ω (USB/UART)
2.5 Ω
40 Ω
0.2 Ω / 1.5 Ω
0.15 Ω
N/A
1.4 Ω / 1.4 Ω
0.15 Ω
N/A
130 µs/ 100 µs
200 µs/100 µs
260 µs /180 µs
510 MHz
450MHz
250 MHz
OFF isolation (OISO)
–26 dB at 250 MHz
–100 dB
–95 dB
Crosstalk (XTALK)
–32 dB at 250 MHz
–85 dB
–85 dB
N/A
0.05%
0.46%
50 nA
200 nA
5 nA
ON-state resistance flatness (ron(flat))
Turn-on/Turn-off time (tON/tOFF)
Bandwidth (BW)
Total Harmonic Distortion (THD)
Leakage current (IIO(ON))
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RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
DESCRIPTION
MIN
MAX
UNITS
VBUS
VBUS voltage
4.0
6.5
V
VBAT
VBAT voltage
3.0
4.4
V
VDDIO
VDDIO voltage
1.65
3.6
V
ID_Cap
ID capacitance
3
nF
USB_I/O
USB path signal range
0
3.6
V
UART_I/O
UART path signal range
0
2.7
V
Audio_I/O
Audio path signal range
–1.5
1.5
V
MIC_I/O
MIC path signal range
0
2.3
V
Temperature
Operating Temperature
–40
85
°C
ELECTRICAL SPECIFICATIONS
DIGITAL SIGNALS – I2C INTERFACE (SCL and SDA)
TA = –40°C to 85°C, Typical values are at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VDDIO
Logic and I/O supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
VOH
SDA High-level output voltage
IOH = –3 mA
VOL
SDA Low-level output voltage
IOL = 3 mA
fSCL
SCL frequency
MIN
MAX
1.65
3.6
V
VDDIO × 0.7
VDDIO
V
0
VDDIO × 0.3
V
VDDIO × 0.7
UNIT
V
0
0.4
V
400
kHz
UNIT
JIG AND ISET FAST-MODE CHARGER OUTPUT (OPEN-DRAIN OUTPUT)
TA = –40°C to 85°C, Typical values are at TA = 25°C (unless otherwise noted)
MIN
MAX
VOL_JIG
Low-level output voltage
PARAMETER
IOL = 10 mA, VBAT = 3.0 V
TEST CONDITIONS
0
0.5
V
VOL_ISET
Low-level output voltage
IOL = 10 mA, VBAT = 3.0 V
0
0.7
V
MIN
MAX
1.16
VDDIO
V
0
0.33
V
UNIT
INTB AND BOOT (PUSH-PULL OUTPUT)
TA = –40°C to 85°C, Typical values are at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VOH
High-level output voltage
IOH = –4 mA , VDDIO = 1.65 V
VOL
Low-level output voltage
IOL = 4 mA , VDDIO = 1.65 V
UNIT
TOTAL SWITCH CURRENT CONSUMPTION
TA = –40°C to 85°C, Typical values are at TA = 25°C (unless otherwise noted)
TYP
MAX
IBAT(Standby)
VBAT Standby Current Consumption
PARAMETER
VBUS = 0 V, Idle state
TEST CONDITIONS
MIN
36
50
µA
IBAT(Operating)
VBAT Operating Current Consumption
VBUS = 0 V, USB switches ON
60
80
µA
IVBUS
VBUS Operating Current Consumption
No load on OUT pin, VBUS = 5 V
135
155
µA
TYP
MAX
UNIT
VBUS CAP SWITCH CHARACTERISTICS
TA = –40°C to 85°C, Typical values are at TA = 25°C (unless otherwise noted)
PARAMETER
RDS-VBUSCAP
6
VBUS CAP switch resistance
TEST CONDITIONS
VBUS = 5 V, IOUT = –20 mA
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90
Ω
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VOLTAGE PROTECTION
TA = –40°C to 85°C, Typical values are at TA = 25°C (unless otherwise noted)
PARAMETER
VVBUS_UVLO
TEST CONDITIONS
MIN
TYP MAX
VBUS under voltage+
Voltage is Rising, device power-up
3.0
3.25
3.6
VBUS under voltage–
Voltage is Falling, device reset
2.7
3
3.3
VVBUS_VALID
VBUS interrupt threshold
Voltage is Rising
VVBAT_UVLO
VBAT under voltage+
Voltage is Rising, device power-up
2.5
2.8
3.1
VBAT under voltage–
Voltage is Falling, device reset
2.3
2.6
2.9
3.6
UNIT
V
V
V
LOAD SWITCH CHARACTERISTICS
TA = –40°C to 85°C, Typical values are at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
RDSVBUSSWITCH
VBUS switch resistance
VBUS = 5 V, IOUT = 100 mA
tONa
Turn-ON time automatic mode
RL = 36 Ω, CL = 400 pF, Vbus rising > 3.6V
175
ms
tOFFa
Turn-OFF time automatic mode
RL = 36 Ω, CL = 400 pF, Vbus falling < 3.6V
2.5
ms
tONm
Turn-ON time manual mode
RL = 36 Ω, CL = 400 pF, From receipt of I2C ACK
bit
230
µs
tOFFm
Turn-OFF time manual mode
RL = 36 Ω, CL = 400 pF, From receipt of I2C ACK
bit
180
µs
IOCP
Programmable overcurrent
protection
VBUS = 5.5V
90
I2C reg0x22h, Bit [2:0] = 000
0.8
1.0
1.2
I2C reg0x22h, Bit [2:0] = 001 (default)
1.3
1.5
1.7
I2C reg0x22h, Bit [2:0] = 010
2.0
I2C reg0x22h, Bit [2:0] = 011
IOCL
Programmable overcurrent limiter
VBUS = 5.5V
150
mΩ
A
2.0
I2C reg0x21h, Bit [7:5] = 000
1.25
1.5
1.75
I2C reg0x21h, Bit [7:5] = 001 (default)
1.67
2.0
2.33
I2C reg0x21h, Bit [7:5] = 010
2.5
I2C reg0x21h, Bit [7:5] = 011
2.5
A
VBUS OVERVOLTAGE PROTECTION (OVP)
VBUS
VOVP
Input overvoltage protection
threshold
VBUS increasing from 6 V to 8 V
VBUS
tOFF(OVP)
OVP delay
Delay from VBUS > VOVP to Load switch OFF
200
µs
VBUS
VHYS-OVP
Hysteresis on OVP
VBUS decreasing from 8 V to 6 V
140
mV
VBUS
tON(OVP)
Recovery time from input
overvoltage condition
Delay from VBUS < VOVP-VHYS, to Load switch ON
9
ms
OTP
rOTP
OTP Rising Turn Off
Temperature rising until load switch shut off
130
°C
OTP
fOTP
OTP Falling Turn On
Temperature falling after OTP shutoff until switch
turn on
120
°C
6.8
7
7.2
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AUDIO SWITCH ELECTRICAL CHARACTERISTICS (1) (2)
VBAT = 3.0 V to 4.4 V, VDDIO = 2.8 V, TA = –40°C to 85°C, Typical values are at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
ANALOG SWITCH
VAUDIO
Analog signal range
rON
ON-state resistance
–1.5
3
V
2.5
5
Ω
0.15
0.5
Ω
ΔrON
S_L or
VI = ±0.8 V, IO = –20 mA, VBAT = 3.0 V
S_R , DM or
ON-state resistance match
VI = 0.8 V, II = –20 mA, VBAT = 3.0 V
DP
between channels
rON(flat)
ON-state resistance
flatness
VI = ±0.8 V, IO = –20 mA, VBAT = 3.0 V
0.15
0.5
Ω
IIO(OFF)
VI or VO OFF leakage current
(VI = -0.8 V, VO = 0.8 V) or (VI = 0.8 V,
VO = –0.8 V), VBAT = 4.4 V, Switch OFF
200
500
nA
IIO(ON)
VO ON leakage current
10
300
VI = OPEN, VO = –0.8 V or 0.8 V, VBAT = 4.4 V,
Switch ON
nA
DYNAMIC
tON
Turn-ON time
tOFF
Turn-OFF time
CI(OFF)
VI OFF capacitance
CO(OFF)
VO OFF capacitance
From
receipt of
I2C ACK bit
200
VI or VO = VBAT, RL = 100 Ω, CL = 35 pF
DC bias = 0 V or 1.6 V f = 10 MHz, Switch OFF
CI(ON), CO(ON) VI, VO ON capacitance
DC bias = 0 V or 1.6 V f = 10 MHz, Switch ON
BW
Bandwidth
RL = 50 Ω, Switch ON
OISO
OFF Isolation
f = 20 kHz, RL = 50 Ω, Switch OFF
XTALK
Crosstalk
THD
Total harmonic distortion
(1)
(2)
8
µs
100
5.5
pF
10
pF
13
pF
450
MHz
–100
dB
f = 20 kHz, RL = 50 Ω
–85
dB
RL = 16 Ω, CL = 20 pF, f = 20 Hz–20 kHz ,
1.6 Vpp output
0.05
%
RL = 16 Ω, CL = 20 pF, f = 20 Hz–20 kHz ,
3 Vpp output
0.1
%
VI is equal to the asserted voltage on S_R and S_L pins. VO is equal to the asserted voltage on DP and DM pins. II is equal to the
current on the S_R and S_L pins. IO is equal to the current on the DP and DMpins
Audio Switch is intended for signals to be asserted on S_R/S_L pins and pass to DM/DP
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MIC SWITCH ELECTRICAL CHARACTERISTICS (1)
VBAT = 3.0 V to 4.4 V, VDDIO = 2.8 V, TA = –40°C to 85°C, Typical values are at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
ANALOG SWITCH
VMICIO
Analog signal range
rON
ON-state resistance
IIO(OFF)
VBAT
V
MIC, VBUS
VI = 2.3 V, IO = –20 mA, VBAT = 3.0 V
0
40
52
Ω
MIC, DP
VI = 2.3 V, II = –5 mA, VBAT = 3.0 V
15
25
Ω
5
500
nA
VI or VO OFF leakage current
VI = 0.3 V, VO = 2.3 V or (VI = 2.3 V, VO = 0.3
V),
VBAT = 4.4 V, Switch OFF
tON
Turn-ON time
VI or VO = VBAT, RL = 100 Ω, CL = 35 pF
tOFF
Turn-OFF time
CI(OFF)
VI OFF capacitance
CO(OFF)
VO OFF capacitance
DYNAMIC
From receipt of
I2C ACK bit
260
DC bias = 0 V or 3.6 V, f = 10 MHz, Switch OFF
130
pF
10.5
pF
140
pF
MHz
CI(ON), CO(ON) VI, VO ON capacitance
DC bias = 0 V or 3.6 V f = 10 MHz, Switch ON
BW
Bandwidth, MIC to VBUS
RL = 50 Ω, Switch ON
40
Bandwidth, MIC to DP
RL = 50 Ω, Switch ON
250
OISO
OFF Isolation
f = 20 kHz, RL = 50 Ω, Switch OFF
–95
XTALK
Crosstalk
f = 20 kHz, RL = 50 Ω, to audio output
–85
THD
Total harmonic distortion
RL = 600 Ω, CL = 20 pF, f = 20 Hz–20 kHz ,
Vin = 0.1 Vpp centered at VBAT/2
0.05
(1)
µs
180
dB
dB
0.65
%
VI is equal to the asserted voltage on VBUS/DP pin. VO is equal to the asserted voltage on MIC pin. II is equal to the current on the
VBUS/DP pin. IO is equal to the current on the MIC pin.
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USB & UART SWITCH ELECTRICAL CHARACTERISTICS
VBAT = 3 V to 4.4 V, VDDIO = 2.8 V, TA = –40°C to 85°C, Typical values are at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
ANALOG SWITCH
VUSBIO
Analog signal range
0
3.6
VUARTIO
Analog signal range
0
2.7
rON
ON-state resistance
DM_HT,DM
DP_HT,DP
VI = 0 V to 3.6 V, IO = –20 mA, VBAT = 3.0
V
6
11
TxD, DM
RxD, DP
VI = 0 V to 3.6 V, IO = –20 mA, VBAT = 3.0
V
7
14.3
ID, IDBP
VI = 0 V to 3.6 V, IO = –20 mA, VBAT = 3.0
V
30
VI = 0.4 V, IO = –20 mA, VBAT = 3.0 V
0.2
1
TxD, DM
RxD, DP
VI = 0.4 V, IO = –20 mA, VBAT = 3.0 V
1.5
3
rON
ON-state resistance
ΔrON
ON-state resistance match DM_HT,DM
between channels
DP_HT,DP
V
Ω
Ω
Ω
rON(flat)
ON-state resistance
flatness
DM_HT, DP_HT,
TxD, RxD, DM, DP
VI = 0 V to 3.6 V, IO = –20 mA,
VBAT = 3.0 V
1.4
3.2
Ω
IIO(OFF)
VI or VO OFF leakage
current
DM_HT, DP_HT,
TxD, RxD, DM, DP
VI = 0.3 V, VO = 2.7 V or VI = 2.7 V,
VO = 0.3 V, VBAT = 4.4 V, Switch OFF
45
200
nA
IIO(ON)
VO ON leakage current
DM_HT, DP_HT,
TxD, RxD, DM, DP
VI = OPEN, VO = 0.3 V or 2.7 V,
VBAT = 4.4 V, Switch ON
50
200
nA
tON
Turn-ON time
VI or VO = VBAT, RL = 100 Ω, CL = 35 pF
tOFF
Turn-OFF time
From receipt of I2C
ACK bit
CI(OFF)
VI OFF capacitance
CO(OFF)
VO OFF capacitance
DYNAMIC
130
µs
100
DC bias = 0 V or 1.6 V, f = 10 MHz,
Switch OFF
4
pF
7
pF
CI(ON), CO(ON) VI, VO ON capacitance
DC bias = 0 V or 3.6 V f = 10 MHz,
Switch ON
9
pF
BW
Bandwidth
RL = 50 Ω, Switch ON
510
MHz
OISO
OFF Isolation
f = 240 kHz, RL = 50 Ω, Switch OFF
–26
dB
XTALK
Crosstalk
f = 240 kHz, RL = 50 Ω
–32
dB
10
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GENERAL OPERATION
The TSU6721 is a multimedia switch that connects a common USB connector to USB, UART or audio signals.
The device also has a MIC switch that connects to either VBUS or DP. It has an integrated load switch to support
charging. The load switch has OverVoltage Protection as well as OverCurrent Limiting Protection. In addition, the
TSU6721 also has an ID bypass switch to transmit ID signal from the connector to the host. It has an internal
FET switch that disconnects the coupling capacitor connected to the VBUS line.
Standby Mode
Standby mode is the default mode upon power up and occurs when no accessory has been detected. During this
mode, the VBUS and ID lines are continually monitored through comparators to determine when an accessory is
inserted. Power consumption is minimal during standby mode.
Load Switch
The integrated load switch provides both overvoltage/undervoltage and overcurrent limiting protection:
Overvoltage Protection
When the input voltage rises above VOVP, the internal load switch is turned off. The response is very rapid, with
the FET turning off in less than 1µs tOFF(OVP). The OVP_EN interrupt bit is set high when an overvoltage
condition is detected. When the input voltage returns below VOVP-VHYS_OVP and remains above VUVLO, the
VBUS switch is turned on again after a deglitch time of tON(OVP). This deglitch time ensures that the input
supply has stabilized before turning the switch on. When the OVP condition is cleared, the OVP_OCP_DIS
interrupt bit is set high.
Undervoltage Protection
When VBUS is not present and VBAT is less than 2.5V, VBAT and VBUS voltages are below the undervoltage
threshold and TSU6721 is powered off.
Overcurrent Limiting Protection
The TSU6721 also provides overcurrent limiting protection. When current increases beyond the IOCP threshold, a
time-out delay is initiated. After the delay has expired, and the current is still greater than IOCP, then load switch is
disabled. The maximum current that flows through the load switch is controlled by the IOCL limit. This feature
provides control on the VBUS charging current and minimizes the chance of internal circuitry damage caused by
overcurrent event. The overcurrent level can be programmed through I2C.
Power Supervisor
TSU6721 uses VBAT as the primary supply voltage. VBUS is the secondary supply. VDDIO is used for I2C
communication.
Table 1. Supply Voltage States
VBAT
VBUS
VDDIO
DETECTION
LOAD SWITCH
I2C
COMMENTS
Yes
No
No
Enabled
Not Enabled
Not Enabled
VBAT is supply
Yes
Yes
No
Enabled
Enabled
Not enabled
VBAT is supply. LOAD SWITCH controlled by
VBUS
Yes
No
Yes
Enabled
Not Enabled
Enabled
VBAT is supply
Yes
Yes
Yes
Enabled
Enabled
Enabled
VBAT is supply. LOAD SWITCH controlled by
VBUS
No
Yes
No
Enabled
Enabled
Not Enabled
VBUS is supply. LOAD SWITCH controlled by
VBUS
No
Yes
Yes
No
No
Yes
Not valid
No
No
No
Power Down Reset
Not valid
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ACCESSORY ID DETECTION
If VBUS is high and the attachment is a non-compliant charger (see Table 5), the impedance on the ID pin is
then determined. If VBUS is low and an accessory is attached, then an ADC for impedance sensing is used on
the ID pin to identify which accessory is attached and/or what kind of remote control key button is pushed.
The TSU6721 features impedance detection for identification of various accessories that might be attached to the
micro-USB port. Each accessory is identified by a unique resistor value connected between the ID pin and
Ground. During impedance detection a current source is applied to the ID pin. The current source is then applied
to the ID pin while an internal voltage reference is incremented till it matches the ID pin voltage. This produces a
5-bit ADC value that corresponds to the ID resistance found. Once an ID resistance is identified, a current source
is continuously applied to determine when the resistance is detached.
TSU6721
VCC
VBUS
DD+
ISRC
ID
VREF
GND
(1)
RID
CID,MAX
(1)
Maximum ID_Cap capacitance as noted in RECOMMENDED OPERATING CONDITIONS
Figure 1. Impedance Detection Circuitry
Impedance Buckets for Each Accessory and Remote Control Key Button
In order to implement ID detection, each accessory and remote control key button of audio accessory should
contain below ID impedance resistor value which is 1% tolerance accuracy.
Switch Matrix
MCPC accessory table is selected only when MCPC mode is enabled in Control Reg02h. VBUS to OUT Load
Switch is enabled anytime VBUS is applied to the USB connector.
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Table 2. Accessory ID and Switch States
SWITCH STATE
ACCESSORY
ID
Res
(%)
ADC
Value
DP/DM
STATUS OUTPUT
VBUS
ID
ID_HT
USB
UART
Audio
MIC
ISET
JIG
BOOT
OTG
0
–
00000
ON
OFF
OFF
OFF
ON
OFF
OFF
OFF
Video
75
5%
00000
OFF
OFF
ON
OFF
OFF
OFF
OFF
OFF
MHL
1K
5%
00000
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
Send_End Button
2K
10%
00001
OFF
OFF
ON
ON
OFF
OFF
OFF
OFF
Stereo Headset RC S1
Button
2.604K
5%
00010
OFF
OFF
ON
ON
OFF
OFF
OFF
OFF
Stereo Headset RC S2
Button
3.208K
5%
00011
OFF
OFF
ON
ON
OFF
OFF
OFF
OFF
Stereo Headset RC S3
Button
4.014K
5%
00100
OFF
OFF
ON
ON
OFF
OFF
OFF
OFF
Stereo Headset RC S4
Button
4.82K
5%
00101
OFF
OFF
ON
ON
OFF
OFF
OFF
OFF
Stereo Headset RC S5
Button
6.03K
5%
00110
OFF
OFF
ON
ON
OFF
OFF
OFF
OFF
Stereo Headset RC S6
Button
8.03K
5%
00111
OFF
OFF
ON
ON
OFF
OFF
OFF
OFF
Stereo Headset RC S7
Button
10.03K
5%
01000
OFF
OFF
ON
ON
OFF
OFF
OFF
OFF
Stereo Headset RC S8
Button
12.03K
5%
01001
OFF
OFF
ON
ON
OFF
OFF
OFF
OFF
Stereo Headset RC S9
Button
14.46K
5%
01010
OFF
OFF
ON
ON
OFF
OFF
OFF
OFF
Stereo Headset RC S10
Button
17.26K
5%
01011
OFF
OFF
ON
ON
OFF
OFF
OFF
OFF
Stereo Headset RC S11
Button
20.5K
5%
01100
OFF
OFF
ON
ON
OFF
OFF
OFF
OFF
Stereo Headset RC S12
Button
24.07K
5%
01101
OFF
OFF
ON
ON
OFF
OFF
OFF
OFF
Audio Device Type 3
28.7K
5%
01110
OFF
OFF
ON
OFF
OFF
OFF
OFF
OFF
Reserved Accessory #1
34K
5%
01111
OFF
OFF
ON
ON
OFF
OFF
OFF
OFF
Reserved Accessory #2
40.2K
5%
10000
OFF
OFF
ON
ON
OFF
OFF
OFF
OFF
Reserved Accessory #3
49.9K
5%
10001
OFF
OFF
ON
ON
OFF
OFF
OFF
OFF
Reserved Accessory #4
64.9K
5%
10010
OFF
OFF
ON
ON
OFF
OFF
OFF
OFF
Audio Device Type 2
80.27K
5%
10011
OFF
OFF
ON
OFF
OFF
OFF
OFF
OFF
Phone Powered Device
102K
5%
10100
OFF
ON
OFF
OFF
OFF
OFF
OFF
OFF
TTY Converter
121K
5%
10101
OFF
OFF
ON
ON
OFF
OFF
OFF
OFF
UART Cable
150K
5%
10110
OFF
ON
OFF
OFF
OFF
OFF
OFF
OFF
Type 1 Charger
200K
5%
10111
ON
OFF
OFF
OFF
OFF
ON
OFF
OFF
Factory Mode - Boot Off USB
255K
5%
11000
ON
OFF
OFF
OFF
OFF
OFF
ON
OFF
Factory Mode - Boot On USB
301K
5%
11001
ON
OFF
OFF
OFF
OFF
OFF
ON
ON
Audio/Video Cable
365K
5%
11010
OFF
OFF
ON
OFF
OFF
OFF
OFF
OFF
A/V + VBUS
365K
5%
11010
OFF
OFF
ON
OFF
OFF
OFF
OFF
OFF
Type 2 Charger
442K
5%
11011
ON
OFF
OFF
OFF
OFF
ON
OFF
OFF
Factory Mode - Boot Off
UART
523K
5%
11100
OFF
ON
OFF
OFF
OFF
OFF
ON
OFF
Factory Mode - Boot On
UART
619K
5%
11101
OFF
ON
OFF
OFF
OFF
OFF
ON
ON
1000.07K
10%
11110
OFF
OFF
ON
ON
OFF
OFF
OFF
OFF
1002K
10%
11110
OFF
OFF
ON
ON
OFF
OFF
OFF
OFF
Sterero Audio Device Type 1
Mono Audio Device Type 1
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Table 3. Accessory ID and Switch States MCPC Mode
SWITCH STATE
ACCESSORY
ID
RES (%)
ADC
VALUE
10000
DP/DM
STATUS OUTPUT
VBUS
ID
ISET
JIG
BOOT
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
ON
ON
OFF
OFF
OFF
OFF
ON
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
USB
UART
AUDI
O
MIC
ID_HT
OFF
OFF
ON
ON
OFF
OFF
ON
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
Send_End_SW
47K
5%
Send_End_SW with VBUS
47K
5%
Maintanence
180K
5%
Mode 1 Stereo
47K + 240K
5%
Mode 1 Stereo with VBUS
47K + 240K
5%
390K
5%
Mode 3 Monaural
47K + 510K
5%
Mode 3 Monaural with VBUS
47K + 510K
5%
Mode 2 Monaural
47K + 750K
5%
11110
DM to S_L; DP OPEN
ON
OFF
OFF
OFF
OFF
Mode 2 Monaural with VBUS
47K + 750K
5%
11110
DM to S_L; DP OPEN
OFF
OFF
OFF
OFF
OFF
Reserved
14
10001
10000
10001
10110
10111
11000
11001
11000
11001
11010
11011
11100
11101
11100
11101
DM to S_L; DP to MIC
DM to S_L; DP to MIC
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CHARGER DETECTION
Table 4. Chargers Detected and Switch States
SWITCH STATE
ACCESSORY
ID
ADC
VALUE
RES (%)
DP/DM
STATUS OUTPUT
VBUS
ID
USB
UART
AUDIO
MIC
ID_HT
ISET
JIG
BOOT
No ID
–
–
11111
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
Apple Charger
–
–
11111
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
Non-standard Charger
–
–
11111
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
USB Standard Downstream
Port
–
–
11111
ON
OFF
OFF
OFF
ON
OFF
OFF
OFF
USB Charging Downstream
Port
–
–
11111
ON
OFF
OFF
OFF
ON
ON
OFF
OFF
Dedicated Charging Port
–
–
11111
ON
OFF
OFF
OFF
ON
ON
OFF
OFF
Table 5 lists the configurations of the DP_CON (D+) and DM_CON (D-) that are internal to the various device
types.
Table 5. Charger Detection Table
DEVICE TYPE
VBUS
DP_CON (D+)
DM_CON (D–)
Standard Downstream Port
>4 V
Pull-down R 15k to GND
Pull-down R 15k
Charging Downstream Port
>4 V
Pull-down R 15k to GND
VDM_SRC =0.6V
Dedicated Charging Port
>4 V
Short to D–
Short to D+
Apple Charger
>4 V
2.0 < VDP < 2.8
2.0 < VDM < 2.8
U200
>4 V
VDP = 1.34
VDM = 1.34
Non-compliant USB Charger Any
Device
>4 V
Open
Open
Power-On Reset
When power (from 0 V) is applied to VBAT, an internal power-on reset holds the TSU6721 in a reset condition
until VBAT has reached VPOR. At that point, the reset condition is released, and the TSU6721 registers and I2C
state machine initialize to their default states.
After the initial power-up phase, VBAT must be lowered to below 0.2 V and then back up to the operating voltage
(VDDIO) for a power-reset cycle.
Software Reset
The TSU6721 has software a reset feature. Set the reset bit in the I2C register high to reset TSU6721. After
resetting, INTB will keep low until INT_Mask bit of Control register (0x02) is cleared.
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Key Press Identification
Key
Key Press Timing
Long Key Press Timing
INTB
Key Press
Interrupt
Long Key
Press Interrupt
Long Key
Release Interrupt
(A)
(B)
(C)
A.
Key press
B.
Released key press → Set KP Interrupt → Set error bit in Button register → INTB pulled low
C.
I2C read of INT register → Clear KP interrupt → INTB goes back high
Figure 2. Short Key Press
Key
Key Press Timing
Long Key Press Timing
INTB
Key Press
Interrupt
Long Key
Press Interrupt
Long Key
Release Interrupt
(A)
(B)
(C)
A.
Key press
B.
Released key press → Set KP Interrupt → Set Key (S/E, 1–12) bit in Button register → INTB pulled low .
C.
I2C read of INT register → Clear KP interrupt → INTB goes back high.
Figure 3. Normal Key Press
16
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Key
Key Press Timing
Long Key Press Timing
INTB
Key Press
Interrupt
Long Key
Press Interrupt
Long Key
Release Interrupt
(A)
(B)
(C)
(D)
A.
Key press
B.
Long key press timing reached → Set LKP interrupt bit → Set Key (S/E, 1–12) bit in Button register → INTB pulled
low
C.
I2C read of INT register → Clear LKP interrupt bit → INTB goes back high
D.
Released key press → Set LKR Interrupt bit → INTB pulled low
E.
I2C read of INT register → Clear LKR interrupt bit→ INTB goes back high
(E)
Figure 4. Long Key Press
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Key
Key Press Timing
Long Key Press Timing
INTB
Key Press
Interrupt
Long Key
Press Interrupt
Long Key
Release Interrupt
(A)
(B)
(C)
(D)
A.
Key press detected when accessory attached
B.
Long key press timing reached → Set SK interrupt bit → Set Key (S/E, 1–12) bit in Button register → INTB pulled low
C.
I2C read of INT register → Clear SK interrupt bit → INTB goes back high
D.
Released key press detected when accessory ID resistor is 1 MΩ → Set SKR Interrupt bit → INTB pulled low
E.
I2C read of INT register → Clear SKR interrupt bit → INTB goes back high
(E)
Figure 5. Stuck Key Press
Figure 6. Audio/Remote Controller Accessory
STANDARD I2C INTERFACE DETAILS
The bidirectional I2C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data
transfer may be initiated only when the bus is not busy.
I2C communication with this device is initiated by the master sending a START condition, a high-to-low transition
on the SDA input/output while the SCL input is high (see Figure 7). After the start condition, the device address
byte is sent, MSB first, including the data direction bit (R/W). This device does not respond to the general call
address. After receiving the valid address byte, this device responds with an ACK, a low on the SDA input/output
during the high of the ACK-related clock pulse.
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SDA
SCL
S
P
Stop Condition
Start Condition
Figure 7. Definition of Start and Stop Conditions
The data byte follows the address ACK. The R/W bit is kept low for transfer from the master to the slave. The
data byte is followed by an ACK sent from this device. Data are output only if complete bytes are received and
acknowledged. The output data is valid at time (tpv) after the low-to-high transition of SCL, during the clock cycle
for the ACK.
On the I2C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control
commands (START or STOP) (see Figure 8).
SDA
SCL
Data Line
Change
Figure 8. Bit Transfer
A Stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the
master (see Figure 7).
The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not
limited. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before the
receiver can send an ACK bit.
A slave receiver that is addressed must generate an ACK after the reception of each byte. The device that
acknowledges has to pull down the SDA line during the ACK clock pulse so that the SDA line is stable low during
the high pulse of the ACK-related clock period (see Figure 9). Setup and hold times must be taken into account.
Data Output
by Transmitter
NACK
Data Output
by Receiver
ACK
SCL From
Master
1
2
8
9
S
Clock Pulse for
Acknowledgment
Start
Condition
Figure 9. Acknowledgment on I2C Bus
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Writes
Data is transmitted to the TSU6721 by sending the device slave address and setting the LSB to a logic 0 (see
Figure 10 for device address). The command byte is sent after the address and determines which register
receives the data that follows the command byte. The next byte is written to the specified register on the rising
edge of the ACK clock pulse.
SCL
Slave Address
SDA
ST 0
1
0
0
Start
1
0
Sub Address
1
0
A
0
0
0
0
0
0
Date Byte
1
0
A D7 D6 D5 D4 D3 D2 D1 D0 A D7 D6 D5 D4 D3 D2 D1 D0 A SP
ACK
From
Slave
W/R
Register Address
(Control Reg)
ACK From Slave
Auto-Inc.
Date Byte
ACK
From
Slave
Data to Control
Register
Data to Control
Register
ACK Stop
From
Slave
Figure 10. Repeated Data Write to a Single Register
Slave Address
SDA
ST 0
1
0
0
Start
1
0
Sub Address
1
0
A
1
0
0
0
1
0
Date Byte
0
0
Date Byte
A D7 D6 D5 D4 D3 D2 D1 D0 A D7 D6 D5 D4 D3 D2 D1 D0 A
ACK Data to Timing Set 1
From
Register
Slave
W/R
Register Address
(Timing Set 1 Reg)
ACK From Slave
Auto-Inc.
ACK
From
Slave
Data to Timing Set 2
Register
ACK
From
Slave
Figure 11. Burst Data Write to Multiple Registers
Reads
The bus master first must send the TSU6721 slave address with the LSB set to logic 0. The command byte is
sent after the address and determines which register is accessed. After a restart, the device slave address is
sent again but, this time, the LSB is set to logic 1. Data from the register defined by the command byte then is
sent by the TSU6721. Data is clocked into the SDA output shift register on the rising edge of the ACK clock
pulse. See Figure 12.
Slave Address
SDA
ST 0
Start
1
0
0
1
0
Sub Address
1
0
A
0
0
0
0
0
0
Slave Address
1
1
Register Address
W/R
(Interrupt 1 Reg)
ACK From Slave
Auto-Inc.
A RS 0
0
0
1
0
1
1
A D7 D6 D5 D4 D3 D2 D1 D0
Data from Interrupt 1 Reg.
W/R
ACK From Slave
ACK Re-Start
From
Slave
Date Byte
continued
1
Date Byte
Date Byte
A D7 D6 D5 D4 D3 D2 D1 D0 A D7 D6 D5 D4 D3 D2 D1 D0 NA SP
Data from Interrupt 1 Reg.
ACK From Master
Data from Interrupt 1 Reg.
ACK From Master
Stop
No ACK From Master (Message Ends)
Figure 12. Repeated Data Read from a Single Register – Combined Mode
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SCL
Slave Address
SDA
ST 0
1
0
0
1
Sub Address
0
1
0
A
1
0
0
0
0
Slave Address
0
1
1
Register Address
W/R
(Interrupt 1 Reg)
ACK From Slave
Auto-Inc.
Start
A RS 0
1
0
0
1
ACK Re-Start
From
Slave
Date Byte
0
1
1
A D7 D6 D5 D4 D3 D2 D1 D0
W/R
ACK From Slave
Data from Interrupt 1 Reg.
Date Byte
Date Byte
A D7 D6 D5 D4 D3 D2 D1 D0 A D7 D6 D5 D4 D3 D2 D1 D0 NA SP
continued
Data from Interrupt 2 Reg.
ACK From Master
Data from Int Mask 1 Reg.
Stop
No ACK From Master (Message Ends)
ACK From Master
Figure 13. Burst Data Read from Multiple Registers – Combined Mode
Slave Address
SDA ST 0
1
0
0
Start
1
0
Sub Address
1
0
A
0
0
0
0
0
Slave Address
0
1
W/R
Register Address
(Interrupt 1 Reg)
ACK From Slave
Auto-Inc.
1
A SP ST 0
ACK
Start
From Stop
Slave
1
0
0
1
0
Date Byte
1
1
A D7 D6 D5 D4 D3 D2 D1 D0
W/R
ACK From Slave
Data from Interrupt 1 Reg.
Continued
Date Byte
Date Byte
A D7 D6 D5 D4 D3 D2 D1 D0 A D7 D6 D5 D4 D3 D2 D1 D0 NA SP
continued
Data from Interrupt 1 Reg.
ACK From Master
Data from Interrupt 1 Reg.
Stop
No ACK From Master (Message Ends)
ACK From Master
Figure 14. Repeated Data Read from a Single Register – Split Mode
SCL
Slave Address
SDA ST 0
Start
1
0
0
1
0
Sub Address
1
0
A
1
0
0
0
0
0
Slave Address
1
1
A SP ST 0
W/R
Register Address ACK
Start
(Interrupt 1 Reg) From Stop
ACK From Slave
Slave
Auto-Inc.
Date Byte
continued
1
0
0
1
0
Date Byte
1
1
A D7 D6 D5 D4 D3 D2 D1 D0
W/R
ACK From Slave
Data from Interrupt 1 Reg.
Continued
Date Byte
A D7 D6 D5 D4 D3 D2 D1 D0 A D7 D6 D5 D4 D3 D2 D1 D0 NA SP
Data from Interrupt 2 Reg.
ACK From Master
Data from Int Mask 1 Reg.
ACK From Master
Stop
No ACK From Master (Message Ends)
Figure 15. Burst Data Read from Multiple Registers – Split Mode
Notes (Applicable to Figure 10 – Figure 15):
• SDA is pulled low on Ack. from slave or Ack. from master.
• Register writes always require sub-address write before first data byte.
• Repeated data writes to a single register continue indefinitely until Stop or Re-Start.
• Repeated data reads from a single register continue indefinitely until No Ack. from master.
• Burst data writes start at the specified register address, then advance to the next register address, even to
the read-only registers. For these registers, data write appears to occur, though no data are changed by the
writes. After register 14h is written, writing resumes to register 01h and continues until Stop or Re-Start.
• Burst data reads start at the specified register address, then advance to the next register address. Once
register 14h is read, reading resumes from register 01h and continues until No Ack. from master.
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I2C REGISTER MAP
TYPE
RESET
VALUE
Device ID
R
00010010
Control
R/W
xx011111
03h
Interrupt 1
R
00000000
OVP_OCP_OTP
_DIS
04h
Interrupt 2
R
00000000
05h
Interrupt Mask 1
R/W
06h
Interrupt Mask 2
07h
ADDRESS
REGISTER
01h
02h
BIT 7
BIT 6
BIT 5
BIT4
BIT 3
BIT 2
BIT1
MCPC Mode
Switch Open
Raw Data
Manual S/W
Wait
INT Mask
OCP_EN
OVP_EN
LKR
LKP
KP
Detach
Attach
VBUS
OTP_EN
CONNECT
Stuck_Key_
RCV
Stuck_Key
ADC_
Change
Reserved_
Attach
A/V_Change
00000000
OVP_OCP_OTP
_DIS
OCP_EN
OVP_EN
LKR
LKP
KP
Detach
Attach
R/W
00000000
VBUS
OTP_EN
CONNECT
Stuck_Key_
RCV
Stuck_Key
ADC_
Change
Reserved_
Attach
A/V_Change
ADC
R
xxx11111
08h
Timing Set 1
R/W
00000000
Key Press
Device Sleep
09h
Timing Set 2
R/W
00000000
Switching Wait
Long Key Press
0Ah
Device Type 1
R
00000000
Version ID
BIT0
Vendor ID
ADC Value
USB OTG
DCP
CDP
A/V
TTY
Type1/Type
2 Charger
UART
USB
Audio Type2
Audio Type1
PPD
JIG_UART
_OFF
JIG_UART
_ON
JIG_USB
_OFF
JIG_USB_ON
0Bh
Device Type 2
R
00000000
Audio Type3
0Ch
Button 1
R
00000000
7
6
5
4
3
2
1
Send_End
0Dh
Button 2
R
x0000000
Unknown
Error
12
11
10
9
8
13h
Manual S/W 1
R/W
00000000
DM Switching
14h
Manual S/W 2
R/W
xxx00000
15h
Device Type 3
R
0000x000
1Bh
Reset
W
xxxxxxx0
DP Switching
ISET
Video
U200 Chg
ISET Enable
Time
Load Switch
Enable Time
Apple Chg
VBUS Switching
BOOT
JIG
ID Switching
VBUS nonstandard
A/V VBUS
VBUS
Debounce
MHL
Reset
20h
Timer Setting
R/W
00010101
21h
OCL/OCP
Setting 1
R/W
001010x1
22h
OCL/OCP
Setting 2
R/W
xxx11001
23h
Device Type 4
R/W
xxxxx111
BCDv1.2 Timer
OCL Protection Level Setting
ADC Start Time
BCDv1.2
Enable
OCP Timeout Delay Setting
OC Enable
OCP Protection Level Setting
MCPC ID Resistor Value
Notes:
1. Do not use blank register bits.
2. Write “0” to the blank register bits.
3. Values read from the blank register bits are not defined and invalid.
4. When reading I2C table after an interrupt first read register Interrupt 1 (03h) followed by Interrupt 2 (04h).
5. Interrupt 1 (03h) and Interrupt 2 (04h) should not be read when INT Mask = 0.
6. I2C should not be accessed within 5 ms of device power-up.
Slave Address
22
NAME
SIZE
(BITS)
Slave address
8
BIT 7
0
BIT 6
1
BIT 5
0
DESCRIPTION
BIT 4
BIT 3
0
1
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BIT 2
0
BIT 1
1
BIT 0
R/W
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Device ID
Address: 01h
Reset Value: 00010010
Type: Read
BIT NO.
NAME
SIZE
(BITS)
2-0
Vendor ID
3
A unique number for vendor
010b for Texas Instruments
7-3
Version ID
5
A unique number for chip version
00010b for TSU6721
DESCRIPTION
Control
Address: 02h
Reset Value: xx011111
Type: Read/Write
BIT NO.
NAME
SIZE
(BITS)
0
INT Mask
1
0: Unmask interrupt
1: Mask interrupt
1
Wait
1
0: Wait until host re-sets this bit(WAIT bit) high
1: Wait until Switching timer is expired defined in Timing Set 2
2
Manual S/W
1
0: Manual Switching
1: Automatic Switching
3
RAW Data
1
0: Report the status changes on ID to Host
1: Don't report the status changes on ID
4
Switch Open
1
0: Open all Switches (Including load switch)
1: Automatic Switching by accessory status
5
MCPC Mode
1
0: Non-MCPC Mode
1: MCPC Mode
7-6
Unused
2
DESCRIPTION
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Interrupt 1
Address: 03h
Reset Value: 00000000
Type: Read and Clear
BIT NO.
NAME
SIZE
(BITS)
0
Attach
1
1: Accessory is attached
1
Detach
1
1: Accessory is detached
2
KP
1
1: Key press
3
LKP
1
1: Long key press
4
LKR
1
1: Long key release
5
OVP_EN
1
1: OVP enabled
6
OCP_EN
1
1: OCP enabled
7
OVP_OCP_OTP_DI
S
1
1: OVP_OCP_OTP disabled (device is out of OVP, OCP or OTP)
DESCRIPTION
Interrupt 2
Address: 04h
Reset Value: 00000000
Type: Read and Clear
24
BIT
NO.
NAME
SIZE
(BITS)
0
A/V_Change
1
1: Accessory Change is detected when A/V cable is attached
1
Reserved_Attach
1
1: Reserved Device is attached
2
ADC_Change
1
1: ADC value is changed when RAW data is enabled
3
Stuck_Key
1
1: Stuck Key is detected
4
Stuck_Key_RCV
1
1: Stuck Key is recovered
5
Connect
1
1:Switch is connected (closed)
6
OTP_EN
1
1: Over Temperature Protection enabled
7
VBUS
1
1: VBUS detected
DESCRIPTION
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Interrupt Mask 1
Address: 05h
Reset Value: 00000000
Type: Read/Write
BIT NO.
NAME
SIZE
(BITS)
0
Attach
1
0: Unmask Attach Interrupt
1: Mask Attach Interrupt
1
Detach
1
0: Unmask Key press Interrupt
1: Mask Detach Interrupt
2
KP
1
0: Unmask Key press Interrupt
1: Mask Key press Interrupt
3
LKP
1
0: Unmask Long key press Interrupt
1: Mask Long key press Interrupt
4
LKR
1
0: Unmask Long key release Interrupt
1: Mask Long key release Interrupt
5
OVP_EN
1
0: Unmask OVP_EN Interrupt
1: Mask OVP_EN Interrupt
6
OCP_EN
1
0: Unmask OCP_EN Interrupt
1: Mask OCP_EN Interrupt
7
OVP_OCP_OTP_DIS
1
0: Unmask OVP_OCP_OTP_DIS Interrupt
1: Mask OVP_OCP_OTP_DIS Interrupt
DESCRIPTION
Interrupt Mask 2
Address: 06h
Reset Value: 00000000
Type: Read/Write
BIT NO.
NAME
SIZE
(BITS)
0
A/V_Change
1
0: Unmask A/V_Change Interrupt
1: Mask A/V_Change Interrupt
1
Reserved_Attach
1
0: Unmask Reserved_Attach Interrupt
1: Mask Reserved_Attach Interrupt
2
ADC_Change
1
0: Unmask ADC_Change Interrrupt
1: Mask ADC_Change Interrrupt
3
Stuck_Key
1
0: Unmask Stuck_Key Interrupt
1: Mask Stuck_Key Interrupt
4
Stuck_Key_RCV
1
0: Unmask Stuck_Key_RCV Interrupt
1: Mask Stuck_Key_RCV Interrupt
5
Connect
1
0: Unmask Connect Interrupt
1: Mask Connect Interrupt
6
OTP_EN
1
0: Unmask OTP_EN Interrupt
1: Mask OTP_EN Interrupt
7
VBUS
1
0: Unmask VBUS Interrupt
1: Mask VBUS Interrupt
DESCRIPTION
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ADC Value
Address: 07h
Reset Value: xxx11111
Type: Read
BIT NO.
NAME
4-0
ADC value
SIZE (BITS) DESCRIPTION
5
7-5
Unused
3
ADC value read from ID
Timing Set 1
Address: 08h
Reset Value: 00000000
Type: Read/Write
BIT NO.
NAME
3-0
Device Sleep
SIZE (BITS) DESCRIPTION
4
Device Sleep duration
7-4
Key press
4
Normal key press duration
Timing Set 2
Address: 09h
Reset Value: 00000000
Type: Read/Write
BIT NO.
NAME
SIZE
(BITS)
3-0
Long key press
4
Long key press duration
7-4
Switching wait
4
Waiting duration before switching
DESCRIPTION
Time Table
26
SETTING VALUE
DEVICE SLEEP
KEY PRESS
LONG KEY PRESS
SWITCHING WAIT(1)
0000
50 ms
100 ms
300 ms
10 ms
0001
100 ms
200 ms
400 ms
30 ms
0010
150 ms
300 ms
500 ms
50 ms
0011
200 ms
400 ms
600 ms
70 ms
0100
300 ms
500 ms
700 ms
90 ms
0101
400 ms
600 ms
800 ms
110 ms
0110
500 ms
700 ms
900 ms
130 ms
0111
600 ms
800 ms
1000 ms
150 ms
1000
700 ms
900 ms
1100 ms
170 ms
1001
800 ms
1000 ms
1200 ms
190 ms
1010
900 ms
–
1300 ms
210 ms
1011
1000 ms
–
1400 ms
–
1100
–
–
1500 ms
–
1101
–
–
–
–
1110
–
–
–
–
1111
–
–
–
–
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Device Type 1
Address: 0Ah
Reset Value: 00000000
Type: Read
BIT
NO.
NAME
SIZE
(BITS)
DESCRIPTION
0
Audio type 1
1
Audio device type 1
1
Audio type 2
1
Audio device type 2
2
USB
1
USB host
3
UART
1
UART
4
Type1/Type2
1
Type1/Type2 Charger
5
CDP
1
Charging Downstream Port (USB Host Hub Charger)
6
DCP
1
Dedicated Charging Port
7
USB OTG
1
USB on-the-go device
Device Type 2
Address: 0Bh
Reset Value: 00000000
Type: Read
BIT NO.
NAME
0
JIG_USB_ON
SIZE (BITS) DESCRIPTION
1
Factory mode cable
1
JIG_USB_OFF
1
Factory mode cable
2
JIG_UART_ON
1
Factory mode cable
3
JIG_UART_OFF
1
Factory mode cable
4
PPD
1
Phone-powered device
5
TTY
1
TTY converter
6
A/V
1
A/V Cable
7
Audio Type 3
1
Audio device type 3
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Button 1
Address: 0Ch
Reset Value: 00000000
Type: Read and Clear
BIT NO.
NAME
0
Send_End
SIZE (BITS) DESCRIPTION
1
Send_End key is pressed
1
1
1
Number 1 key is pressed
2
2
1
Number 2 key is pressed
3
3
1
Number 3 key is pressed
4
4
1
Number 4 key is pressed
5
5
1
Number 5 key is pressed
6
6
1
Number 6 key is pressed
7
7
1
Number 7 key is pressed
Button 2
Address: 0Dh
Reset Value: x0000000
Type: Read and Clear
BIT NO.
NAME
0
8
1
Number 8 key is pressed
1
9
1
Number 9 key is pressed
2
10
1
Number 10 key is pressed
3
11
1
Number 11 key is pressed
4
12
1
Number 12 key is pressed
5
Error
1
Error key is pressed
6
Unknown
1
Unknown key is pressed
7
Unused
1
28
SIZE (BITS) DESCRIPTION
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Manual S/W 1
Address: 13h
Reset Value: 00000000
Type: Read/Write
BIT
NO.
NAME
SIZE (BITS)
DESCRIPTION
1-0
VBUS Switching
2
00: Open all switch
01: VBUS is connected to VBUS_OUT (charger)
10: VBUS is connected to MIC
4-2
DP Switching
3
000: Open all switch
001: DP is connected to DP_HT of USB port
010: DP is connected to S_R
011: DP is connected to RxD of UART
100: Reserved 101: DP is connected to MIC
110-111: Reserved
7-5
DM Switching
3
000: Open all switch
001: DM is connected to DM_HT of USB port
010: DM is connected to S_L
011: DM is connected to TxD of UART
100-111: Reserved
Manual S/W 2
Address: 14h
Reset Value: xxx00000
Type: Read/Write
BIT
NO.
NAME
SIZE (BITS)
DESCRIPTION
1-0
ID Switching
2
00:
01:
10:
11:
2
JIG
1
0: Low (JIG OFF)
1: High (JIG ON)
3
BOOT
1
0: Low (BOOT OFF)
1: High (BOOT ON)
4
ISET
1
0: Low (ISET OFF)
1: High (ISET ON)
7-5
Unused
3
Open all switch
Reserved
ID is connected to IDBP
Reserved
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Device Type 3
Address: 15h
Reset Value: x000x000
Type: Read
BIT
NO.
NAME
SIZE (BITS)
DESCRIPTION
0
MHL
1
MHL device detected
1
VBUS Debounce
1
This bit goes high after the 8ms VBUS debounce time
2
VBUS NonStandard
1
A non-standard charger device detected. This bit goes high after BCDv1.2 timer expires
3
Unused
1
4
A/V VBUS
1
A/V Dock with VBUS connected
5
Apple Chg
1
Apple Charger
6
U200 Chg
1
U200 Charger
7
Video
1
75 Ohm video cable
Reset
Address:1Bh
Reset Value: xxxxxxx0
Type: Write
BIT NO.
NAME
0
Reset
1
7-1
Unused
6
30
SIZE (BITS) DESCRIPTION
Manual reset on device
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Timer Setting
Address: 20h
Reset Value:00010101
Type: Read and Write
BIT NO.
NAME
SIZE (BITS)
2-0
ADC Start Time
3
DESCRIPTION
000:
001:
010:
011:
100:
101:
110:
111:
1ms
2ms
4ms
8ms
12ms
16ms
20ms
24ms
5-3
BCDv1.2 Timer
3
000:
001:
010:
011:
100:
101:
0.6s
1.2s
1.8s
2.4s
3s
3.6s
6
Load Switch Enable
Time
1
0: 150ms
1: 450ms
7
ISET Enable Time
1
0: 40ms
1:100ms
OCP Setting 1
Address: 21h
Reset Value:001010x1
Type: Read and Write
BIT NO.
NAME
0
BCDv1.2 Enable
SIZE (BITS) DESCRIPTION
1
0: disabled
1: enabled
1
Unused
1
4-2
OCP Timeout Delay
3
000:
001:
010:
011:
100:
101:
1ms
2ms
4ms
8ms
12ms
16ms
7-5
OCL Current Limiter
Setting
1
000:
001:
010:
011:
1.5A
2.0A
2.5A
2.5A
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OCP Setting 2
Address: 22h
Reset Value:xxx11001
Type: Read and Write
BIT NO.
NAME
2-0
OCP Protection Level
Setting
SIZE (BITS) DESCRIPTION
3
000:
001:
010:
011:
4-3
OC Enable
2
00:
01:
10:
11:
7-5
Unused
3
1.0A
1.5A
2.0A
2.0A
OCP & OCL disabled
OCP disabled & OCL enabled
Unused
OCP & OCL enabled
Device Type 4
Address: 23h
Reset Value:xxxxx111
Type: Read and Write
32
BIT
NO.
NAME
SIZE (BITS)
2-0
MCPC ID
Resistor Value
3
7-3
Unused
5
DESCRIPTION
000:
001:
010:
011:
100:
101:
110:
47k ohms
180k ohms
390k ohms
287k ohms (Mode 1)
557k ohms (Mode 3)
797k ohms (Mode 2)
Error 111: Reset
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APPLICATION SCHEMATIC
VBAT
1kΩ ~
10kΩ
ISET Resistor
OUT
PMIC
10µF
VBAT
JIG
JIG
ISET
0.1µF
ISET
VDDIO
AP OR
BASEBAND
Battery
1µF~
10µF
1.7 ~ 3.6V
VDDIO
1µF~
10µF
0.1µF
1kΩ ~
10kΩ
1kΩ ~
10kΩ
SCL
SCL
SDA
SDA
2.2Ω
INTB
INTB
TxD
TxD
RxD
RxD
VBUS
2.2Ω
TSU6721
DM_HOST
DM_HOST
DP_HOST
DP_HOST
IDBP
IDBP
BOOT
BOOT
1pF~
10pF
ESD
V+
0.1µF
DM
DP
2.2Ω
1pF
ESD
1µF
MICRO
USB
DN
DP
1pF
ESD
2.2Ω (optional )
ID
GND
1pF
ESD
ID
GND
MIC_BIAS
MIC
AUDIO
CODEC
S_R
S_L
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CRITICAL COMPONENTS
PIN NAME
PIN NUMBER
VBUS
A5, B5
D3
VDDIO
CRITICAL COMPONENT
2.2 Ω
1 µF~10 µF
0.1 µF
1 µF~10 µF
VBAT
C3
Battery
0.1 µF
JIG
E3
MIC
B3
1 kΩ~10 kΩ
2.2 kΩ
10 µF
ISET
A2
Resistor determined by Battery Charger
S_R
D4
220 µF (1)
S_L
C4
220 µF (1)
OUT
A4, B4
SCL
A1
1 kΩ~10 kΩ
SDA
B1
1 kΩ~10 kΩ
DM
C5
DP
D5
ID
E5
(1)
10 µF
2.2 Ω
ESD Protection Diode
2.2 Ω
ESD Protection Diode
2.2 Ω (1)
ESD Protection Diode
Optional Components
SCHEMATIC GUIDELINES
1. VBUS, VDDIO, and VBAT require decoupling capacitors to reduce noise from circuit elements. The
capacitors act as a shunt to block off the noise. The 0.1µF capacitor smoothes out high frequencies and has
a lower series inductance. The 1µF~10µF and 1µF capacitors smooth out the lower frequencies and have a
much higher series inductance. Placing both decoupling capacitors will provide better load regulation across
the frequency spectrum.
2. OUT requires a 10µF load capacitor to prevent sudden increases of voltage on the pin during charging
3. JIG is an open-drain output and therefore requires a 1kΩ ~ 10kΩ pull-up resistor to VBAT
4. ISET is an open drain output. It can be used by the battery charger to set the input current limit with a series
resistor (for example 75Ω determined by the charger)
5. SCL and SDA require 1kΩ ~ 10kΩ pull-up resistors to VDDIO to prevent floating inputs
6. Depending on the codec used, S_R and S_L may require DC blocking capacitors as high as 220µF. The
capacitor might not be needed if the codec has the capability to provide ground centered signals.
7. Mic requires a 2.2kΩ pull-up resistor to MIC_BIAS to provide DC bias for the microphone. Additionally the
10µF capacitor is required to block the DC signals from MIC_BIAS to the Audio Codec
8. VBUS, DM and DP are recommended to have an external resistor 2.2Ω to provide extra ballasting to protect
the chip and internal circuitry
(a) For ID, if there is less stress on the ID pin then the external 2.2Ω resistor is optional
34
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9. DDM, DP, and ID are rated for 6kV IEC contact discharge protection. To prevent failure in case of an IEC
contact discharge of 8kV or greater, it is recommended to have an external ESD Protection Diode (~1pF of
capacitance allowed) rated for greater than 8kV IEC protection. It is also recommended to have an external
ESD Protection Diode to prevent DP and DM from failure in the event of EOS related to electrical surge
propagated downstream from the AC power supply
10. VBUS is rated for 6kV IEC contact discharge protection. To prevent failure in case of an IEC contact
discharge of 8kV or greater, it is recommended to have an external ESD Protection Diode (~1pF of
capacitance allowed) rated for greater than 8kV IEC protection. It is also recommended to have an external
ESD Protection Diode to prevent VBUS from failure in the event of EOS related to electrical surge
propagated downstream from the AC power supply.
PCB ROUTING GUIDELINES
Routing Guidelines for USB Signal Integrity
1. All the USB lines DP_CON, DM_CON, DP_HT, DM_HT, TxD and RxD
(a) Must have 45Ω single ended characteristic impedance
(b) Must have 90Ω differential ended impedance
(c) To fulfill USB 2.0 requirements
2. TSU6721 location
(a) Close to the USB connector as possible
(b) The distance between the USB controller and the device less than 1 inch
(c) Shorter length of the trace will reduce effect of stray noise and radiate less EMI
3. Minimize use of VIAs for USB related signals
(a) Differential transmission lines should be matched as close as possible
(b) No VIAs for optimum USB2.0 performance
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TSU6721YFFR
ACTIVE
DSBGA
YFF
25
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
TSU6721
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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