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TSU8111
SCDS335A – SEPTEMBER 2012 – REVISED AUGUST 2014
TSU8111 Dual SP2T USB 2.0 High Speed Switch with Single Cell Charger
1 Features
2 Applications
•
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Dual Single-Pole Double-Throw (SP2T) USB 2.0
High Speed Switch
– UART Path Supports either UART or USB 2.0
High Speed Signals
Integrated Single-Cell Charger
– Integrated Low Dropout Linear Regulator
(LDO)
– 1% Charge Voltage Regulation Accuracy
– 8% Charge Current Accuracy
– Programmable Charging Current Limit up to
950 mA for Wall Adapters
USB Battery Charging Specification v1.1 (BCv1.1)
Compliant Charger Detection
– VBUS Detection
– Data Contact Detection
– Primary and Secondary Detection
– USB Chargers (DCP, CDP, SDP) Supported
5-bit Accessory Detection on ID pin
– Automatic Switching by Accessory Type
I2C Interface
– Manual Switching Capability
– Interrupts Generated for Attach and Detach
– Supports Control Signals Used in
Manufacturing (JIG, BOOT)
28-V Tolerance on VBUS Pin With Overvoltage
Protection
Thermal Regulation and Thermal Shutdown for
Output Current Control
JESD 22 ESD Performance
– 12-kV Human Body Model
(VBUS/DP_CON/DM_CON/ID_CON)
– 2-kV Human Body Model (All Other Pins)
IEC ESD Performance
– ±4-kV Contact Discharge (IEC 61000-4-2)
(VBUS/DP_CON/DM_CON/ID_CON to GND)
Surge Protection on
VBUS/DP_CON/DM_CON/ID_CON to GND
– Protects USB Connector Pins Without External
Components
Mobile Phones
Netbooks/Notebooks
Tables
Portable Handheld Devices
3 Description
The TSU8111 is a dual single-pole double-throw
(SP2T) micro-USB switch with an integrated linear
charger. The integrated charger eliminates the need
for an external charger IC, reducing cost and board
space. The device operates from either a USB port or
dedicated charger and supports charging currents of
up to 950 mA. Power for the device is supplied
through VBAT or through VBUS when attached. The
TSU8111 detects BCv1.1-compatible chargers as
well as accessories that use an ID resistor. The USB
switch matrix can be controlled either by automatic
detection or manually through I2C.
Device Information(1)
PART NUMBER
TSU8111
PACKAGE
DSBGA (20)
BODY SIZE (NOM)
2.14 mm × 1.76 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Actual Fast-charging Current vs Register Setting
Across Device Temperature Range
1000
Actual LDO Output Current (mA)
1
900
800
700
600
500
400
300
200
-40°C
25°C
85°C
100
0
0
100
200 300 400 500 600 700 800
ISET Curent Setting in Register 22h (mA)
900 1000
D001
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TSU8111
SCDS335A – SEPTEMBER 2012 – REVISED AUGUST 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
4
4
5
5
5
8
8
8
Absolute Maximum Ratings ......................................
Handling Ratings ......................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ...............................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
7.3
7.4
7.5
7.6
8
Feature Description.................................................
Device Functional Modes........................................
Programming ..........................................................
Register Map...........................................................
10
11
12
16
Application and Implementation ........................ 25
8.1 Application Information............................................ 25
8.2 Typical Application ................................................. 25
9 Power Supply Recommendations...................... 26
10 Layout................................................................... 27
10.1 Layout Guidelines ................................................. 27
10.2 Layout Example .................................................... 27
11 Device and Documentation Support ................. 28
Detailed Description .............................................. 9
11.1 Trademarks ........................................................... 28
11.2 Electrostatic Discharge Caution ............................ 28
11.3 Glossary ................................................................ 28
7.1 Overview ................................................................... 9
7.2 Functional Block Diagram ......................................... 9
12 Mechanical, Packaging, and Orderable
Information ........................................................... 28
4 Revision History
Changes from Original (September 2012) to Revision A
•
2
Page
Changed this data sheet to new SDS format plus replaced all text, tables and graphics. ................................................... 1
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SCDS335A – SEPTEMBER 2012 – REVISED AUGUST 2014
5 Pin Configuration and Functions
YFP Package
(TOP VIEW)
YFP Package
(BOTTOM VIEW)
E
E
D
D
C
C
B
B
A
A
4
3
2
1
1
2
3
4
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
BOOT
B2
O
BOOT mode used for factory test modes. Push-pull output (active high)
DM_CON
C4
I/O
USB DM connected to USB receptacle
DM_HT
D1
I/O
USB DM on device side
DP_CON
D4
I/O
USB DP connected to USB receptacle
DP_HT
E1
I/O
USB DP on device side
A2, D3
—
Ground
ID_CON
E4
I/O
USB ID connected to USB receptacle
INTB
C3
O
Interrupt to host. Push-pull output (active high)
JIG
C2
O
JIG detection used for factory test modes. Open-drain output (active low)
RxD
C1
I/O
UART Rx – capable of passing USB 2.0 HS signals
SCL
E3
I
I2C clock
SDA
E2
I/O
I2C data
UART Tx – capable of passing USB 2.0 HS signals
GND
TxD
B1
I/O
VBAT
A3, B3
I
Supply voltage from battery
VBUS
A4, B4
I
Supply voltage from micro-USB connector. Charger is enabled when this supply is present.
VDDIO
D2
I
I2C and interrupt interface logic supply voltage
VLDO
A1
O
Low dropout regulator (LDO) charger output
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SCDS335A – SEPTEMBER 2012 – REVISED AUGUST 2014
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
Supply voltage
(1)
MIN
MAX
VBAT
–0.5
6
VBUS
–0.5
28
VDDIO
–0.5
4.6
VDM_CON, VDP_CON, VID_CON, VDP_HT, VDM_HT
–0.5
VBAT +
0.5 (2)
–0.5
VBAT +
0.5 (2)
VSDA
–0.5
4.6
VLDO
–0.5
6
VJIG
–0.5
VBAT +
0.5 (2)
VINTB, VBOOT
–0.5
4.6
Input-output terminal voltage,
VIO
VRxD, VTxD
Output voltage
Input current
IBAT
1
IBUS
1
IK
Analog port diode current
–50
IIK
Digital logic input clamp current
–50
ISCL
ISDA
Input-output terminal current,
IIO(on)
IIO
IIO(peak)
On-state continuous switch current
On-state peak switch current
(2)
V
V
A
mA
–50
50
–50
50
–60
60
–150
150
mA
100
IGND
IINTB, IBOOT
(1)
V
50
ILDO
Output current
UNIT
–50
mA
50
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
If VBUS is present without VBAT, then the absolute maximum voltage is VBUS + 0.5 V, and shall not exceed 6 V in total.
6.2 Handling Ratings
Tstg
Storage temperature range
VBUS, DP_CON,
DM_CON, ID_CON
Human body model (HBM), stress voltage (1)
V(ESD)
Electrostatic
discharge
Charged device model (CDM), stress voltage
(2)
All other pins
IEC-61000-4-2 contact discharge
(1)
(2)
4
MIN
MAX
UNIT
–65
150
°C
–12
12
–2
2
–4
4
kV
kV
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
Supply voltage
MIN
MAX
VBAT
3
4.4
VBUS
4
6.5
1.65
3.6
0
3.6
VDDIO
Input-output terminal voltage, VIO
VDM_CON, VDP_CON, VID_CON, VDP_HT, VDM_HT, VRxD, VTxD
ID pin capacitance
CID
LDO output capacitance
CLDO
Operating free-air temperature
TA
1
1
–40
85
UNIT
V
V
nF
°C
6.4 Thermal Information
TSU8111
THERMAL METRIC
(1)
YFP
UNIT
20 PINS
RθJA
Junction-to-ambient thermal resistance
70.3
RθJC(top)
Junction-to-case (top) thermal resistance
0.4
RθJB
Junction-to-board thermal resistance
10.4
ψJT
Junction-to-top characterization parameter
1.8
ψJB
Junction-to-board characterization parameter
10.4
(1)
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
6.5 Electrical Characteristics
VBAT = 3 V to 4.4 V, VDDIO = 2.8 V, TA = –40°C to 85°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
USB and UART PATHS (1)
8
Ω
VI = 0.4 V, IO = –2 mA, VBAT = 3.6 V
0.5
Ω
On-state resistance flatness
VI = 0 V to 3.6 V, IO = –2 mA, VBAT = 3.6 V
0.7
Ω
IIO(OFF)
Off-state leakage current
VI = 0.3 V, VO = 2.7 V or VI = 2.7 V, VO = 0.3
V, VBAT = 4.4 V, Switch off
45
nA
IIO(ON)
On-state leakage current
VI = OPEN, VO = 0.3 V or 2.7 V, VBAT = 4.4 V,
Switch on
50
nA
CI(OFF)
Off-state capacitance at input
DC bias = 0 V or 3.6 V, f = 10 MHz, Switch off
4
pF
CO(OFF)
Off-state capacitance at output
DC bias = 0 V or 3.6 V, f = 10 MHz, Switch off
7.5
pF
CI(ON)
On-state capacitance at input
DC bias = 0 V or 3.6 V, f = 10 MHz, Switch off
8.6
pF
CO(ON)
On-state capacitance at output
DC bias = 0 V or 3.6 V, f = 10 MHz, Switch off
8.6
pF
BW
Bandwidth
RL = 50 Ω, Switch on
820
MHz
OISO
Off isolation
f = 240 MHz, RL = 50 Ω, Switch off
-36
dB
XTALK
Crosstalk
f = 240 MHZ, RL = 50 Ω
-35
dB
Rising
250
Falling
45
RON
On-state resistance
VI = 0 V to 3.6 V, IO = –2 mA, VBAT = 3.6 V
ΔRON
On-state resistance match
between channels
RON(flat)
LINEAR CHARGER (2)
VCHG(OK)
VBUS(OVP)
(1)
(2)
Charger input voltage OK
threshold
VBUS over-voltage protection
(default 7.5 V)
VBUS – VBAT
I2C register 22h [7:6] = 00
6
I2C register 22h [7:6] = 01
6.5
I2C register 22h [7:6] = 10
7
I2C register 22h [7:6] = 11
7.5
mV
V
VO is equal to the asserted voltage on DP_CON and DM_CON. VI is equal to the asserted voltage on DP_HT and DM_HT pins. IO is
equal to the current out of the DP_CON and DM_CON pins. II is equal to the current into the DP_HT and DM_HT pins.
Fast charging current will fall below listed values when junction temperature rises above 85°C due to thermal regulation circuitry.
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Electrical Characteristics (continued)
VBAT = 3 V to 4.4 V, VDDIO = 2.8 V, TA = –40°C to 85°C (unless otherwise noted)
PARAMETER
VBUS(OVP,fail)
VBUS over-voltage falling
threshold for restart charging
VPRECHG
Pre-charge threshold voltage
VCHG(RST)
TEST CONDITIONS
MIN
TYP
mV
2.5
V
I2C register 20h [6:5] = 00
130
2
Charge restart threshold (default I C register 20h [6:5] = 01
100 mV)
I2C register 20h [6:5] = 10
130
I2C register 20h [6:5] = 11
240
LDO dropout voltage
VBUS = 4.5 V, ILDO = 50 mA
150
VLDO
LDO output voltage
VLDO + VDO(LDO) ≤ VBUS ≤ VBUS(OVP)
4.9
ILDO
LDO output current
VLDO = 0 V
IPRECHG
Default pre-charge current
VBAT = 2 V
CLDO
LDO output capacitance
TPRECHG
Pre-charge timeout
μF
30
min
4.02
I2C register 21h [3:0] = 0010
4.04
I2C register 21h [3:0] = 0011
4.06
4.08
I2C register 21h [3:0] = 0101
4.1
I2C register 21h [3:0] = 0110
4.12
I2C register 21h [3:0] = 0111
4.14
I2C register 21h [3:0] = 1000
4.16
I2C register 21h [3:0] = 1001
4.18
I2C register 21h [3:0] = 1010 (default)
I C register 21h [3:0] = 1011
4.22
I2C register 21h [3:0] = 1100
4.24
I2C register 21h [3:0] = 1101
4.26
2
I C register 21h [3:0] = 1110
4.28
I2C register 21h [3:0] = 1111
4.35
I2C register 22h [3:0] = 0000
200
2
I C register 22h [3:0] = 0001
250
I2C register 22h [3:0] = 0010
300
I2C register 22h [3:0] = 0011
350
I2C register 22h [3:0] = 0100
400
2
I C register 22h [3:0] = 0101 (default)
450
I2C register 22h [3:0] = 0110
500
I2C register 22h [3:0] = 0111
550
2
I C register 22h [3:0] = 1000
600
I2C register 22h [3:0] = 1001
650
I2C register 22h [3:0] = 1010
700
2
I C register 22h [3:0] = 1011
750
I2C register 22h [3:0] = 1100
800
I2C register 22h [3:0] = 1101
850
I2C register 22h [3:0] = 1110
900
2
I C register 22h [3:0] = 1111
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V
4.2
2
6
mA
1
I C register 21h [3:0] = 0001
Charging current accuracy
mA
4
I C register 21h [3:0] = 0100
Fast charging current
V
90
2
ISET
mV
50
2
Charging voltage
mV
190
I2C register 21h [3:0] = 0000
UNIT
320
VDO(LDO)
VSET
MAX
mA
950
-8%
8%
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Electrical Characteristics (continued)
VBAT = 3 V to 4.4 V, VDDIO = 2.8 V, TA = –40°C to 85°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
2
I C register 22h [7:4] = 0000
50
I2C register 22h [7:4] = 0001
60
I2C register 22h [7:4] = 0010
70
2
I C register 22h [7:4] = 0011
UNIT
90
I2C register 22h [7:4] = 0101 (default)
100
I2C register 22h [7:4] = 0110
110
2
Full charge current
MAX
80
I2C register 22h [7:4] = 0100
IFULL
TYP
I C register 22h [7:4] = 0111
120
I2C register 22h [7:4] = 1000
130
I2C register 22h [7:4] = 1001
140
2
I C register 22h [7:4] = 1010
150
I2C register 22h [7:4] = 1011
160
I2C register 22h [7:4] = 1100
170
2
I C register 22h [7:4] = 1101
180
I2C register 22h [7:4] = 1110
190
I2C register 22h [7:4] = 1111
200
mA
I2C INTERFACE (SCL and SDA)
VIH
High-level input voltage
VDDIO ×
0.7
VDDIO
V
VIL
Low-level input voltage
0
VDDIO ×
0.3
V
VOH
High-level output voltage
IOH = –3 mA
VDDIO ×
0.7
VDDIO
V
VOL
Low-level output voltage
IOL = 3 mA
0
0.4
V
0.5
V
1.16
VDDIO
V
0
0.33
V
27
36
μA
100
150
μA
0.75
mA
DIGITAL SIGNAL OUTPUTS – JIG, INTB, and BOOT
VOL(JIG)
Low-level output voltage
IOL = 10 mA, VBAT = 3.0 V
VOH(INTB,BOOT)
High-level output voltage
IOH = -4 mA, VDDIO = 1.65 V
VOL(INTB,BOOT)
Low-level output voltage
IOL = 4 mA, VDDIO = 1.65 V
CURRENT CONSUMPTION
IBAT(standby)
VBAT standby current
consumption
VBUS = 0 V, idle state
IBAT(operating)
VBAT operating current
consumption
VBUS = 0 V, USB switch closed
IBUS
VBUS operating current
consumption
VBUS = 5 V, VBAT floating
0.6
VOLTAGE PROTECTION
VBUS(UVLO)
VBUS(valid)
VBAT(UVLO)
VBUS under voltage – upper
threshold
VBUS rising
2.85
VBUS under voltage – lower
threshold
VBUS falling
2.55
VBUS interrupt threshold
VBUS rising
3.6
VBAT under voltage – upper
threshold
VBAT rising
2.65
VBAT under voltage – lower
threshold
VBAT falling
2.45
V
V
V
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6.6 Timing Requirements
MIN
fSCL
I2C clock frequency
TYP
64
MAX
UNIT
400
kHz
MAX
UNIT
6.7 Switching Characteristics
PARAMETER
TEST CONDITIONS
MIN
TYP
ton
Switch turn-on time
From receipt of I2C ACK bit
57
µs
toff
Switch turn-off time
From receipt of I2C ACK bit
5.2
µs
6.8 Typical Characteristics
Actual LDO Output Current (mA)
1000
900
800
700
600
500
400
300
200
-40°C
25°C
85°C
100
0
0
100
VBAT = 4 V
200 300 400 500 600 700 800
ISET Curent Setting in Register 22h (mA)
900 1000
D001
VBUS = 5 V
Figure 1. Actual Fast-charging Current vs
Register Setting Across Device Temperature Range
8
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7 Detailed Description
7.1 Overview
The TSU8111 is designed to interface a portable device (PD) to external peripherals through a micro-USB
connector.
The device will automatically detect accessories via the mini-USB or micro-USB 5-pin connectors. The type of
accessory detected will be stored in the TSU8111’s I2C registers, and can be read by the host processor. The
TSU8111 has a network of USB 2.0 High Speed switches that can be automatically opened and closed based on
the accessory detected. See Automatic Switching Mode for details of which switches are closed during each
mode of operation. The TSU8111 also offers a manual switching mode through I2C, allowing the host processor
to decide which switches will be opened and closed.The TSU8111 also provides a linear charger with a
maximum programmable charging current of 950 mA.
7.2 Functional Block Diagram
VBAT
Linear
Charger
VLDO
Power
Management
State Machine
VBUS
DP_HT
DP_CON
Switch
Matrix
DM_HT
RxD
DM_CON
TxD
ID_CON
VDDIO
SCL
2
SDA
INTB
I C Interface
and
Hardware
Control
Charger Detection
Accessory
Detection ADC
JIG
BOOT
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7.3 Feature Description
7.3.1 Linear Charger
The TSU8111 has a linear battery charger with charging currents adjustable from 200 mA to 950 mA. If 3.7 V <
VBUS < 7.5 V and VBUS > VBAT + 250 mV, then the charger starts charging automatically. If VBAT < VPRECHG, the
device starts with a pre-charge mode with a charging current of 90 mA. Once VBAT reaches VPRECHG, the device
switches to fast charge mode with soft start. When VBAT approaches VSET, constant-voltage (CV) charging mode
starts with programmed regulation voltage. At CV mode, if the charging current reaches the programmed full
charge current, the TSU8111 will generate an interrupt to the host indicating a full charge and will start the
charger shutoff timer. If the shutoff timer is disabled, the charger stays at CV mode until stopped by the host
processor.
Power on
Pre-charge phase . Charging
current is set by I PRECHG
Yes
No
VBAT < VPRECHG ?
Yes
Charge with
IPRECHG
tPRECHG
expired?
No
VBAT < VPRECHG ?
No
Yes
Constantcurrent (CC)
mode. Charge
with ISET
FCHGTM expired?
Fast charge phase . Charging
current is set by I SET
Timer fault
Yes
No
Yes
VBAT < VSET ?
No
Constant-voltage (CV)
mode < IFULL ?
No
Yes
Yes
CH_DONE ?
No
Figure 2. TSU8111 Charger Flow Chart
10
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Feature Description (continued)
7.3.2 Voltage Protection
7.3.2.1 Overvoltage Protection
When VBUS rises above VBUS(OVP), the linear charger is turned off, removing power from the circuit. The OVP EN
interrupt bit is set high when an overvoltage condition is detected. When the input voltage returns below
VBUS(OVP) – VBUS(OVP(hys)) and remains above VBUS(UVLO) , the charger is turned on again.
7.3.2.2 Undervoltage Protection
The TSU8111 is powered off when VBUS and VBAT are below the lower thresholds of VBUS(UVLO) and VBAT(UVLO).
When VBAT rises above 2.5 V, the device will be turned on but the linear charger will remain powered off. Both
the TSU8111 and the linear charger will only be turned on when VBUS > 3.7 V and VBUS – VBAT > 250 mV.
7.3.3 Power-on Reset
When power is applied to VBAT, an internal power-on reset holds the TSU8111 in a reset condition. When VBAT
reaches VPOR, the TSU8111 I2C registers and state machine initialize to their default states.
After the initial power-up phase, VBAT must be lowered below 0.2 V and then back up to VDDIO to initiate a power
reset cycle.
7.3.4 Software Reset
To initiate a software reset on the TSU8111, perform the steps below:
1. Hold SDA and SCL low for at least 30 ms to reset the digital logic of the TSU8111.
2. Write a 1 to bit 0 of register 1Bh. This will reset the TSU8111, and the bit will be cleared after the reset. After
the reset, INTB will keep low until the INT Mask bit of register 02h is cleared.
7.3.5 Power Supervisor
The TSU8111 uses VBAT as the primary supply voltage. VBUS is the secondary supply. VDDIO is used for I2C
communication.
7.4 Device Functional Modes
7.4.1 Standby Mode
Standby mode is the default mode upon power up and occurs when no accessory is attached. During this time,
the VBUS and ID lines are continually monitored through comparators to determine when an accessory is
attached. If an accessory is attached, then the TSU8111 will enter either automatic or manual switching mode,
depending on bit 2 in register 02h.
7.4.2 Automatic Switching Mode
The TSU8111 uses a current source and an internal comparator to detect a resistance on the ID pin. The current
source creates VID on the ID pin, which is compared to a changing VREF input to the comparator. An incrementing
5-bit counter increases VREF until the comparator output changes. At this point, the TSU8111 latches the 5-bit
counter value and determines the accessory type from Table 1.
When the TSU8111 detects VBUS but no ID resistor, the TSU8111 runs charger detection on the DP and DM
lines. The TSU8111 can detect chargers compatible with the USB Battery Charging Specification version 1.1
(BCv1.1). The switch status for the BCv1.1 charger types can be found at the end of Table 1.
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Device Functional Modes (continued)
Table 1. Accessory and Charger Detection Lookup Table
SWITCH STATE
DETECTED
IMPEDANCE
ON ID (kΩ)
RESISTOR
TOLERANCE
(%)
5-BIT
COUNTER
ADC VALUE
OTG
0
N/A
MHL
1
5
28.7
Reserved Accessory #1
Reserved Accessory #2
Reserved Accessory #3
ACCESSORY
DP / DM
FACTORY CABLE
DP_HT /
DM_HT
RxD / TxD
JIG
BOOT
00000
ON
OFF
OFF
OFF
00000
OFF
OFF
OFF
OFF
5
01110
OFF
OFF
OFF
OFF
34
5
01111
OFF
OFF
OFF
OFF
40.2
5
10000
OFF
OFF
OFF
OFF
49.9
5
10001
OFF
OFF
OFF
OFF
Reserved Accessory #4
64.9
5
10010
OFF
OFF
OFF
OFF
Audio Device Type 2
80.27
5
10011
OFF
OFF
OFF
OFF
Phone Powered Device
102
5
10100
OFF
ON
OFF
OFF
TTY Converter
121
5
10101
OFF
OFF
OFF
OFF
UART Cable
150
5
10110
OFF
ON
OFF
OFF
Type 1 Charger
200
5
10111
ON
OFF
OFF
OFF
Factory Mode Cable – Boot Off
USB
255
5
11000
ON
OFF
ON
OFF
Factory Mode Cable – Boot On
USB
301
5
11001
ON
OFF
ON
ON
Audio / Video Cable
365
5
11010
OFF
OFF
OFF
OFF
Type 2 Charger
442
5
11011
ON
OFF
OFF
OFF
Factory Mode Cable – Boot Off
UART
523
5
11100
OFF
ON
ON
OFF
Factory Mode Cable – Boot On
UART
619
5
11101
OFF
ON
ON
ON
Stereo Headset with Remote
(Audio Device Type 1)
1000.07
10
11110
OFF
OFF
OFF
OFF
Monio/Stereo Headset (Audio
Device Type 1)
1002
10
11110
OFF
OFF
OFF
OFF
No ID
N/A
N/A
11111
OFF
OFF
OFF
OFF
USB Standard Downstream Port
(SDP)
N/A
N/A
11111
ON
OFF
OFF
OFF
USB Charging Downstream Port
(CDP)
N/A
N/A
11111
ON
OFF
OFF
OFF
Dedicated Charging Port (DCP)
N/A
N/A
11111
OFF
OFF
OFF
OFF
Audio Device Type 3
7.4.3 Manual Switching Mode
Write a 0 to bit 2 of register 02h to enable manual switching mode. The switch status of DP and DM can then be
controlled by writing to register 13h [7:2]. See Register Map for details about switch status using register 13h.
7.5 Programming
The bidirectional I2C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be
connected to a positive supply via a pullup resistor when connected to the output stages of a device. Data
transfer may be initiated only when the bus is not busy.
I2C communication with this device is initiated by the master sending a START condition, a high-to-low transition
on the SDA input/output while the SCL input is high (see Figure 3). After the start condition, the device address
byte is sent, most significant bit (MSB) first, including the data direction bit (R/W). This device does not respond
to the general call address. After receiving the valid address byte, this device responds with an ACK, a low on
the SDA input/output during the high of the ACK-related clock pulse.
12
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Programming (continued)
SDA
SCL
S
P
Stop Condition
Start Condition
Figure 3. Definition of START and Stop Conditions
The data byte follows the address ACK. The R/W bit is kept low for transfer from the master to the slave. The
data byte is followed by an ACK sent from this device. Data are the output only if complete bytes are received
and acknowledged. The output data is valid at time tpv after the low-to-high transition of SCL, during the clock
cycle for the ACK.
On the I2C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control
commands (START or STOP). See Figure 4.
SDA
SCL
Data Line
Change
Figure 4. Bit Transfer
A STOP condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the
master (see Figure 3).
The number of data bytes transferred between the START and STOP conditions from transmitter to receiver is
not limited. Each byte of eight bits is followed by one ACK bit. The transmitted must release the SDA line before
the receiver can send an ACK bit.
A slave receiver that is addressed must generate an ACK after the reception of each byte. The device that
acknowledges has to pull down the SDA line during the ACK clock pulse so that the SDA line is stable low during
the high pulse of the ACK-related clock period (see Figure 5). Setup and hold times must be taken into account.
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Programming (continued)
Data Output
by Transmitter
NACK
Data Output
by Receiver
ACK
SCL From
Master
1
2
8
9
S
Clock Pulse for
Acknowledgment
Start
Condition
Figure 5. Acknowledgement on I2C Bus
7.5.1 Writes
Data is transmitted to the TSU8111 by sending the device slave address and setting the LSB to a logic 0 (see
Figure 6 for device address). The command byte is sent after the address and determines which register
receives the data that follows the command byte. The next byte is written to the specified register on the rising
edge of the ACK clock pulse.
SCL
Slave Address
SDA
ST 0
1
0
0
Start
1
Sub Address
0
1
0
A
0
0
0
0
0
Data Byte
0
1
0
A D7 D6 D5 D4 D3 D2 D1 D0 A D7 D6 D5 D4 D3 D2 D1 D0 A SP
Register Address
(Control Reg)
W/R
ACK from slave
Auto-Inc.
Data Byte
ACK
from
slave
Data to Control
Register
ACK
from
slave
Data to Control Register ACK Stop
from
slave
Figure 6. Repeated Data Write to a Single Register
Slave Address
SDA
ST
0
1
Start
0
0
1
Sub Address
0
1
0
A
1
W/R
ACK from slave
Auto-Inc.
0
0
0
1
0
Data Byte
0
Register Address
(Timing Set 1 Reg)
0
Data Byte
A D7 D6 D5 D4 D3 D2 D1 D0 A D7 D6 D5 D4 D3 D2 D1 D0 A
ACK
from
slave
Data to Timing Set 1
Register
ACK
from
slave
Data to Timing Set 2
Register
Figure 7. Burst Data Write to Multiple Registers
7.5.2 Reads
The bus master must first send the TSU8111 slave address with the LSB set to logic 0. The command byte is
sent after the address and determines which register is accessed. After a restart, the device slave address is
sent again but, this time, the LSB is set to logic 1. Data from the register defined by the command byte then is
sent by the TSU8111. Data is clocked into the SDA output shift register on the rising edge of the ACK clock
pulse, see Figure 8.
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Programming (continued)
Slave Address
SDA
ST
0
1
0
0
Sub Address
1
Start
0
1
0
A
0
0
0
W/R
ACK from slave
Auto-Inc.
0
0
Slave Address
0
1
1
Register Address
(Interrupt 1 Reg)
A RS 0
ACK Re-Start
from
slave
1
0
0
1
Data Byte
0
1
1
A D7 D6 D5 D4 D3 D2 D1 D0
Data from Interrupt 1 Reg.
W/R
ACK from slave
Continued
Data Byte
Data Byte
A D7 D6 D5 D4 D3 D2 D1 D0 A D7 D6 D5 D4 D3 D2 D1 D0 NA SP
Data from Interrupt 1 Reg.
ACK from master
Data from Interrupt 1 Reg.
Stop
No ACK from master (message ends)
ACK from master
Figure 8. Repeated Data Read from a Single Register – Combined Mode
SCL
Slave Address
SDA
ST
0
1
0
0
Sub Address
1
Start
0
1
0
A
1
0
0
W/R
ACK from slave
Auto-Inc.
0
0
Slave Address
0
1
1
Register Address
(Interrupt 1 Reg)
A RS 0
ACK Re-Start
from
slave
1
0
0
1
Data Byte
0
1
1
A D7 D6 D5 D4 D3 D2 D1 D0
Data from Interrupt 1 Reg.
W/R
Ack. from slave
Continued
Data Byte
Data Byte
A D7 D6 D5 D4 D3 D2 D1 D0 A D7 D6 D5 D4 D3 D2 D1 D0 NA SP
Data from Interrupt 2 Reg.
ACK from master
Data from Int Mask 1 Reg.
Stop
No ACK from master (Message ends)
ACK from master
Figure 9. Burst Data Read from Multiple Registers – Combined Mode
Slave Address
SDA
ST 0
1
0
0
Start
1
Sub Address
0
1
0
A
0
0
0
W/R
ACK from slave
Auto-Inc.
0
0
Slave Address
0
1
1
Register Address
(Interrupt 1 Reg)
A SP ST 0
ACK
Start
from Stop
slave
1
0
0
1
Data Byte
0
1
1
A D7 D6 D5 D4 D3 D2 D1 D0
Data from Interrupt 1 Reg.
W/R
ACK from slave
Continued
Data Byte
Data Byte
A D7 D6 D5 D4 D3 D2 D1 D0 A D7 D6 D5 D4 D3 D2 D1 D0 NA SP
Data from Interrupt 1 Reg.
ACK from master
Data from Interrupt 1 Reg.
Stop
No ACK from master (Message ends)
ACK from master
Figure 10. Repeated Data Read from a Single Register – Split Mode
SCL
Slave Address
SDA
ST 0
Start
1
0
0
1
Sub Address
0
1
0
A
1
0
W/R
ACK from slave
Auto-Inc.
0
0
0
0
Slave Address
1
Register Address
(Interrupt 1 Reg)
1
A SP ST 0
ACK
Start
from Stop
slave
Data Byte
1
0
0
1
Data Byte
0
1
1
A D7 D6 D5 D4 D3 D2 D1 D0
W/R
Ack. from slave
Data from Interrupt 1 Reg.
Continued
Data Byte
A D7 D6 D5 D4 D3 D2 D1 D0 A D7 D6 D5 D4 D3 D2 D1 D0 NA SP
Data from Interrupt 2 Reg.
ACK from master
Data from Int Mask 1 Reg.
ACK from master
Stop
No ACK from master (Message ends)
Figure 11. Burst Data Read from Multiple Registers – Split Mode
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Programming (continued)
Additional notes on I2C interface:
1. SDA is pulled low on ACK from either the slave or the master.
2. Register writes always require sub-address writes before the first data byte.
3. Repeated data writes to a single register continue indefinitely until stop or restart.
4. Repeated data reads from a single register continue indefinitely until no ACK from master.
5. Burst data writes start at the specified register address, then advance to the next register address, even to
the read-only registers. For these registers, data write appears to occur, though no data are changed by the
writes. After register 14h is written, writing resumes to register 01h and continues until stop or restart.
6. Burst data reads start at the specified register address, then advance to the next register address. Once
register 14h is read, reading resumes from register 01h and continues until no ACK from master.
7.6 Register Map (1) (2)
(1)
(2)
Write “0” to the blank register bits.
Values read from the blank register bits are invalid and undefined.
TYPE
RESET
VALUE
ADDR
REGISTER
01h
Device ID
R
1011010
02h
Control
R/W
xxx11111
03h
Interrupt 1
R
x0000000
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
Switch Open
Raw Data
Manual Sw.
Wait
INT Mask
OVP EN
LKR
LKP
KP
Detach
Attach
Stuck Key
RCV
Stuck Key
ADC
Change
Reserved
Attach
A/V Charging
LKP
KP
Detach
Attach
Stuck Key
ADC
Change
Reserved
Attach
Charging A/V
Version ID
VBUS
Interrupt 2
R
x0000000
OTP EN
CONNECT
05h
Interrupt Mask 1
R/W
x0000000
VBUS
OVP EN
LKR
CONNECT
Stuck Key
RCV
Interrupt Mask 2
R/W
x0000000
OTP EN
07h
ADC
R
xxx11111
08h
Timing Set 1
R/W
0
Key Press
09h
Timing Set 2
R/W
0
Switching Wait
BIT 0
Vendor ID
04h
06h
BIT 1
ADC Value
Device Wake Up
Long Key Press
0Ah
Device Type 1
R
0
USB OTG
DCP
CDP
Type 1 /
Type 2
charger
0Bh
Device Type 2
R
0
Audio
Type 3
Audio /
Video
TTY
PPD
0Ch
Button 1
R
0
7
6
5
4
3
2
1
Send End
0Dh
Button 2
R
x0000000
Unknown
Error
12
11
10
9
8
13h
Manual SW 1
R/W
000000xx
DM Switching
14h
Manual SW 2
R/W
xxxx00xx
1Bh
Reset
W
11111111
20h
Charger Control 1
R/W
11000
21h
Charger Control 2
R/W
11010
22h
Charger Control 3
R//W
11010101
24h
Charger Interrupt
R
25h
Charger Interrupt
Mask
26h
Charger Status
UART
USB
VBUS
MHL
JIG UART
OFF
JIG UART
ON
JIG USB
OFF
JIG USB ON
DP Switching
BOOT SW
JIG ON
Reset
CH DIS
CHRSTTH
CHENOV
FCMEN
FCHGTM
IFULL
OVPV
CV SET
AUTOSTOP
ISET L
xx0xxxxx
CH FAULT
CH DONE
CH CV
CH FC
CH PC
CH IDLE
R/W
xx0xxxxx
CH FAULT
CH DONE
CH CV
CH FC
CH PC
CH IDLE
R
xx0xxxxx
CH FAULT
CH DONE
CH CV
CH FC
CH PC
CH IDLE
FTE
PTE
ISET
7.6.1 Device ID (01h) Register Field Descriptions
Table 2. Device ID (01h) Register Field Descriptions
16
Bit
Field
Type
Reset
7-3
Version ID
R
01011
2-0
Vendor ID
R
010
Description
Unique identifier for chip version (01011)
Unique identifier 010 for Texas Instruments
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7.6.2 Control (02h) Register Field Descriptions
Table 3. Control (02h) Register Field Descriptions
Bit
Field
Type
Reset
Description
7-5
Blank
N/A
N/A
4
Switch Open
R/W
1
0: Open all switches
1: Automatic switching by accessory detection
3
Raw Data
R/W
1
0: Continue reading ID pin resistance after impedance has been detected
1: When ID resistance is connected, do not run ID detection again until the next
attach/detach
2
Manual Sw.
R/W
1
0: Manual switching mode enabled and controlled by register 13h
1: Automatic switching by accessory detection
1
Wait
R/W
1
0: Wait until host resets this bit high
1: Wait until switching timer has expired
0
INT Mask
R/W
1
0: Unmask interrupt
1: Mask interrupt
N/A
7.6.3 Interrupt 1 (03h) Register Field Descriptions
Table 4. Interrupt 1 (03h) Register Field Descriptions
Bit
Field
Type
Reset
7
Unused
N/A
N/A
Description
6
VBUS
R/Clr
0
1: VBUS detected
5
OVP EN
R/Clr
0
1: Overvoltage detected
4
LKR
R/Clr
0
1: Long key release
3
LKP
R/Clr
0
1: Long key press
2
KP
R/Clr
0
1: Key press
1
Detach
R/Clr
0
1: Accessory detach detected
0
Attach
R/Clr
0
1: Accessory attach detected
N/A
7.6.4 Interrupt 2 (04h) Register Field Descriptions
Table 5. Interrupt 2 (04h) Register Field Descriptions
Bit
Field
Type
Reset
7
Unused
N/A
N/A
Description
6
OTP EN
R
0
1: Over-temperature protection enabled
5
Connect
R
0
1: Switch is connected (closed)
4
Stuck Key
RCV
R
0
1: Stuck key is recovered
3
Stuck Key
R
0
1: Stuck key is detected
2
ADC_Change
R
0
1: ADC value is changed when Raw Data is enabled
1
Reserved_Atta
ch
R
0
1: Reserved device is attached
0
A/V_Charging
R
0
1: Charger detected when A/V cable is attached
N/A
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7.6.5 Interrupt Mask 1 (05h) Register Field Descriptions
Table 6. Interrupt Mask 1 (05h) Register Field Descriptions
Bit
Field
Type
Reset
Description
7
Unused
N/A
N/A
6
VBUS
R/W
0
0: Unmask VBUS interrupt
1: Mask VBUS interrupt
5
OVP EN
R/W
0
0: Unmask OVP EN interrupt
1: Mask OVP EN interrupt
4
LKR
R/W
0
0: Unmask long key release interrupt
1: Mask long key release interrupt
3
LKP
R/W
0
0: Unmask long key press interrupt
1: Mask long key press interrupt
2
KP
R/W
0
0: Unmask key press interrupt
1: Mask key press interrupt
1
Detach
R/W
0
0: Unmask detach interrupt
1: Mask detach interrupt
0
Attach
R/W
0
0: Unmask attach interrupt
1: Mask attach interrupt
N/A
7.6.6 Interrupt Mask 2 (06h) Register Field Descriptions
Table 7. Interrupt Mask 2 (06h) Register Field Descriptions
18
Bit
Field
Type
Reset
Description
7
Unused
R/W
N/A
6
OTP EN
R/W
0
0: Unmask OTP EN interrupt
1: Mask OTP EN interrupt
5
Connect
R/W
0
0: Unmask connect interrupt
1: Mask connect interrupt
4
Stuck Key
R/W
0
0: Unmask Stuck Key RCV interrupt
1: Mask Stuck Key RCV interrupt
3
Stuck Key
R/W
0
0: Unmask Stuck Key interrupt
1: Mask Stuck Key interrupt
2
ADC
Change
R/W
0
0: Unmask ADC Change interrupt
1: Mask ADC Change interrupt
1
Reserved
R/W
0
0: Unmask Reserved Attach interrupt
1: Mask Reserved Attach interrupt
0
A/V
Charging
R/W
0
0: Unmask A/V Charging interrupt
1: Mask A/V Charging interrupt
N/A
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7.6.7 ADC (07h) Register Field Descriptions
Table 8. ADC (07h) Register Field Descriptions
Bit
Field
Type
Reset
7-5
Reserved
R
N/A
4-0
ADC value
R
11111
Description
N/A
5-bit ADC counter value latched after accessory detection on ID pin
7.6.8 Timing Set 1 (08h) Register Field Descriptions
Table 9. Timing Set 1 (08h) Register Field Descriptions
Bit
7-4
3-0
Field
Key press
Device
wake up
Type
R/W
R/W
Reset
Description
0000
Normal key press duration
0000: 100 ms
0001: 200 ms
0010: 300 ms
0011: 400 ms
0100: 500 ms
0101: 600 ms
0110: 700 ms
0111: 800 ms
1000: 900 ms
1001: 1000 ms
Any other value: invalid
0000
Device wake up duration
0000: 50 ms
0001: 100 ms
0010: 150 ms
0011: 200 ms
0100: 300 ms
0101: 400 ms
0110: 500 ms
0111: 600 ms
1000: 700 ms
1001: 800 ms
1010: 900 ms
1011: 1000 ms
Any other value: invalid
7.6.9 Timing Set 2 (09h) Register Field Descriptions
Table 10. Timing Set 2 (09h) Register Field Descriptions
Bit
7-4
Field
Switching
wait
Type
R/W
Reset
0000
Description
Wait time between detection complete and switching
0000: 10 ms
0001: 30 ms
0010: 50 ms
0011: 70 ms
0100: 90 ms
0101: 110 ms
0110: 130 ms
0111: 150 ms
1000: 170 ms
1001: 190 ms
1010: 210 ms
Any other value: invalid
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Table 10. Timing Set 2 (09h) Register Field Descriptions (continued)
Bit
3-0
Field
Long key
press
Type
R/W
Reset
0000
Description
Long key press duration
0000: 300 ms
0001: 400 ms
0010: 500 ms
0011: 600 ms
0100: 700 ms
0101: 800 ms
0110: 900 ms
0111: 1000 ms
1000: 1100 ms
1001: 1200 ms
1010: 1300 ms
1011: 1400 ms
1100: 1500 ms
Any other value: invalid
7.6.10 Device Type 1 (0Ah) Register Field Descriptions
Table 11. Device Type 1 (0Ah) Register Field Descriptions
Bit
Field
Type
Reset
Description
7
USB OTG
R
0
USB on-the-go (OTG) device
6
DCP
R
0
Dedicated charging port
5
CDP
R
0
Charging downstream port
4
Type1/Type2
charger
R
0
Type 1 / Type 2 charger
3
UART
R
0
UART
2
USB
R
0
USB host
1
VBUS
R
0
VBUS valid
0
MHL
R
0
MHL device
7.6.11 Device Type 2 (0Bh) Register Field Descriptions
Table 12. Device Type 2 (0Bh) Register Field Descriptions
20
Bit
Field
Type
Reset
7
Audio Type 3
R
0
Audio type 3 cable
Description
6
Audio / Video
R
0
Audio / video cable
5
TTY
R
0
TTY converter
4
PPD
R
0
Phone-powered device
3
JIG UART OFF
R
0
Factory mode cable
2
JIG UART ON
R
0
Factory mode cable
1
JIG USB OFF
R
0
Factory mode cable
0
JIG USB ON
R
0
Factory mode cable
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7.6.12 Button 1 (0Ch) Register Field Descriptions
Table 13. Button 1 (0Ch) Register Field Descriptions
Bit
Field
Type
Reset
Description
7
7
R
0
Number 7 key is pressed
6
6
R
0
Number 6 key is pressed
5
5
R
0
Number 5 key is pressed
4
4
R
0
Number 4 key is pressed
3
3
R
0
Number 3 key is pressed
2
2
R
0
Number 2 key is pressed
1
1
R
0
Number 1 key is pressed
0
Send End
R
0
Send End key is pressed
7.6.13 Button 2 (0Dh) Register Field Descriptions
Table 14. Button 2 (0Dh) Register Field Descriptions
Bit
Field
Type
Reset
7
Unused
N/A
N/A
Description
6
Unknown
R
0
Unknown key is pressed
5
Error
R
0
Error key is pressed
4
12
R
0
Number 12 key is pressed
3
11
R
0
Number 11 key is pressed
2
10
R
0
Number 10 key is pressed
1
9
R
0
Number 9 key is pressed
0
8
R
0
Number 8 key is pressed
N/A
7.6.14 Manual SW 1 (13h) Register Field Descriptions
Table 15. Manual SW 1 (13h) Register Field Descriptions
Bit
7-5
Field
DM
switching
Type
R/W
Reset
Description
000
000: Open all switches
001: DM is connected to DM_HT
010: Open all switches
011: DM is connected to TxD
Any other value: invalid
4-2
DP
switching
R/W
000
000: Open all switches
001: DP is connected to DP_HT
010: Open all switches
011: DP is connected to RxD
Any other value: invalid
1-0
Unused
N/A
N/A
N/A
7.6.15 Manual SW 2 (14h) Register Field Descriptions
Table 16. Manual SW 2 (14h) Register Field Descriptions
Bit
Field
Type
Reset
7-4
Unused
N/A
N/A
Description
3
BOOT
SW
R/W
0
0: Low
1: High
2
JIG ON
R/W
0
0: High impedance
1: GND
1-0
Unused
N/A
N/A
N/A
N/A
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7.6.16 Reset (1Bh) Register Field Descriptions
Table 17. Reset (1Bh) Register Field Descriptions
Bit
Field
Type
Reset
7-1
Unused
N/A
N/A
0
Reset
W
0
Description
N/A
1: Write this value (1) to reset the device.
0: Set to this value (0) after reset completed.
7.6.17 Charger control 1 (20h) Register Field Descriptions
Table 18. Charger control 1 (20h) Register Field Descriptions
Bit
Field
Type
Reset
7
CH DIS
R/W
0
Force charger disable
0: Normal charger operation mode
1: Disable charger. Override charger detection and CHENOV
0
Charging restart threshold voltage
00: 130 mV
01: 130 mV
10: 190 mV
11: 240mV
1
Charger enabled override
0: Charger enabled is controlled by charger detection. Charger is enabled is DCP, CDP, or
Carkit charger is detected.
1: Charge is always enabled.
Fast charge mode enable. Device should be in pre-charge before setting FCMEN = 0 to
disable Fast Charge mode.
0: Fast charge mode is disabled. Charger remains in pre-charge mode.
1: Enable fast charge mode.
6-5
4
CHRSTTH
CHENOV
R/W
R/W
3
FCMEN
R/W
1
2
Unused
N/A
N/A
1-0
FCHGTM
R/W
0
Description
N/A
Fast charge timer – These bits control the maximum amount of time that the charger will
spend in fast charge mode. If the timer is over this time, FTE is changed to 1.
00: 5 hours
01: 6 hours
10: 7 hours
11: Disable fast charge timer
7.6.18 Charger control 2 (21h) Register Field Descriptions
Table 19. Charger control 2 (21h) Register Field Descriptions
Bit
7-4
22
Field
IFULL
Type
Reset
0001
Description
Charge done current threshold level
0000: 50 mA
0001: 60 mA
0010: 70 mA
0011: 80 mA
0100: 90 mA
0101: 100 mA
0110: 110 mA
0111: 120 mA
1000: 130 mA
1001: 140 mA
1010: 150 mA
1011: 160 mA
1100: 170 mA
1101: 180 mA
1110: 190 mA
1111: 200 mA
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Table 19. Charger control 2 (21h) Register Field Descriptions (continued)
Bit
3-0
Field
Type
CV SET
Reset
Description
1010
Constant voltage mode voltage - in fast charge mode, when the battery voltage reaches this
value, the charger transitions from fast charge mode to constant voltage charge mode.
0000: 4.00 V
0001: 4.02 V
0010: 4.04 V
0011: 4.06 V
0100: 4.08 V
0101: 4.10 V
0110: 4.12 V
0111: 4.14 V
1000: 4.16 V
1001: 4.18 V
1010: 4.20 V
1011: 4.22 V
1100: 4.24 V
1101: 4.26 V
1110: 4.28 V
1111: 4.35 V
7.6.19 Battery Charger Control 3 (22h) Register Field Descriptions
Table 20. Battery Charger Control 3 (22h) Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
OVP
R/W
0011
These bits set the overvoltage protection threshold.
00: 6.0 V
01: 6.5 V
10: 7.0 V
11: 7.5 V
5
AUTOST
OP
R/W
0000
Auto charging stop
0: Disable charging shutoff and keep CV mode
1: Enable charging shutoff after 30-minute timer
0001
This bit is used in conjunction with ISET[3:0], and it determines the fast charge mode
current limit.
0: 90 mA
1: 200 mA to 950 mA
0101
This sets the fast charge mode current.
0000: 200 mA
0001: 250 mA
0010: 300 mA
0011: 350 mA
0100: 400 mA
0101: 450 mA
0110: 500 mA
0111: 550 mA
1000: 600 mA
1001: 650 mA
1010: 700 mA
1011: 750 mA
1100: 800 mA
1101: 850 mA
1110: 900 mA
1111: 950 mA
4
3-0
ISET L
ISET
R/W
R/W
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7.6.20 Charger Interrupt (24h) Register Field Descriptions
Table 21. Charger Interrupt (24h) Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
Unused
N/A
0
Always reads 0
5
CH Fault
R/Clr
0
1: Charger in fault state
4
CH DONE
R/Clr
0
1: Charge complete / top-off mode
3
CH CV
R/Clr
0
1: Charger state in constant voltage (CV) mode
2
CH FC
R/Clr
0
1: Charger state in fast charge mode (constant current)
1
CH PC
R/Clr
0
1: Charger state in pre-charge mode
0
CH IDLE
R/Clr
0
1: Charge state idle
7.6.21 Charger Interrupt Mask (25h) Register Field Descriptions
Table 22. Charger Interrupt Mask (25h) Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
Unused
N/A
0
Always reads 0
5
CH_Fault
R/W
0
0: Unmask CH Fault interrupt
1: Mask CH Fault interrupt
4
CH_DON
E
R/W
0
0: Unmask CH Done interrupt
1: Mask CH Done interrupt
3
CH_CV
R/W
0
0: Unmask CH CV interrupt
1: Mask CH CV interrupt
2
CH_FC
R/W
0
0: Unmask CH FC interrupt
1: Mask CH FC interrupt
1
CH_PC
R/W
0
0: Unmask CH PC interrupt
1: Mask CH PC interrupt
0
CH_IDLE
R/W
0
0: Unmask CH IDLE interrupt
1: Mask CH IDLE interrupt
7.6.22 Charger Status (26h) Register Field Descriptions
Table 23. Charger Status (26h) Register Field Descriptions
Bit
Field
Type
Reset
Description
7
FTE
R/W
0
Fast charge timer expired interrupt
0: Timer not expired
1: 30-minute fast charge timer expired. Charge disabled. Restart when re-attaching charger
or toggling CHENOV.
PTE
R/W
0
Pre-charge timer expired interrupt
0: Timer not expired
1: 30-minute pre-charge timer has expired. Charger disabled. Restart when re-attaching
charger or toggling CHENOV.
5
CH Fault
R/W
0
1: Charger fault other than PTE or FTE
4
CH Done
R/W
0
1: Charge complete / top-off mode
3
CH CV
R/W
0
1: Charger state in constant voltage mode
2
CH FC
R/W
0
1: Charge state in fast charge mode (constant current)
1
CH PC
R/W
0
1: Charger state in pre-charge mode
0
CH IDLE
R/W
0
1: Charge state in idle (not charging)
6
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8 Application and Implementation
8.1 Application Information
The TSU8111 device can be used in portable device (PD) applications for interfacing the PD with external
peripherals. The TSU8111 is ideal for use when a PD needs two separate USB signal paths, accessory
detection, charger detection, and a battery charging IC.
8.2 Typical Application
VDDIO
VBUS
VLDO
1 kΩ
to
10 kΩ
1 kΩ
to
10 kΩ
1 kΩ
to
10 kΩ
1 µF
VBAT
JIG
VDDIO
SCL
Battery
1 µF
to
10 µF
0.1 µF
1 µF
to
10 µF
0.1 µF
+
–
1 µF
to
10 µF
1 pF
ESD
0.1 µF
SDA
INTB
Host
Processor
1.65 V
to
3.6 V
TSU8111
VBUS
TxD
RxD
VBUS
DM_CON
DM
2.2 Ω
1 pF
ESD
2.2 Ω
1 pF
ESD
2.2 Ω
1 pF
ESD
DM_HT
DP_HT
DP_CON
Micro-USB
connector
DP
BOOT
ID_CON
ID
GND
Figure 12. Interface from Host Processor to USB Connector and Battery
8.2.1 Design Requirements
For this design example, use the parameters listed in Table 24.
Table 24. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
VBAT
3 V to 4.4 V
VBUS
4 V to 6.5 V
VDDIO
1.65 V to 3.6 V
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8.2.2 Detailed Design Procedure
To begin the design process, determine the following:
• Desired ESD protection on micro-USB signal lines
– Addition of optional 1-pF ESD diodes on the USB lines protects against ±8-kV IEC-61000-4-2 contact
discharge. The optional 2.2-Ω resistors provide additional protection for the internal circuitry near the USB
inputs.
• Output current on LDO
– Use the charging specifications for the Li-Ion or Li-Polymer battery to determine the desired output current
register setting for the TSU8111 LDO.
8.2.3 Application Curves
On-resistance to DP_HT/DM_HT (
)
10
9
8
7
6
5
4
3
2
-40°C
25°C
85°C
1
0
0
1
2
3
4
5
USB signal (DP / DM) input voltage (V)
C001
Figure 13. USB Signal vs On-resistance
9 Power Supply Recommendations
The TSU8111 has three different power supply input pins: VBAT, VBUS, and VDDIO. VBAT is the primary supply
and accepts any voltage between –0.5 V and 6 V, but the operating voltage is between 3 V and 4.4 V. VBUS is
the secondary power supply from the micro-USB connector and accepts any voltage between –0.5 V and 28 V,
but the operating voltage is between 4 V and 6.5 V. VDDIO is the supply for I2C communication and accepts any
voltage between –0.5 V and 4.6 V, but the operating voltage is between 1.65 V and 3.6 V.
The VBAT and VBUS pins each require a 0.1-μF and a 1-μF to 10-μF decoupling capacitor. The 0.1-μF capacitor
smooths out high frequency noise and has a lower series inductance. The 1-μF to 10-μF capacitor smooths out
lower frequency noise and has a much higher series inductance. Placing both capacitors near each power supply
input will provide better load regulation across the frequency spectrum.
The VLDO pin requires a 1-μF load capacitor.
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10 Layout
10.1 Layout Guidelines
•
•
•
•
•
•
•
•
The TSU8111 should be placed as close to the USB connector as possible to reduce the effect of stray noise.
Decoupling capacitors, as mentioned in Power Supply Recommendations, should be as close to the device
as possible. This will also reduce the effect of ESR and ripple seen on voltages due to transient spikes.
Lengths of all traces should be kept less than 2 inches.
For 1-oz copper thickness, the width of the USB traces should be at least 15 mils.
Traces to the VBAT, VBUS, and VLDO pins should be capable of carrying 1 A. This will keep routing
resistance less than 100-mΩ and minimize voltage drops when charging with high currents.
Maximize the use of vias on VBUS, VBAT, and GND. Increasing the number of vias will reduce routing
resistance and improve thermal performance.
Minimize the use of vias for USB traces to preserve USB signal integrity.
All USB traces (DP_CON, DM_CON, DP_HT, DM_HT, TxD, and RxD) should have 45-Ω single-ended
impedance and 90-Ω differential impedance to fulfill USB 2.0 requirements.
10.2 Layout Example
Polygonal Copper Pour
VIA to VBAT Plane
VIA to GND Plane (Inner Layer)
VIA to Bottom Layer for Logic
To system
DP_HT
YFP Package
(Bottom View)
DM_HT
90-Ω differential
or 45-Ω singleended
characteristic
impedance for
USB paths
2.2 Ω
2.2 Ω
D
2.2 Ω
DP_CON
1 pF
To microUSB
connector
DM_CON
1 pF
B
VBUS
A
1
RxD
ID_CON
1 pF
C
USB path length
matching
recommended
To system
1 pF
E
2
3
4
0.1 µF
1 µF
To
10 µF
USB input as
close to TSU8111
as possible
TxD
1 µF
VLDO
Thicker traces on
VBAT, VBUS, and
VLDO for 1 A
To battery
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11 Device and Documentation Support
11.1 Trademarks
All trademarks are the property of their respective owners.
11.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TSU8111YFPR
ACTIVE
DSBGA
YFP
20
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
A8
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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