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TSV911, TSV912, TSV914
SBOS878D – JULY 2017 – REVISED OCTOBER 2019
TSV91x Rail-to-Rail Input/Output, 8-MHz Operational Amplifiers
1 Features
3 Description
•
•
•
•
•
•
•
•
•
The TSV91x family, which includes single-, dual-, and
quad-channel operational amplifiers (op amps), is
specifically
designed
for
general-purpose
applications. Featuring rail-to-rail input and output
(RRIO) swings, wide bandwidth (8 MHz), and low
offset voltage (0.3 mV, typical), this family is designed
for a variety of applications that require a good
balance between speed and power consumption. The
op amps are unity-gain stable and feature an ultralow input bias current, which enables the family to be
used in applications with high-source impedances.
The low input bias current allows the devices to be
used for sensor interfaces, battery-supplied and
portable applications, and active filtering.
1
•
Rail-to-rail input and output
Low noise: 18 nV/√Hz at 1 kHz
Low power consumption: 550 µA (typical)
High-gain bandwidth: 8 MHz
Operating supply voltage from 2.5 V to 5.5 V
Low input bias current: 1 pA (typical)
Low input offset voltage: 1.5 mV (maximum)
Low offset voltage drift: ±0.5 µV/°C (typical)
ESD internal protection: ±4-kV human-body model
(HBM)
Extended temperature range: –40°C to 125°C
2 Applications
•
•
•
•
•
•
•
•
•
•
•
Battery-powered applications
Motor control
Power modules
HVAC: heating, ventilating, and air conditioning
Washing machines
Refrigerators
Medical instrumentation
Active filters
Sensor signal conditioning
Audio receiver
Automotive infotainment
The robust design of the TSV91x provides ease-ofuse to the circuit designer. Features include a unitygain stable, integrated RFI-EMI rejection filter, no
phase reversal in overdrive condition, and high
electrostatic discharge (ESD) protection (4-kV HBV).
Device Information(1)
PART NUMBER
TSV911
TSV912
TSV914
PACKAGE
BODY SIZE (NOM)
SOT-23 (5)
1.60 mm × 2.90 mm
SC70 (5)
1.25 mm × 2.00 mm
SOIC (8)
3.91 mm × 4.90 mm
WSON (8)
2.00 mm × 2.00 mm
SOT-23 (8)
1.60 mm × 2.90 mm
SOIC (14)
8.65 mm × 3.91 mm
TSSOP (14)
4.40 mm × 5.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Small-Signal Overshoot vs Load Capacitance
Low-Side Motor Control
60
VBUS
ILOAD
ZLOAD
5V
+
VOUT
TSV91x
VSHUNT
RSHUNT
0.1
RF
165 k
Overshoot (%)
50
40
30
20
10
Overshoot+
Overshoot-
0
RG
3.4 k
0
50
100
150
200
Capacitive Load (pF)
250
300
C025
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TSV911, TSV912, TSV914
SBOS878D – JULY 2017 – REVISED OCTOBER 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
4
5
8
7.1
7.2
7.3
7.4
7.5
7.6
7.7
Absolute Maximum Ratings ...................................... 8
ESD Ratings.............................................................. 8
Recommended Operating Conditions....................... 8
Thermal Information: TSV911................................... 8
Thermal Information: TSV912................................... 9
Thermal Information: TSV914................................... 9
Electrical Characteristics: VS (Total Supply Voltage) =
(V+) – (V–) = 2.5 V to 5.5 V ..................................... 10
7.8 Typical Characteristics ............................................ 12
8
Detailed Description ............................................ 18
8.1 Overview ................................................................. 18
8.2 Functional Block Diagram ....................................... 18
8.3 Feature Description................................................. 19
8.4 Device Functional Modes........................................ 19
9
Application and Implementation ........................ 20
9.1 Application Information............................................ 20
9.2 Typical Application .................................................. 20
10 Power Supply Recommendations ..................... 22
10.1 Input and ESD Protection ..................................... 22
11 Layout................................................................... 23
11.1 Layout Guidelines ................................................. 23
11.2 Layout Example .................................................... 23
12 Device and Documentation Support ................. 24
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
24
24
24
24
24
24
24
13 Mechanical, Packaging, and Orderable
Information ........................................................... 24
4 Revision History
Changes from Revision C (January 2019) to Revision D
•
Page
Added SOT-23 (8) (DDF) package information to data sheet................................................................................................ 1
Changes from Revision B (April 2018) to Revision C
Page
•
Deleted preview notations for TSV911IDBV ......................................................................................................................... 1
•
Added SC70 package information to Device Information table.............................................................................................. 1
•
Deleted package preview notation from TSV911 DBV (SOT-23) package ........................................................................... 4
•
Added DCK (SC70) package information to Device Comparison Table ................................................................................ 4
•
Deleted TSV911 DBV (SOT-23) package preview notation from Pin Configuration and Functions section.......................... 5
•
Added TSV911 DCK (SC70) package drawing and pin functions ........................................................................................ 5
•
Added TSV911 DBV and DCK package thermal information................................................................................................. 8
Changes from Revision A (October 2017) to Revision B
Page
•
Changed TSV914 14-pin TSSOP package from preview to production data in Device Information table ............................ 1
•
Deleted package preview note from 8-pin WSON package in Device Information table ...................................................... 1
•
Deleted package preview note from PW (TSSOP) package from Device Comparison table ............................................... 4
•
Deleted package preview note from DSG (WSON) package from Device Comparison table ............................................... 4
•
Deleted package preview note from TSV912 DSG package pinout drawing in Pin Configuration and Functions section .... 6
•
Added DGK (VSSOP) thermal information to Thermal Information: TSV912 table .............................................................. 9
•
Deleted package preview note to TSV914 PW (TSSOP) package Thermal Information table.............................................. 9
•
Added PW (TSSOP) package information to Thermal Information: TSV914 table ................................................................ 9
•
Changed TSV914 PW (TSSOP) junction-to-ambient thermal resistance from 135.8°C/W to 205.8°C/W ............................. 9
•
Changed TSV914 PW (TSSOP) junction-to-case(top) thermal resistance from 64°C/W to 106.7°C/W................................ 9
•
Changed TSV914 PW (TSSOP) junction-to-board thermal resistance from 79°C/W to 133.9°C/W...................................... 9
2
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Product Folder Links: TSV911 TSV912 TSV914
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SBOS878D – JULY 2017 – REVISED OCTOBER 2019
•
Changed TSV914 PW (TSSOP) junction-to-top characterization parameter from 15.7°C/W to 34.4°C/W ........................... 9
•
Changed TSV914 PW (TSSOP) junction-to-board characterization parameter from 78.4°C/W to 132.6°C/W ..................... 9
Changes from Original (July 2017) to Revision A
Page
•
Changed TSV914 14-pin SOIC package from preview to production data in Device Information table................................ 1
•
Deleted TSV911 SC70, SOT-553 and SOIC packages from Device Information table ........................................................ 1
•
Deleted TSV912 VSSOP packages from Device Information table ...................................................................................... 1
•
Deleted TSV911 SC70 and SOIC packages from pinout drawings and Pin Functions table ................................................ 5
•
Deleted TSV912 DGK and DGS packages from pinout images Pin Functions table ............................................................ 6
•
Deleted package preview note from TSV914 pinout drawing and Pin Functions table ........................................................ 7
•
Added TSV914 Thermal Information table ............................................................................................................................ 9
•
Added 2017 copyright notice to Figure 35............................................................................................................................ 20
Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: TSV911 TSV912 TSV914
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TSV911, TSV912, TSV914
SBOS878D – JULY 2017 – REVISED OCTOBER 2019
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5 Device Comparison Table
PACKAGE LEADS
NO. OF
CHANNELS
DBV
DCK
D
DSG
PW
DDF
TSV911
1
5
5
—
—
—
—
TSV912
2
—
—
8
8
—
8
TSV914
4
—
—
14
—
14
—
DEVICE
4
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Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: TSV911 TSV912 TSV914
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SBOS878D – JULY 2017 – REVISED OCTOBER 2019
6 Pin Configuration and Functions
TSV911 DBV Package
5-Pin SOT-23
Top View
OUT
1
V-
2
+IN
3
TSV911 DCK Package
5-Pin SC70
Top View
5
V+
4
-IN
IN+
1
V±
2
IN±
3
5
V+
4
OUT
Not to scale
Pin Functions: TSV911
PIN
NAME
NO.
I/O
DBV (SOT-23)
DCK (SC70)
–IN
4
3
+IN
3
OUT
1
V–
V+
DESCRIPTION
I
Inverting input
1
I
Noninverting input
4
O
Output
2
2
—
Negative (lowest) supply or ground (for single-supply operation)
5
5
—
Positive (highest) supply
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Product Folder Links: TSV911 TSV912 TSV914
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SBOS878D – JULY 2017 – REVISED OCTOBER 2019
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TSV912 D, DGK, DDF Packages
8-Pin SOIC, VSSOP
Top View
OUT A
1
8
V+
-IN A
2
7
OUT B
+IN A
3
6
V-
4
5
TSV912 DSG Package (1)
8-Pin WSON With Exposed Thermal Pad
Top View
OUT A
1
-IN B
-IN A
2
+IN B
+IN A
3
V-
4
(1)
Exposed
Thermal
Die Pad
on
Underside(1)
8
V+
7
OUT B
6
-IN B
5
+IN B
Connect exposed thermal pad to V–. See
Packages with an Exposed Thermal Pad
section for more information.
Pin Functions: TSV912
PIN
I/O
DESCRIPTION
NAME
NO.
–IN A
2
I
Inverting input, channel A
+IN A
3
I
Noninverting input, channel A
–IN B
6
I
Inverting input, channel B
+IN B
5
I
Noninverting input, channel B
OUT A
1
O
Output, channel A
OUT B
7
O
Output, channel B
V–
4
—
Negative (lowest) supply or ground (for single-supply operation)
V+
8
—
Positive (highest) supply
6
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Product Folder Links: TSV911 TSV912 TSV914
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SBOS878D – JULY 2017 – REVISED OCTOBER 2019
TSV914 D, PW Packages
14-Pin SOIC, TSSOP
Top View
14
OUT D
13
-IN D
3
12
+IN D
V+
4
11
V-
+IN B
5
10
+IN C
-IN B
6
9
-IN C
OUT B
7
8
OUT C
OUT A
1
-IN A
2
+IN A
A
B
D
C
Pin Functions: TSV914
PIN
I/O
DESCRIPTION
NAME
NO.
–IN A
2
I
Inverting input, channel A
+IN A
3
I
Noninverting input, channel A
–IN B
6
I
Inverting input, channel B
+IN B
5
I
Noninverting input, channel B
–IN C
9
I
Inverting input, channel C
+IN C
10
I
Noninverting input, channel C
–IN D
13
I
Inverting input, channel D
+IN D
12
I
Noninverting input, channel D
OUT A
1
O
Output, channel A
OUT B
7
O
Output, channel B
OUT C
8
O
Output, channel C
OUT D
14
O
Output, channel D
V–
11
—
Negative (lowest) supply or ground (for single-supply operation)
V+
4
—
Positive (highest) supply
Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: TSV911 TSV912 TSV914
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SBOS878D – JULY 2017 – REVISED OCTOBER 2019
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature (unless otherwise noted) (1)
MIN
MAX
UNIT
6
V
Supply voltage
Voltage (2)
Signal input pins
Common-mode
Current (2)
Output short-circuit
(V–) – 0.5
(V+) + 0.5
Differential
(V+) – (V–) + 0.2
–10
(3)
10
mA
–40
Junction, TJ
Storage, Tstg
(1)
(2)
(3)
mA
Continuous
Specified, TA
V
–65
125
°C
150
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Input pins are diode-clamped to the power-supply rails. Current limit input signals that can swing more than 0.5 V beyond the supply
rails to 10 mA or less.
Short-circuit to ground, one amplifier per package.
7.2 ESD Ratings
over operating free-air temperature range (unless otherwise noted)
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±4000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VS
MAX
UNIT
Supply voltage
2.5
5.5
V
Specified temperature
–40
125
°C
7.4 Thermal Information: TSV911
TSV911
THERMAL METRIC (1)
DBV (SOT-23)
DCK (SC70)
5 PINS
5 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
221.7
263.3
°C/W
RθJC(top)
Junction-to-case(top) thermal resistance
144.7
75.5
°C/W
RθJB
Junction-to-board thermal resistance
49.7
51.0
°C/W
ψJT
Junction-to-top characterization parameter
26.1
1.0
°C/W
ψJB
Junction-to-board characterization parameter
49.0
50.3
°C/W
(1)
8
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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SBOS878D – JULY 2017 – REVISED OCTOBER 2019
7.5 Thermal Information: TSV912
TSV912
THERMAL METRIC (1)
D (SOIC)
DGK (VSSOP)
DSG (WSON)
DDF (SOT-23)
8 PINS
8 PINS
8 PINS
8 PINS
UNIT
RθJA
Junction-to-ambient thermal
resistance
157.6
201.2
94.4
184.4
°C/W
RθJC(top)
Junction-to-case(top) thermal
resistance
104.6
85.7
116.5
112.8
°C/W
RθJB
Junction-to-board thermal resistance
99.7
122.9
61.3
99.9
°C/W
ψJT
Junction-to-top characterization
parameter
55.6
21.2
13
18.7
°C/W
ψJB
Junction-to-board characterization
parameter
99.2
121.4
61.7
99.3
°C/W
RθJC(bot)
Junction-to-case(bottom) thermal
resistance
N/A
N/A
34.4
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.6 Thermal Information: TSV914
TSV914
THERMAL METRIC (1)
D (SOIC)
PW (TSSOP)
14 PINS
14 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
106.9
205.8
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
69
106.7
°C/W
RθJB
Junction-to-board thermal resistance
63
133.9
°C/W
ψJT
Junction-to-top characterization parameter
25.9
34.4
°C/W
ψJB
Junction-to-board characterization parameter
62.7
132.6
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: TSV911 TSV912 TSV914
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7.7 Electrical Characteristics: VS (Total Supply Voltage) = (V+) – (V–) = 2.5 V to 5.5 V
at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
±0.3
±1.5
UNIT
OFFSET VOLTAGE
VS = 5 V
VOS
Input offset voltage
dVOS/dT
Drift
VS = 5 V
TA = –40°C to 125°C
PSRR
Power-supply rejection ratio
VS = 2.5 V – 5.5 V, VCM = (V–)
Channel separation, DC
At DC
VS = 5 V
TA = –40°C to 125°C
±3
mV
±0.5
µV/°C
±7
µV/V
100
dB
INPUT VOLTAGE RANGE
VCM
Common-mode voltage range
CMRR
Common-mode rejection ratio
VS = 2.5 V to 5.5 V
(V–) – 0.1
(V+) + 0.1
VS = 5.5 V
(V–) – 0.1 V < VCM < (V+) – 1.4 V
TA = –40°C to 125°C
80
103
VS = 5.5 V, VCM = –0.1 V to 5.6 V
TA = –40°C to 125°C
57
87
VS = 2.5 V, (V–) – 0.1 V < VCM < (V+) – 1.4 V
TA = –40°C to 125°C
88
VS = 2.5 V, VCM = –0.1 V to 1.9 V
TA = –40°C to 125°C
81
V
dB
INPUT BIAS CURRENT
IB
Input bias current
IOS
Input offset current
±1
pA
±0.05
pA
4.77
µVPP
NOISE
En
Input voltage noise (peak-to-peak)
en
Input voltage noise density
in
Input current noise density
VS = 5 V, f = 0.1 Hz to 10 Hz
VS = 5 V, f = 10 kHz
12
VS = 5 V, f = 1 kHz
18
f = 1 kHz
10
fA/√Hz
nV/√Hz
INPUT CAPACITANCE
CID
Differential
2
pF
CIC
Common-mode
4
pF
OPEN-LOOP GAIN
VS = 2.5 V, (V–) + 0.04 V < VO < (V+) – 0.04 V
RL = 10 kΩ
AOL
Open-loop voltage gain
100
VS = 5.5 V, (V–) + 0.05 V < VO < (V+) – 0.05 V
RL = 10 kΩ
104
130
dB
VS = 2.5 V, (V–) + 0.06 V < VO < (V+) – 0.06 V
RL = 2 kΩ
100
VS = 5.5 V, (V–) + 0.15 V < VO < (V+) – 0.15 V
RL = 2 kΩ
130
FREQUENCY RESPONSE
GBP
Gain bandwidth product
VS = 5 V, G = 1
8
MHz
φm
Phase margin
VS = 5 V, G = 1
55
°
SR
Slew rate
VS = 5 V, G = 1
RL = 2 kΩ
CL = 100 pF
4.5
V/µs
Settling time
To 0.1%, VS = 5 V, 2-V step , G = 1
CL = 100 pF
0.5
tS
µs
To 0.01%, VS = 5 V, 2-V step , G = 1
CL = 100 pF
1
tOR
Overload recovery time
VS = 5 V, VIN × gain > VS
THD + N
Total harmonic distortion + noise (1)
VS = 5 V, VO = 1 VRMS, G = 1, f = 1 kHz
0.2
µs
Voltage output swing from supply
rails
VS = 5.5 V, RL = 10 kΩ
15
VS = 5.5 V, RL = 2 kΩ
50
0.0008%
OUTPUT
VO
(1)
10
mV
Third-order filter; bandwidth = 80 kHz at –3 dB.
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Electrical Characteristics: VS (Total Supply Voltage) = (V+) – (V–) = 2.5 V to 5.5 V (continued)
at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ISC
Short-circuit current
VS = 5 V
±50
mA
ZO
Open-loop output impedance
VS = 5 V, f = 10 MHz
100
Ω
VS = 5.5 V, IO = 0 mA
550
POWER SUPPLY
IQ
Quiescent current per amplifier
VS = 5.5 V, IO = 0 mA TA = –40°C to 125°C
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750
1100
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µA
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7.8 Typical Characteristics
at TA = 25°C, VS = 5.5 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
35
50
30
40
Population (%)
Population (%)
25
20
15
30
20
10
Offset Voltage (µV)
2.8
2.4
2
1.6
1.2
0.8
0
0
1500
1250
1000
750
500
0
250
-250
-500
-750
-1000
-1250
-1500
0
0.4
10
5
Offset Voltage Drift (µV/C)
C001
C002
TA = –40°C to 125°C
Figure 2. Offset Voltage Drift Distribution
2500
400
2000
300
1500
Offset Voltage (µV)
Offset Voltage (µV)
Figure 1. Offset Voltage Production Distribution
500
200
100
0
±100
±200
1000
500
0
±500
±1000
±300
±1500
±400
±2000
±500
±2500
±50
±25
0
25
50
75
100
125
Temperature (ƒC)
150
-4
-3
-2
-1
0
1
2
3
4
Input Common Mode Voltage (V)
C003
C005
V+ = 2.75 V, V– = –2.75 V
Figure 4. Offset Voltage vs Common-Mode Voltage
120
Open Loop Voltage Gain (dB)
Offset Voltage (µV)
1000
500
0
±500
±1000
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Supply Voltage (V)
5.5
100
210
Gain
Phase 180
80
150
60
120
40
90
20
60
0
30
-20
100
0
1k
10k
100k
Frequency (Hz)
C004
VS = 2.5 V to 5.5 V
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1M
10M
C006
CL = 10 pF
Figure 5. Offset Voltage vs Power Supply
12
Phase Margin (q)
Figure 3. Offset Voltage vs Temperature
Figure 6. Open-Loop Gain and Phase vs Frequency
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Typical Characteristics (continued)
at TA = 25°C, VS = 5.5 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
Input Bias Current and offset current (pA)
Closed Loop Voltage Gain (dB)
40
30
20
10
0
-10
-20
G = +1
G = +10
G = -1
-30
-40
1k
10k
100k
Frequency (Hz)
1M
250
IBN
200
IBP
IOS
150
100
50
0
±50
±50
10M
25
50
75
100
125
Temperature (ƒC)
Figure 7. Closed-Loop Gain vs Frequency
C008
Figure 8. Input Bias Current vs Temperature
3
120
2
PSRRPSRR+
CMRR
100
125ƒC
1
-40ƒC
85ƒC
PSRR and CMRR (dB)
Output Voltage (V)
0
±25
C007
25ƒC
0
25ƒC
85ƒC
±1
-40ƒC
125ƒC
±2
80
60
40
20
±3
10
20
30
40
50
60
Output Current (mA)
C009
0
1k
10k
100k
Frequency (Hz)
V+ = 2.75 V, V– = –2.75 V
Figure 9. Output Voltage Swing vs Output Current
1M
10M
C011
Figure 10. CMRR and PSRR vs Frequency
(Referred to Input)
10
55
9
8
CMRR (µV/V)
CMRR (µV/V)
50
45
40
7
6
5
4
3
35
2
1
30
±50
±25
0
25
50
75
100
Temperature (ƒC)
VS = 5.5 V
VCM = (V–) – 0.1 V to
(V+) + 0.1 V
TA= –40°C to 125°C
125
±50
±25
RL= 10 kΩ
Figure 11. CMRR vs Temperature
0
25
50
75
100
125
Temperature (ƒC)
C012
VCM = (V–) –0.1 V to
(V+) –1.4 V
TA= –40°C to 125°C
VS = 5.5 V
150
C016
RL= 10 kΩ
Figure 12. CMRR vs Temperature
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Typical Characteristics (continued)
at TA = 25°C, VS = 5.5 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
10
Voltage (1µV/div)
PSRR (µV/V)
9
8
7
6
5
±50
0
±25
25
50
75
100
Time (1s/div)
125
Temperature (ƒC)
C014
C013
VS = 2.5 V to 5.5 V
VS = 2.5 V to 5.5 V
Figure 14. 0.1-Hz to 10-Hz Input Voltage Noise
-90
100
-95
80
-100
THD + N (dB)
Input Voltage Noise
Spectral Density (nV/—Hz)
Figure 13. PSRR vs Temperature
120
60
40
-110
-115
20
0
10
-105
100
1k
Frequency (Hz)
10k
100k
-120
100
1k
Frequency (Hz)
C015
VS = 5.5 V
G=1
±40
±40
±60
±60
±80
0.01
0.1
VCM = 2.5 V
BW = 80 kHz
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0.01
0.1
1
Output Voltage Amplitude (VRMS)
C018
RL = 2 kΩ
f = 1 kHz
Figure 17. THD + N vs Amplitude
14
±120
0.001
1
Output Voltage Amplitude (VRMS)
VS = 5.5 V
G=1
±80
±100
±100
±120
0.001
C017
RL = 2 kΩ
BW = 80 kHz
Figure 16. THD + N vs Frequency
THD + N (dB)
THD + N (dB)
Figure 15. Input Voltage Noise Spectral Density vs
Frequency
VCM = 2.5 V
VOUT = 0.5 VRMS
10k
VS = 5.5 V
G = –1
VCM = 2.5 V
BW = 80 kHz
C019
RL = 2 kΩ
f = 1 kHz
Figure 18. THD + N vs Amplitude
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Typical Characteristics (continued)
at TA = 25°C, VS = 5.5 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
800
600
Quiescent Current (µA)
Quiescent current (µA)
700
580
560
540
520
600
500
400
300
200
100
0
500
1.5
2
2.5
3
3.5
4
4.5
5
Supply Voltage (V)
±50
5.5
0
25
50
75
100
125
Temperature (ƒC)
Figure 19. Quiescent Current vs Supply Voltage
C021
Figure 20. Quiescent Current vs Temperature
200
60
50
160
Overshoot (%)
Open Loop Output Impedance (:)
±25
C020
120
80
40
30
20
10
Overshoot+
40
Overshoot0
0
0
10k
100k
1M
Frequency (Hz)
50
Figure 21. Open-Loop Output Impedance vs Frequency
150
200
250
Capacitive Load (pF)
10M
C024
100
V+ = 2.75 V
RL = 10 kΩ
300
C025
V– = –2.75 V
VOUT step = 100 mVp-p
G = 1 V/V
Figure 22. Small-Signal Overshoot vs Load Capacitance
60
Voltage (1V/div)
Overshoot (%)
50
40
30
20
10
Input
Overshoot(+)
Output
Overshoot(-)
0
0
50
100
150
200
Capacitive Load (pF)
V+ = 2.75 V
G = –1 V/V
V– = –2.75 V
VOUT step = 100 mVp-p
250
Time (200 µs/div)
300
C026
RL = 10 kΩ
Figure 23. Small-Signal Overshoot vs Load Capacitance
C036
V+ = 2.75 V, V– = –2.75 V
Figure 24. No Phase Reversal
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Typical Characteristics (continued)
at TA = 25°C, VS = 5.5 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
Input
Voltage (2 V/V)
Voltage (20 mV/div)
Output
INPUT
OUTPUT
Time (1 µs/div)
Time (0.1µs/div)
C028
C030
V+ = 2.75 V, V– = –2.75 V, G = –10 V/V
V+ = 2.75 V, V– = –2.75 V, G = 1 V/V
Figure 25. Overload Recovery
Figure 26. Small-Signal Step Response
Voltage (1 V/div)
Short Circuit Current Limit (mA)
80
Input
Output
60
40
20
Sinking
0
Sourcing
±20
±40
±60
±80
Time (1 µs/div)
±50
±25
V+ = 2.75 V
G = 1 V/V
V– = –2.75 V
25
50
75
100
125
C034
CL = 100 pF
Figure 27. Large-Signal Step Response
Figure 28. Short-Circuit Current vs Temperature
120
-20
Channel Seperation (dB)
140
0
100
EMIRR (dB)
0
Temperature (ƒC)
C031
80
60
40
20
-40
-60
-80
-100
-120
0
10M
100M
1G
Frequency (Hz)
C041
-140
100
1k
PRF = –10 dBm
10k
100k
Frequency (Hz)
1M
10M
C038
V+ = 2.75 V, V– = –2.75 V
Figure 29. Electromagnetic Interference Rejection Ratio
Referred to Noninverting Input (EMIRR+) vs Frequency
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Figure 30. Channel Separation vs Frequency
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Typical Characteristics (continued)
at TA = 25°C, VS = 5.5 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
200
Open Loop Voltage Gain (dB)
90
Phase Margin (degrees)
75
60
45
30
15
160
120
80
40
0
0
0
10
20
30
40
50
60
70
80
90
Capacitive Load (pF)
0
100
0.5
1
VS = 5.5 V
2
2.5
3
3.5
4
4.5
5
5.5
C023
VS = 5.5 V
Figure 31. Phase Margin vs Capacitive Load
Figure 32. Open Loop Voltage Gain vs Output Voltage
100
100
75
75
50
50
Output voltage (mV)
Output Voltage (mV)
1.5
Output Voltage (V)
C037
25
0
±25
±50
25
0
-25
-50
-75
-100
±75
-125
-150
±100
0
0.3
0.6
0
0.9
Settling time (µs)
Figure 33. Large Signal Settling Time (Positive)
0.3
0.6
0.9
1.2
Settling time (µs)
C032
1.5
C033
Figure 34. Large Signal Settling Time (Negative)
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8 Detailed Description
8.1 Overview
The TSV91x series is a family of low-power, rail-to-rail input and output op amps. These devices operate from
2.5 V to 5.5 V, are unity-gain stable, and are designed for a wide range of general-purpose applications. The
input common-mode voltage range includes both rails and allows the TSV91x series to be used in virtually any
single-supply application. Rail-to-rail input and output swing significantly increases dynamic range, especially in
low-supply applications and are designed for driving sampling analog-to-digital converters (ADCs).
8.2 Functional Block Diagram
V+
Reference
Current
V
IN+
V
INÛ
V
Class AB
Control
Circuitry
BIAS1
V
O
V
BIAS2
VÛ
(Ground)
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8.3 Feature Description
8.3.1 Rail-to-Rail Input
The input common-mode voltage range of the TSV91x family extends 100 mV beyond the supply rails for the full
supply voltage range of 2.5 V to 5.5 V. This performance is achieved with a complementary input stage: an Nchannel input differential pair in parallel with a P-channel differential pair, as shown in the Functional Block
Diagram. The N-channel pair is active for input voltages close to the positive rail, typically (V+) – 1.4 V to 100 mV
above the positive supply, whereas the P-channel pair is active for inputs from 100 mV below the negative
supply to approximately (V+) – 1.4 V. There is a small transition region, typically (V+) – 1.2 V to (V+) – 1 V, in
which both pairs are on. This 200-mV transition region can vary up to 200 mV with process variation. Thus, the
transition region (with both stages on) can range from (V+) – 1.4 V to (V+) – 1.2 V on the low end, and up to
(V+) – 1 V to (V+) – 0.8 V on the high end. Within this transition region, PSRR, CMRR, offset voltage, offset drift,
and THD can degrade compared to device operation outside this region.
8.3.2 Rail-to-Rail Output
Designed as a low-power, low-voltage operational amplifier, the TSV91x series delivers a robust output drive
capability. A class AB output stage with common-source transistors achieves full rail-to-rail output swing
capability. For resistive loads of 10 kΩ, the output swings to within 15 mV of either supply rail, regardless of the
applied power-supply voltage. Different load conditions change the ability of the amplifier to swing close to the
rails.
8.3.3 Packages with an Exposed Thermal Pad
The TSV91x family is available in packages such as the WSON-8 (DSG) which feature an exposed thermal pad.
Inside the package, the die is attached to this thermal pad using an electrically conductive compound. For this
reason, when using a package with an exposed thermal pad, the thermal pad must either be connected to V– or
left floating. Attaching the thermal pad to a potential other then V– is not allowed, and the performance of the
device is not assured when doing so.
8.3.4 Overload Recovery
Overload recovery is defined as the time required for the operational amplifier output to recover from a saturated
state to a linear state. The output devices of the operational amplifier enter a saturation region when the output
voltage exceeds the rated operating voltage, because of the high input voltage or the high gain. After the device
enters the saturation region, the charge carriers in the output devices require time to return to the linear state.
After the charge carriers return to the linear state, the device begins to slew at the specified slew rate. Therefore,
the propagation delay (in case of an overload condition) is the sum of the overload recovery time and the slew
time. The overload recovery time for the TSV91x series is approximately 200 ns.
8.4 Device Functional Modes
The TSV91x family has a single functional mode. These devices are powered on as long as the power-supply
voltage is between 2.5 V (±1.25 V) and 5.5 V (±2.75 V).
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TSV91x series features 8-MHz bandwidth and 4.5-V/µs slew rate with only 550 µA of supply current per
channel, providing good AC performance at low power consumption. DC applications are well served with a low
input noise voltage of 18 nV / √Hz at 1 kHz, low input bias current, and a typical input offset voltage of 0.3 mV.
9.2 Typical Application
Figure 35 shows the TSV91x configured in a low-side, motor-control application.
VBUS
ILOAD
ZLOAD
5V
+
VOUT
TSV91x
VSHUNT
RSHUNT
0.1
RF
165 k
RG
3.4 k
Figure 35. TSV91x in a Low-Side, Motor-Control Application
9.2.1 Design Requirements
The design requirements for this design are:
• Load current: 0 A to 1 A
• Output voltage: 4.95 V
• Maximum shunt voltage: 100 mV
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Typical Application (continued)
9.2.2 Detailed Design Procedure
The transfer function of the circuit in Figure 35 is shown in Equation 1.
VOUT ILOAD u RSHUNT u Gain
(1)
The load current (ILOAD) produces a voltage drop across the shunt resistor (RSHUNT). The load current is set from
0 A to 1 A. To keep the shunt voltage below 100 mV at maximum load current, the largest shunt resistor is
defined using Equation 2.
VSHUNT _ MAX 100mV
RSHUNT
100m:
ILOAD _ MAX
1A
(2)
Using Equation 2, RSHUNT is 100 mΩ. The voltage drop produced by ILOAD and RSHUNT is amplified by the TSV91x
to produce an output voltage of approximately 0 V to 4.95 V. The gain required by the TSV91x to produce the
necessary output voltage is calculated using Equation 3:
Gain
VOUT _ MAX
VIN _ MAX
VOUT _ MIN
VIN _ MIN
(3)
Using Equation 3, the required gain is calculated to be 49.5 V/V, which is set with resistors RF and RG.
Equation 4 is used to size the resistors, RF and RG, to set the gain of the TSV91x to 49.5 V/V.
RF
Gain 1
RG
(4)
Selecting RF as 165 kΩ and RG as 3.4 kΩ provides a combination that equals roughly 49.5 V/V. Figure 36 shows
the measured transfer function of the circuit shown in Figure 35.
9.2.3 Application Curve
5
Output (V)
4
3
2
1
0
0
0.2
0.4
0.6
0.8
ILOAD (A)
1
C219
Figure 36. Low-Side, Current-Sense, Transfer Function
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10 Power Supply Recommendations
The TSV91x series is specified for operation from 2.5 V to 5.5 V (±1.25 V to ±2.75 V); many specifications apply
from –40°C to 125°C. The Typical Characteristics section presents parameters that can exhibit significant
variance with regard to operating voltage or temperature.
CAUTION
Supply voltages larger than 6 V can permanently damage the device; see the Absolute
Maximum Ratings table.
Place 0.1-µF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or highimpedance power supplies. For more detailed information on bypass capacitor placement, see the Layout
Example section.
10.1 Input and ESD Protection
The TSV91x series incorporates internal ESD protection circuits on all pins. For input and output pins, this
protection consists of current-steering diodes connected between the input and power-supply pins. These ESD
protection diodes provide in-circuit, input overdrive protection, as long as the current is limited to 10-mA, as
stated in the Absolute Maximum Ratings table. Figure 37 shows how a series input resistor is added to the driven
input to limit the input current. The added resistor contributes thermal noise at the amplifier input and the value
must be kept to a minimum in noise-sensitive applications.
V+
IOVERLOAD
10-mA maximum
Device
VOUT
VIN
5 kW
Figure 37. Input Current Protection
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11 Layout
11.1 Layout Guidelines
For best operational performance of the device, use good printed-circuit board (PCB) layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and of op amp
itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power
sources local to the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for singlesupply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground
planes. A ground plane helps distribute heat and reduces electromagnetic interference (EMI) noise
pickup. Make sure to physically separate digital and analog grounds, paying attention to the flow of the
ground current. For more detailed information, see Circuit Board Layout Techniques.
• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much
better as opposed to in parallel with the noisy trace.
• Place the external components as close to the device as possible. As shown in Figure 39, keeping RF
and RG close to the inverting input minimizes parasitic capacitance on the inverting input.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly
reduce leakage currents from nearby traces that are at different potentials.
• Cleaning the PCB following board assembly is recommended for best performance.
• Any precision integrated circuit can experience performance shifts resulting from moisture ingress into the
plastic package. Following any aqueous PCB cleaning process, baking the PCB assembly is
recommended to remove moisture introduced into the device packaging during the cleaning process. A
low-temperature, post-cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.
11.2 Layout Example
+
VIN A
+
VIN B
VOUT A
RG
VOUT B
RG
RF
RF
Figure 38. Schematic Representation for Figure 39
Place components
close to device and to
each other to reduce
parasitic errors.
OUT A
VS+
OUT A
V+
-IN A
OUT B
+IN A
-IN B
Use low-ESR,
ceramic bypass
capacitor. Place as
close to the device
as possible.
GND
RF
OUT B
GND
RF
RG
VIN A
GND
RG
V±
Use low-ESR,
ceramic bypass
capacitor. Place as
close to the device
as possible.
GND
VS±
+IN B
Ground (GND) plane on another layer
VIN B
Keep input traces short
and run the input traces
as far away from
the supply lines
as possible.
Figure 39. Layout Example
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
Texas Instruments, Circuit Board Layout Techniques, SLOA089
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
Table 1. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TSV911
Click here
Click here
Click here
Click here
Click here
TSV912
Click here
Click here
Click here
Click here
Click here
TSV914
Click here
Click here
Click here
Click here
Click here
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Community Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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28-Sep-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TSV911AIDBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
1U2F
TSV911AIDCKR
ACTIVE
SC70
DCK
5
3000
RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 125
1EK
TSV912AIDDFR
ACTIVE
SOT-23-THIN
DDF
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
T12A
TSV912AIDGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
T912
TSV912AIDGKT
ACTIVE
VSSOP
DGK
8
250
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
T912
TSV912AIDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 125
TSV912
TSV912AIDSGR
ACTIVE
WSON
DSG
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
T912
TSV912AIDSGT
ACTIVE
WSON
DSG
8
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
T912
TSV912AIPWR
ACTIVE
TSSOP
PW
8
2000
RoHS & Green
NIPDAU | SN
Level-2-260C-1 YEAR
-40 to 125
TSV912
TSV914AIDR
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TSV914AD
TSV914AIPWR
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 125
TSV914
TSV914AIPWT
ACTIVE
TSSOP
PW
14
250
RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 125
TSV914
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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