TSW1250EVM

User's Guide SLOU260F – April 2009 – Revised January 2012 TSW1250EVM: High-Speed LVDS Deserializer and Analysis System 1 2 3 4 5 6 7 Contents Introduction .................................................................................................................. 2 Functionality ................................................................................................................. 2 Hardware Configurations ................................................................................................... 2 3.1 Power Connections ................................................................................................ 3 3.2 Switches and Jumpers ............................................................................................ 4 3.3 LEDs ................................................................................................................. 6 3.4 Input Connections .................................................................................................. 7 3.5 Output Connections ................................................................................................ 8 3.6 USB I/O Connection ............................................................................................... 9 Software Installation ........................................................................................................ 9 Graphics User Interface (GUI) ............................................................................................ 9 5.1 Toolbar ............................................................................................................. 10 5.2 Message Window ................................................................................................. 12 5.3 Device-Specific Selections ...................................................................................... 13 5.4 Test Parameters .................................................................................................. 13 5.5 Central Pane Display ............................................................................................. 13 Schematics and Bill of Materials ........................................................................................ 17 6.1 Schematics ........................................................................................................ 17 6.2 Bill of Materials .................................................................................................... 22 Circuit Board Layout and Layer Stackup ............................................................................... 24 List of Figures 1 Position of Power Connections............................................................................................ 3 2 Position of Switches and Jumpers ........................................................................................ 5 3 Position of LEDs 4 Position of Input, Output, and USB Connections ....................................................................... 7 5 Pinout of Header Posts for Parallel Output Data 6 TSW1250 GUI 7 8 9 10 11 12 13 14 15 16 17 ............................................................................................................ ....................................................................... ............................................................................................................. Time Domain Test ......................................................................................................... Single FFT Test ............................................................................................................ Schematic Diagram Page 1 .............................................................................................. Schematic Diagram Page 2 .............................................................................................. Schematic Diagram Page 3 .............................................................................................. Schematic Diagram Page 4 .............................................................................................. Schematic Diagram Page 5 .............................................................................................. TSW1250C Layout Top Layer – Signal ................................................................................ TSW1250C Layout Layer Two – GND1 ................................................................................ TSW1250C Layout Layer 3 – PWR1 ................................................................................... TSW1250C Layout Layer 4 – GND2 .................................................................................... 6 8 10 14 16 17 18 19 20 21 24 25 26 27 Windows is a trademark of Microsoft Corporation. SLOU260F – April 2009 – Revised January 2012 Submit Documentation Feedback TSW1250EVM: High-Speed LVDS Deserializer and Analysis System Copyright © 2009–2012, Texas Instruments Incorporated 1 Introduction www.ti.com 18 TSW1250C Layout Layer 5 – Signal .................................................................................... 28 19 TSW1250C Layout Layer 6 – Signal .................................................................................... 29 20 TSW1250C Layout Layer 7 – GND3 .................................................................................... 30 21 TSW1250C Layout Layer 8 – PWR2 ................................................................................... 31 22 TSW1250C Layer 9 – GND4............................................................................................. 32 23 TSW1250C Bottom Layer – Signal 24 ..................................................................................... Circuit Board Stackup ..................................................................................................... 33 34 List of Tables 1 1 Bill of Materials ............................................................................................................ 22 Introduction The Texas Instruments TSW1250 EVM is designed to evaluate the performance of high-speed ADC with serial LVDS output data format. Currently the TSW1250EVM supports the hi-speed ADS52XX series devices and Ultrasound AFE580X series devices from MHR group of Texas Instruments Inc. In the following paragraphs the ADS52XX series devices and AFE58XX series devices from MHR group will be called MHR_ADC for simplification and clearness purpose. The TSW1250 includes a High-Speed LVDS Deserializer and Analysis System which provide a comprehensive set of hardware and user interface software to effectively evaluate the performance of a MHR_ADC. The TSW1250 hardware has a high-speed connector that plugs into the MHR_ADC EVM. TSW1250EVM has FIFO memory sufficient to capture as much as 64K samples of data. A USB connection transfers the captured data to a personal computer for post-processing. The user Interface software controls the hardware of both TSW1250 and displays the FFT and important statistics related to the performance of the MHR_ADC. 2 Functionality The TSW1250EVM connects to MHR_ADC EVM through a Samtec high-speed connector. The data format for the LVDS data is presented in a serialized format, where individual bits of the output data are presented on an LVDS line one bit at a time. The current MHR_ADC data is serialized onto a single LVDS pair at a rate that is 12/14/16 times the sample rate with 12/14/16-bit resolution. A DDR LVDS bit clock is used to strobe the serial data bits and to desterilize the data. An additional clock pair provided at the sample rate of the MHR_ADC identifies the sample-word boundaries in the serial data. A single-bit clock and a single sample-rate clock (frame clock) are used for all of the LVDS data channels. The sample rate is up to 65 MHz. The FPGA firmware for the TSW1250 consists of two major functions: the LVDS interface and the FIFO capture. The LVDS interface code in the FPGA reformats the data into a standard single-ended parallel data word with sample clock. This parallel sample word plus clock is output continuously to header posts on the TSW1250 for capture by a logic analyzer. The TSW1250 FPGA has enough FIFO buffer to capture as much as a 65536-sample record length from the continuous sample data stream coming from the LVDS interface. The TSW1250EVM includes a UART function that can transfer data to and from a USB interface device on the TSW1250 board. The USB interface device on the TSW1250EVM connects to a personal computer (PC) running Windows™ over a standard USB cable. The operation of the FIFO capture logic is controlled by writes from the PC USB port to a register map defined within the FPGA. The user interface software on the PC selects by register operations such things as record length of data to capture, which channel of a MHR_ADC to capture from, and then the user interface software downloads the captured data from the TSW1250 for processing in the form of an FFT or time-domain display. 3 Hardware Configurations In this section, the various portions of the TSW1250EVM hardware are described. 2 TSW1250EVM: High-Speed LVDS Deserializer and Analysis System SLOU260F – April 2009 – Revised January 2012 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated Hardware Configurations www.ti.com 3.1 Power Connections The TSW1250EVM hardware is designed to operate from a single-supply voltage of greater than 6 Vdc. For convenience, two options can supply power to the TSW1250EVM. A bench power supply can supply power to banana jack connections on the TSW1250EVM, or a laptop-style power module that is included with the TSW1250 hardware can supply power. Figure 1 shows the relative position of the power connections on the TSW1250EVM. TSW1250 Selects 5 V Output for J15 (Default) J22 Selects J7 for 6 V Input (Default) Selects J5 for 6 V Input JP8 Ground 6 V I/O +6 V Input J14 J15 J7 Figure 1. Position of Power Connections CAUTION TI recommends that the black banana jack J14 be connected to a bench ground even if the 6-V external power brick is connected to J7. Intermittent loss of the USB connection can sometimes be observed without a good ground from the TSW1250EVM to the bench ground reference. Care must be taken in the selection of the input power supply. One jumper selects whether the 6-V input power comes from the banana jack, or whether it comes from the external power module. Another jumper selects whether to connect the onboard regulated 5 V to the red banana jack for output. If the red banana jack is used to input 6 V from a bench power supply, the onboard regulated 5 V must not be connected to the red banana jack for output at the same time. Doing so causes the onboard 5-V regulator to fail over time. SLOU260F – April 2009 – Revised January 2012 Submit Documentation Feedback TSW1250EVM: High-Speed LVDS Deserializer and Analysis System Copyright © 2009–2012, Texas Instruments Incorporated 3 Hardware Configurations 3.2 3.2.1 www.ti.com Switches and Jumpers Pushbuttons Four pushbutton switches are mounted on the TSW1250EVM. Two pushbutton switches currently have defined functions; two of the switches are reserved for future use. 4 Switches Description SW3 Causes the FPGA to reload its bit file from the FPGA EEPROM. SW4 Causes the FPGA to clear the FIFO storage, but does not clear any of the register settings in the FPGA. Any configuration of the FPGA done through register operations such as setting the UART baud rate will persist after pushing the RESET pushbutton. SW2,SW5 Reserved for future use TSW1250EVM: High-Speed LVDS Deserializer and Analysis System SLOU260F – April 2009 – Revised January 2012 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated Hardware Configurations www.ti.com 3.2.2 Jumpers Jumpers Description J10, J11 Select the bit file to be programmed into the FPGA. Always set as the Figure-3. Other settings are for future development. JP8 Selects the source of the power supply to the TSW1250EVM. Jump Left sides: Select the external 6-V power module through power jack J7. (Default). Jump Right sides: Select an external 6-V bench power supply through the red banana jack J15. J15 is an input for this selection. J22 Jump to connect the onboard regulated clean, low-noise 5 V to the red banana jack J15 as an output. J16 For factory to program the USB EEPROM. Installs always. J17 Disable the 1.2-V power regulator for the FPGA core logic. Always OPEN. J1, J12 JTAG chain. Set is as default. CAUTION It is possible to select the red banana jack J15 as an input to be connected to a 6-V bench supply and at the same time install jumper J22 to connect the regulated 5 V to the red banana jack as an output. However, this causes the 5-V regulator on the TSW1250 to fail over time. SW5 J16 SW3 SW2 SW3 Reset USB EEPROM (Default Shorted) J11 J10 Selects FPGA bit file from EEPROM (Default CFG) JTAG TDI => TDO (Default Shorted) J1 open J17 J12 TSW1250 J22 JP8 Ground 6 V I/O +6V Input Figure 2. Position of Switches and Jumpers SLOU260F – April 2009 – Revised January 2012 Submit Documentation Feedback TSW1250EVM: High-Speed LVDS Deserializer and Analysis System Copyright © 2009–2012, Texas Instruments Incorporated 5 Hardware Configurations 3.3 www.ti.com LEDs Six LEDs are on the TSW1250EVM to indicate the presence of power and the state of the FPGA. See Figure 3. LED D16 illuminates to indicate the presence of a 6-V power supply to the board. D7 Lit when FPGA finishes loading bit file The rest of the LEDs are mainly for internal development reference. ADC D1 Lit after FPGA reset completed DCM D2 Flashes when clock from ADC present USB D3 Lit during USB access D4 Flashes while 200 MHz osc present TSW1250 D16 Lit when 6 V present Ground 6 V I/O 6 V Input Figure 3. Position of LEDs 6 TSW1250EVM: High-Speed LVDS Deserializer and Analysis System SLOU260F – April 2009 – Revised January 2012 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated Hardware Configurations www.ti.com 3.4.1 Input Connections Samtec LVDS Connector J6 ch 4 HEADER POSTS HEADER POSTS CLK GND HEADER POSTS LVDS HEADER POSTS JTAG J21 ch 8 USB 3.4 HEADER POSTS HEADER POSTS LVDS GND CLK TSW1250 6 V Input GND CLK J18 ch 5 HEADER POSTS HEADER POSTS GND 6 V I/O CLK Ground J3 ch 1 Figure 4. Position of Input, Output, and USB Connections Figure 4 illustrates the position of the various input and output connections on the TSW1250EVM. The connection between the TSW1250EVM and the MHR_ADC EVM to be tested is through a 120-pin Samtec connector. Sixteen LVDS data pairs plus two LVDS clock pairs have a defined position in the connector pinout that is common between the TSW1250EVM and MHR_ADCEVMs. The bit clock runs at a higher multiple of the MHR_ADC sample clock and is used to strobe the serial data into the TSW1250EVM and then deserializes the data. A second clock is provided, called the frame clock or FCLK, that runs at the sample rate and is used to delineate the sample boundaries in the serial data stream. There are 16 extra LVDS pairs defined in the connector and routed to the TSW1250EVM FPGA for future expansion. The data direction for the LVDS data pairs is always defined as the MHR_ADC EVM driving the signal through the connector to the TSW1250EVM FPGA, with integrated 100-Ω termination in the FPGA. Five extra CMOS single-ended signals are defined in the Samtec connector that are sourced from the FPGA through the connector to the MHR_ADC EVM. These signals are optionally defined to allow the FPGA (under control of the TSW1250 user interface software) control the SPI serial programming of the MHR_ADC EVMs that support this feature. The supported SPI signals SEN (SPI Enable), SCLK (SPI Clk), SDATA (SPI Data) and SPI Reset and SPI Power Down are sourced by the TSW1250EVM FPGA to allow the TSW1250 user Interface to configure the operational mode of the MHR_ADC under evaluation. The Samtec connectors snap together with no screws or other mechanism to hold the TSW1250EVM and the MHR_ADC EVM together. The TSW1250EVM comes with standoff posts for setting the TSW1250EVM flat on a bench or table. The MHR_ADC EVM has shorter standoff posts so that the TSW1250EVM and MHR_ADC EVM will lay flat on a bench or table and stay snapped together during use. SLOU260F – April 2009 – Revised January 2012 Submit Documentation Feedback TSW1250EVM: High-Speed LVDS Deserializer and Analysis System Copyright © 2009–2012, Texas Instruments Incorporated 7 Hardware Configurations 3.4.2 www.ti.com JTAG Connector The TSW1250EVM includes an industry-standard JTAG connector that loops the JTAG ports of the FPGA and the FPGA EEPROM. Jumpers on the TSW1250EVM allow for either the FPGA or the FPGA EEPROM to be removed from the JTAG chain. The most frequent use for the JTAG connector is to program the TSW1250EVM FPGA. An FPGA programming pod can be purchased inexpensively from Xilinx™ to program the FPGA or the FPGA EEPROM. The FPGA programming pod can be used to load a programming bit file directly into the FPGA for debug and development. However, once the FPGA is power-cycled or programmed by the PROGRAM pushbutton, this loaded FPGA bit file will be lost and the FPGA will revert to the bit file that is stored in the FPGA EEPROM. The FPGA programming pod also can be used to store a new FPGA programming bit file in the FPGA EEPROM so that the TSW1250 can be upgraded as new revisions of FPGA firmware become available. The part number of the Xilinx Platform Cable USB programming pod that can be used to program or upgrade the TSW1250EVM is DLC9G. The programming pod operates from a USB port of a PC and connects directly with the TSW1250 JTAG connector through a ribbon cable supplied with the programming pod. 3.5 Output Connections (This feature is in the process of development) Two ways are available to output the parallel clock and sample data from the TSW1250EVM. The MHR_ADC sample data can be presented as a continuous stream of CMOS single-ended data on output header posts, or a set record length of MHR_ADC parallel data samples can be captured in the TSW1250EVM FIFOs and output to a PC through the USB serial port. The data capture by the FIFOs and TSW1250 user interface is the most convenient way to capture data from an MHR_ADC, but sometimes the continuous stream of data is desirable. For example, an application may require a larger capture depth for an FFT on a million continuous data samples or more. For this, the output header posts are available so that a logic analyzer can be used to capture MHR_ADC data in real time. The pinout of the output data headers is shown in Figure 5. In all cases, the output header is a standard two-row header of square 0.025-inch posts on 0.1-inch centers. One of the two rows of posts are connected to ground down the whole row of posts, whereas the other row of posts are signal. The sample-rate clock is presented on the first post, and after skipping one no-connect post (or three posts for Channel 1) the parallel data bus is presented from the least-significant bit (bit D0) through the most-significant bit. During the test; the selected channel is always exporting the parallel data to the primary header J5. Users can choose any other channel to export to Auxiliary Header J4. GND NC NC D14 D15 D13 D11 D12 D10 D8 D9 D6 D7 D5 D3 D4 D2 D1 D0 NC CLK J5 Primary Header GND NC NC NC NC D13 D12 D11 D10 D8 D9 D6 D7 D5 D4 D3 D2 D1 D0 NC CLK J4 Auxiliary Header Figure 5. Pinout of Header Posts for Parallel Output Data 8 TSW1250EVM: High-Speed LVDS Deserializer and Analysis System SLOU260F – April 2009 – Revised January 2012 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated Software Installation www.ti.com 3.6 USB I/O Connection Control of the TSW1250EVM is through an USB connection to a PC running Windows operating system. For the computer, the drivers needed to access the USB port are included on the TSW1250 are installed during the installation process. The USB is accessed as a virtual communication port (VCP) and shows up in the Hardware Device Manager as TSW1250. On the TSW1250EVM, the USB port acts as a bridge to UART control of the FPGA. Control of the FPGA is managed by reads and writes to a register map of control registers defined in the design of the FPGA. Normally, register writes from the TSW1250 user interface software sets up the mode of operation of the FPGA. These register writes define such things as the depth of FIFO to use for data capture or from which channel of a MHR_ADC to capture data. Then, a single register access triggers the filling of the capture FIFOs. Immediately after the capture FIFOs have captured the desired amount of data, the FIFO data is streamed back up the USB connection to the TSW1250 user interface software. The UART data rate between the FPGA and the USB port can be set to 115K, 230K, or 460K baud. On first connection of the USB port to a computer, the Microsoft Found New Hardware Wizard appears. Follow the dialog box prompts as covered in the Software Installation section of this User’s Guide. 4 Software Installation The TSW1250EVM GUI (SLOC231) can be downloaded from the TI Web site. Open the "Read me first.pdf" follow the directions to install the GUI and drivers. 5 Graphics User Interface (GUI) TSW1250 provides a GUI for easier control of the EVM and the device under test. When the TSW1250 GUI is started, the screen of Figure 6 appears. Five groups comprise the GUI. 1. Toolbar 2. Message Window 3. Device Specific Selections 4. Test Parameters 5. Central Pane Display SLOU260F – April 2009 – Revised January 2012 Submit Documentation Feedback TSW1250EVM: High-Speed LVDS Deserializer and Analysis System Copyright © 2009–2012, Texas Instruments Incorporated 9 Graphics User Interface (GUI) www.ti.com 1 3 4 5 2 Figure 6. TSW1250 GUI 5.1 Toolbar The toolbar contains options and settings that are independent of the device selected for test or the test to be performed, such as configuration options and save/recall operations. The operations available under the toolbar are grouped in categories of: File Instrument Options Data Capture Options Test Options 5.1.1 File 1 Save Binary File Save the data in binary format. 2 Save Single Tone Data Save the FFT data and its associated frequency. Only the data of the active channel is saved. 3 Save Time Domain data Save the Time Domain data. Only the data of the active channel is saved. 4 Save Measurement to CSV Save the measurement data. The data can be in frequency domain or time domain whichever is active. Multiple channels data are allowed. The targeted channels must complete the CAPTURE process before this save command. (1) (1) 10 Save Measurement to CSV. This function allows the user to save multiple channels simultaneously. For example, if the user intends to save channel 1 and channel 3, then the following steps must be done. 1. Apply the signal input to channel 1. 2. From the GUI, select channel 1 in the Channel Selection box. 3. Press Capture button to complete data capture. 4. Repeat the preceding steps for Channel 3. 5. Select Save Measurement to CSV, and choose the items intended to save. The example chooses every item. TSW1250EVM: High-Speed LVDS Deserializer and Analysis System SLOU260F – April 2009 – Revised January 2012 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated Graphics User Interface (GUI) www.ti.com 5 Save Capture as JPENG, BMP, or PENG Save the image in the file. If the Single Tone FFT test is active, then the FFT plot is being saved, along with the performance statistics and setup information. If the Time Domain test is active, then the Time Domain plot is saved along with the time domain statistics. The saved data plot can be saved in jpeg, png, or bmp format The result is shown in the following table. Single Tone FFT Unit Channel 1 Channel 3 SNR dBFS 71.7 71.68 SINAD dBFS 71.61 71.65 SFDR dBc 64.72 68.74 SFDR w/o 2 and 3 dBc 67.22 68.74 THD dBFS 88.89 93.74 ENOB bits 11.62 11.61 Min Codes 7856 7835 Max Codes 8560 8543 St. Dev. Codes 245.59 247.96 Mean Codes 8208.81 8189.18 Time Domain Signal Frequency MHz 2 2 Amplitude dBFS –27.45 –27.37 Total Ampl. dBFS –27.34 –27.29 Distortion HD2 dBc 64.72 70.52 HD3 dBc 78.21 80.34 HD4 dBc 77.98 79.06 HD5 dBc 86.33 80.59 Marker #1 dBc 0 64.72 ADC Setup 5.1.2 FFT Length points 16384 16384 Sample Rate MSPS 40 40 BW Start kHz 2.442 2.442 BW End MHz 20 20 Instrument Options The Instrument Options menu tab are reserved for future development: 5.1.3 Data Capture Options The Data Capture menu tab contains four options as shown in the following. 1 Continuous Capture Default is non-continuous. Allows to switch to continuous mode. 2 External Trigger Default is internal, check to switch to external. 3 LSB First Default is MSB First, check to change to LSB First 4 UART Baud Rate Default is 460800 bps. Options are available to go to slower rate. SLOU260F – April 2009 – Revised January 2012 Submit Documentation Feedback TSW1250EVM: High-Speed LVDS Deserializer and Analysis System Copyright © 2009–2012, Texas Instruments Incorporated 11 Graphics User Interface (GUI) 5.1.4 www.ti.com Test Options The Test Options menu tab has two options : Time Domain and Single Tone. Time Domain is reserved for future development. Single Tone has the following options: 1 Number of Harmonics The number of harmonics to be displayed. Default is 5. 2 dBFS Check for dBFS, unchecked for dBC. Default is dBFS. 3 RMS Check to enable RMS line in the display. 4 Nullify Bins Specify the start/stop bins to null the spectrum. 5 Nullify Bands Specify the start/stop frequency to null the spectrum. RMS For a Single Tone FFT test, the RMS line may be enabled or disabled. When enabled, a horizontal marker is displayed over the FFT plot to indicate the RMS average of the noise floor of the FFT plot. The RMS average is computed over all of the FFT bins except the bin containing the input frequency. More precisely, RMS line = SINAD + FFT Record Length Process Gain FFT Record Process Gain = 10log(number of points/2) dBFS SNR, SFDR, and SINAD can be expressed in either dBc or dBFS as selected by the dBFS selection under the Single Tone FFT options. By default, the noise calculations for SNR and SINAD do not include the five FFT bins around the expected input frequency or the first five FFT bins at DC. The rest of the FFT bins out to the Nyquist frequency are included in the calculation of the total noise. Vertical marker cursors are present in the FFT display that indicate the beginning and the end of the bandwidth of interest for noise calculations. Because these vertical markers are located at the extreme left-most and right-most positions on the FFT display, these vertical markers often are not noticeable. It is possible to compute the total noise power over a narrower range than the default DC through Nyquist band of frequencies. An integration band for the noise calculations can be set in two ways. • First, click the mouse on one of the vertical cursors and drag it to a new desired location. • Second, the Cursor Band Location window under the Single Tone FFT Test Option in the tool bar can be used to set a new frequency band of integration for the calculation of the total noise power. Also excluded from calculation of the SNR is the power in the first five harmonics of the input frequency. These first five harmonics are included in calculation of SINAD (signal to noise and distortion) and thus this is the principal difference between SNR and SINAD. (SINAD is sometimes called SNDR, signal to noise and distortion ratio.) The number of harmonics to exclude from SNR can be set to a value other than the default 5 in the Number of Harmonics window in the Single Tone FFT Test Option in the toolbar. 5.2 Message Window The lower left portion of the TSW1250 user interface software window under the TI logo is reserved for reporting status, warnings, errors, and informational output. When the TSW1250 software is first run, it queries the TSW1250EVM and displays the revision of the FPGA firmware and the type of MHR_ADC interface the TSW1250EVM is expecting to see based on jumper settings J10 and J11. At any time, this initial information can be displayed again by selecting the Reinitialize Instrument option in the Instrument Options tab of the toolbar. 12 TSW1250EVM: High-Speed LVDS Deserializer and Analysis System SLOU260F – April 2009 – Revised January 2012 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated Graphics User Interface (GUI) www.ti.com 5.3 Device-Specific Selections Drop-down menus that are specific to a particular MHR_ADC device selection are located along the top of the display under the toolbar. Users can select a MHR_ADC device from the device selection drop-down menu. Once a MHR_ADC device part number is selected, the MHR_ADC Channel can be selected in the Channel selection drop-down menu. The format for display of the captured data is chosen in the Test Selection drop-down menu. Single Tone FFT displays the power spectrum of the captured data with calculated AC performance statistics. Time Domain displays the raw captured data in the format of a logic analyzer display and output level over time. In the Window Display drop-down menu, the user chooses a windowing function to be applied to the captured data. A Rectangular Window applies a unity gain to all data points of the captured data. A Hanning Window, Hamming Window, or Blackman-Harris Window function can be applied to the captured data for situations where the sample rate and the input frequency are not or cannot be set precisely to capture an integer number of cycles of the input frequency (sometimes called coherent frequency). The Capture button initiates a data capture once all other selections are made. The data capture can be a single capture and display, or a continuous repeating capture. 5.4 Test Parameters The six test parameters are: Sampling Rate (FS), ADC Input Target Frequency, FFT Record Length (Ns), Auto Calculation of Coherent Input Frequency, Overlay Unwrap Waveform, and ADC Input Coherent Frequency (FC). The sampling rate is called the Sampling Frequency FS. The number is entered in Hertz (Hz), although the letter M may be appended to represent the sampling rate in MHz. For example, 125M = 125 MHz or 125,000,000 Hz. The expected input frequency is entered in the ADC Input Target Frequency input box. If the Auto Calculation of Coherent Input Frequency mode is enabled, then this input frequency is adjusted up or down slightly away from the input frequency automatically to derive a coherent frequency called ADC Input Coherent Frequency (FC). If coherent input frequency is required, the signal generator used to source the input frequency must be set to this exact calculated coherent frequency. The coherent frequency calculation takes the sampling frequency, the input frequency as entered by the user and the FFT record length and adjusts the input frequency so that the captured data starts and ends on the same place of the sine wave of the input frequency. This avoids an artifact of the FFT calculation from presenting a smeared power spectrum due to the fact that the FFT presumes the sample of the input is part of a continuous input signal. If the input and sampling frequency is not coherent, and the sampled data is appended end to end to form a continuous input signal, then an apparent phase discontinuity at the beginning and the end of the sampled data occurs. Making the sampling and input frequencies coherent avoids this apparent discontinuity. If the input frequency cannot be made coherent, then the windowing functions other than Rectangular can be used to process out this effect to some degree. The FFT record length can be set in the FFT Record Length (NS) input text box. The TSW1250EVM supports FFT record lengths of as much as 65536 samples, or as little as 4096 samples. The sampling rate is entered in the ADC Sampling Rate text box, also called the Sampling Frequency FS. The expected input frequency is entered in the ADC Input Frequency input box. The Overlay Unwrap Waveform check box is used in the Time Domain test. It allows a calculated normalized waveform to be overlaid over the sample data. If the sample and input frequencies are coherent, the sampled data is normalized into a calculated representation of a single period of a sine wave. Errors in the sampled data for any reason become immediately apparent as spikes on the unwrapped waveform. 5.5 Central Pane Display The large central pane display area includes two Tabs. Tab1 Time Domain Test Tab2 Single Tone FFT Test SLOU260F – April 2009 – Revised January 2012 Submit Documentation Feedback TSW1250EVM: High-Speed LVDS Deserializer and Analysis System Copyright © 2009–2012, Texas Instruments Incorporated 13 Graphics User Interface (GUI) www.ti.com They are described in the Time Domain Test and Single Tone FFT Test. 5.5.1 Time Domain Test The Time Domain test is shown in Figure 7. The larger central pane displays the raw sampled data whereas the calculated statistics are grouped into categories on the right of the screen. Settings and inputs relevant to the test are entered in drop-down menus or text input boxes on the left portion of the window. 5.5.2 Time Domain Results The captured sample data is displayed in two formats in the Time Domain results window. In the upper half of the window, the arithmetic value of the sample is represented on the vertical scale. In the lower half of the window the individual bits of the data are displayed as if it were captured by a logic analyzer. If Unwrap Waveform is enabled, the normalized calculation of one period of a sine wave is overlaid over the time domain data in the upper half of the display. The Time Domain display automatically scales the horizontal display to represent the full data capture to the amount specified by the FFT Record Length. The horizontal scale may be manually adjusted by highlighting the minimum and maximum sample limits and typing in new scale limits. The Time Domain display automatically scales the vertical display according the bit resolution of the selected MHR_ADC. For example, for a 12-bit AFE58xx, the vertical scale is represented as values from 0 through 4000. For a 14-bit AFE58xx, the vertical scale is represented as values from 0 through 16000. The vertical scale can also be adjusted manually by highlighting limits of the scale and typing in new limits. 5.5.3 Time Domain Statistics For the Time Domain test, sample statistics are displayed on the right of the display. The minimum and maximum sample values are displayed, as is the median sample and the mean, standard deviation, and RMS value of the samples. Figure 7. Time Domain Test 14 TSW1250EVM: High-Speed LVDS Deserializer and Analysis System SLOU260F – April 2009 – Revised January 2012 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated Graphics User Interface (GUI) www.ti.com 5.5.4 Single Tone FFT Test The Single Tone FFT test is shown in Figure 8. The larger central pane displays the FFT power spectrum, whereas the calculated statistics are grouped into categories on the right of the screen. Settings and inputs relevant to the test are entered in drop-down menus or text input boxes on the left portion of the window. 5.5.5 FFT Power Spectrum The FFT power spectrum of the captured data is displayed in the major center portion of the window. The TSW1250 software automatically scales the horizontal axis from DC through the Nyquist frequency, although the scale of the horizontal axis can be changed simply by highlighting the text and typing in a new value. For example, the display in Figure 8 can be used to zoom in on the input frequency by highlighting the 0MHz and typing 25M, and then highlighting the 62.5M and typing in 35M. This causes the portion of the power spectrum from 25 MHz through 35 MHz to fill the power spectrum display. The vertical scale of the power spectrum is automatically scaled to display the noise floor of the FFT result up through 0 dBFS. The vertical scale can also be manually adjusted by highlighting the limits of the vertical scale and typing in new limits. By default, the first few harmonics of the input frequency are marked in the display, as well as an additional marker that can be placed by dragging the marker to any place in the power spectrum, such as a noise spur that is not already marked as a harmonic. By default this additional marker initially goes to the highest spur that is not identified as a harmonic. Display properties can be edited by using the mouse to right-click in the power spectrum display. Visible properties such as the graph palette or plot legend can be edited, and auto-scale of the vertical and horizontal axises can be enabled or not. 5.5.6 Single FFT Statistics For the Single FFT test, a number of calculated statistics and AC performance measurements are displayed to the right of the power spectrum display, grouped into several categories. AC Signal-to-Noise Ratio – SNR is the ratio of the power of the fundamental (PS) or input frequency to the noise floor power (PN), excluding the power at DC and the first five harmonics. SNR is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter’s full-scale range. P SNR = 10Log 10 S PN (1) Signal-to-Noise and Distortion (SINAD) – SINAD is the ratio of the power of the fundamental (PS) to the power of all the other spectral components including noise (PN) and distortion (PD), but excluding DC. PS SINAD = 10Log 10 PN + PD (2) Spurious-Free Dynamic Range (SFDR) – SFDR is ratio of the power of the fundamental to the highest other spectral component (either spur or harmonic). SFDR is typically given in units of dBc (dB to carrier). SFDR w/o 2,3 – Spurious-Free Dynamic Range without the second or third harmonic. Commonly, the largest spectral components after the fundamental are the second and third harmonics of the input frequency, and the input frequency can commonly contain significant power in the second and third harmonics. SFDR w/o 2,3 reports the SFDR with these two harmonics ignored. Total Harmonic Distortion (THD) – THD is the ratio of the power of the fundamental (PS) to the power in the first five harmonics (PD). THD is typically given in data sheets in units of dBc (dB to carrier). P THD = 10Log 10 S PD (3) Effective Number of Bits (ENOB) – The ENOB is a measure of a converter’s performance as compared to the theoretical limit based on quantization noise. SLOU260F – April 2009 – Revised January 2012 Submit Documentation Feedback TSW1250EVM: High-Speed LVDS Deserializer and Analysis System Copyright © 2009–2012, Texas Instruments Incorporated 15 Graphics User Interface (GUI) ENOB = www.ti.com SINAD - 1.76 6.02 (4) Time Domain Several of the statistics of the Time Domain test are repeated here, particularly the minimum and maximum sample values in the FFT record length, as well as the mean and standard deviation of the sample values Signal The frequency of the expected input signal is reported, as well as the power level of the signal in either dBc or dBFS. The amplitude of the input frequency for typical data sheet measurements is commonly set externally to be about 1 dB below Full Scale, or –1 dBFS. Distortion The power values for the second, third, fourth, and fifth harmonics of the input frequency and the user-selectable marker are displayed in either dBFS or dBc. Test setup Input parameters relevant to the test are repeated, particularly FFT record length, sample rate, and the end points of the bandwidth of integration for noise calculations. The lower end point for the bandwidth of integration is normally not zero because the first few FFT bins are not included to remove any DC biasing component of the signal. Figure 8. Single FFT Test 16 TSW1250EVM: High-Speed LVDS Deserializer and Analysis System SLOU260F – April 2009 – Revised January 2012 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated +6V +6V GND +6V GND C106 10uF 10% 16V C33 10uF 10% 16V C54 10uF 10% 16V LOW ESR + GND C102 10uF 10% 16V +6V GND CONN JACK PWR GND GND GND GND 1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10 TPS76701QPWP GND/HTSNK1 GND/HTSNK2 GND GND/HTSNK8 NC1 GND/HTSNK7 EN NC4 IN1 NC3 IN2 RESET NC2 FB/NC GND/HTSNK3 OUT2 GND/HTSNK4 OUT1 GND/HTSNK6 GND/HTSNK5 PWRPAD U12 TPS76733QPWP GND/HTSNK1 GND/HTSNK2 GND GND/HTSNK8 NC1 GND/HTSNK7 EN NC4 IN1 NC3 IN2 RESET NC2 FB/NC GND/HTSNK3 OUT2 GND/HTSNK4 OUT1 GND/HTSNK6 GND/HTSNK5 PWRPAD U13 TPS76733QPWP GND/HTSNK1 GND/HTSNK2 GND GND/HTSNK8 NC1 GND/HTSNK7 EN NC4 IN1 NC3 IN2 RESET NC2 FB/NC GND/HTSNK3 OUT2 GND/HTSNK4 OUT1 GND/HTSNK6 GND/HTSNK5 PWRPAD U11 TPS76750QPWP GND GND GND R50 30.1K 20 19 18 17 16 15 14 13 12 11 21 J14 3 2 + GND GND R13 R45 R51 R49 33.2K R48 100K FB16 FB13 68 OHM @ 100MHz GND GND LOW ESR + C103 10uF 10% 16V + D16 +6V + C105 47uF 10V 20% C51 47uF 10V 20% C88 47uF 10V 20% LED green 68 OHM @ 100MHz FB10 68 OHM @ 100MHz FB12 + + 68 OHM @ 100MHz FB11 68 OHM @ 100MHz C32 .1uF 10% 16V LOW ESR + C107 10uF 10% 16V GND 100K LOW ESR + GND C53 10uF 10% 16V 100K GND LOW ESR + GND C98 10uF 10% 16V 100K C96 47uF 20% 10V 1 2 +6V_IN BANANA_JACK_BLK 20 19 18 17 16 15 14 13 12 11 21 20 19 18 17 16 15 14 13 12 11 21 20 19 18 17 16 15 14 13 12 11 21 GND J22 GND/HTSNK1 GND/HTSNK2 GND GND/HTSNK8 NC1 GND/HTSNK7 EN NC4 IN1 NC3 IN2 RESET NC2 FB/NC GND/HTSNK3 OUT2 GND/HTSNK4 OUT1 GND/HTSNK6 GND/HTSNK5 PWRPAD U9 +5VADC J22 default: Shorted J15 BANANA_JACK_RED 1 1 2 JP8 GND GND C101 47uF 10V 20% C349 10uF 10% 16V C52 10uF 10% 16V C89 10uF 10% 16V 300 R109 GND C348 10uF 10% 16V GND C100 .1uF 10% 16V VCC_BANK5_ADJ GND C104 .1uF 10% 16V +3.3V C34 .1uF 10% 16V +3.3V_USB C67 .1uF 10% 16V +5VADC GND C99 1uF 20% 25V GND C31 + .01uF +6V C97 47uF 20% 10V 1 +6V J17 GND J17 default: OPEN C109 100uF 16V 20% INHIBIT R59 10K +3.3V_USB .1uF C85 .1uF C81 3 2 1 3 2 1 OUT U7 + 4 5 OUT U15 4 5 GND 2 3 1 R58 PTH03000W 24.3K Vo_ADJ Vout 2.2uF 4 GND + C108 100uF 16V 20% C9 C21 C39 .1uF C37 C57 .01uF C40 .01uF .1uF C56 .01uF .1uF C36 .01uF .1uF C20 .01uF .1uF VCC_BANK5_ADJ .1uF C55 +1.2V .1uF C35 +2.5V 5 C19 .1uF C84 +1.2V C7 .1uF C8 VCCO_0 VCCO_0 VCCO_1 VCCO_1 VCCO_2 VCCO_2 VCCO_3 VCCO_3 VCCO_4 VCCO_4 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_7 VCCO_7 VCCO_7 VCCO_8 VCCO_8 VCCO_8 +3.3V D10 U11 D7 D14 U7 U14 A9 A12 Y8 Y13 K15 L15 A17 E17 L18 D20 J20 N20 D1 J1 N1 L3 A4 E4 K6 L6 T16 Y18 U20 U1 Y3 T5 +2.5V 2.2uF C82 +1.8V U14 Vin INHIBIT GND TPS73225-SOT23 EN GND NC/FB IN TPS73018-SOT23 EN GND NC/FB IN +3.3V_USB +3.3V_USB VCC_BANK5_ADJ +3.3V 1 1 1 2 1 2 1 2 1 2 1 JP8 default: Short 1-2 1 2 2 1 2 1 2 1 2 1 2 U1-5 XC4VLX25-SF363-BGA C10 C11 C23 C41 .1uF .01uF C13 C24 C25 C61 .1uF C47 C14 C15 C27 C45 C63 .1uF C49 C16 C17 C28 C29 C65 .01uF .01uF .1uF C64 .01uF .1uF .01uF C66 .01uF C30 .01uF C18 VCCINT1 VCCINT2 VCCINT3 VCCINT4 VCCINT5 VCCINT6 VCCINT7 VCCINT8 VCCINT9 VCCINT10 VCCINT11 VCCINT12 VCCAUX1 VCCAUX2 VCCAUX3 VCCAUX4 VCCAUX5 VCCAUX6 VCCAUX7 VCCAUX8 VREFP_SM VREFN_SM AVDD_SM VP_SM VN_SM AVSS_SM .01uF .1uF C50 .01uF .1uF C62 .01uF .1uF C44 .01uF .1uF C26 .01uF .1uF .01uF C48 .01uF .1uF C60 .1uF C43 .01uF .1uF C42 C59 C46 C12 .01uF .1uF .01uF .01uF .1uF C58 .01uF C38 .01uF .1uF C22 .01uF .1uF 1 6V_IN 1 2 1 2 1 2 2 1 2 1 1 2 1 2 1 2 2 1 2 1 2 2 1 2 1 2 1 2 1 2 1 1 2 1 2 2 1 1 2 1 1 2 1 2 1 2 1 3 1 2 1 2 1 2 1 2 2 1 2 1 2 1 2 2 1 2 1 2 2 1 2 2 1 2 1 2 1 2 1 2 1 2 1 2 J7 1 2 2 B1 W1 Y1 A2 Y2 G3 P3 C7 H7 J7 K7 L7 M7 N7 V7 G8 P8 G9 P9 G10 P10 U10 1 2 1 2 1 2 1 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND 1 2 1 2 1 2 1 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND D11 G11 P11 G12 P12 G13 P13 C14 H14 J14 K14 L14 M14 N14 V14 G18 P18 A19 Y19 A20 B20 W20 Y20 1 2 Copyright © 2009–2012, Texas Instruments Incorporated 1 2 1 2 2 1 2 SLOU260F – April 2009 – Revised January 2012 Submit Documentation Feedback 1 +2.5V G6 P6 F7 G7 P7 R7 F14 G14 P14 R14 G15 P15 +1.2V H6 N6 F8 R8 F13 R13 H15 N15 W14 W15 W16 Y14 Y15 Y16 Schematics 1 6.1 2 Schematics and Bill of Materials 2 6 2 www.ti.com Schematics and Bill of Materials Figure 9. Schematic Diagram Page 1 TSW1250EVM: High-Speed LVDS Deserializer and Analysis System 17 +3.3V TSW1250EVM: High-Speed LVDS Deserializer and Analysis System 1K R47 SW5 1 Copyright © 2009–2012, Texas Instruments Incorporated 1K R46 RESET +3.3V 2 2 SW4 RESET R44 10K 1 R43 10K D4 GREEN +3.3V D3 GREEN D1 VCC WP SCL SDA 24LC32A A1 A2 A3 GND GREEN D2 GREEN 1 2 3 4 330 R40 8 7 6 5 330 R41 330 R42 330 R39 U8 +3.3V_USB EEPROM 32K (4K x 8) 3 4 2 R38 1K C72 10uF CH8-D6 CH8-D9 CH8-D1 CH8-D2 CH8-D8 SH5 CH8-D3 SH5 CH8-D4 SH5 SH5 SH5 SH5 SH5 CH8-D10 CH8-D11 CH8-D5 CH8-D13 CH8-D7 CH8-D0 SH5 CH8-D12 R2633 ohm R25 33 ohm R37 1K +3.3V_USB 1 2 1K @ 100MHZ Do not installed L3 SH5 SH5 CH8-CLKOUT SH5 SH5 SH5 SH5 SH5 J8 1 +5V_USB 3 2 1 OUT U5 4 5 R19 R20 R15 R16 T19 T20 R17 R18 T17 T18 U18 U19 T15 U15 V19 V20 U16 U17 W18 W19 Y17 W17 V17 V18 GPIO1 GPIO2 GPIO3 GPIO4 SOUT RTS DTR 1 C77 22pF DP DM U1-4 C78 22pF PUR GPIO1 GPIO2 GPIO3 GPIO4 SDA XC4VLX25-SF363-BGA DP DM PUR P3.0 P3.1 P3.3 P3.4 SDA SCL R2 R1 R6 R5 T2 T1 R4 R3 U3 U2 T4 T3 T6 U6 V2 V1 U5 U4 W3 W2 Y4 W4 V4 V3 RI RTS DTR SOUT GPIO1 GPIO2 GPIO3 GPIO4 GPIO1 GPIO2 GPIO3 GPIO4 /CTS /DSR SIN /DCD Y1 RI /DCD SIN /CTS /DSR RI RTS DTR SOUT Do not installed C75 33pF 4 2 Do not installed C73 33pF FPGA_PDN SH4 FPGA_SEN SH4 FPGA_SDATA SH4 FPGA_SCLK SH4 FPGA_RST SH4 +3.3V_USB 12MHz w/ 18pF /CTS /DSR SIN /DCD RST SUSP 2 9 VREGEN RI 16 1 /DCD 15 /CTS /DSR SIN 3 1 R214.99K X1 X2 17 13 14 23 24 27 26 TUSB3410IVF U6 RESET* SUSPEND VREGEN* RI*/CP DCD* SIN/IR_SIN CTS* DSR* TEST0 TEST1 X1/CLKI X2 +3.3V_USB R19 90.9K SOUT/IR_SOUT RTS* DTR* CLKOUT WAKEUP* R18 100K IO_L20P_8 IO_L20N_VREF_8 IO_L21P_8 IO_L21N_8 IO_L23P_VRN_8 IO_L23N_VRP_8 IO_L24P_CC_LC_8 IO_L24N_CC_LC_8 IO_L25P_CC_LC_8 IO_L25N_CC_LC_8 IO_L26P_8 IO_L26N_8 IO_L27P_8 IO_L27N_8 IO_L28P_8 IO_L28N_VREF_8 IO_L29P_8 IO_L29N_8 IO_L30P_8 IO_L30N_8 IO_L31P_8 IO_L31N_8 IO_L32P_8 IO_L32N_8 6 7 5 32 31 30 29 10 11 19 SOUT 2 20 21 R23 1.5K J16 22 RTS DTR 12 CLKOUT IO_L20P_7 IO_L20N_VREF_7 IO_L21P_7 IO_L21N_7 IO_L23P_VRN_7 IO_L23N_VRP_7 IO_L24P_CC_LC_7 IO_L24N_CC_LC_7 IO_L25P_CC_SM7_LC_7 IO_L25N_CC_SM7_LC_7 IO_L26P_SM6_7 IO_L26N_SM6_7 IO_L27P_SM5_7 IO_L27N_SM5_7 IO_L28P_7 IO_L28N_VREF_7 IO_L29P_SM4_7 IO_L29N_SM4_7 IO_L30P_SM3_7 IO_L30N_SM3_7 IO_L31P_SM2_7 IO_L31N_SM2_7 IO_L32P_SM1_7 IO_L32N_SM1_N_7 TP7 WKUP R20 10K +3.3V_USB C71 4.7uF C74 1000pF TPS76933DBVT EN GND NC/FB IN 4 25 3 VDD18 VCC25 VCC3 GND28 GND18 GND8 18 28 18 8 CONN USB TYP B FEM DIODE D5 R22 33K R24 15K +3.3V_USB C76 1uF Schematics and Bill of Materials www.ti.com Figure 10. Schematic Diagram Page 2 SLOU260F – April 2009 – Revised January 2012 Submit Documentation Feedback 3 2 U10 OUT OUT VCC 4 5 6 LV7745DEV-200MHz GND NC OE 3.3uF 1 2 R53 49.9 .1uF C86 1 2 +3.3V R54 49.9 .1uF C87 GREEN 330 4.7K R6 Q3 DTC114EET1 D7 +3.3V PROG_B SH5 SH5 SH5 SH5 SH5 SH5 SH5 SH5 SH5 R31 R34 1K 0 ohm CH5-D1 CH6-D7 CH6-D6 CH5-D0 CH5-D4 CH6-D3 CH6-D4 CH5-D2 CH5-D5 CH6-D12 CH5-D3 CH6-D11 CH6-D13 SH5 SH5 SH5 SH5 HSWAP_EN SH5 CH5-CLKOUT R4 10K R7 ZERO R55 DONE 1 + CH6-D0 CH5-D12 CH5-D13 CH6-D1 CH6-D2 CH5-D11 CH5-D10 CH6-D5 CH6-D8 CH5-D7 CH5-D9 CH6-D9 CH6-D10 CH5-D6 CH5-D8 SH5 SH5 SH5 SH5 SH5 SH5 SH5 SH5 SH5 SH5 SH5 SH5 SH5 SH5 SH5 CCLK R52 4.7K SH5 CH6-CLKOUT +3.3V R36 100 R35 100 R33 1K D5 D6 D7 F10 E10 E11 F11 F12 E12 E13 F9 E8 E9 B12 A11 A10 B9 C11 B11 B10 C10 B13 A13 A8 B8 B14 A14 A7 B7 F15 E15 E6 F6 D15 E14 E7 D6 D13 C13 C8 D8 D12 C12 C9 D9 U1-1 CE +3.3V TDP_0 TDN_0 A1 A2 A3 A4 A5 A6 B1 B2 B3 B4 B5 B6 CCLK_0 DONE_0 PROG_B_0 INIT_B_0 HSWAPEN_0 RDWR_B_0 CS_B_0 D_IN_0 0 ohm R32 GND GND OE/RESET NC1 D6 D7 VCCINT VCCO CLK CE D5 GND U2 XCF32PFSG48 T13 T10 T11 R9 R10 T8 T9 R12 T12 R11 W13 W12 Y5 W5 Y12 Y11 Y6 W6 W11 W10 Y7 W7 Y10 Y9 W9 W8 V16 V15 V6 V5 T14 U13 U8 T7 V13 V12 V9 V8 U12 V11 V10 U9 GND GND NC10 NC9 NC8 GND TDO D2 NC7 NC6 TMS VCCINT VBATT_0 PWRDWN_B_0 DOUT_BUSY_0 TDI_0 TDO_0 TMS_0 TCK_0 M0_0 M1_0 M2_0 IO_L1P_GC_LC_4 IO_L1N_GC_LC_4 IO_L2P_GC_LC_4 IO_L2N_GC_LC_4 IO_L3P_GC_LC_4 IO_L3N_GC_LC_4 IO_L4P_GC_LC_4 IO_L4N_GC_VREF_LC_4 IO_L5P_GC_LC_4 IO_L5N_GC_LC_4 IO_L6P_GC_LC_4 IO_L6N_GC_LC_4 IO_L7P_GC_VRN_LC_4 IO_L7N_GC_VRP_LC_4 IO_L8P_GC_CC_LC_4 IO_L8N_GC_CC_LC_4 IO_L1P_D15_CC_LC_2 IO_L1N_D14_CC_LC_2 IO_L2P_D13_LC_2 IO_L2N_D12_LC_2 IO_L3P_D11_LC_2 IO_L3N_D10_LC_2 IO_L4P_D9_LC_2 IO_L4N_D8_VREF_LC_2 IO_L5P_D7_LC_2 IO_L5N_D6_LC_11 IO_L6P_D5_LC_2 IO_L6N_D4_LC_2 IO_L7P_D3_LC_2 IO_L7N_D2_LC_2 IO_L8P_D1_LC_2 IO_L8N_D0_LC_2 XC4VLX25-SF363-BGA IO_L1P_GC_CC_LC_3 IO_L1N_GC_CC_LC_3 IO_L2P_GC_VRN_LC_3 IO_L2N_GC_VRP_LC_3 IO_L3P_GC_LC_3 IO_L3N_GC_LC_3 IO_L4P_GC_LC_3 IO_L4N_GC_VREF_LC_3 IO_L5P_GC_LC_3 IO_L5N_GC_LC_3 IO_L6P_GC_LC_3 IO_L6N_GC_LC_3 IO_L7P_GC_LC_3 IO_L7N_GC_LC_ IO_L8P_GC_LC_3 IO_L8N_GC_LC_3 IO_L1P_D31_LC_1 IO_L1N_D30_LC_1 IO_L2P_D29_LC_1 IO_L2N_D28_LC_1 IO_L3P_D27_LC_1 IO_L3N_D26_LC_1 IO_L4P_D25_LC_1 IO_L4N_D24_VREF_LC_1 IO_L5P_D23_LC_1 IO_L5N_D22_LC_1 IO_L6P_D21_LC_1 IO_L6N_D20_LC_1 IO_L7P_D19_LC_1 IO_L7N_D18_LC_1 IO_L8P_D17_CC_LC_1 IO_L8N_D16_CC_LC_1 +3.3V F6 F5 F4 F3 F2 F1 E6 E5 E4 E3 E2 E1 +1.8V BUSY D7 D6 D5 D4 D3 D2 D1 D0 M1 2 M2 RESET SW2 1 2 PROM RESET D2 HEADER 3 J10 +3.3V TDI_0 TDO_0 M0 CH7-D0 SH5 CH7-D8 SH5 CH7-D7 SH5 CH7-D1 SH5 CH7-D3 SH5 CH7-D9 SH5 CH7-D6 SH5 CH7-D2 SH5 CH7-D4 SH5 CH7-D10 SH5 CH7-D5 SH5 CH7-D13 SH5 CH7-D12 SH5 CH7-D11 SH5 1 2 3 C83 3 1 HEADER 3 J11 +3.3V 4 2 J1 +3.3V SW3 1 PROGRAM 4 2 RN1 4.7K 3 J12 R1 0 ohm 1 CH7-CLKOUT SH5 C1 10uF C79 +1.8V 10uF .1uF C6 .1uF C2 +3.3V TMS TCK TDO TDI R2 0 ohm C4 .1uF C80 .01uF C5 .01uF .1uF C3 2 4 6 8 10 12 14 +3.3V R3 0 ohm +3.3V 1 +3.3V 1 2 3 D0 D1 H6 H5 H4 H3 H2 H1 G6 G5 G4 G3 G2 G1 D0 D1 EN_EXT_SEL TCK VCCJ GND VCCINT VCCO REV_SEL1 REV_SEL0 NC11 TDI BUSY CLKOUT NC2 NC3 D4 VCCO CF CEO NC4 NC5 D3 VCCO C1 C2 C3 C4 C5 C6 D1 D2 D3 D4 D5 D6 D4 8 7 6 5 1 2 3 4 1 2 1 1 2 1 2 2 1 2 Copyright © 2009–2012, Texas Instruments Incorporated 2 SLOU260F – April 2009 – Revised January 2012 Submit Documentation Feedback D3 JTAG J2 1 3 5 7 9 11 13 NOTES: SETUP FOR MASTER SELECT MAP OPERATION M0=M1=1 M2=0 2. PROM CONFIGURATION SHORT 1 AND 3; SHORT 2 AND 4 1. DEFAULT SETUP FOR J1 AND J12 www.ti.com Schematics and Bill of Materials Figure 11. Schematic Diagram Page 3 TSW1250EVM: High-Speed LVDS Deserializer and Analysis System 19 20 DCLK_P DCLK_M FCLK_P FCLK_M TSW1250EVM: High-Speed LVDS Deserializer and Analysis System Input25_P Input25_M Input27_P Input27_M Input26_P Input26_M Input10_P Input10_M Input8_P Input8_M Input7_P Input7_M Input5_P Input5_M Input0_P Input0_M Input1_P Input1_M Input11_P Input11_M Input9_P Input9_M Input6_P Input6_M Input4_P Input4_M Input2_P Input2_M M15 M16 M19 L19 N16 N17 B17 C17 D16 E16 A18 B18 D17 D18 B19 C20 F18 E18 C18 C19 F16 F17 D19 E19 G16 G17 E20 F20 H16 H17 F19 G19 IO_L27P_5 IO_L27N_5 IO_L28P_5 IO_L28N_VREF_5 IO_L29P_5 IO_L29N_5 IO_L4P_5 IO_L4N_VREF_5 IO_L5P_5 IO_L5N_5 IO_L6P_5 IO_L6N_5 IO_L7P_5 IO_L7N_5 IO_L8P_CC_LC_5 IO_L8N_CC_LC_5 IO_L9P_CC_LC_5 IO_L9N_CC_LC_5 IO_L10P_5 IO_L10N_5 IO_L11P_5 IO_L11N_5 IO_L12P_5 IO_L12N_VREF_5 IO_L13P_5 IO_L13N_5 IO_L14P_5 IO_L14N_5 IO_L15P_5 IO_L15N_5 IO_L16P_5 IO_L16N_5 XC4VLX25-SF363-BGA U1-2 IO_L17P_5 IO_L17N_5 IO_L18P_5 IO_L18N_5 IO_L20P_5 IO_L20N_VREF_5 IO_L21P_5 IO_L21N_5 IO_L22P_5 IO_L22N_5 IO_L23P_VRN_5 IO_L23N_VRP_5 IO_L24P_CC_LC_5 IO_L24N_CC_LC_5 IO_L25P_CC_LC_5 IO_L25N_CC_LC_5 IO_L30P_5 IO_L30N_5 IO_L31P_5 IO_L31N_5 IO_L32P_5 IO_L32N_5 IO_L26P_5 IO_L26N_5 IO_L1P_5 IO_L1N_5 IO_L2P_5 IO_L2N_5 IO_L3P_5 IO_L3N_5 IO_L19P_5 IO_L19N_5 J17 J18 H20 G20 H18 H19 K16 K17 K20 J19 L16 L17 K18 K19 M17 M18 N18 N19 P16 P17 P19 P20 M20 L20 B15 A15 A16 B16 C15 C16 J15 J16 Input17_P Input17_M Input18_P Input18_M Input21_P Input21_M Input23_P Input23_M Input15_P Input15_M Input14_P Input14_M Input3_P Input3_M Input16_P Input16_M Input19_P Input19_M Input20_P Input20_M Input24_P Input24_M Input22_P Input22_M Input12_P Input12_M Input13_P Input13_M Copyright © 2009–2012, Texas Instruments Incorporated Input15_M Input15_P Input14_M Input14_P Input13_M Input13_P Input12_M Input12_P Input11_M Input11_P Input10_M Input10_P Input9_M Input9_P Input8_M Input8_P FCLK_M FCLK_P DCLK_M DCLK_P Input7_M Input7_P Input6_M Input6_P Input5_M Input5_P Input4_M Input4_P Input3_M Input3_P Input2_M Input2_P Input1_M Input1_P Input0_M Input0_P G1 G3 G5 G7 G2 G4 G6 G8 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 J9 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 CONN_QSH_30X2-D-A FPGA_RST SH2 FPGA_PDN SH2 FPGA_SEN SH2 FPGA_SDATA SH2 FPGA_SCLK SH2 Input27_M Input27_P Input26_M Input26_P Input25_M Input25_P Input24_M Input24_P Input23_M Input23_P Input22_M Input22_P Input21_M Input21_P Input20_M Input20_P Input19_M Input19_P Input18_M Input18_P Input17_M Input17_P Input16_M Input16_P Schematics and Bill of Materials www.ti.com Figure 12. Schematic Diagram Page 4 SLOU260F – April 2009 – Revised January 2012 Submit Documentation Feedback SLOU260F – April 2009 – Revised January 2012 Submit Documentation Feedback J5 DATA_OUT 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 CH2_D0 CH2_D1 CH2_D2 CH2_D3 CH2_D4 CH2_D5 CH2_D6 CH2_D7 CH2_D8 CH2_D9 CH2_D10 CH2_D11 CH2_D12 CH2_D13 CH2_D14 CH2_D15 CH2_CLKOUT Copyright © 2009–2012, Texas Instruments Incorporated SMT FIDUCIAL FD1 FD3 22 R29 1 2 3 4 5 6 7 8 RN8 22 ohm 1 2 3 4 5 6 7 8 22 R27 CH1_D0 CH1_D1 CH1_D2 CH1_D3 CH1_D4 CH1_D5 CH1_D6 CH1_D7 CH1_D8 CH1_D9 CH1_D10 CH1_D11 CH1_D12 CH1_D13 CH1_CLKOUT SMT FIDUCIAL SMT FIDUCIAL FD2 HEADER MALE 20x2 POS .100 VERT 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 HEADER MALE 20x2 POS .100 VERT 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 J3 DATA_OUT CH2-CLKOUT CH6-D8 CH6-D9 CH6-D10 CH6-D11 CH6-D12 CH6-D13 SH3 SH3 SH3 SH3 SH3 SH3 SH3 SH3 SH3 SH3 SH3 SH3 SH3 SH3 SH3 SH3 SH3 SH3 SH3 SH3 SH3 SH3 1 2 3 4 5 6 7 8 RN11 22 ohm CH6-D0 CH6-D1 CH6-D2 CH6-D3 CH6-D4 CH6-D5 CH6-D6 CH6-D7 1 2 3 4 5 6 7 8 RN13 22 ohm SH3 CH6-CLKOUT CH5-D0 CH5-D1 CH5-D2 CH5-D3 CH5-D4 CH5-D5 CH5-D6 CH5-D7 CH1-CLKOUT 16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 22 RN12 22 ohm R61 RN10 22 ohm R60 CH1-D0 CH1-D1 CH1-D2 CH1-D3 CH1-D4 CH1-D5 CH1-D6 CH1-D7 CH1-D8 CH1-D9 CH1-D10 CH1-D11 CH1-D12 CH1-D13 16 15 14 13 12 11 10 9 SH3 CH5-CLKOUT 16 CH2-D0 15 CH2-D1 14 CH2-D2 CH2-D3 13 CH2-D4 12 CH2-D5 11 CH2-D6 10 CH2-D7 9 CH2-D8 CH2-D9 CH2-D10 CH2-D11 CH2-D12 CH2-D13 CH2-D14 CH2-D15 CH5-D8 CH5-D9 CH5-D10 CH5-D11 CH5-D12 CH5-D13 RN6 22 ohm 16 15 14 13 12 11 10 9 SH3 SH3 SH3 SH3 SH3 SH3 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 RN4 22 ohm 1 2 3 4 5 6 7 8 RN2 22 ohm 22 16 15 14 13 12 11 10 9 IO_L1P_6 IO_L1N_6 IO_L2P_6 IO_L2N_6 IO_L3P_6 IO_L3N_6 IO_L4P_6 IO_L4N_VREF_6 IO_L5P_6 IO_L5N_6 IO_L6P_6 IO_L6N_6 IO_L7P_6 IO_L7N_6 IO_L8P_CC_LC_6 IO_L8N_CC_LC_6 IO_L9P_CC_LC_6 IO_L9N_CC_LC_6 IO_L10P_6 IO_L10N_6 IO_L11P_6 IO_L11N_6 IO_L12P_6 IO_L12N_VREF_6 IO_L13P_6 IO_L13N_6 IO_L14P_6 IO_L14N_6 IO_L15P_6 IO_L15N_6 IO_L16P_6 IO_L16N_6 HDR 16X2 MALE .100CTR J19 CH6_CLKOUT2 1 4 3 CH6_D0 6 5 CH6_D1 8 7 CH6_D2 10 9 CH6_D3 12 11 CH6_D4 14 13 CH6_D5 16 15 CH6_D6 18 17 CH6_D7 20 19 CH6_D8 22 21 CH6_D9 24 23 CH6_D10 26 25 CH6_D11 28 27 CH6_D12 30 29 CH6_D13 32 31 HDR 16X2 MALE .100CTR J18 CH5_CLKOUT2 1 4 3 6 5 8 7 10 9 12 11 14 13 16 15 18 17 20 19 22 21 24 23 26 25 28 27 30 29 32 31 CH5_D0 16 CH5_D1 15 CH5_D2 14 CH5_D3 13 CH5_D4 12 CH5_D5 11 CH5_D6 10 9 CH5_D7 CH5_D8 CH5_D9 CH5_D10 CH5_D11 CH5_D12 CH5_D13 B6 A6 A5 B5 C6 C5 B4 C4 D5 E5 A3 B3 D4 D3 B2 C1 F3 E3 C3 C2 F5 F4 D2 E2 G5 G4 E1 F1 H5 H4 F2 G2 J4 J3 H1 G1 J6 J5 H3 H2 K5 K4 K1 J2 L5 L4 K3 K2 M4 M3 M1 L1 M6 M5 M2 L2 N5 N4 N3 N2 P5 P4 P2 P1 SH2 SH2 SH2 SH2 SH2 SH2 SH3 SH3 SH3 SH3 SH3 SH3 CH8-D8 CH8-D9 CH8-D10 CH8-D11 CH8-D12 CH8-D13 CH7-D8 CH7-D9 CH7-D10 CH7-D11 CH7-D12 CH7-D13 SH2 SH2 SH2 SH2 SH2 SH2 SH2 SH2 SH3 SH3 SH3 SH3 SH3 SH3 SH3 SH3 RN15 22 ohm CH8-D0 CH8-D1 CH8-D2 CH8-D3 CH8-D4 CH8-D5 CH8-D6 CH8-D7 1 2 3 4 5 6 7 8 RN17 22 ohm SH2 CH8-CLKOUT 1 2 3 4 5 6 7 8 SH3 CH7-CLKOUT CH7-D0 CH7-D1 CH7-D2 CH7-D3 CH7-D4 CH7-D5 CH7-D6 CH7-D7 XC4VLX25-SF363-BGA IO_L17P_6 IO_L17N_6 IO_L18P_6 IO_L18N_6 IO_L19P_6 IO_L19N_6 IO_L20P_6 IO_L20N_VREF_6 IO_L21P_6 IO_L21N_6 IO_L22P_6 IO_L22N_6 IO_L23P_VRN_6 IO_L23N_VRP_6 IO_L24P_CC_LC_6 IO_L24N_CC_LC_6 IO_L25P_CC_LC_6 IO_L25N_CC_LC_6 IO_L26P_6 IO_L26N_6 IO_L27P_6 IO_L27N_6 IO_L28P_6 IO_L28N_VREF_6 IO_L29P_6 IO_L29N_6 IO_L30P_6 IO_L30N_6 IO_L31P_6 IO_L31N_6 IO_L32P_6 IO_L32N_6 U1-3 16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 R62 RN16 22 ohm R63 RN14 22 ohm 22 22 16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9 6 8 10 12 14 16 18 20 22 24 26 28 30 32 5 7 9 11 13 15 17 19 21 23 25 27 29 31 HDR 16X2 MALE .100CTR CH8_D0 CH8_D1 CH8_D2 CH8_D3 CH8_D4 CH8_D5 CH8_D6 CH8_D7 CH8_D8 CH8_D9 CH8_D10 CH8_D11 CH8_D12 CH8_D13 J21 CH8_CLKOUT2 1 4 3 HDR 16X2 MALE .100CTR J20 CH7_CLKOUT2 1 4 3 CH7_D0 6 5 CH7_D1 8 7 CH7_D2 10 9 CH7_D3 12 11 CH7_D4 14 13 CH7_D5 16 15 CH7_D6 18 17 CH7_D7 20 19 CH7_D8 22 21 CH7_D9 24 23 CH7_D10 26 25 CH7_D11 28 27 CH7_D12 30 29 CH7_D13 32 31 CH4-D0 CH4-D1 CH4-D2 CH4-D3 CH4-D4 CH4-D5 CH4-D6 CH4-D7 CH4-D8 CH4-D9 CH4-D10 CH4-D11 CH4-D12 CH4-D13 CH4-CLKOUT CH3-D0 CH3-D1 CH3-D2 CH3-D3 CH3-D4 CH3-D5 CH3-D6 CH3-D7 CH3-D8 CH3-D9 CH3-D10 CH3-D11 CH3-D12 CH3-D13 CH3-D14 CH3-D15 CH3-CLKOUT 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 22 ohm RN7 22 ohm RN3 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 22 ohm RN9 22 ohm RN5 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 22 R30 22 R28 CH4_D0 CH4_D1 CH4_D2 CH4_D3 CH4_D4 CH4_D5 CH4_D6 CH4_D7 CH4_D8 CH4_D9 CH4_D10 CH4_D11 CH4_D12 CH4_D13 CH4_CLKOUT DATA_OUT J6 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 HEADER MALE 20x2 POS .100 VERT DATA_OUT J4 HEADER MALE 20x2 POS .100 VERT CH3_CLKOUT 2 1 4 3 CH3_D0 6 5 CH3_D1 8 7 CH3_D2 10 9 CH3_D3 12 11 CH3_D4 14 13 CH3_D5 16 15 CH3_D6 18 17 CH3_D7 20 19 CH3_D8 22 21 CH3_D9 24 23 CH3_D10 26 25 CH3_D11 28 27 CH3_D12 30 29 CH3_D13 32 31 CH3_D14 34 33 CH3_D15 36 35 38 37 40 39 www.ti.com Schematics and Bill of Materials Figure 13. Schematic Diagram Page 5 TSW1250EVM: High-Speed LVDS Deserializer and Analysis System 21 Schematics and Bill of Materials 6.2 www.ti.com Bill of Materials Table 1. Bill of Materials TSW1200EVM BOM – Revision: C QTY Reference Not Installed Part Foot Print Part Number Manufacturer Tol Volt Wat 3 C1, C72, C79 10 μF 603 ECJ-1VB0J106M Panasonic 20% 6.3V 4 C2, C4, C6, C80 0.1uF 603 GRM188R71H104KA93D Murata 5% 50V 2 C3, C5 0.01 μF 603 C0603C103K5RACTU Kemet 10% 50V 26 C7, C9, C11, C13, C15, C17, C19, C21, C23, C25, C27, C29, C35, C37, C39, C41, C43, C45, C47, C49, C55, C57, C59, C61, C63, C65 0.1 μF 201 ECJ-ZEBFJ104K Panasonic 5% 50V 26 C8, C10, C12, C14, C16, C18, C20, C22, C24, C26, C28, C30, C36, C38, C40, C42, C44, C46, C48, C50, C56, C58, C60, C62, C64, C66 0.01 μF 201 ECJ-ZEB1A103K Panasonic 5% 50V 1 C31 0.01 μF 402 ECJ-0EB1E103K Panasonic 10% 25V 1 C32 0.1 μF 402 ECJ-0EB1C104K Panasonic 10% 16V 11 C33, C52, C53, C89, C98, C102, C103, C106, C107, C348, C349 10 μF 1206 Panasonic ECJ-3YB1C106K 10% 16V 4 C34, C67, C100, C104 0.1 μF 402 Panasonic ECJ-0EB1C104K 10% 16V 5 C51, C88, C96, C101, C105 47 μF tant_b Kemet T494B476M010AS 20% 10V 1 C54 10 μF 1206 ECJ-3YB1C106K Panasonic 10% 16V 1 C71 4.7 μF 603 GRM188F51A475ZE20D Murata 0.6 10V 0 C73, C75 33 pF 603 GRM1885C2A330JA01D Murata 5% 100V 1 C74 1000 pF 603 ECJ-1VB1H102K Panasonic 10% 50V 1 C76 1 μF 603 ECJ-1VB1A105K Panasonic 10% 10V 2 C77, C78 22 pF 603 GRM1885C2A220JA01D Murata 5% 100V 2 C81, C85 0.1 μF 603 ECJ-1VB1H104K Panasonic 10% 50V 2 C82, C84 2.2 μF 603 ECJ-1VB1A225K Panasonic 10% 10V 1 C83 3.3 μF TANT_B TAJB335K016R AVX 10% 16V 2 C86, C87 0.1 μF 603 GRM188R71H104KA93D Murata 10% 50V 1 C97 47 μF tant_b T494B476M010AS Kemet 20% 10V 1 C99 1 μF 603 ECJ-1V41E105M Panasonic 20% 25V 2 C108, C109 100 μF smd_cap_elec_TCE EEE-TG1C101P Panasonic 20% 16V 5 D1–D4, D7 GREEN diode_0805 DC1112H-TR Stanley 1 D5 DIODE SOT23_DIODE BAS21TA Zetec Inc. 1 D16 LED green LED_0805 LNJ306G5UUX Panasonic 5 FB10–FB13, FB16 68 Ω at 100MHz 1206 EXC-ML32A680U Panasonic Short pins 1-2 with shunt connector DigiKey # S9000-ND 1 JP8 HEADER 3POS 0.1 CTR JUMPER3 HTSW-103-07-F-S Samtec Short pins with shunt connector DigiKey # S9000-ND (as shown on silkscreen) 2 J1, J12 HEADER 2×2 hdr2X2_100ctr_alt 90131-0122 Molex 1 J2 CONN 7×2 CON_2X7_2mm_M 87831-1420 Molex 4 J3–J6 HEADER MALE 20×2 POS 0.100 VERT CON20X2_100ctr_M_tsw 1100_mate HTSW-120-07-L-D Samtec 1 J7 CONN JACK PWR PWRJACK RAPC722 Switchcraft 1 J8 CONN USB TYP B FEM conn_usb_typb_fem 897-43-004-90-000 Milmax 1 J9 CONN_QSH_30×2-D-A conn_QSH_30X2-D-A QSH-060-01-F-D-A Samtec 2 J10, J11 HEADER 3 jumper3 22-28-4030 Molex 22 NOT INSTALLED TSW1250EVM: High-Speed LVDS Deserializer and Analysis System Short pins 1-2 with shunt connector DigiKey # S9000-ND SLOU260F – April 2009 – Revised January 2012 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated Schematics and Bill of Materials www.ti.com Table 1. Bill of Materials (continued) TSW1200EVM BOM – Revision: C QTY Reference Not Installed Part Foot Print Part Number Manufacturer Tol Volt Wat 1 J14 BANANA_JACK_BLK banana_jack ST-351B BLK Alectron Connectors 1 J15 BANANA_JACK_RED banana_jack ST-351B RED Alectron Connectors 2 J16, J22 HEADER 2 JUMPER2 22-28-4020 Molex 1 J17 HEADER 2 JUMPER2 22-28-4020 Molex 4 J18–J21 HDR 16×2 MALE 0.100CTR CON16X2_100ctr_M_alt TSW-116-07-L-D Samtec 0 L3 1K at 100 MHz smd_0805 BLM21AG102SN1D Murata 1 Q3 DTC114EET1 sc75 DTC114EET1 ON SEMI 1 RN1 4.7K RNET4_8_0603 EXB-V8V472JV Panasonic 5% 16 RN2, RN17 22 Ω rnet8_16_0603 742C163220JTR CTS 5% .063W 5 R1–R3, R31, R32 0Ω 603 ERJ-3GEY0R00V Panasonic 5% 1/10W 5 R4, R20, R43, R44, R59 10K 603 ERJ-3EKF1002V Panasonic 1% 1/10W 1 R6 4.7K 603 ERJ-3GEYJ472V Panasonic 5% 1/10W 5 R7, R39–R42 330 603 RC0603FR-07330RL Yageo 3 R13, R48, R51 100K 603 ERJ-3EKF1003V Panasonic 1% 1 R18 100K 603 ERJ-3EKF1003V Panasonic 1% 1/10W 1 R19 90.9K 603 ERJ-3EKF9092V Panasonic 1% 1/10W 1 R21 4.99K 603 ERJ-3EKF4991V Panasonic 1% 1/10W 1 R22 33K 603 RC0603FR-0733KL Yageo 1% 1/10W 1 R23 1.5K 603 ERJ-3EKF1501V Panasonic 1% 1/10W 1 R24 15K 603 ERJ-3EKF1502V Panasonic 1% 1/10W 2 R25, R26 33 Ω 603 RC0603FR-0733RL Yageo 1% 1/10W 8 R27–R30, R60–R63 22 603 RC0603FR-0722RL Yageo 1% 1/10W 6 R33, R34, R37, R38, R46, R47 1K 603 ERJ-3EKF1001V Panasonic 1% 1/10W 2 R35, R36 100 603 ERJ-3EKF1000V Panasonic 1% 1 R45 100K 603 ERJ-3EKF1003V Panasonic 1% 1/10W 1 R49 33.2K 603 ERJ-3EKF3322V Panasonic 1% 1/10W 1 R50 30.1K 603 ERJ-3EKF3012V Panasonic 1% 1/10W 1 R52 4.7K 603 ERA-V15J472V Panasonic 5% 1/16W 2 R53, R54 49.9 603 ERJ-3EKF49R9V Panasonic 1% 1/10W 0 R55 ZERO 603 ERJ-3GEY0R00V Panasonic 5% 1/10W 1 R58 24.3K 603 ERJ-3EKF2432V Panasonic 1% 1 R109 300 603 ERJ-3EKF3000V Panasonic 1 SW2 RESET SW_RESET_PTS635 PTS635SL43 ITT Industries/C&K Div 3 SW3–SW5 PROGRAM SW_RESET_PTS635 PTS635SL43 ITT Industries/C&K Div 1 TP7 T POINT R testpoint 5002 Keystone 1 U1 XC4VLX25-SF363-BGA MBGA_PT8MM_363 XC4VLX25-SF363-11BGA Xilinx TI Provide 1 U2 XCF16P/FSG48 MBGA_FS48_PT8MM XCF16PFSG48 Xilinx TI Provide 1 U5 TPS76933DBVT dbv5 TPS76933DBVT TI TI Provide 1 U6A TUSB3410IVF pqfp32 TUSB3410IVF TI TI Provide 1 U7 TPS73018-SOT23 DBV5 TPS73018DBVT TI TI Provide 1 U8 EEPROM 32K (4K x 8) DIP8_3 24LC32A-I/P Microchip 1 XU8 Socket, dip 8 DIP8_3 ED58083-ND DigiKey 1 U9 TPS76750QPWP HTSSOP_20_260x177_2 6_pwrpad TPS76750QPWP TI 1 U10 LV7745DEV-200MHz SMD_XTAL_7X5MM_6PI N LV7745DEV-200MHz PLETRONICS 2 U11, U13 TPS76733QPWP HTSSOP_20_260x177_2 6_pwrpad TPS76733QPWP TI NOT INSTALLED NOT INSTALLED SLOU260F – April 2009 – Revised January 2012 Submit Documentation Feedback Short pins with shunt connector DigiKey # S9000-ND 1/10W 1/10W 1/10W TI Provide TI Provide TSW1250EVM: High-Speed LVDS Deserializer and Analysis System Copyright © 2009–2012, Texas Instruments Incorporated 23 Circuit Board Layout and Layer Stackup www.ti.com Table 1. Bill of Materials (continued) TSW1200EVM BOM – Revision: C QTY Reference Not Installed Part Foot Print Part Number Manufacturer Tol Volt Wat 1 U12 TPS76701QPWP HTSSOP_20_260x177_2 6_pwrpad TPS76701QPWP TI TI Provide 1 U14 PTH03000W SMD_PWRMOD_EUT5 PTH03000WAS TI TI Provide 1 U15 TPS73225-SOT23 DBV5 TPS73225DBVT TI TI Provide 1 Y1 12MHz w/ 18pF smd_xtal_AMB3B ABM3B-12.000MHZ-10-1U-T Abracon 4 SCREW 4-40 X 3/8" PMS 440 0038 PH Building Fasteners 4 STANDOFF RD 4-40THR .875" ALUM 1846 Keystone 7 PCB legs Circuit Board Layout and Layer Stackup Figure 14. TSW1250C Layout Top Layer – Signal 24 TSW1250EVM: High-Speed LVDS Deserializer and Analysis System SLOU260F – April 2009 – Revised January 2012 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated Circuit Board Layout and Layer Stackup www.ti.com Figure 15. TSW1250C Layout Layer Two – GND1 SLOU260F – April 2009 – Revised January 2012 Submit Documentation Feedback TSW1250EVM: High-Speed LVDS Deserializer and Analysis System Copyright © 2009–2012, Texas Instruments Incorporated 25 Circuit Board Layout and Layer Stackup www.ti.com Figure 16. TSW1250C Layout Layer 3 – PWR1 26 TSW1250EVM: High-Speed LVDS Deserializer and Analysis System SLOU260F – April 2009 – Revised January 2012 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated Circuit Board Layout and Layer Stackup www.ti.com Figure 17. TSW1250C Layout Layer 4 – GND2 SLOU260F – April 2009 – Revised January 2012 Submit Documentation Feedback TSW1250EVM: High-Speed LVDS Deserializer and Analysis System Copyright © 2009–2012, Texas Instruments Incorporated 27 Circuit Board Layout and Layer Stackup www.ti.com Figure 18. TSW1250C Layout Layer 5 – Signal 28 TSW1250EVM: High-Speed LVDS Deserializer and Analysis System SLOU260F – April 2009 – Revised January 2012 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated Circuit Board Layout and Layer Stackup www.ti.com Figure 19. TSW1250C Layout Layer 6 – Signal SLOU260F – April 2009 – Revised January 2012 Submit Documentation Feedback TSW1250EVM: High-Speed LVDS Deserializer and Analysis System Copyright © 2009–2012, Texas Instruments Incorporated 29 Circuit Board Layout and Layer Stackup www.ti.com Figure 20. TSW1250C Layout Layer 7 – GND3 30 TSW1250EVM: High-Speed LVDS Deserializer and Analysis System SLOU260F – April 2009 – Revised January 2012 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated Circuit Board Layout and Layer Stackup www.ti.com Figure 21. TSW1250C Layout Layer 8 – PWR2 SLOU260F – April 2009 – Revised January 2012 Submit Documentation Feedback TSW1250EVM: High-Speed LVDS Deserializer and Analysis System Copyright © 2009–2012, Texas Instruments Incorporated 31 Circuit Board Layout and Layer Stackup www.ti.com Figure 22. TSW1250C Layer 9 – GND4 32 TSW1250EVM: High-Speed LVDS Deserializer and Analysis System SLOU260F – April 2009 – Revised January 2012 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated Circuit Board Layout and Layer Stackup www.ti.com Figure 23. TSW1250C Bottom Layer – Signal SLOU260F – April 2009 – Revised January 2012 Submit Documentation Feedback TSW1250EVM: High-Speed LVDS Deserializer and Analysis System Copyright © 2009–2012, Texas Instruments Incorporated 33 Circuit Board Layout and Layer Stackup www.ti.com Figure 24. Circuit Board Stackup 34 TSW1250EVM: High-Speed LVDS Deserializer and Analysis System SLOU260F – April 2009 – Revised January 2012 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated EVALUATION BOARD/KIT/MODULE (EVM) ADDITIONAL TERMS Texas Instruments (TI) provides the enclosed Evaluation Board/Kit/Module (EVM) under the following conditions: The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user indemnifies TI from all claims arising from the handling or use of the goods. Should this evaluation board/kit not meet the specifications indicated in the User’s Guide, the board/ kit may be returned within 30 days from the date of delivery for a full refund. THE FOREGOING LIMITED WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY SELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE, NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES. Please read the User's Guide and, specifically, the Warnings and Restrictions notice in the User's Guide prior to handling the product. This notice contains important safety information about temperatures and voltages. For additional information on TI's environmental and/or safety programs, please visit www.ti.com/esh or contact TI. No license is granted under any patent right or other intellectual property right of TI covering or relating to any machine, process, or combination in which such TI products or services might be or are used. TI currently deals with a variety of customers for products, and therefore our arrangement with the user is not exclusive. TI assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or services described herein. REGULATORY COMPLIANCE INFORMATION As noted in the EVM User’s Guide and/or EVM itself, this EVM and/or accompanying hardware may or may not be subject to the Federal Communications Commission (FCC) and Industry Canada (IC) rules. For EVMs not subject to the above rules, this evaluation board/kit/module is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION OR EVALUATION PURPOSES ONLY and is not considered by TI to be a finished end product fit for general consumer use. It generates, uses, and can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to part 15 of FCC or ICES-003 rules, which are designed to provide reasonable protection against radio frequency interference. Operation of the equipment may cause interference with radio communications, in which case the user at his own expense will be required to take whatever measures may be required to correct this interference. General Statement for EVMs including a radio User Power/Frequency Use Obligations: This radio is intended for development/professional use only in legally allocated frequency and power limits. Any use of radio frequencies and/or power availability of this EVM and its development application(s) must comply with local laws governing radio spectrum allocation and power limits for this evaluation module. It is the user’s sole responsibility to only operate this radio in legally acceptable frequency space and within legally mandated power limitations. Any exceptions to this is strictly prohibited and unauthorized by Texas Instruments unless user has obtained appropriate experimental/development licenses from local regulatory authorities, which is responsibility of user including its acceptable authorization. For EVMs annotated as FCC – FEDERAL COMMUNICATIONS COMMISSION Part 15 Compliant Caution This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate the equipment. FCC Interference Statement for Class A EVM devices This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a commercial environment. This equipment generates, uses, and can radiate radio frequency energy and, if not installed and used in accordance with the instruction manual, may cause harmful interference to radio communications. Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required to correct the interference at his own expense. REGULATORY COMPLIANCE INFORMATION (continued) FCC Interference Statement for Class B EVM devices This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures: • Reorient or relocate the receiving antenna. • Increase the separation between the equipment and receiver. • Connect the equipment into an outlet on a circuit different from that to which the receiver is connected. • Consult the dealer or an experienced radio/TV technician for help. For EVMs annotated as IC – INDUSTRY CANADA Compliant This Class A or B digital apparatus complies with Canadian ICES-003. Changes or modifications not expressly approved by the party responsible for compliance could void the user’s authority to operate the equipment. Concerning EVMs including radio transmitters This device complies with Industry Canada licence-exempt RSS standard(s). Operation is subject to the following two conditions: (1) this device may not cause interference, and (2) this device must accept any interference, including interference that may cause undesired operation of the device. Concerning EVMs including detachable antennas Under Industry Canada regulations, this radio transmitter may only operate using an antenna of a type and maximum (or lesser) gain approved for the transmitter by Industry Canada. To reduce potential radio interference to other users, the antenna type and its gain should be so chosen that the equivalent isotropically radiated power (e.i.r.p.) is not more than that necessary for successful communication. This radio transmitter has been approved by Industry Canada to operate with the antenna types listed in the user guide with the maximum permissible gain and required antenna impedance for each antenna type indicated. Antenna types not included in this list, having a gain greater than the maximum gain indicated for that type, are strictly prohibited for use with this device. Cet appareil numérique de la classe A ou B est conforme à la norme NMB-003 du Canada. Les changements ou les modifications pas expressément approuvés par la partie responsable de la conformité ont pu vider l’autorité de l'utilisateur pour actionner l'équipement. Concernant les EVMs avec appareils radio Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitation est autorisée aux deux conditions suivantes : (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit accepter tout brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le fonctionnement. Concernant les EVMs avec antennes détachables Conformément à la réglementation d'Industrie Canada, le présent émetteur radio peut fonctionner avec une antenne d'un type et d'un gain maximal (ou inférieur) approuvé pour l'émetteur par Industrie Canada. Dans le but de réduire les risques de brouillage radioélectrique à l'intention des autres utilisateurs, il faut choisir le type d'antenne et son gain de sorte que la puissance isotrope rayonnée équivalente (p.i.r.e.) ne dépasse pas l'intensité nécessaire à l'établissement d'une communication satisfaisante. Le présent émetteur radio a été approuvé par Industrie Canada pour fonctionner avec les types d'antenne énumérés dans le manuel d’usage et ayant un gain admissible maximal et l'impédance requise pour chaque type d'antenne. Les types d'antenne non inclus dans cette liste, ou dont le gain est supérieur au gain maximal indiqué, sont strictement interdits pour l'exploitation de l'émetteur. 【Important Notice for Users of this Product in Japan】 This development kit is NOT certified as Confirming to Technical Regulations of Radio Law of Japan If you use this product in Japan, you are required by Radio Law of Japan to follow the instructions below with respect to this product: 1. 2. 3. Use this product in a shielded room or any other test facility as defined in the notification #173 issued by Ministry of Internal Affairs and Communications on March 28, 2006, based on Sub-section 1.1 of Article 6 of the Ministry’s Rule for Enforcement of Radio Law of Japan, Use this product only after you obtained the license of Test Radio Station as provided in Radio Law of Japan with respect to this product, or Use of this product only after you obtained the Technical Regulations Conformity Certification as provided in Radio Law of Japan with respect to this product. Also, please do not transfer this product, unless you give the same notice above to the transferee. Please note that if you could not follow the instructions above, you will be subject to penalties of Radio Law of Japan. Texas Instruments Japan Limited (address) 24-1, Nishi-Shinjuku 6 chome, Shinjukku-ku, Tokyo, Japan http://www.tij.co.jp 【ご使用にあたっての注】 本開発キットは技術基準適合証明を受けておりません。 本製品のご使用に際しては、電波法遵守のため、以下のいずれかの措置を取っていただく必要がありますのでご注意ください。 1. 2. 3. 電波法施行規則第6条第1項第1号に基づく平成18年3月28日総務省告示第173号で定められた電波暗室等の試験設備でご使用い ただく。 実験局の免許を取得後ご使用いただく。 技術基準適合証明を取得後ご使用いただく。 なお、本製品は、上記の「ご使用にあたっての注意」を譲渡先、移転先に通知しない限り、譲渡、移転できないものとします。 　　　上記を遵守頂けない場合は、電波法の罰則が適用される可能性があることをご留意ください。 日本テキサス・インスツルメンツ株式会社 東京都新宿区西新宿６丁目２４番１号 西新宿三井ビル http://www.tij.co.jp SPACER SPACER SPACER SPACER SPACER SPACER SPACER SPACER SPACER SPACER SPACER SPACER SPACER SPACER SPACER SPACER EVALUATION BOARD/KIT/MODULE (EVM) WARNINGS, RESTRICTIONS AND DISCLAIMERS For Feasibility Evaluation Only, in Laboratory/Development Environments. Unless otherwise indicated, this EVM is not a finished electrical equipment and not intended for consumer use. It is intended solely for use for preliminary feasibility evaluation in laboratory/development environments by technically qualified electronics experts who are familiar with the dangers and application risks associated with handling electrical mechanical components, systems and subsystems. It should not be used as all or part of a finished end product. Your Sole Responsibility and Risk. You acknowledge, represent and agree that: 1. 2. 3. 4. You have unique knowledge concerning Federal, State and local regulatory requirements (including but not limited to Food and Drug Administration regulations, if applicable) which relate to your products and which relate to your use (and/or that of your employees, affiliates, contractors or designees) of the EVM for evaluation, testing and other purposes. You have full and exclusive responsibility to assure the safety and compliance of your products with all such laws and other applicable regulatory requirements, and also to assure the safety of any activities to be conducted by you and/or your employees, affiliates, contractors or designees, using the EVM. Further, you are responsible to assure that any interfaces (electronic and/or mechanical) between the EVM and any human body are designed with suitable isolation and means to safely limit accessible leakage currents to minimize the risk of electrical shock hazard. You will employ reasonable safeguards to ensure that your use of the EVM will not result in any property damage, injury or death, even if the EVM should fail to perform as described or expected. You will take care of proper disposal and recycling of the EVM’s electronic components and packing materials. Certain Instructions. It is important to operate this EVM within TI’s recommended specifications and environmental considerations per the user guidelines. Exceeding the specified EVM ratings (including but not limited to input and output voltage, current, power, and environmental ranges) may cause property damage, personal injury or death. If there are questions concerning these ratings please contact a TI field representative prior to connecting interface electronics including input power and intended loads. Any loads applied outside of the specified output range may result in unintended and/or inaccurate operation and/or possible permanent damage to the EVM and/or interface electronics. Please consult the EVM User's Guide prior to connecting any load to the EVM output. If there is uncertainty as to the load specification, please contact a TI field representative. During normal operation, some circuit components may have case temperatures greater than 60°C as long as the input and output are maintained at a normal ambient operating temperature. These components include but are not limited to linear regulators, switching transistors, pass transistors, and current sense resistors which can be identified using the EVM schematic located in the EVM User's Guide. When placing measurement probes near these devices during normal operation, please be aware that these devices may be very warm to the touch. As with all electronic evaluation tools, only qualified personnel knowledgeable in electronic measurement and diagnostics normally found in development environments should use these EVMs. Agreement to Defend, Indemnify and Hold Harmless. You agree to defend, indemnify and hold TI, its licensors and their representatives harmless from and against any and all claims, damages, losses, expenses, costs and liabilities (collectively, "Claims") arising out of or in connection with any use of the EVM that is not in accordance with the terms of the agreement. This obligation shall apply whether Claims arise under law of tort or contract or any other legal theory, and even if the EVM fails to perform as described or expected. Safety-Critical or Life-Critical Applications. If you intend to evaluate the components for possible use in safety critical applications (such as life support) where a failure of the TI product would reasonably be expected to cause severe personal injury or death, such as devices which are classified as FDA Class III or similar classification, then you must specifically notify TI of such intent and enter into a separate Assurance and Indemnity Agreement. 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