TSW14J10EVM

User's Guide SLAU580B – June 2014 – Revised September 2016 TSW14J10 FMC-USB Interposer Card This user's guide describes the functionality, hardware, operation, and software instructions for the TSW14J10 FMC-USB interposer card. Throughout this document, the abbreviations TSW14J10EVM, EVM, and the term evaluation module are synonymous with the TSW14J10 Evaluation Module, unless otherwise noted. 1 2 3 4 5 6 Contents Introduction ................................................................................................................... 2 Functionality .................................................................................................................. 2 Hardware Configuration ..................................................................................................... 4 3.1 Power Connections ................................................................................................ 4 3.2 Jumpers .............................................................................................................. 4 3.3 Connectors .......................................................................................................... 5 Software Start Up ............................................................................................................ 9 4.1 Installation Instructions ............................................................................................. 9 4.2 USB Interface and Drivers ....................................................................................... 11 Downloading Firmware Example ......................................................................................... 13 DAC and ADC GUI Configuration File Changes When Using a Xilinx Development Platform .................. 15 6.1 DAC38J84EVM with Xilinx VC707 Development Board Setup Example .................................. 16 6.2 ADC32RF45EVM With Xilinx VC707 Development Board Setup Example ............................... 21 6.3 ADC12J4000EVM With Xilinx VC707 Development Board Setup Example .............................. 25 6.4 ADC12J4000EVM With a Xilinx Zynq ZC706 Development Board Setup Example...................... 30 6.5 DAC38J84EVM With a Xilinx Zynq ZC706 Development Board Setup Example......................... 32 List of Figures 1 TSW14J10EVM, ADS42JB69EVM, and Kintex KC705 Development Card ......................................... 3 2 TSW14J10 EVM Block Diagram ........................................................................................... 4 3 GUI Installation ............................................................................................................... 9 4 TSW14J10EVM Serial Number 5 6 7 8 9 10 11 12 13 14 15 16 17 18 .......................................................................................... High Speed Data Converter Pro GUI Top Level ....................................................................... Hardware Device Manager ............................................................................................... DAC38J84EVM GUI Setup Example .................................................................................... Quick Start Menu ........................................................................................................... LMK04828 Clock Outputs Menu ......................................................................................... LMK04828 Clock Outputs Menu ......................................................................................... HSDC Pro GUI ............................................................................................................. HSDC Pro GUI: Lane Rate and REFCLK Settings .................................................................... ADC32RF45EVM, TSW14J10EVM and VC707 Board ............................................................... ADC32RFxx GUI LMK0828 Clock Outputs Tab ....................................................................... Updated LMK0828 Clock Outputs Tab .................................................................................. HSDC Pro GUI ............................................................................................................. Captured Results for Channel A ......................................................................................... ADC12J4000EVM, TSW14J10EVM and VC707 Board ............................................................... 11 11 12 16 17 18 19 20 20 21 22 23 23 24 25 Altera is a registered trademark of Altera Corporation. Xilinx, Kintex are registered trademarks of Xilinx Corporation. SLAU580B – June 2014 – Revised September 2016 Submit Documentation Feedback TSW14J10 FMC-USB Interposer Card Copyright © 2014–2016, Texas Instruments Incorporated 1 Introduction www.ti.com 19 ADC12J4000EVM GUI .................................................................................................... 26 20 LMK04828 Address 0x100 ................................................................................................ 27 21 LMK04828 Address 0x110 ................................................................................................ 28 22 HSDC Pro GUI 23 24 25 26 27 28 29 ............................................................................................................. Captured Results for the ADC12J4000 in Bypass Mode ............................................................ ADC12J4000EVM, TSW14J10EVM and ZC706 board ............................................................... Captured Results for the ADC12J4000 in Bypass Mode ............................................................ DAC38J84EVM, TSW14J10EVM and ZC706 Board .................................................................. Serial Number Selection Window ........................................................................................ HSDC Pro GUI ............................................................................................................. HSDC Pro GUI ............................................................................................................. 28 29 30 31 32 33 34 34 List of Tables TSW14J10 Jumper Descriptions 5 2 FPGA FMC Connector (J5) Description of the TSW14J10 5 3 1 .......................................................................................... ............................................................ ADC/DAC EVM FMC Connector (J4) Description of the TSW14J10 ................................................. 1 7 Introduction The Texas Instruments TSW14J10 Evaluation Module (EVM) allows users to operate the High Speed Data Converter Pro Graphic User Interface (HSDC Pro GUI) Software on certain Xilinx® and Altera® development kits that incorporate the FMC connector. This FMC-FMC adapter has a four bus FTDI USBto-GPIO device, that when connected to a PC, provides an interface to the FPGA on the development platform allowing the HSDC Pro GUI to operate as if it were connected to a TI development board. The TSW14J10 is compatible with all TI ADC and DAC JESD204B-based EVMs. Contact FPGA vendors for other available firmware not provided by HSDC Pro Software to test ADC and DAC EVMs with their development platform. 2 Functionality The TSW14J10 uses two industry standard FMC connectors that provide an interface between an FMCbased development board and all TI JESD204B ADC and DAC EVMs. To acquire data, receive data, and do register read and writes using a host PC, the FPGA transmits and receives data across three Serial Peripheral Interface (SPI) busses using dedicated pins on the FMC that connect to the FTDI on the TSW14J10. The fourth bus connects to a JTAG connector. When connecting the provided cable between this connector and a JTAG connecter on a FPGA development platform, the HSDC Pro GUI can be used to configure the FPGA. This interface is also routed to the FMC connector when setting jumpers to the appropriate configuration (see Table 1). The TSW14J10 routes the SPI busses through level translators that allow the signals going to the FPGA development board and the ADC/DAC EVM to be either 3.3-V or 1.8-V levels. All devices on the TSW14J10 are powered from the USB connection. Figure 1 shows an ADS42JB69EVM connected to a Xilinx Kintex® KC705 development board using a TSW14J10EVM. 2 TSW14J10 FMC-USB Interposer Card SLAU580B – June 2014 – Revised September 2016 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Functionality www.ti.com Figure 1. TSW14J10EVM, ADS42JB69EVM, and Kintex KC705 Development Card The major features of the TSW14J10 are: • 10 transceiver lanes with speeds up to 12.5 Gbps • Industry-standard JTAG connector • Supports 1.8-V, 3.3-V CMOS IO interface • Onboard FT4232HL USB device for JTAG, SPI interface • Supported by TI HSDC PRO software • 2 Samtec high-speed, high-density FMC connectors SLAU580B – June 2014 – Revised September 2016 Submit Documentation Feedback TSW14J10 FMC-USB Interposer Card Copyright © 2014–2016, Texas Instruments Incorporated 3 Hardware Configuration www.ti.com Figure 2 shows a block diagram of the TSW14J10 EVM. FPGA Development Board FMC CONNECTOR JTAG Connector Level Translators JESD204B Interface Data, Device CLK, SYSREF, SYNC, GPIO TSW14J10 EVM USB to SERIAL USB PORT FMC CONNECTOR ADC or DAC EVM Figure 2. TSW14J10 EVM Block Diagram 3 Hardware Configuration In this section, the various portions of the TSW14J10EVM hardware are described. The TSW14J10EVM comes with a 10 pin ribbon cable that is used as a programming option for the FPGA on the FPGA Development Board, plastic screws and nuts to secure the three boards together, and stand-off extenders to be used on the ADC/DAC EVM due to the new height of the interface FMC connector. 3.1 Power Connections The TSW14J10EVM hardware is designed to operate from a single-supply voltage of +5 VDC. By default, this power input is provided by the USB connection. A second option is to provide external +5 V to test point TP12 and shunt pins 1-2 on JP1. This will remove the USB power from the +5-V power traces and connect it to TP12. The external source should be able to provided 0.5 A. 3.2 Jumpers The TSW14J10 contains several jumpers (JP) and solder jumpers (SJP) that enable certain functions on the board. The description of the jumpers are found in Table 1. In addition to the jumpers, there are several 0 Ohm resistors that are used as jumpers. If using the TSW14J10EVM with the Xilinx ZC706 and a TI DAC EVM, the following resistors need to be removed or installed to route the SYNC signals from the DAC EVM to the correct pins on the ZC706 board: Install R142, R144, R146 and R148 Remove R143 and R145 4 TSW14J10 FMC-USB Interposer Card SLAU580B – June 2014 – Revised September 2016 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Hardware Configuration www.ti.com Table 1. TSW14J10 Jumper Descriptions 3.3 3.3.1 Component Description Default JP1 USB power select. Default is power from the USB interface. 2-3 JP2–JP5 FTDI connected to JTAG connector or FMC. Default is JTAG connector. 1-2 JP6 Translator voltage level select (1.8 V or 3.3 V). Default is 3.3 V. 2-3 SJP1 Direction control for buffer U9. Default is A to B. 1-2 SJP2 Direction control for buffer U10. Default is B to A. 2-3 SJP3 Direction control for buffer U11. Default is B to A. 2-3 Connectors FPGA Development Platform FMC Connector The TSW14J10 EVM has one FPGA Mezzanine Card Connector (FMC) to allow for direct plug in of a TI JESD204B serial interface ADC or DAC EVM and another to plug into an FPGA development board. The specifications for this connector were mostly derived from the ANSI/VITA 57.1 FPGA Mezzanine Card Standard. This standard describes the compliance requirements for a low overhead protocol bridge between a carrier card’s IO and an FPGA processing device on a carrier card. This specification is being used by FPGA vendors on their development platforms. FMC connector J5 provides the interface between the TSW14J10EVM and a FPGA development platform. This 400-pin Samtec high-speed, high- density connector, part number SEAF-40-05.0-S-10-2-A-K, is suitable for high-speed differential pairs up to 21 Gbps. In addition to the JESD204B standard signals, 13 CMOS single-ended signals are sourced from the USB interface to the FMC connector. These signals are used by the HSDC Pro GUI to program internal registers and read and write data to the FPGA. The connector pinout description is shown in Table 2. Table 2. FPGA FMC Connector (J5) Description of the TSW14J10 FMC Signal Name FMC Pin Standard JESD204 Application Mapping Description DP0_M2C_P/N C6/C7 Lane 0+/- (M->C) JESD Serial data transmitted from Mezzanine and received by Carrier DP1_M2C_P/N A2/A3 Lane 1+/- (M->C) JESD Serial data transmitted from Mezzanine and received by Carrier DP2_M2C_P/N A6/A7 Lane 2+/- (M->C) JESD Serial data transmitted from Mezzanine and received by Carrier DP3_M2C_P/N A10/A11 Lane 3+/- (M->C) JESD Serial data transmitted from Mezzanine and received by Carrier DP4_M2C_P/N A14/A15 Lane 4+/- (M->C) JESD Serial data transmitted from Mezzanine and received by Carrier DP5_M2C_P/N A18/A19 Lane 5+/- (M->C) JESD Serial data transmitted from Mezzanine and received by Carrier DP6_M2C_P/N B16/B17 Lane 6+/- (M->C) JESD Serial data transmitted from Mezzanine and received by Carrier DP7_M2C_P/N B12/B13 Lane 7+/- (M->C) JESD Serial data transmitted from Mezzanine and received by Carrier DP8_M2C_P/N B8/B9 Lane 8+/- (M->C) JESD Serial data transmitted from Mezzanine and received by Carrier DP9_M2C_P/N B4/B5 Lane 9+/- (M->C) JESD Serial data transmitted from Mezzanine and received by Carrier DP0_C2M_P/N C2/C3 Lane 0+/- (C->M) JESD Serial data transmitted from Carrier and received by Mezzanine DP1_C2M_P/N A22/A23 Lane 1+/- (C->M) JESD Serial data transmitted from Carrier and received by Mezzanine DP2_C2M_P/N A26/A27 Lane 2+/- (C->M) JESD Serial data transmitted from Carrier and received by Mezzanine DP3_C2M_P/N A30/A31 Lane 3+/- (C->M) JESD Serial data transmitted from Carrier and received by Mezzanine DP4_C2M_P/N A34/A35 Lane 4+/- (C->M) JESD Serial data transmitted from Carrier and received by Mezzanine DP5_C2M_P/N A38/A39 Lane 5+/- (C->M) JESD Serial data transmitted from Carrier and received by Mezzanine DP6_C2M_P/N B36/B37 Lane 6+/- (C->M) JESD Serial data transmitted from Carrier and received by Mezzanine DP7_C2M_P/N B32/B33 Lane 7+/- (C->M) JESD Serial data transmitted from Carrier and received by Mezzanine DP8_C2M_P/N B28/B29 Lane 8+/- (C->M) JESD Serial data transmitted from Carrier and received by Mezzanine DP9_C2M_P/N B24/B25 Lane 9+/- (C->M) JESD Serial data transmitted from Carrier and received by Mezzanine GTX_CLKP/M D4/D5 DEVCLKA+/- (M->C) Primary carrier-bound reference clock required for FPGA gigabit transceivers. Equivalent to device clock. Standard JESD204 Application Mapping Description Device Clock, SYSREF, and SYNC FMC Signal Name FMC Pin SLAU580B – June 2014 – Revised September 2016 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated TSW14J10 FMC-USB Interposer Card 5 Hardware Configuration www.ti.com Table 2. FPGA FMC Connector (J5) Description of the TSW14J10 (continued) CLK_LA0_P/N G6/G7 DEVCLKB+/- (M->C) Secondary carrier-bound device clock. Used for special FPGA functions such as sampling SYSREF. D8/D9 D8/D9 DEVCLK+/- (C->M) Mezzanine-bound device Clock. Used for low noise conversion clock. CAR_SYSREFP/M G9/G10 SYSREF+/- (M->C) Carrier-bound SYSREF signal D11/D12 D11/D12 SYSREF+/- (C->M) Mezzanine-bound SYSREF signal SYNCP/M G12/G13 SYNC+/- (C>M) ADC Mezzanine-bound SYNC signal for use in class 0/1/2 JESD204 systems DAC_SYNC_P/M F10/F11 DAC SYNC+/- (M>C) Carrier-bound SYNC signal for use in class 0/1/2 JESD204 systems. ALT_DAC_SYNC_PM F19/F20 Alt. DAC SYNC+/- (M>C) Alternate Carrier-bound SYNC signal for use in class 0/1/2 JESD204B systems. ALT_SYNCP/M H31/H32 Alt. SYNC+/- (C>M) Alternate ADC Mezzanine-bound SYNC signal. For use when SYNC (C->M) is not available. SYNC K22 DAC SYNC (M>C) Alternate Carrier-bound CMOS level SYNC signal for use in class 0/1/2 JESD204 systems. FMC Signal Name FMC Pin Direction Description F1 F1 D1 D1 PRESENT H2 ADC/DAC-to-FPGA EVM Present indicator ADBUS0_T C14 USB-to-FPGA USB SPI Interface signal ADBUS1_T C15 USB-to-FPGA USB SPI Interface signal ADBUS2_T H8 FPGA-to-USB USB SPI Interface signal ADBUS3_T D14 USB-to-FPGA USB SPI Interface signal ADBUS4_T C10 USB-to-FPGA USB SPI Interface signal BDBUS0_T D15 USB-to-FPGA USB SPI Interface signal BDBUS1_T G15 USB-to-FPGA USB SPI Interface signal BDBUS2_T H10 FPGA-to-USB USB SPI Interface signal BDBUS3_T G16 USB-to-FPGA USB SPI Interface signal CDBUS0_T H16 USB-to-FPGA USB SPI Interface signal CDBUS1_T H17 USB-to-FPGA USB SPI Interface signal CDBUS2_T H11 FPGA-to-USB USB SPI Interface signal CDBUS3_T H7 USB-to-FPGA USB SPI Interface signal TCK D29 USB-to-JTAG JTAG connector clock TDI D30 USB-to-JTAG JTAG connector TDI TDO D31 JTAG-to-USB JTAG connector TDO TMS D33 USB-to-JTAG JTAG connector TMS OVRA K19 ADC-to-FPGA ADC over range indicator OVRB E18 ADC-to-FPGA ADC over range indicator OVRC J22 ADC-to-FPGA ADC over range indicator OVRD J21 ADC-to-FPGA ADC over range indicator DAC-SYNC+/- E2/E3 DAC-to-FPGA Spare sync FPGA_CLK2P/N J2/J3 FPGA-to-DAC Spare clock FPGA_CLK1P/N K4/K5 FPGA-to-DAC Spare clock LED_SYNC1 C18 FPGA-to-ADC SYNC LED indicator SPLED0 D17 FPGA-to-ADC Spare LED SPLED1 D18 FPGA-to-ADC Spare LED C19 C19 Spare connection C26 C26 Spare connection C27 C27 Spare connection D26 D26 Spare connection E19 E19 Spare connection G27 G27 Spare connection Special Purpose I/O 6 TSW14J10 FMC-USB Interposer Card Power good from mezzanine to carrier Power good from carrier to mezzanine SLAU580B – June 2014 – Revised September 2016 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Hardware Configuration www.ti.com Table 2. FPGA FMC Connector (J5) Description of the TSW14J10 (continued) 3.3.2 G36 G36 Spare connection G37 G37 Spare connection H37 H37 Spare connection H38 H38 Spare connection ADC/DAC FMC Connector FMC connector J4 provides the interface between the TSW14J10EVM and an ADC or DAC EVM. In addition to the JESD204B standard signals, 8 CMOS single-ended signals are sourced from the USB interface to the FMC connector. These signals are used to allow the HSDC Pro GUI to control the SPI serial programming of an ADC or DAC EVM that supports this feature. Several other spare signals are available that connect between this connector and the FPGA FMC connector. The connector pinout description is shown in Table 3. Table 3. ADC/DAC EVM FMC Connector (J4) Description of the TSW14J10 FMC Signal Name FMC Pin Standard JESD204 Application Mapping Description DP0_M2C_P/N C6/C7 Lane 0+/- (M->C) JESD Serial data transmitted from Mezzanine and received by Carrier DP1_M2C_P/N A2/A3 Lane 1+/- (M->C) JESD Serial data transmitted from Mezzanine and received by Carrier DP2_M2C_P/N A6/A7 Lane 2+/- (M->C) JESD Serial data transmitted from Mezzanine and received by Carrier DP3_M2C_P/N A10/A11 Lane 3+/- (M->C) JESD Serial data transmitted from Mezzanine and received by Carrier DP4_M2C_P/N A14/A15 Lane 4+/- (M->C) JESD Serial data transmitted from Mezzanine and received by Carrier DP5_M2C_P/N A18/A19 Lane 5+/- (M->C) JESD Serial data transmitted from Mezzanine and received by Carrier DP6_M2C_P/N B16/B17 Lane 6+/- (M->C) JESD Serial data transmitted from Mezzanine and received by Carrier DP7_M2C_P/N B12/B13 Lane 7+/- (M->C) JESD Serial data transmitted from Mezzanine and received by Carrier DP8_M2C_P/N B8/B9 Lane 8+/- (M->C) JESD Serial data transmitted from Mezzanine and received by Carrier DP9_M2C_P/N B4/B5 Lane 9+/- (M->C) JESD Serial data transmitted from Mezzanine and received by Carrier DP0_C2M_P/N C2/C3 Lane 0+/- (C->M) JESD Serial data transmitted from Carrier and received by Mezzanine DP1_C2M_P/N A22/A23 Lane 1+/- (C->M) JESD Serial data transmitted from Carrier and received by Mezzanine DP2_C2M_P/N A26/A27 Lane 2+/- (C->M) JESD Serial data transmitted from Carrier and received by Mezzanine DP3_C2M_P/N A30/A31 Lane 3+/- (C->M) JESD Serial data transmitted from Carrier and received by Mezzanine DP4_C2M_P/N A34/A35 Lane 4+/- (C->M) JESD Serial data transmitted from Carrier and received by Mezzanine DP5_C2M_P/N A38/A39 Lane 5+/- (C->M) JESD Serial data transmitted from Carrier and received by Mezzanine DP6_C2M_P/N B36/B37 Lane 6+/- (C->M) JESD Serial data transmitted from Carrier and received by Mezzanine DP7_C2M_P/N B32/B33 Lane 7+/- (C->M) JESD Serial data transmitted from Carrier and received by Mezzanine DP8_C2M_P/N B28/B29 Lane 8+/- (C->M) JESD Serial data transmitted from Carrier and received by Mezzanine DP9_C2M_P/N B24/B25 Lane 9+/- (C->M) JESD Serial data transmitted from Carrier and received by Mezzanine GTX_CLKP/M D4/D5 DEVCLKA+/- (M->C) Primary carrier-bound reference clock required for FPGA gigabit transceivers. Equivalent to device clock. Device Clock, SYSREF, and SYNC FMC Signal Name FMC Pin Standard JESD204 Application Mapping Description CLK_LA0_P/N G6/G7 DEVCLKB+/- (M->C) Secondary carrier-bound device clock. Used for special FPGA functions such as sampling SYSREF. D8/D9 D8/D9 DEVCLK+/- (C->M) Mezzanine-bound device clock. Used for low noise conversion clock. CAR_SYSREFP/M G9/G10 SYSREF+/- (M->C) Carrier-bound SYSREF signal D11/D12 D11/D12 SYSREF+/- (C->M) Mezzanine-bound SYSREF signal SYNCP/M G12/G13 SYNC+/- (C>M) ADC Mezzanine-bound SYNC signal for use in class 0/1/2 JESD204 systems DAC_SYNC_P/M F10/F11 DAC SYNC+/- (M>C) Carrier-bound SYNC signal for use in class 0/1/2 JESD204 systems ALT_DAC_SYNC_PM F19/F20 Alt. DAC SYNC+/- (M>C) Alternate Carrier-bound SYNC signal for use in class 0/1/2 JESD204B systems ALT_SYNCP/M H31/H32 Alt. SYNC+/- (C>M) Alternate ADC Mezzanine-bound SYNC signal. For use when SYNC (C->M) is not available. Special Purpose I/O SLAU580B – June 2014 – Revised September 2016 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated TSW14J10 FMC-USB Interposer Card 7 Hardware Configuration www.ti.com Table 3. ADC/DAC EVM FMC Connector (J4) Description of the TSW14J10 (continued) 3.3.3 FMC Signal Name FMC Pin Direction Description F1 F1 ADC/DAC-to-FPGA Power good from mezzanine to carrier D1 D1 FPGA-to-ADC/DAC Power good from carrier to mezzanine PRESENT H2 ADC/DAC-to-FPGA EVM Present indicator ADBUS5_T C15 USB-to-ADC/DAC USB SPI Interface signal ADBUS6_T D14 USB-to-ADC/DAC USB SPI Interface signal ADBUS7_T D15 USB-to-ADC/DAC USB SPI Interface signal BDBUS4_T G15 USB-to-ADC/DAC USB SPI Interface signal BDBUS5_T G16 USB-to-ADC/DAC USB SPI Interface signal BDBUS6_T H16 USB-to-ADC/DAC USB SPI Interface signal BDBUS7_T H17 USB-to-ADC/DAC USB SPI Interface signal CDBUS4_T C14 USB-to-ADC/DAC USB SPI Interface signal OVRA K19 ADC-to-FPGA ADC over range indicator OVRB E18 ADC-to-FPGA ADC over range indicator OVRC J22 ADC-to-FPGA ADC over range indicator OVRD J21 ADC-to-FPGA ADC over range indicator FPGA_CLK2P/N J2/J3 FPGA-to-DAC Spare clock FPGA_CLK1P/N K4/K5 FPGA-to-DAC Spare clock LED_SYNC1 C18 FPGA-to-ADC SYNC LED indicator SPLED0 D17 FPGA-to-ADC Spare LED SPLED1 D18 FPGA-to-ADC Spare LED C19 C19 Spare connection C26 C26 Spare connection C27 C27 Spare connection D26 D26 Spare connection E19 E19 Spare connection G27 G27 Spare connection G36 G36 Spare connection G37 G37 Spare connection H37 H37 Spare connection H38 H38 Spare connection K20 K20 Spare connection K23 K23 Spare connection JTAG Connector The TSW14J10EVM includes an industry-standard JTAG connector that is connected to the DDBUS of the USB interface device. This interface allows the HSDC Pro GUI the capability to configure an FPGA on a development platform if it has a corresponding JTAG connector that is routed directly to the FPGA JTAG pins. Connect the provide JTAG cable between the TSW14J10 JTAG connector and the FPGA development board JTAG connector. NOTE: FPGA development boards may require jumpers and or switches be placed in a certain configuration to connect the JTAG connector to the FPGA JTAG pins. If the FPGA development platform has the JTAG signals routed on the FMC connector, jumpers JP2-5 can be set (shunt pins 2-3) to route these signals to the FMC connector instead of the JTAG connector. 8 TSW14J10 FMC-USB Interposer Card SLAU580B – June 2014 – Revised September 2016 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Software Start Up www.ti.com 3.3.4 USB I/O Connection HSDC Pro GUI control is accomplished through USB connector J3. This will provide the interface between HSDC Pro GUI running on a PC Windows operating system and a FPGA development platform. For the computer, the drivers needed to access the USB port are included in the HSDC Pro GUI installation software. The drivers are automatically installed during the installation process. On the TSW14J10EVM, the USB port is used to identify the type and serial number of the EVM under test, load the desired FPGA configuration file, capture ADC EVM data from the FPGA, and send test pattern data to the FPGA for DAC EVM testing. 4 Software Start Up 4.1 Installation Instructions Download the latest version of the HSDC Pro GUI (slwc107x.zip) to a local directory on a host PC. This can be found on the TI website by entering “HIGH SPEED DATA CONVERTER PRO GUI INSTALLER” or “TSW14J10EVM” in the search parameter window at www.ti.com. Unzipping the software package generates a folder called High Speed Data Converter Pro - Installer vx.xx.exe, where x.xx is the version number. Run this program to start the installation Follow the on-screen instructions during installation. NOTE: If an older version of the GUI has already been installed, make sure to uninstall it before loading a newer version. Figure 3. GUI Installation Make sure to disconnect all USB cables from any TSW14xxx boards before installing the software. Click on the Install button. A new window opens. Click the Next button. Accept the License Agreement. Click on Next to start the installation. After the installer has finished, click on Next one last time. The installation is now complete. The GUI executable and associated files will reside in the following directory. "C:\Program Files (x86)\Texas Instruments\High Speed Data Converter Pro" SLAU580B – June 2014 – Revised September 2016 Submit Documentation Feedback TSW14J10 FMC-USB Interposer Card Copyright © 2014–2016, Texas Instruments Incorporated 9 Software Start Up www.ti.com When new TI High Speed Data Converter EVM's or JESD204B interface modes become available that are not currently supported by the latest release of HSDC Pro GUI, the HSDCProv_xpxx_Patch_setup executable, available on the TI website under the High Speed Data Converter Pro Software product folder (http://www.ti.com/tool/dataconverterpro-sw), will allow the user to add these to the GUI device list. After the patch has been downloaded, follow the on screen instructions to run the patch. The software will display the files that will be added. After running the patch, go ahead and open HSDC Pro and the new parts and modes will appear in the ADC and DAC device drop down selection box. The patch is always specific to a core GUI version and will not work for a GUI version that the patch was not explicitly created for. 10 TSW14J10 FMC-USB Interposer Card SLAU580B – June 2014 – Revised September 2016 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Software Start Up www.ti.com 4.2 USB Interface and Drivers Connect a USB cable between J3 of the TSW14J10EVM and a host PC. Click on the High Speed Data Converter Pro icon that was created on the desktop panel or go to "C:\Program Files (x86)\Texas Instruments\High Speed Data Converter Pro" and double click on the executable called High Speed Data Converter Pro.exe to start the GUI. The GUI first attempts to connect to the EVM USB interface. If the GUI identifies a valid board serial number, a pop-up opens displaying this value, as shown in Figure 4. It is possible to connect several TSW14J10 EVMs to one host PC but the GUI can only connect to one at a time. In the case where multiple boards are connected to the PC, the pop-up will display all of the serial numbers found. The user then selects which board the GUI will be associated with. Figure 4. TSW14J10EVM Serial Number Click on the OK button to connect the GUI to the board. The top-level GUI opens and appears as shown in Figure 5. Figure 5. High Speed Data Converter Pro GUI Top Level If the message No Board Connected opens, double check the USB cable connection. If the cable connection appears fine, try establishing a connection by clicking on the Instrument Option tab at the top left of the GUI and select Connect to the Board. If this still does not correct this issue, check the status of the host USB port. SLAU580B – June 2014 – Revised September 2016 Submit Documentation Feedback TSW14J10 FMC-USB Interposer Card Copyright © 2014–2016, Texas Instruments Incorporated 11 Software Start Up www.ti.com When the software is installed and the USB cable has been connected to the TSW14J10EVM and the PC, the TSW14J10 USB serial converter should be located in the Hardware Device Manager under the Universal Serial Bus controllers as shown in Figure 6. This is a quad device which is why there is an A, B, C, and D USB serial converter shown. When the USB cable is removed, these four will no longer be visible in the Device Manager. If the drivers are present in the Device Manager window and the software still does not connect, cycle power to the board and repeat the previous steps. Figure 6. Hardware Device Manager 12 TSW14J10 FMC-USB Interposer Card SLAU580B – June 2014 – Revised September 2016 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Downloading Firmware Example www.ti.com 5 Downloading Firmware Example If the FPGA development platform is to be programmed using the TSW14J10EVM, either connect the provided ribbon cable between the TSW14J10 JTAG connector and the FPGA development platform JTAG connector or move the shunts on JP2–JP5 to pins 2-3 if the JTAG signals are routed to the FMC connector. The HSDC Pro GUI software provides support for certain FPGAs and modes of operation. The firmware files needed are special .svf formatted files for Xilinx devices and .rbf formatted files for Altera devices. The files used by the GUI currently reside in the directory called "C:\Program Files (x86)\Texas Instruments\High Speed Data Converter Pro\14J10KC705 Details\ Firmware" for the Xilinx Kintex KC705 board, "C:\Program Files (x86)\Texas Instruments\High Speed Data Converter Pro\14J10VC707 Details\ Firmware" for the Xilinx Virtex VC707 board, and "C:\Program Files (x86)\Texas Instruments\High Speed Data Converter Pro\14J10ZC706 Details\ Firmware" for the Xilinx Zync ZC706 board. To load a Xilinx KC705 development platform firmware after the GUI has established connection (setup as shown in Figure 1), click on the Select ADC window in the top left of the GUI and select ADS42JB69_LMF_421, as shown in Figure 5. The GUI asks if you want to update the Firmware for the ADC. Click on Yes. The GUI starts loading the firmware from the PC to the Xilinx Kintex 7 FPGA. While the firmware is loading, the GPIO LED's on the FPGA platform will all be on. This process takes about 2 minutes. Once completed, the INIT LED (DS21) and DONE LED (DS20) will illuminate on the KC705. After the ADS42JBx9EVM is programmed, the KC705 GPIO LED status will be as follows: 0 – On (DAC SYNC indicator) 1 – On (ADC SYNC indicator) 2 – Off (JESD reset) 3 – On (ADC JESD mode enabled) 4 – Off (DAC JESD mode enabled) 5 – Blinking (System clock divided down) 6 – Blinking (JESD Core clock divided down) 7 – Blinking (Reference clock divided down) These same status LED's apply to the Xilinx VC707 development platform. For the Xilinx Zync ZC706 platform, only three status LED's are used. After this board is programmed and running with an ADC or DAC, the status of the GPIO LED's will be as follows: L - Blinking (Reference clock divided down) C - Blinking (JESD Core clock divided down) R - Blinking (System clock divided down) If the ADS42Jx9EVM is not programmed, the GPIO LED status is as follows: 0 – On (DAC SYNC indicator) 1 – Off (ADC SYNC indicator) 2 – On (JESD reset) 3 – Off (ADC JESD mode enabled) 4 – Off (DAC JESD mode enabled) 5 – Blinking (System clock divided down) 6 – N/A (JESD Core clock divided down) 7 – N/A (Reference clock divided down) SLAU580B – June 2014 – Revised September 2016 Submit Documentation Feedback TSW14J10 FMC-USB Interposer Card Copyright © 2014–2016, Texas Instruments Incorporated 13 Downloading Firmware Example www.ti.com If the two boards are not synchronized after both have been configured, this is indicated by GPIO LED 2 being Off on the KC705 board and D3 being On on the ADS42JB69EVM. Pressing the CPU reset (SW7) on the KC705 board resets the JESD204B link and should synchronize the two boards. After synchronization has been established, enter a valid sampling rate in the HSDC Pro GUI and click on Capture to display valid data from the ADC EVM. For information regarding the use of the TSW14J10EVM with a TI ADC or DAC JESD204B serial interface EVM, consult the High Speed Data Converter Pro GUI User’s Guide (SLWU087) along with the individual EVM User’s Guide. 14 TSW14J10 FMC-USB Interposer Card SLAU580B – June 2014 – Revised September 2016 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated www.ti.com 6 DAC and ADC GUI Configuration File Changes When Using a Xilinx Development Platform DAC and ADC GUI Configuration File Changes When Using a Xilinx Development Platform The configuration files that come with the TI ADC and DAC EVM GUIs are setup to operate with the Altera-based TI TSW14J56EVM. These files will work with the TSW14J10EVM when using a Xilinx platform but need a couple of changes to the settings of the LMK04828 registers. The firmware for the Xilinx Development Platforms use a separate clock input for REFCLK and Core clock to give maximum flexibility and support all line rates and subclasses with a single programmable design. The Xilinx IP used in the firmware can be driven by a single clock in many circumstances (see the clocking section of the Xilinx IP product guide for more details). The REFCLK and Core clock are determined by the following lane rate conditions: REFCLK = Lane rate / 10, and Core clock = Lane rate / 10 when lane rate is between 1 G and 3.2 G REFCLK = Lane rate / 20 and Core clock = Lane rate / 40 when lane rate is between 3.2 G and 10.3125 G* Note: The GTEX2 transceivers with speed grade -2 devices used on the Xilinx development platforms have a maximum rate of 10.3125 Gbps. In addition, the KC705 transceivers have a frequency band gap from 8 Gbps to 9.8 Gbps. The ADC and DAC GUIs do not always use the same LMK04828 outputs for these two clocks. The output from the LMK04828 connected to FMC connector pins D4 and D5 will be the REFCLK. The output from the LMK04828 connected to FMC connector pins G6 and G7 will be the Core clock. Consult the EVM schematic to verify the outputs. On the KC705 platform, only 4 TX and 4 RX JESD204B lanes were routed to the HPC FMC connector. On the VC707 and ZC706, there are at least 8 RX and TX lanes routed. The Xilinx firmware designed to be used with the TSW14J10EVM running HSDC Pro GUI uses internal FPGA memory only. Due to both of these constraints, the user must be careful when selecting the number of samples and number of lanes to be used in both ADC and DAC testing. The total memory and JESD204B lanes that are available are as follows: KC705 4 lanes RX and TX 128K total samples VC707 8 lanes RX and TX 256K total samples ZC706 8 lanes RX and TX 128K total samples For example when using the KC705, if the user is capturing data from a dual ADC, the most lanes that can be used is 4 and the highest value that can be entered for number of samples in HSDC Pro GUI will be 64K. SLAU580B – June 2014 – Revised September 2016 Submit Documentation Feedback TSW14J10 FMC-USB Interposer Card Copyright © 2014–2016, Texas Instruments Incorporated 15 DAC and ADC GUI Configuration File Changes When Using a Xilinx Development Platform 6.1 www.ti.com DAC38J84EVM with Xilinx VC707 Development Board Setup Example This section provides an example of the TSW14J10EVM being used to test the DAC38J84EVM with a Xilinx VC707 development platform as shown in Figure 7. This example shows what must be modified in the DAC3XJ8X GUI for a setup using 4 lanes (LMFS = 4421), 1x interpolation, and a DAC sample rate of 368.64M. Setup the hardware as follows: Figure 7. DAC38J84EVM GUI Setup Example 1. 2. 3. 4. 5. 16 Connect J5 of the TSW14J10 to FMC HPC connector J35 on the VC707. Connect the DAC to the other end of the TSW14J10. Connect the power cables to the VC707 and DAC38J84. Connect a USB cable between the TSW14J10 and a host computer with the HSDC Pro GUI loaded. Connect a USB cable between the DAC38J84 and a host computer with the DAC3XJ8X GUI loaded. TSW14J10 FMC-USB Interposer Card SLAU580B – June 2014 – Revised September 2016 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated www.ti.com DAC and ADC GUI Configuration File Changes When Using a Xilinx Development Platform Power up the DAC38J84 and VC707. Program the DAC38J84 as follows: After opening the DAC GUI, enter the parameters as shown in Figure 8. Figure 8. Quick Start Menu The GUI calculates the lane rate and displays it in the box called SerDes Linerate. For this example, the lane rate is 7372.8Mbps. Using the lane rate conditions in Section 6, REFCLK = 368.64 MHz and Core clock = 184.32 MHz. Click on the Program LMK04828 and DAC3XJ8X button. After the programming has completed, click on the LMK04828 Controls tab. Next, click on the Clock Outputs tab. SLAU580B – June 2014 – Revised September 2016 Submit Documentation Feedback TSW14J10 FMC-USB Interposer Card Copyright © 2014–2016, Texas Instruments Incorporated 17 DAC and ADC GUI Configuration File Changes When Using a Xilinx Development Platform www.ti.com For the DAC3XJ8X GUI, the REFCLK is provided by CLKout 0 and the Core clock is provided by CLKout 12. Notice that the default setting for CLKout 12 is Group Powerdown, as shown in Figure 9. Figure 9. LMK04828 Clock Outputs Menu Since the DAC Clock is 368.64 MHz, to provide a REFCLK of 368.64 MHz, change the DCLK Divider for CLKout 0 to “8”. To generate a Core clock of 184.32 MHz, set the DCLK Divider for CLKout 12 to “16”. Also, remove the checkmark from the Group Powerdown box to enable this output. 18 TSW14J10 FMC-USB Interposer Card SLAU580B – June 2014 – Revised September 2016 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated www.ti.com DAC and ADC GUI Configuration File Changes When Using a Xilinx Development Platform The Clock Outputs menu is now as shown in Figure 10. Figure 10. LMK04828 Clock Outputs Menu SLAU580B – June 2014 – Revised September 2016 Submit Documentation Feedback TSW14J10 FMC-USB Interposer Card Copyright © 2014–2016, Texas Instruments Incorporated 19 DAC and ADC GUI Configuration File Changes When Using a Xilinx Development Platform www.ti.com Open HSDC Pro GUI, select the DAC tab, then select DAC3XJ84_LMF_442 in the device button. After the firmware is loaded, enter 368.64M in the Data Rate (SPS) window, select 2’s Complement in the DAC Option window and generate a 10-MHz test tone using the IQ Multitone Generator located in the lower left of the GUI. Click on the Create Tones button. The display appears as shown in Figure 11. Figure 11. HSDC Pro GUI Click the Send button. A new window opens showing the lane rate of the interface and the required frequency of REFCLK, as shown in Figure 12. Figure 12. HSDC Pro GUI: Lane Rate and REFCLK Settings Go back to the DAC GUI Quick Start tab and click the Reset DAC JESD Core button. Click on Trigger LMK04828 SYSREF. There should now be a 10-MHz tone present at all four DAC EVM outputs. 20 TSW14J10 FMC-USB Interposer Card SLAU580B – June 2014 – Revised September 2016 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated www.ti.com 6.2 DAC and ADC GUI Configuration File Changes When Using a Xilinx Development Platform ADC32RF45EVM With Xilinx VC707 Development Board Setup Example The following is an example of the TSW14J10EVM being used to test the ADC32RF45EVM with a Xilinx Virtex VC707 development platform as shown in Figure 13. Figure 13. ADC32RF45EVM, TSW14J10EVM and VC707 Board The following example shows what must be modified in the ADC32RF45 GUI for a setup using the JESD204B mode setting of LMFS = 82820 (8 lanes, 2 converters, 8 octets/frame, 20 samples/frame) with the ADC in bypass mode, and a sample rate of 2G. Connect the hardware as follows: 1. Connect the TSW14J10 to FMC HPC connector FMC1 on the VC707. 2. Connect the ADC to the other end of the TSW14J10. 3. Connect the power cables to the VC707 and ADC32RF45. 4. Connect a USB cable between the TSW14J10 and a host computer with HSDC Pro GUI loaded. 5. Connect a USB cable between the ADC32RF45 and a host computer with ADC32RFxx GUI loaded. 6. Provide a 600-MHz, 12-dBM filtered IF source to AINP SMA J2. SLAU580B – June 2014 – Revised September 2016 Submit Documentation Feedback TSW14J10 FMC-USB Interposer Card Copyright © 2014–2016, Texas Instruments Incorporated 21 DAC and ADC GUI Configuration File Changes When Using a Xilinx Development Platform www.ti.com Setup the hardware per the ADC32RFxx EVM User’s Guide (SLAU620) in the section titled ADC32RFxx Quick-Start Procedure (5-Sample Mode) but use two synchronized external 2-GHz clock sources for the input to J7 and J5. Configure the ADC32RF45EVM for LMFS = 82820 mode, per steps 1–9 of the ADC32RFxx EVM User’s Guide using the ADC32RFxx GUI. After the ADC32RFx EVM has been configured, click on the LMK04828 tab. Next, click on the Clock Outputs tab. The GUI appears as shown in Figure 14. Figure 14. ADC32RFxx GUI LMK0828 Clock Outputs Tab For this example, the lane rate is 8 Gbps. Using the equation in Section 6 for lane rates greater than 3.2 Gbps: Reference clock Core clock = Lane Rate / 20 = Lane Rate / 40 8G / 20 8G / 40 = 400 MHz = 200 MHz In the ADC32RFxx GUI, the ADC REFCLK and SYSREF are provided by CLKout 2 and 3. The FPGA Reference clock and SYSREF are provided by CLKout 0 and 1. The FPGA Core clock (for Xilinx platforms only) is provided by CLKout 12. Notice that the default setting for CLKout 12 is Group Powerdown. To generate a Reference clock = 400 MHz, set the DCLK Divider to 5 for CLKout 0. To generate a Core clock = 200 MHz, set the DCLK Divider to 10 for CLKout 12 and unselect the Group Powerdown option for this clock. The GUI will now appear as shown in Figure 15. 22 TSW14J10 FMC-USB Interposer Card SLAU580B – June 2014 – Revised September 2016 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated www.ti.com DAC and ADC GUI Configuration File Changes When Using a Xilinx Development Platform Figure 15. Updated LMK0828 Clock Outputs Tab Open HSDC Pro GUI, select the ADC tab, and then select “ADC32RF45_LMF_82820” using the device drop-down arrow. After the firmware is loaded, enter "32768" in the Analysis Window (samples). Next enter "2G" in the ADC Output Data Rate window. The GUI will display the new lane rate and JESD reference clock required by the capture platform FPGA, as shown in Figure 16. Click the OK button. Figure 16. HSDC Pro GUI Click the Capture button. The captured results should look as shown in Figure 17. SLAU580B – June 2014 – Revised September 2016 Submit Documentation Feedback TSW14J10 FMC-USB Interposer Card Copyright © 2014–2016, Texas Instruments Incorporated 23 DAC and ADC GUI Configuration File Changes When Using a Xilinx Development Platform www.ti.com Figure 17. Captured Results for Channel A 24 TSW14J10 FMC-USB Interposer Card SLAU580B – June 2014 – Revised September 2016 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated www.ti.com 6.3 DAC and ADC GUI Configuration File Changes When Using a Xilinx Development Platform ADC12J4000EVM With Xilinx VC707 Development Board Setup Example The following is an example of the TSW14J10EVM being used to test the ADC12J4000EVM with a Xilinx Virtex VC707 development platform as shown in Figure 18. Figure 18. ADC12J4000EVM, TSW14J10EVM and VC707 Board The following example shows the required modifications in the ADC12J4000 GUI for a setup using the JESD204B mode setting of LMFS = 8885 (8 lanes, 8 converters, 8 octets/frame, 5 samples/frame) with the ADC in bypass mode, and a sample rate of 4G. Setup the hardware per Section 6.2 but using the ADC12J4000EVM. Setup the hardware per the ADC12J4000EVM User’s Guide (SLAU551), internal clock mode, but use a 600-MHz IF connected to VIN. Use the ADC12J4000EVM GUI A, shown in Figure 19, and follow steps 3.4–3.9 and 3.11 in the ADC12J4000EVM User’s Guide to configure the ADC EVM. SLAU580B – June 2014 – Revised September 2016 Submit Documentation Feedback TSW14J10 FMC-USB Interposer Card Copyright © 2014–2016, Texas Instruments Incorporated 25 DAC and ADC GUI Configuration File Changes When Using a Xilinx Development Platform www.ti.com Figure 19. ADC12J4000EVM GUI For this example, the lane rate is 8 Gbps. Using the equation in Section 6 for lane rates greater than 3.2 Gbps: Reference clock Core clock = Lane Rate / 20 = Lane Rate / 40 8G / 20 8G / 40 = 400 MHz = 200 MHz Since the LMK04828 input clock (2 GHz) is the ADC sample clock divided by 2, to achieve the proper frequency for the reference clock, this must be divided by 5. To achieve the proper core clock frequency, this must be divided by 10. After the ADC12J4000 EVM has been configured, in the GUI, click on the Low Level View tab and perform the following writes to provide the proper divider for the LMK04828 outputs used by the Xilinx FPGA: 1. Go to LMK04828 address 0x110 and enter a “5” in the write data box and click the Write Register button. 2. Click the Read Register button and verify a “5” is read back. 3. Go to address 0x100, do a Read Register and verify the value “A” is read back. If not, write this value to this address. 26 TSW14J10 FMC-USB Interposer Card SLAU580B – June 2014 – Revised September 2016 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated www.ti.com DAC and ADC GUI Configuration File Changes When Using a Xilinx Development Platform Figure 20. LMK04828 Address 0x100 SLAU580B – June 2014 – Revised September 2016 Submit Documentation Feedback TSW14J10 FMC-USB Interposer Card Copyright © 2014–2016, Texas Instruments Incorporated 27 DAC and ADC GUI Configuration File Changes When Using a Xilinx Development Platform www.ti.com Figure 21. LMK04828 Address 0x110 Open the HSDC Pro GUI, select the ADC tab, then select “ADC12J4000_BYPASS” using the device dropdown arrow. After the firmware is loaded, make sure the Analysis Window (samples) is no greater than 65,536 (due to the limit of the internal FPGA memory used for this capture). Next enter "2G" in the ADC Output Data Rate window. Click the Capture button. The GUI will display the new lane rate and JESD reference clock required by the capture platform FPGA, as shown in Figure 22. Click the OK button. Figure 22. HSDC Pro GUI 28 TSW14J10 FMC-USB Interposer Card SLAU580B – June 2014 – Revised September 2016 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated www.ti.com DAC and ADC GUI Configuration File Changes When Using a Xilinx Development Platform The captured results appear as shown in Figure 23. Figure 23. Captured Results for the ADC12J4000 in Bypass Mode SLAU580B – June 2014 – Revised September 2016 Submit Documentation Feedback TSW14J10 FMC-USB Interposer Card Copyright © 2014–2016, Texas Instruments Incorporated 29 DAC and ADC GUI Configuration File Changes When Using a Xilinx Development Platform 6.4 www.ti.com ADC12J4000EVM With a Xilinx Zynq ZC706 Development Board Setup Example The following is an example of the TSW14J10EVM being used to test the ADC12J4000EVM with a Xilinx Zynq ZC706 development platform as shown in Figure 24. Figure 24. ADC12J4000EVM, TSW14J10EVM and ZC706 board Since the ZC706 development board does not have a JTAG connector that can be connected to the TSW14J10EVM for programing the FPGA firmware, the bit file must be loaded using the Xilinx Vivado design tool. The first step is to program the ADC12J4000 which will provide the reference and core clocks to the ZC706. 1. Connect the TSW14J10 to the FMC HPC connector J37 on the ZC706. 2. Connect the ADC to the other end of the TSW14J10. 3. Connect the power cables to the ZC706 and ADC12J4000. 4. Connect a micro USB cable between J1 of the ZC706 and a host computer with Vivado loaded. 5. Connect a USB cable between the TSW14J10 and a host computer with HSDC Pro GUI loaded. 6. Connect a USB cable between the ADC12J4000 and a host computer with ADC12J4000 GUI loaded. Power up the ADC12J4000 and ZC706. Program the ADC12J4000 per instructions in Section 6.3. To program the FPGA, do the following steps: 1. Due to an issue Vivado has with the file path name, move the file “TSW14J10_ZC706_2vp8.bit”, located at C:\Program Files(86)\Texas Instruments\High Speed Data Converter Pro\14J10ZC706 Details\Firmware” to C:\. 2. Open the Xilinx Vivado design tool. 3. Double click on “Open Hardware Manager”. 4. Click on “Open Target”. 5. Select “Open New Target”. Click on “Next”. 30 TSW14J10 FMC-USB Interposer Card SLAU580B – June 2014 – Revised September 2016 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated DAC and ADC GUI Configuration File Changes When Using a Xilinx Development Platform www.ti.com 6. Click on “Finish”. 7. Click on “Program device”. Select the device that appears. 8. Navigate to C:\ 9. Select “TSW14J10_ZC706_2vp8.bit. 10. Click on “Program device”. 11. A new window will open showing the status of the programming. Once this reached 100%, the FPGA is programmed and ready to be used with the TSW14J10 to run the HSDC Pro GUI. Open the HSDC Pro GUI, select the ADC tab, then select “ADC12J4000_BYPASS” using the device dropdown arrow. After the firmware is loaded, make sure the Analysis Window (samples) is no greater than 65,536 (due to the limit of the internal FPGA memory used for this capture). Next, enter "2G" in the ADC Output Data Rate window. Click the Capture button. The GUI will display the new lane rate (8G) and JESD reference clock required by the capture platform FPGA (400 MHz). Click the OK button. The captured results will appear as shown in Figure 25. Figure 25. Captured Results for the ADC12J4000 in Bypass Mode SLAU580B – June 2014 – Revised September 2016 Submit Documentation Feedback TSW14J10 FMC-USB Interposer Card Copyright © 2014–2016, Texas Instruments Incorporated 31 DAC and ADC GUI Configuration File Changes When Using a Xilinx Development Platform 6.5 www.ti.com DAC38J84EVM With a Xilinx Zynq ZC706 Development Board Setup Example The following is an example of the TSW14J10EVM being used to test the DAC38J84EVM with a Xilinx Zynq ZC706 development platform as shown in Figure 26. Figure 26. DAC38J84EVM, TSW14J10EVM and ZC706 Board The ZC706 development platform does not have traces routed on FMC connector pins F10 and F11, which are normally used for the JESD204B DAC SYNC differential signals. To accommodate for this, the TSW14J10EVM has options to move the SYNC signals to FMC pins H19 and H20 by making the following resistor changes: 1. Remove R143, R145. 2. Install 0-Ω resistors for R142, R144, R146, and R149. These resistors are all located on the bottom side of the TSW14J10EVM near the FMC connector. NOTE: This modification is only required when testing a DAC EVM with a ZC706. Since the ZC706 development board does not have a JTAG connector that can be connected to the TSW14J10EVM for programing the FPGA firmware, the bit file must be loaded using the Xilinx Vivado design tool. The first step is to program the DAC38J84EVM which will provide the reference and core clocks to the ZC706. 1. Connect the TSW14J10 to FMC HPC connector J37 on the ZC706. 2. Connect the DAC to the other end of the TSW14J10. 3. Connect the power cables to the ZC706 and DAC38J84. 32 TSW14J10 FMC-USB Interposer Card SLAU580B – June 2014 – Revised September 2016 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated www.ti.com DAC and ADC GUI Configuration File Changes When Using a Xilinx Development Platform 4. Connect a micro USB cable between J1 of the ZC706 and a host computer with Vivado loaded. 5. Connect a USB cable between the TSW14J10 and a host computer with HSDC Pro GUI loaded. 6. Connect a USB cable between the DAC38J84 and a host computer with DAC3XJ8X GUI loaded. Power up the DAC38J84 and ZC706. Program the DAC38J84 per instructions in Section 6.1. To program the FPGA, complete the following steps: 1. Due to an issue Vivado has with the file path name, move the file “TSW14J10_ZC706_2vp8.bit”, located at C:\Program Files(86)\Texas Instruments\High Speed Data Converter Pro\14J10ZC706 Details\Firmware” to C:\. 2. Open Xilinx Vivado design tool. 3. Double click on “Open Hardware Manager”. 4. Click on “Open Target”. 5. Select “Open New Target”. Click on “Next”. 6. Click on “Finish”. 7. Click on “Program device”. Select the device that appears. 8. Navigate to C:\ 9. Select “TSW14J10_ZC706_2vp8.bit. 10. Click on “Program device”. 11. A new window will open showing the status of the programming. Once this reached 100%, the FPGA is programmed and ready to be used with the TSW14J10 to run the HSDC Pro GUI. Open HSDC Pro GUI. A new window opens indicating a connection to the ZC706, as shown in Figure 27. Figure 27. Serial Number Selection Window In the GUI, select the DAC tab, then select DAC3XJ84_LMF_442 in the device button. After the firmware is loaded, enter 368.64M in the Data Rate (SPS) window, select 2’s complement in the DAC Output window and generate a 10-MHz test tone using the IQ Multitone Generator located in the lower left of the GUI. Click the Create Tones button. The display will appear as shown in Figure 28. SLAU580B – June 2014 – Revised September 2016 Submit Documentation Feedback TSW14J10 FMC-USB Interposer Card Copyright © 2014–2016, Texas Instruments Incorporated 33 DAC and ADC GUI Configuration File Changes When Using a Xilinx Development Platform www.ti.com Figure 28. HSDC Pro GUI Click the Send button. A new window opens showing the lane rate of the interface the required frequency of REFCLK, as shown in Figure 29. Figure 29. HSDC Pro GUI Go back the DAC GUI Quick Start tab and click on “Reset DAC JESD Core”. Click on “Trigger LMK04828 SYSREF”. There should now be a 10-MHz tone present at all four DAC EVM outputs. Other EVM’s that have tested with the ZC706 platform include the ADS42JB49/69, ADC32RF45, and DAC38J84. 34 TSW14J10 FMC-USB Interposer Card SLAU580B – June 2014 – Revised September 2016 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Revision History www.ti.com Revision History Changes from A Revision (October 2014) to B Revision ............................................................................................... Page • • • • • Updated the DAC38J84EVM with Xilinx VC707 Development Board Setup Example section. ............................... Added the ADC32RF45EVM With Xilinx VC707 Development Board Setup Example section. .............................. Added the ADC12J4000EVM With Xilinx VC707 Development Board Setup Example section. .............................. Added the ADC12J4000EVM With a Xilinx Zynq ZC706 Development Board Setup Example section ..................... Added the DAC38J84EVM With a Xilinx Zynq ZC706 Development Board Setup Example section. ........................ SLAU580B – June 2014 – Revised September 2016 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Revision History 16 21 25 30 32 35 STANDARD TERMS AND CONDITIONS FOR EVALUATION MODULES 1. Delivery: TI delivers TI evaluation boards, kits, or modules, including demonstration software, components, and/or documentation which may be provided together or separately (collectively, an “EVM” or “EVMs”) to the User (“User”) in accordance with the terms and conditions set forth herein. Acceptance of the EVM is expressly subject to the following terms and conditions. 1.1 EVMs are intended solely for product or software developers for use in a research and development setting to facilitate feasibility evaluation, experimentation, or scientific analysis of TI semiconductors products. EVMs have no direct function and are not finished products. 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If TI elects to repair or replace such EVM, TI shall have a reasonable time to repair such EVM or provide replacements. Repaired EVMs shall be warranted for the remainder of the original warranty period. Replaced EVMs shall be warranted for a new full ninety (90) day warranty period. 3 Regulatory Notices: 3.1 United States 3.1.1 Notice applicable to EVMs not FCC-Approved: This kit is designed to allow product developers to evaluate electronic components, circuitry, or software associated with the kit to determine whether to incorporate such items in a finished product and software developers to write software applications for use with the end product. This kit is not a finished product and when assembled may not be resold or otherwise marketed unless all required FCC equipment authorizations are first obtained. Operation is subject to the condition that this product not cause harmful interference to licensed radio stations and that this product accept harmful interference. Unless the assembled kit is designed to operate under part 15, part 18 or part 95 of this chapter, the operator of the kit must operate under the authority of an FCC license holder or must secure an experimental authorization under part 5 of this chapter. 3.1.2 For EVMs annotated as FCC – FEDERAL COMMUNICATIONS COMMISSION Part 15 Compliant: CAUTION This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate the equipment. FCC Interference Statement for Class A EVM devices NOTE: This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a commercial environment. This equipment generates, uses, and can radiate radio frequency energy and, if not installed and used in accordance with the instruction manual, may cause harmful interference to radio communications. Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required to correct the interference at his own expense. SPACER SPACER SPACER SPACER SPACER SPACER SPACER SPACER FCC Interference Statement for Class B EVM devices NOTE: This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures: • • • • Reorient or relocate the receiving antenna. Increase the separation between the equipment and receiver. Connect the equipment into an outlet on a circuit different from that to which the receiver is connected. Consult the dealer or an experienced radio/TV technician for help. 3.2 Canada 3.2.1 For EVMs issued with an Industry Canada Certificate of Conformance to RSS-210 Concerning EVMs Including Radio Transmitters: This device complies with Industry Canada license-exempt RSS standard(s). Operation is subject to the following two conditions: (1) this device may not cause interference, and (2) this device must accept any interference, including interference that may cause undesired operation of the device. Concernant les EVMs avec appareils radio: Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitation est autorisée aux deux conditions suivantes: (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit accepter tout brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le fonctionnement. Concerning EVMs Including Detachable Antennas: Under Industry Canada regulations, this radio transmitter may only operate using an antenna of a type and maximum (or lesser) gain approved for the transmitter by Industry Canada. To reduce potential radio interference to other users, the antenna type and its gain should be so chosen that the equivalent isotropically radiated power (e.i.r.p.) is not more than that necessary for successful communication. This radio transmitter has been approved by Industry Canada to operate with the antenna types listed in the user guide with the maximum permissible gain and required antenna impedance for each antenna type indicated. Antenna types not included in this list, having a gain greater than the maximum gain indicated for that type, are strictly prohibited for use with this device. Concernant les EVMs avec antennes détachables Conformément à la réglementation d'Industrie Canada, le présent émetteur radio peut fonctionner avec une antenne d'un type et d'un gain maximal (ou inférieur) approuvé pour l'émetteur par Industrie Canada. Dans le but de réduire les risques de brouillage radioélectrique à l'intention des autres utilisateurs, il faut choisir le type d'antenne et son gain de sorte que la puissance isotrope rayonnée équivalente (p.i.r.e.) ne dépasse pas l'intensité nécessaire à l'établissement d'une communication satisfaisante. Le présent émetteur radio a été approuvé par Industrie Canada pour fonctionner avec les types d'antenne énumérés dans le manuel d’usage et ayant un gain admissible maximal et l'impédance requise pour chaque type d'antenne. Les types d'antenne non inclus dans cette liste, ou dont le gain est supérieur au gain maximal indiqué, sont strictement interdits pour l'exploitation de l'émetteur 3.3 Japan 3.3.1 Notice for EVMs delivered in Japan: Please see http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_01.page 日本国内に 輸入される評価用キット、ボードについては、次のところをご覧ください。 http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_01.page 3.3.2 Notice for Users of EVMs Considered “Radio Frequency Products” in Japan: EVMs entering Japan may not be certified by TI as conforming to Technical Regulations of Radio Law of Japan. If User uses EVMs in Japan, not certified to Technical Regulations of Radio Law of Japan, User is required by Radio Law of Japan to follow the instructions below with respect to EVMs: 1. 2. 3. Use EVMs in a shielded room or any other test facility as defined in the notification #173 issued by Ministry of Internal Affairs and Communications on March 28, 2006, based on Sub-section 1.1 of Article 6 of the Ministry’s Rule for Enforcement of Radio Law of Japan, Use EVMs only after User obtains the license of Test Radio Station as provided in Radio Law of Japan with respect to EVMs, or Use of EVMs only after User obtains the Technical Regulations Conformity Certification as provided in Radio Law of Japan with respect to EVMs. Also, do not transfer EVMs, unless User gives the same notice above to the transferee. Please note that if User does not follow the instructions above, User will be subject to penalties of Radio Law of Japan. SPACER SPACER SPACER SPACER SPACER 【無線電波を送信する製品の開発キットをお使いになる際の注意事項】 開発キットの中には技術基準適合証明を受けて いないものがあります。 技術適合証明を受けていないもののご使用に際しては、電波法遵守のため、以下のいずれかの 措置を取っていただく必要がありますのでご注意ください。 1. 2. 3. 電波法施行規則第6条第1項第1号に基づく平成18年3月28日総務省告示第173号で定められた電波暗室等の試験設備でご使用 いただく。 実験局の免許を取得後ご使用いただく。 技術基準適合証明を取得後ご使用いただく。 なお、本製品は、上記の「ご使用にあたっての注意」を譲渡先、移転先に通知しない限り、譲渡、移転できないものとします。 上記を遵守頂けない場合は、電波法の罰則が適用される可能性があることをご留意ください。 日本テキサス・イ ンスツルメンツ株式会社 東京都新宿区西新宿６丁目２４番１号 西新宿三井ビル 3.3.3 Notice for EVMs for Power Line Communication: Please see http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_02.page 電力線搬送波通信についての開発キットをお使いになる際の注意事項については、次のところをご覧ください。http:/ /www.tij.co.jp/lsds/ti_ja/general/eStore/notice_02.page SPACER 4 EVM Use Restrictions and Warnings: 4.1 EVMS ARE NOT FOR USE IN FUNCTIONAL SAFETY AND/OR SAFETY CRITICAL EVALUATIONS, INCLUDING BUT NOT LIMITED TO EVALUATIONS OF LIFE SUPPORT APPLICATIONS. 4.2 User must read and apply the user guide and other available documentation provided by TI regarding the EVM prior to handling or using the EVM, including without limitation any warning or restriction notices. The notices contain important safety information related to, for example, temperatures and voltages. 4.3 Safety-Related Warnings and Restrictions: 4.3.1 User shall operate the EVM within TI’s recommended specifications and environmental considerations stated in the user guide, other available documentation provided by TI, and any other applicable requirements and employ reasonable and customary safeguards. Exceeding the specified performance ratings and specifications (including but not limited to input and output voltage, current, power, and environmental ranges) for the EVM may cause personal injury or death, or property damage. If there are questions concerning performance ratings and specifications, User should contact a TI field representative prior to connecting interface electronics including input power and intended loads. Any loads applied outside of the specified output range may also result in unintended and/or inaccurate operation and/or possible permanent damage to the EVM and/or interface electronics. Please consult the EVM user guide prior to connecting any load to the EVM output. If there is uncertainty as to the load specification, please contact a TI field representative. During normal operation, even with the inputs and outputs kept within the specified allowable ranges, some circuit components may have elevated case temperatures. These components include but are not limited to linear regulators, switching transistors, pass transistors, current sense resistors, and heat sinks, which can be identified using the information in the associated documentation. When working with the EVM, please be aware that the EVM may become very warm. 4.3.2 EVMs are intended solely for use by technically qualified, professional electronics experts who are familiar with the dangers and application risks associated with handling electrical mechanical components, systems, and subsystems. User assumes all responsibility and liability for proper and safe handling and use of the EVM by User or its employees, affiliates, contractors or designees. User assumes all responsibility and liability to ensure that any interfaces (electronic and/or mechanical) between the EVM and any human body are designed with suitable isolation and means to safely limit accessible leakage currents to minimize the risk of electrical shock hazard. User assumes all responsibility and liability for any improper or unsafe handling or use of the EVM by User or its employees, affiliates, contractors or designees. 4.4 User assumes all responsibility and liability to determine whether the EVM is subject to any applicable international, federal, state, or local laws and regulations related to User’s handling and use of the EVM and, if applicable, User assumes all responsibility and liability for compliance in all respects with such laws and regulations. User assumes all responsibility and liability for proper disposal and recycling of the EVM consistent with all applicable international, federal, state, and local requirements. 5. Accuracy of Information: To the extent TI provides information on the availability and function of EVMs, TI attempts to be as accurate as possible. However, TI does not warrant the accuracy of EVM descriptions, EVM availability or other information on its websites as accurate, complete, reliable, current, or error-free. SPACER SPACER SPACER SPACER SPACER SPACER SPACER 6. Disclaimers: 6.1 EXCEPT AS SET FORTH ABOVE, EVMS AND ANY WRITTEN DESIGN MATERIALS PROVIDED WITH THE EVM (AND THE DESIGN OF THE EVM ITSELF) ARE PROVIDED "AS IS" AND "WITH ALL FAULTS." TI DISCLAIMS ALL OTHER WARRANTIES, EXPRESS OR IMPLIED, REGARDING SUCH ITEMS, INCLUDING BUT NOT LIMITED TO ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF ANY THIRD PARTY PATENTS, COPYRIGHTS, TRADE SECRETS OR OTHER INTELLECTUAL PROPERTY RIGHTS. 6.2 EXCEPT FOR THE LIMITED RIGHT TO USE THE EVM SET FORTH HEREIN, NOTHING IN THESE TERMS AND CONDITIONS SHALL BE CONSTRUED AS GRANTING OR CONFERRING ANY RIGHTS BY LICENSE, PATENT, OR ANY OTHER INDUSTRIAL OR INTELLECTUAL PROPERTY RIGHT OF TI, ITS SUPPLIERS/LICENSORS OR ANY OTHER THIRD PARTY, TO USE THE EVM IN ANY FINISHED END-USER OR READY-TO-USE FINAL PRODUCT, OR FOR ANY INVENTION, DISCOVERY OR IMPROVEMENT MADE, CONCEIVED OR ACQUIRED PRIOR TO OR AFTER DELIVERY OF THE EVM. 7. USER'S INDEMNITY OBLIGATIONS AND REPRESENTATIONS. USER WILL DEFEND, INDEMNIFY AND HOLD TI, ITS LICENSORS AND THEIR REPRESENTATIVES HARMLESS FROM AND AGAINST ANY AND ALL CLAIMS, DAMAGES, LOSSES, EXPENSES, COSTS AND LIABILITIES (COLLECTIVELY, "CLAIMS") ARISING OUT OF OR IN CONNECTION WITH ANY HANDLING OR USE OF THE EVM THAT IS NOT IN ACCORDANCE WITH THESE TERMS AND CONDITIONS. THIS OBLIGATION SHALL APPLY WHETHER CLAIMS ARISE UNDER STATUTE, REGULATION, OR THE LAW OF TORT, CONTRACT OR ANY OTHER LEGAL THEORY, AND EVEN IF THE EVM FAILS TO PERFORM AS DESCRIBED OR EXPECTED. 8. Limitations on Damages and Liability: 8.1 General Limitations. IN NO EVENT SHALL TI BE LIABLE FOR ANY SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL, OR EXEMPLARY DAMAGES IN CONNECTION WITH OR ARISING OUT OF THESE TERMS ANDCONDITIONS OR THE USE OF THE EVMS PROVIDED HEREUNDER, REGARDLESS OF WHETHER TI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED TO, COST OF REMOVAL OR REINSTALLATION, ANCILLARY COSTS TO THE PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES, RETESTING, OUTSIDE COMPUTER TIME, LABOR COSTS, LOSS OF GOODWILL, LOSS OF PROFITS, LOSS OF SAVINGS, LOSS OF USE, LOSS OF DATA, OR BUSINESS INTERRUPTION. NO CLAIM, SUIT OR ACTION SHALL BE BROUGHT AGAINST TI MORE THAN ONE YEAR AFTER THE RELATED CAUSE OF ACTION HAS OCCURRED. 8.2 Specific Limitations. IN NO EVENT SHALL TI'S AGGREGATE LIABILITY FROM ANY WARRANTY OR OTHER OBLIGATION ARISING OUT OF OR IN CONNECTION WITH THESE TERMS AND CONDITIONS, OR ANY USE OF ANY TI EVM PROVIDED HEREUNDER, EXCEED THE TOTAL AMOUNT PAID TO TI FOR THE PARTICULAR UNITS SOLD UNDER THESE TERMS AND CONDITIONS WITH RESPECT TO WHICH LOSSES OR DAMAGES ARE CLAIMED. THE EXISTENCE OF MORE THAN ONE CLAIM AGAINST THE PARTICULAR UNITS SOLD TO USER UNDER THESE TERMS AND CONDITIONS SHALL NOT ENLARGE OR EXTEND THIS LIMIT. 9. Return Policy. Except as otherwise provided, TI does not offer any refunds, returns, or exchanges. Furthermore, no return of EVM(s) will be accepted if the package has been opened and no return of the EVM(s) will be accepted if they are damaged or otherwise not in a resalable condition. If User feels it has been incorrectly charged for the EVM(s) it ordered or that delivery violates the applicable order, User should contact TI. All refunds will be made in full within thirty (30) working days from the return of the components(s), excluding any postage or packaging costs. 10. Governing Law: These terms and conditions shall be governed by and interpreted in accordance with the laws of the State of Texas, without reference to conflict-of-laws principles. User agrees that non-exclusive jurisdiction for any dispute arising out of or relating to these terms and conditions lies within courts located in the State of Texas and consents to venue in Dallas County, Texas. Notwithstanding the foregoing, any judgment may be enforced in any United States or foreign court, and TI may seek injunctive relief in any United States or foreign court. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2016, Texas Instruments Incorporated spacer IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. 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