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TUSB1002A
SLLSF63A – MARCH 2018 – REVISED NOVEMBER 2018
TUSB1002A USB3.2 10 Gbps Dual-Channel Linear Redriver
1 Features
3 Description
•
The TUSB1002A is the industry’s first dual-channel
USB 3.2 x1 SuperSpeedPlus (SSP) redriver and
signal conditioner. The device offers low power
consumption on a 3.3-V supply with its ultra-lowpower architecture. It supports the USB3.2 low power
modes
which
further
reduces
idle
power
consumption.
1
•
•
•
•
•
•
•
•
•
•
•
•
•
Supports USB3.2 x1 SuperSpeed (5 Gbps) and
SuperSpeedPlus (10 Gbps)
Supports PCI Express Gen3, SATA Express, and
SATA Gen3.
Ultra Low-Power Architecture
– Active: < 300 mW
– Disconnect/U2/U3: < 1.9 mW
– Shutdown: < 700 µW
Adjustable Voltage Output Swing Linear Range up
to 1200 mVpp
No Host/Device Side Requirement
16 Settings for up to 16 dB at 10 Gbps of Linear
Equalization
Adjustable DC Equalization Gain
Hot-Plug Capable
Pin-to-Pin Compatible With LVPE502A and
LVPE512 USB 3.0 Redriver
Pin-to-Pin Compatible with TUSB1002 Redriver
Temperature Range: 0°C to 70°C (Commercial)
and –40°C to 85°C (Industrial)
±5 kV HBM ESD
Available in Single 3.3 V Supply.
Available in 4 mm x 4 mm VQFN
2 Applications
•
•
•
•
•
•
The TUSB1002A implements a linear equalizer,
supporting up to 16 dB of loss due to Inter-Symbol
Interference (ISI). When USB signals travel across a
PCB or cable, signal integrity degrades due to loss
and inter-symbol interference. The linear equalizer
compensates for the channel loss, and thereby,
extends the channel length and enables systems to
pass USB compliance. The dual lane implementation
and small package size provides flexibility in the
placement of the TUSB1002A in the USB3.2 path.
The TUSB1002A is available in either a 24-pin 4 mm
x 4 mm VQFN. It is also available in a commercial
grade
(TUSB1002A)
or
industrial
grade
(TUSB1002AI).
Device Information(1)
PART NUMBER
TUSB1002A
TUSB1002AI
PACKAGE
VQFN (24)
BODY SIZE (NOM)
4.00 mm x 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Notebook and Desktop PC
TVs
Tablets
Cell Phones
Active Cable
Docking Stations
SPACER
RXP1
+
RXN1 -
+
USB 3.1
Host
+
TXP2
-
TXN2
+
TXP1
-
TXN1
TUSB1002A
+
+
RXP2
-
RXN2
-
USB 3.1
Receptacle
Simplified Schematic
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TUSB1002A
SLLSF63A – MARCH 2018 – REVISED NOVEMBER 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
7
1
1
1
2
3
5
Absolute Maximum Ratings ...................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 5
Electrical Characteristics........................................... 6
Timing Requirements ................................................ 9
Switching Characteristics .......................................... 9
Typical Characteristics ............................................ 11
Detailed Description ............................................ 14
7.1
7.2
7.3
7.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
14
14
15
18
7.5 U0 Mode.................................................................. 18
7.6 U1 Mode.................................................................. 18
7.7 U2/U3 Mode ............................................................ 18
8
Application and Implementation ........................ 19
8.1 Application Information............................................ 19
8.2 Typical USB3.2 Application .................................... 19
8.3 Typical SATA, PCIe and SATA Express
Application................................................................ 22
9 Power Supply Recommendations...................... 25
10 Layout................................................................... 25
10.1 Layout Guidelines ................................................. 25
10.2 Layout Example .................................................... 26
11 Device and Documentation Support ................. 27
11.1
11.2
11.3
11.4
11.5
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
27
27
27
27
27
12 Mechanical, Packaging, and Orderable
Information ........................................................... 27
4 Revision History
Changes from Original (March 2018) to Revision A
Page
•
Changed text From: "Inclusion of these 330nF capacitors and 220k resistors is optional but highly recommended."
To: "Inclusion of the 330 nF capacitors and 220k resistors is optional." in the Detailed Design Procedure........................ 20
•
Added ordered list of implementation options for USB connector to TUSB1002A RX pins ................................................ 20
2
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SLLSF63A – MARCH 2018 – REVISED NOVEMBER 2018
5 Pin Configuration and Functions
RSVD1
TX1N
TX1P
GND
RX2N
RX2P
24
23
22
21
20
19
RGE Package
24-Pin VQFN
Top View
VCC
1
18
GND
CH1_EQ1
2
17
CH2_EQ2
CH1_EQ2
3
16
CH2_EQ1
CFG1
4
15
CFG2
EN
5
14
DCBOOST#
GND
6
13
VCC
Thermal
7
8
9
10
11
12
MODE
RX1N
RX1P
GND
TX2N
TX2P
Pad
Not to scale
Pin Functions
PIN
TYPE
INTERNAL PULLUP
PULLDOWN
DESCRIPTION
NAME
NO.
RX1P
9
RX1N
8
RX2P
19
RX2N
20
TX1P
22
TX1N
23
TX2P
12
TX2N
11
CH1_EQ1
2
I (4-level)
CH1_EQ1. Configuration pin used to control Rx EQ level for RX1P/N. The state
of this pin is sampled after the rising edge of EN. Refer to Figure 2 for details of
timing. This pin along with CH1_EQ2 allows for up to 16 equalization settings.
CH1_EQ2
3
I (4-level)
CH1_EQ2. Configuration pin used to control Rx EQ level for RX1P/N. The state
of this pin is sampled after the rising edge of EN. Refer to Figure 2 for details of
timing. This pin along with CH1_EQ1 allows for up to 16 equalization settings.
Differential input for SuperSpeed (SS) and SuperSpeedPlus (SSP) positive
signals for Channel 1
90Ω Differential
Input
Differential input for SuperSpeed (SS) and SuperSpeedPlus (SSP) negative
signals for Channel 1
Differential input for SuperSpeed (SS) and SuperSpeedPlus (SSP) positive
signals for Channel 2
90Ω Differential
Input
Differential input for SuperSpeed (SS) and SuperSpeedPlus (SSP) negative
signals for Channel 2.
Differential output for SuperSpeed (SS) and SuperSpeedPlus (SSP) positive
signals for Channel 1.
90Ω Differential
Output
Differential output for SuperSpeed (SS) and SuperSpeedPlus (SSP) negative
signals for Channel 1.
Differential output for SuperSpeed (SS) and SuperSpeedPlus (SSP) positive
signals for Channel 2.
90Ω Differential
Output
Differential output for SuperSpeed (SS) and SuperSpeedPlus (SSP) negative
signals for Channel 2.
PU (approx 45K)
PD (approx 95K)
CH2_EQ1
16
I (4-level)
CH2_EQ1. Configuration pin used to control Rx EQ level for RX2P/N. The state
of this pin is sampled after the rising edge of EN. Refer to Figure 2 for details of
timing. This pin along with CH2_EQ2 allows for up to 16 equalization settings.
CH2_EQ2
17
I (4-level)
CH2_EQ2. Configuration pin used to control Rx EQ level for RX2P/N. The state
of this pin is sampled after the rising edge of EN. Refer to Figure 2 for details of
timing. This pin along with CH2_EQ1 allows for up to 16 equalization settings.
EN
5
I (2-level)
PU (approx 400 K)
EN. Places TUSB1002A into shutdown mode when asserted low. Normal
operation when pin is asserted high. When in shutdown, TUSB1002A’s receiver
terminations will be high impedance and tx/rx channels will be disabled.
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SLLSF63A – MARCH 2018 – REVISED NOVEMBER 2018
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Pin Functions (continued)
PIN
TYPE
INTERNAL PULLUP
PULLDOWN
DESCRIPTION
4
I (4-level)
PU (approx 45K)
PD (approx 95K)
CFG1. This pin along with CFG2 will select VOD linearity range and DC gain
for both channels 1 and 2. The state of this pin is sampled after the rising edge
of EN. Refer to Figure 2 for details of timing. Refer to Table 3 for VOD linearity
range and DC gain options.
15
I (4-level)
PU (approx 45K)
PD (approx 95K)
CFG2. This pin along with CFG1 will set VOD linearity range and DC gain for
both channels 1 and 2. The state of this pin is sampled after the rising edge of
EN. Refer to Figure 2 for details of timing. Refer to Table 3 for VOD linearity
range and DC gain options.
PU (approx 45 K)
PD (approx 95K)
MODE. This pin is for selecting different modes of operation. The state of this
pin is sampled after the rising edge of EN. Refer to Figure 2 for details of
timing.
0 = Basic Redriver Mode.
R = PCIe / Test Mode. PCIe Mode and TI Internal use only
F = USB3.2 x1 Dual Channel Operation enabled (TUSB1002A normal mode).
1 = USB3.2 x1 Single-channel operation.
NAME
NO.
CFG1
CFG2
MODE
7
I (4-level)
RSVD1
24
O
DCBOOST#
RSVD1. Under normal operation, this pin will be driven low by TUSB1002A.
Recommend leaving this pin unconnected on PCB.
14
I (2-level)
VCC
1, 13
Power
3.3 V (±10%) Supply.
GND
6, 10, 18,
21
GND
Ground
Thermal
pad
4
PU (approx 400 K)
DCBOOST#. This pin when asserted low will increase the DC Gain level
defined inTable 3 by +1 dB unless already at +2dB. If DC Gain level defined
inTable 3 is already at +2 dB, then asserting this pin low will not change the DC
Gain level. This pin can be left unconnected if this function is not needed.
1 = DC Gain defined by Table 3.
0 = DC Gain defined by Table 3 is increased by +1 dB.
Thermal pad. Recommend connecting to a solid ground plane.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Supply Voltage
Range
Voltage Range
on I/O pins
Tstg
(1)
MIN
MAX
UNIT
VCC
-0.3
4
V
Differential voltage for RX1P/N and RX2P/N
-2.5
2.5
V
Voltage at RX pins
-0.5
4
V
Voltage on Control pins
-0.5
4
V
Storage temperature
-65
150
°C
Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per
ANSI/ESDA/JEDEC JS-001, all pins (1)
±5000
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins (2)
±1500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VCC
Supply voltage
VPSN
Supply noise on VCC pins
TA
TJ
MIN
NOM
MAX
3
3.3
3.6
UNIT
V
100
mV
TUSB1002A Ambient temperature
0
70
°C
TUSB1002AI Ambient temperature
-40
85
°C
TUSB1002A Junction temperature
0
105
°C
TUSB1002AI Junction temperature
-40
105
°C
6.4 Thermal Information
TUSB1002A
THERMAL METRIC (1)
RGE (VQFN)
UNIT
24 PINS
RθJA
Junction-to-ambient thermal resistance
38.5
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
41.6
°C/W
RθJB
Junction-to-board thermal resistance
16.3
°C/W
ΨJT
Junction-to-top characterization parameter
1.0
°C/W
ΨJB
Junction-to-board characterization parameter
16.4
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
6.9
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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SLLSF63A – MARCH 2018 – REVISED NOVEMBER 2018
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6.5 Electrical Characteristics
over operating free-air temperature and voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER
PU0_SSP_1200mV
Power under USB3.1
operation in U0 operating at
SuperSpeedPlug datarate
with linear range set to
1200mV.
At 10 Gbps; VCC = 3.3 V; EN = 1; Pattern
= CP9; VOD = 1200mVpp
330
mW
PU0_SSP_1000mV
Power under USB3.1
operation in U0 operating at
SuperSpeedPlug datarate
with linear range set to
1000mV.
At 10 Gbps; VCC = 3.3 V; EN = 1; Pattern
= CP9; VOD = 1000mVpp
310
mW
PU0_SSP_900mV
Power under USB3.1
operation in U0 operating at
SuperSpeedPlug datarate
with linear range set to
900mV.
At 10 Gbps; VCC = 3.3 V; EN = 1; Pattern
= CP9; VOD = 900mVpp
295
mW
PU1
Power in U1 with linear range
set to 1200mV.
In U1; VCC = 3.3 V; EN = 1; VOD =
1200mVpp
330
mW
PU2U3
Power when in U2/U3 state.
VCC = 3.3 V; EN = 1; Both channels in
U2/U3;
1.5
mW
PDISCONNECT_NONE
Power when no USB device
detected on both TX1P/N and
TX2P/N.
VCC = 3.3 V; EN = 1; RX1 and RX2
termination disabled;
1.9
mW
PDISCONNECT_ONE
Power when a single USB
device detected on either
TX1P/N or TX2P/N.
VCC = 3.3 V; EN = 1; Either RX1 or RX2
termination enabled but not both enabled;
1.9
mW
PSHUTDOWN
Shutdown power when EN =
0.
VCC = 3.3 V; EN = 0;
0.7
mW
4-level Inputs (CFG[2:1], MODE, CH1_EQ[2:1], CH2_EQ[2:1])
Threshold "0" / "R"
VCC = 3.3 V
0.55
V
Threshold "R" / "F"
VCC = 3.3 V
1.65
V
Threshold "F" / "1"
VCC = 3.3 V
2.8
IIH
High-level input current
VCC = 3.6 V; VIN = 3.6 V
IIL
Low-level input current
VCC = 3.6 V; VIN = 0 V
RPU
Internal pullup resistance
45
kΩ
RPD
Internal pulldown resistance
95
kΩ
VTH
V
20
80
µA
-160
-40
µA
EN, DCBOOST#
VIH
High-level input voltage
VCC = 3.3 V
1.7
3.6
VIL
Low-level input voltage
VCC = 3.3 V
0
0.7
V
V
IIH
High-level input current
VCC = 3.6 V; VIN = 3.6 V
-10
10
µA
IIL
Low-level input current
VCC = 3.6 V; VIN = 0 V
-15
15
µA
RPU_EN
Internal pullup resistance for
EN and DCBOOST#
400
kΩ
USB3.1 Receiver Interface (RX1P/N and RX2P/N)
RL_100
RL_5
MHz
GHz
Rx Differential return loss at
100 MHz to 2.5 GHz
SDD11 100 MHz to 2.5 GHz at 90-ohms
-18
dB
Rx Differential return loss at 5
GHz
SDD11 5 GHz at 90-ohms
-14
dB
-6
dB
-12
dB
-50
dB
16
dB
RL_10 GHz
Rx Differential return loss from
SDD11 5 GHz to 10 GHz at 90-ohms
5 to 10 GHz
RL_CM
Rx common mode return loss
X-Talk
Differential crosstalk between
TX and RX signal pairs
EACGAIN_5 GHz
Max AC Equalization Gain
6
SCC11 0.5 to 5 GHz at 90-ohms
50 mVpp CP10 at 5 GHz; VCC = 3.3V;
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Electrical Characteristics (continued)
over operating free-air temperature and voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
EDC_GAIN0
DC Gain at 0 dB setting
200 mVpp VID at 100 MHz; 1200mV
Linear Range Setting;
.7
dB
EDC_GAIN1
DC Gain at 1 dB setting
200 mVpp VID at 100 MHz; 1200mV
Linear Range Setting;
1.6
dB
EDC_GAIN2
DC Gain at 2 dB setting
200 mVpp VID at 100 MHz; 1000mV
Linear Range Setting;
2.3
dB
EDC_GAIN-1
DC Gain at -1 dB setting
200 mVpp VID at 100 MHz; 1200mV
Linear Range Setting;
-0.25
dB
VDIFF_IN
Input differential peak-peak
voltage swing range
1200
mV
VRX-DC-CM
RX DC common mode voltage
RRX-DC-CM
RX DC common mode
impedance
Measured at connector; Present when
USB Device detected on TXP/N;
18
30
Ω
RRX-DC-DIFF
RX DC differential impedance
Measured at connector; Present when
USB Device detected on TXP/N;
72
120
Ω
ZRX-DC-DIFF
1. Rx DC CM Impedance with Rx
DC Input CM Input Impedance terminations not powered. 2. Measured
V > 0 during RESET or power over the range 0 - 500 mV with respect to
down.
GND. 3. Only DC input CM Input
impedance V > 0 is specified.
VRX-SIGNAL-DET
Input differential peak-to-peak
signal detect assert level
At 10 Gbps; No loss input channel and
PRBS7 pattern.
85
mV
VRX-IDLE-DET
Input differential peak-to-peak
signal detect de-assert level
At 10 Gbps; No loss input channel and
PRBS7 pattern.
60
mV
VRX-LFPS-DET
LFPS detect threshold.
Below min is squelched
VRX-CM-AC-P
Peak RX AC common mode
voltage
Measured at package pin.
0
V
35
kΩ
100
310
mV
150
mV
USB3.1 Transmitter Interface (TX1P/N and TX2P/N)
RL_TX_100 MHz
Tx Differential return loss at
100 MHz
SDD22 100 MHz - 2.5 GHz at 90-ohms
-20
dB
RL_TX_2.5
GHz
Tx Differential return loss at 5
GHz
SDD22 5 GHz at 90-ohms
-16
dB
RL_TX_10
GHz
Tx Differential return loss from
SDD22 5 GHz to 10 GHz at 90-ohms
5 to 10 GHz
-8.5
dB
RL_TX_CM
Tx common mode return loss
SCC22 0.5 to 5 GHz at 90-ohms
VTX-DIFFPP-1200
Differential peak-to-peak TX
voltage swing linear dynamic
range at 100MHz
1200 mVpp setting; 100MHz; Measured
at -1dB compression point = 20
log(VOD/VOD_linear)
Differential peak-to-peak TX
voltage swing linear dynamic
range at 5GHz
VTX-DIFFPP-1000
VTX-DIFFPP-900
VTX-RCV-DETECT
-6.7
dB
1000
mV
1200 mVpp setting; 5GHz; Measured at
-1dB compression point = 20
log(VOD/VOD_linear)
1300
mV
Differential peak-to-peak TX
voltage swing linear dynamic
range at 100MHz
1000 mVpp setting; 100MHz; Measured
at -1dB compression point = 20
log(VOD/VOD_linear)
900
mV
Differential peak-to-peak TX
voltage swing linear dynamic
range at 5GHz
1000 mVpp setting; 5GHz; Measured at
-1dB compression point = 20
log(VOD/VOD_linear)
1150
mV
Differential peak-to-peak TX
voltage swing linear dynamic
range at 100MHz
900 mVpp setting; 100MHz; Measured at
-1dB compression point = 20
log(VOD/VOD_linear)
800
mV
Differential peak-to-peak TX
voltage swing linear dynamic
range at 5GHz
900 mVpp setting; 5GHz; Measured at
-1dB compression point = 20
log(VOD/VOD_linear)
1000
mV
Amount of voltage change
allowed during Rx Detection.
Measured at package pins.
600
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Electrical Characteristics (continued)
over operating free-air temperature and voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Max allowed instantaneous commodemode voltage at connector side of AC
coupling capacitor. This is an absolute
voltage spec referenced to the receive
side termination ground.
VTX-CM-IDLE-DELTA
Transmitter idle common
mode voltage change U2/U3
state.
VTX-DC-CM
TX DC common mode voltage 1200mVpp linear range setting;
VTX-CM-AC-PP-ACTIVE
Transmitter AC common
mode peak-peak voltage in
U0. Maximum mismatch from
TXP+TXN for both time and
amplitude.
VTX-IDLE-DIFF-AC-PP
AC electrical idle differential
peak-to-peak output voltage
VTX-CM-DC-ACTIVE-
Absolute DC common mode
voltage between U1 and U0
IDLE-DELTA
MIN
TYP
-600
0
1200mVpp linear setting; CHx_EQ
setting matches input channel insertion
loss;
0
1.85
MAX
UNIT
600
mV
2.05
V
116
mV
10
mV
200
mV
RTX-DC-CM
TX DC common mode
impedance
18
30
Ω
RTX-DC-DIFF
TX DC differential impedance
72
120
Ω
ITX-SHORT
Transmitter short-circuit
current limit.
107
mA
CAC-COUPLING
External AC coupling
capacitor on differential pairs.
265
nF
8
75
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6.6 Timing Requirements
over operating free-air temperature and voltage range (unless otherwise noted)
MIN
td_pg
Internal power good asserted high when VCC is at 2.5V
tCFG_SU
CFG (1) pins setup before internal Reset (2) high
tCFG_HD
CFG (1) pins hold after internal Reset (2) high
500
tVCC_RAMP
VCC supply ramp requirement
0.1
(1)
(2)
NOM
MAX
UNIT
5
µs
0
µs
µs
50
ms
Following pins comprise CFG pins: MODE, CFG[2:1], CH1_EQ[2:1], CH2_EQ[2:1]
Internal reset is the logical AND of EN pin and internal power good.
6.7 Switching Characteristics
over operating free-air temperature and voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tIDLEEntry
Delay from U0 to electrical idle
VCC = 3.0 V; EN = 1;See Figure 1
150
ps
tIDLEEntry_U1
U1 exit time. Break in electrical idle
to transmission of LFPS.
VCC = 3.0 V; EN = 1; See Figure 1
150
ps
tIDLEEntry_U2
U2/U3 exit time; Break in electrical
idle to transmission of LFPS
VCC = 3.0 V; EN = 1; See Figure 1
6
µs
U3
tDIFF_DLY
Differential propagation delay
VCC = 3.0 V; EN = 1;
150
ps
tPWRUP_ACTI
Time from assertion of EN to device
active and performing Rx.Detect on
both ports
VCC = 3.0 V; EN = 1;
8
ms
Transmitter rise/fall time
VCC = 3.3 V; EN = 1; 10 Gbps; 20% to
80% of differential output; 1200 mVpp
linear range setting; Fast Input rise/fall
time;
27
ps
Transmitter rise/fall mismatch
VCC = 3.3 V; EN = 1; 10 Gbps; 20% to
80% of differential output; 1200 mVpp
linear range setting; 1000 mVpp VID
.6
ps
Transmitter residual deterministic
jitter
VCC = 3.3 V; EN = 1; 10 Gbps; 1200
mVpp linear range setting; Input channel
loss of 12 dB; Output channel loss of 1.5
dB; Optimized EQ;
0.05
UI
VE
tTX_RISE_FAL
L
tRF_MISMATC
H
tTX_DJ
Figure 1. Idle Entry and Exit Latency
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Figure 2. Power-Up Diagram
10
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6.8 Typical Characteristics
VCC = 3.3V , 25°C, 200 mVpp VID sine wave, ZO = 100 Ω, RGE package
20
20
EQ1_DC0_1200 mV
EQ3_DC0_1200 mV
EQ5_DC0_1200 mV
EQ7_DC0_1200 mV
EQ9_DC0_1200 mV
EQ11_DC0_1200 mV
EQ13_DC0_1200 mV
EQ15_DC0_1200 mV
10
15
SDD21 (dB)
SDD21 (dB)
15
EQ2_DC0_1200 mV
EQ4_DC0_1200 mV
EQ6_DC0_1200 mV
EQ8_DC0_1200 mV
EQ10_DC0_1200 mV
EQ12_DC0_1200 mV
EQ14_DC0_1200 mV
EQ16_DC0_1200 mV
5
0
10
5
0
-5
0.01
0.1
1
Frequency (GHz)
10
-5
0.01
20
Figure 3. 1200 mV DC0 Gain Odd EQ Settings Curves
1
Frequency (GHz)
10
20
D004
Figure 4. 1200 mV DC0 Even EQ Settings Curves
7
20
EQ1_DC-1_1200 mV
EQ1_DC2_1200 mV
EQ1_DC0_1200 mV
EQ1_DC1_1200 mV
5
EQ1_DC0_1000 mV
EQ3_DC0_1000 mV
EQ5_DC0_1000 mV
EQ7_DC0_1000 mV
EQ9_DC0_1000 mV
EQ11_DC0_1000 mV
EQ13_DC0_1000 mV
EQ15_DC0_1000 mV
15
3
SDD21 (dB)
SDD21 (dB)
0.1
D003
1
10
5
-1
0
-3
-5
0.01
0.1
1
Frequency (GHz)
-5
0.01
10
Figure 5. 1200 mV DC Gain Adjustments Curves
1
Frequency (GHz)
10
20
D006
Figure 6. 1000 mV DC0 Gain Odd EQ Settings Curves
20
7
EQ2_DC0_1000 mV
EQ4_DC0_1000 mV
EQ6_DC0_1000 mV
EQ8_DC0_1000 mV
EQ10_DC0_1000 mV
EQ12_DC0_1000 mV
EQ14_DC0_1000 mV
EQ16_DC0_1000 mV
10
5
SDD21 (dB)
15
SDD21 (dB)
0.1
D005
5
EQ1_DC0_1000 mV
EQ1_DC1_1000 mV
EQ1_DC2_1000 mV
EQ1_DC-1_1000 mV
3
1
-1
0
-3
-5
0.01
0.1
1
Frequency (GHz)
10
20
-5
0.01
0.1
D007
Figure 7. 1000 mV DC0 Gain Even EQ Settings Curves
1
Frequency (GHz)
10
D008
Figure 8. 1000 mV DC Gain Adjustments Curves
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Typical Characteristics (continued)
VCC = 3.3V , 25°C, 200 mVpp VID sine wave, ZO = 100 Ω, RGE package
20
20
EQ1_DC0_900 mV
EQ3_DC0_900 mV
EQ5_DC0_900 mV
EQ7_DC0_900 mV
EQ9_DC0_900 mV
EQ11_DC0_900 mV
EQ13_DC0_900 mV
EQ15_DC0_900 mV
10
15
SDD21 (dB)
SDD21 (dB)
15
5
0
10
5
0
-5
0.01
0.1
1
Frequency (GHz)
10
-5
0.01
20
Figure 9. 900 mV DC0 Gain Odd EQ Settings Curves
5
SDD11 (dB)
3
1
-1
-3
0.1
1
Frequency (GHz)
1
Frequency (GHz)
10
20
D010
Figure 10. 900 mV DC0 Gain Even EQ Settings Curves
EQ1_DC0_900 mV
EQ1_DC1_900 mV
-5
0.01
0.1
D009
7
SDD21 (dB)
EQ2_DC0_900 mV
EQ4_DC0_900 mV
EQ6_DC0_900 mV
EQ8_DC0_900 mV
EQ10_DC0_900 mV
EQ12_DC0_900 mV
EQ14_DC0_900 mV
EQ16_DC0_900 mV
10
1
-1
-3
-5
-7
-9
-11
-13
-15
-17
-19
-21
-23
-25
0.01
0.1
D011
Figure 11. 900 mV DC Gain Adjustment Curves
1
Frequency (GHz)
10
D012
Figure 12. SDD11 Return Loss
1800
0
1600
1400
1200
-10
VOD (mV)
SDD22 (dB)
-5
-15
1000
800
600
400
-20
DC0_EQ1_900 mV
DC0_EQ1_1000 mV
DC0_EQ1_1200 mV
200
-25
0.01
0
0.1
1
Frequency (GHz)
10
0
200
D013
Figure 13. SDD22 Return Loss
12
20
400
600
800
VID (mV)
1000
1200
14001500
D014
Figure 14. 5-GHz Sine Wave VID vs VOD Linearity Range
Setting
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Typical Characteristics (continued)
VCC = 3.3V , 25°C, 200 mVpp VID sine wave, ZO = 100 Ω, RGE package
1400
1200
VOD (mV)
1000
800
600
400
DC0_EQ1_900mV
DC0_EQ1_1000mV
DC0_EQ1_1200mV
200
0
0
200
400
600
800 1000 1200 1400 1600 1800 2000
VID (V)
D015
Figure 15. 100-MHz Sine Wave VID vs VOD Linearity Range Setting
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7 Detailed Description
7.1 Overview
The TUSB1002A is the industry’s first, dual lane USB 3.2 x1 SuperSpeedPlus redriver. As signals traverse
through a channel (like FR4 trace) the amplitude of the signal is attenuated. The attenuation varies depending on
the frequency content of the signal. Depending the length of the channel this attenuation could be large enough
resulting in signal integrity issues at a USB 3.2 receiver. By placing a TUSB1002A between USB3.2 host and
device the attenuation effect of the channel can eliminated or minimized. The result is a USB3.2 compatible eye
at the devices receiver. With up to 16 receiver equalization settings, the TUSB1002A can support many different
channel loss combinations. The TUSB1002A offers low power consumption on a single 3.3 V supply with its ultra
low power architecture. It supports the USB3.2 low power modes which further reduces idle power consumption.
The TUSB1002A settings are configured through pins. In addition to equalization adjustment, the TUSB1002A
provides knobs for adjusting DC gain and voltage output linearity range.
7.2 Functional Block Diagram
GND
VIterm
ARXTERM_EN1
TX1P
RX1P
TX
RX
RX1N
LFPS
LOS
TX1N
ATXEN1
AIDLE1
ARXDET1
ALFPS1
Rx
Detect
ALOSZ1
GND
VIterm
ARXTERM_EN2
TX2P
RX2P
TX
TX2N
RX
RX2N
ATXEN2
Rx
Detect
AIDLE2
ALFPS2
LFPS
ARXDET2
ALOSZ2
CFG1
CFG2
CH1_EQ1
CH1_EQ2
DCBOOST#
LOS
CH2_EQ1
Digital
FSM
CH2_EQ2
MODE
RSVD1
EN
14
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7.3 Feature Description
7.3.1 4-Level Control Inputs
The TUSB1002A has (MODE, CFG1, CFG2, CH1_EQ1, CH1_EQ2, CH2_EQ1, and CH2_EQ2) 4-level inputs
pins that are used to control the equalization gain and the output voltage swing dynamic range. These 4-level
inputs use a resistor divider to help set the 4 valid levels and provide a wider range of control settings. These
resistors together with the external resistor connection combine to achieve the desired voltage level.
Table 1. 4-Level Control Pin Settings
LEVEL
SETTINGS
0
Option 1: Tie 1 kΩ 5% to GND.
Option 2: Tie directly to GND.
R
Tie 20 kΩ 5% to GND.
F
Float (leave pin open)
1
Option 1: Tie 1 kΩ 5% to VCC.
Option 2: Tie directly to VCC.
NOTE
In order to conserve power, the TUSB1002A disables 4-level input’s internal pull-up/pulldown resistors after the state of 4-level pins have been sampled on rising edge of EN. A
change of state for any four level input pin is not applied to TUSB1002A until after EN pin
transitions from low to high.
7.3.2 Linear Equalization
With a linear equalizer, the TUSB1002A can electrically shorten a particular channel allowing for longer run
lengths.
X in trace
USB
Type A
USB Host
X in trace
USB Host
Y in trace
TUSB1002A
USB
Type A
Figure 16. Linear Equalizer
With a TUSB1002A, a longer trace can be made to have similar insertion loss as a shorter trace. For example, a
long trace of X + Y inches can be made to have similar loss characteristics of a shorter trace of X inches.
The receiver equalization level for each channel is determined by the state of the CHx_EQ1 and CHx_EQ2 pins,
where x = 1 or 2.
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Table 2. EQ Configuration Options for 1200mV Linearity 0 dB DC Gain Setting
EQ SETTING #
CHx_EQ2 PIN LEVEL
CHx_EQ1 PIN LEVEL
EQ GAIN at 2.5GHz / 5 GHz (dB)
1
0
0
1.0 / 3.6
2
0
R
2.1 / 5.5
3
0
F
3.0 / 6.8
4
0
1
4.0 / 8.1
5
R
0
4.6 / 9.0
6
R
R
5.5 / 10.0
7
R
F
6.2 / 10.8
8
R
1
6.9 / 11.6
9
F
0
7.3 / 11.9
10
F
R
7.9 / 12.6
11
F
F
8.4 / 13.1
12
F
1
9.0 / 13.7
13
1
0
9.4 / 14.1
14
1
R
9.9 / 14.6
15
1
F
10.3 / 14.9
16
1
1
10.7 / 15.3
7.3.3 Adjustable VOD Linear Range and DC Gain
The CFG1 and CFG2 pins can be used to adjust the TUSB1002A output voltage swing linear range and receiver
equalization DC gain. Table 3 details the available options.
For best performance, the TUSB1002A should be operated within its defined VOD linearity range. The gain of
the incoming VID should be kept to less than or equal to the TUSB1002A VOD linear range setting. The can be
determined by Equation 1:
VID at 5 GHz = VOD x (10 -(Gv/20))
where
•
Gv = TUSB1002A Gain and VOD = TUSB1002A VOD linearity setting.
(1)
For example, for a VOD linearity range setting of 1200 mV, the maximum incoming VID signal at 5 GHz with a
CHx_EQ[1:0] setting of 2 (5.5 dB) is 1200 x (10 -(5.5/20)) = 637 mVpp. The TUSB1002A can be operated outside
its VOD linear range but jitter will be higher.
Table 3. VOD Linear Range and DC Gain
16
CH2 DC GAIN (dB)
CH1 VOD LINEAR
RANGE (mVpp)
CH2 VOD LINEAR
RANGE (mVpp)
+1
0
900
900
0
+1
900
900
F
0
0
900
900
0
1
+1
+1
900
900
5
R
0
0
0
1000
1000
6
R
R
+1
0
1000
1000
7
R
F
0
-1
1000
1000
8
R
1
+2
+2
1000
1000
9
F
0
-1
-1
1200
1200
10
F
R
+2
+2
1200
1200
11
F
F
0
0
1200
1200
12
F
1
+1
+1
1200
1200
13
1
0
+2
0
1200
1200
14
1
R
0
+2
1200
1200
15
1
F
0
+1
1200
1200
16
1
1
+1
0
1200
1200
SETTING #
CFG1 PIN LEVEL
CFG2 PIN LEVEL
CH1 DC GAIN (dB)
1
2
0
0
0
R
3
0
4
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7.3.4 USB3.2 Dual Channel Operation (MODE = “F”)
TheTUSB1002A in dual-channel operation waits for far-end terminations on both channels 1 and 2 before
transitioning to fully active state (U0 mode). This mode of operation, defined as MODE pin = ‘F’, is the most
common configuration for USB3.2 Source (DFP) and Sink (UFP) applications.
In a USB3.2 x2 application, two TUSB1002A redrivers are used: One on the config lane and the other on the
non-config lane. The TUSB1002A on the non-config lane must be placed in basic redriver mode (MODE pin =
"0"). The TUSB1002A on the config lane should be placed in USB3.2 dual channel operation (MODE pin = "F").
The expectation is the USB power delivery (PD) controller will hold both TUSB1002A in shutdown mode until a
connection can be established. Upon establishing a connection, the USB PD controller will place each
TUSB1002A into the appropriate mode.
7.3.5 USB3.2 Single Channel Operation (MODE = “1”)
In some applications, like Type-C USB3.2 active cables, only one of the two channels may be active. For this
application, setting MODE pin = ‘1’, enables single-channel operation. In this mode of operation, the TUSB1002A
attempts far-end termination on both channels 1 and 2. The channel which has a far-end termination detected is
enabled while the remaining channel is disabled. If far-end termination is detected on both channels, then
TUSB1002A behaves in dual channel operation (both channels enabled).
7.3.6 PCIe/SATA/SATA Express Redriver Operation (MODE = “R”; CFG1 = "0"; CFG2 = "0" )
The TUSB1002A can be used as a PCI Express (PCIe) Gen3, SATA Gen3, or SATA Express redriver. When
TUSB1002A's MODE pin = “R”, CFG1 pin = "0", and CFG2 pin = "0", the TUSB1002A enables both channels
(upstream and downstream) receiver and transmitter paths upon detecting far-end termination on both TX1 and
TX2. Both upstream and downstream paths remain enabled until EN pin is de-asserted low. All USB3.2 power
management functionality is disabled in this mode. In this mode, the TUSB1002A is transparent to PCIe link
power management (L0s, L1) and SATA interface power states. Once far-end termination is detected on both
TX1 and TX2, the TUSB1002A power is at P(U0_SSP_1200mV) regardless of the PCIe or SATA power state. To save
power during system S3/S4/S5 states it is suggested to de-assert the EN pin to conserve power.
NOTE
In this mode the linearity range will be fixed at 1200mVpp and DC gain to 0dB.
7.3.7 Basic Redriver Operation (MODE = “0”)
The TUSB1002A can be used as a basic redriver for non-USB3.2 x1 applications. When the TUSB1002A MODE
pin = “0”, the TUSB1002A enables both channels receiver and transmitter paths. The channel receiver and
transmitter termination are both enabled. All USB3.2 power management functionality is disabled.
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7.4 Device Functional Modes
7.4.1 Shutdown Mode
The Shutdown mode is entered when EN pin is low and VCC is active and stable. This mode is the lowest power
state of the TUSB1002A. While in this mode, the TUSB1002A receiver terminations is disabled.
7.4.2 Disconnect Mode
Next to Shutdown Mode, the Disconnect mode is the lowest power state of the TUSB1002A. The TUSB1002A
enters this mode when exiting Shutdown mode. In this state, the TUSB1002A periodically checks for far-end
receiver termination on both SSTX1 and SSTX2. Upon detection of the far-end receiver’s termination on both
ports, the TUSB1002A transitions to a fully active mode called U0 mode.
7.5 U0 Mode
The U0 mode is the highest power state of the TUSB1002A. Anytime high-speed traffic (SuperSpeed or
SuperSpeedPlus) is being received, the TUSB1002A remains in this mode. The TUSB1002A only exits this
mode if electrical idle is detected on both SSRX1 and SSRX2. While in this mode, the TUSB1002A hs speed
receivers and transmitters are powered and active.
7.6 U1 Mode
The U1 mode is the intermediate mode between U0 mode and U2/U3 mode. In U1 mode, the TUSB1002A
receiver termination remains enabled and the TXP/N DC common mode is maintained.
7.7 U2/U3 Mode
Next to the disconnect mode, the U2/U3 mode is next lowest power state. While in this mode, the TUSB1002A
periodically performs far-end receiver detection. Anytime the far-end receiver termination is not detected on
either CH1 or CH2, the TUSB1002A leaves the U2/U3 mode and transition to the Disconnect mode. It also
monitors the SSRX1 and SSRX2 for a valid LFPS. Upon detection of a valid LFPS, the TUSB1002A immediately
transitions to the U0 mode.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TUSB1002A is a linear redriver designed specifically to compensation for ISI jitter caused by attenuation
through a passive medium like traces and cables. Because the TUSB1002A has two independent channels, it
can be optimized to correct ISI in both the upstream and downstream direction through 16 different equalization
choices. Placing the TUSB1002A between a USB3.2 Host/device controller and a USB3.2 receptacle can correct
signal integrity issues resulting in a more robust system.
8.2 Typical USB3.2 Application
Downstream
FR4 Trace
of Length X
C
+
RXP1
C
RXN1
C
TXP2
USB 3.1
Host
B
C
FR4 Trace
of Length Y
+
+
TXP1
C
-
-
TXN1
C
RXP2
C
RXN2
C
TUSB1002A
+
-
C
TXN2
+
+
-
-
D
USB 3.1
Receptacle
A
Upstream
Figure 17. TUSB1002A in USB3.2 x1 Host Application
8.2.1 Design Requirements
For this design example, use the parameters shown in Table 4.
Table 4. Design Parameters
PARAMETER
VALUE
VCC supply (3 V to 3.6 V)
3.3 V
Mode of Operation (Dual or Half Channel)
MODE = F (Floating) for USB3.2 Dual Channel
TX1, TX2, RX1 A/C coupling Capacitor (75 nF to 265 nF)
100 nF
Optional RX2 A/C coupling Capacitor (297 nF to 363 nF)
330 nF ±10%
Optional RX2 pull-down resistors on USB receptacle side of AC
capacitor (200K to 242K ohms)
220 kΩ
A to B FR4 Length (inches)
8
A to B FR4 Trace Width (mils)
4
C to D FR4 length (inches)
2
C to D FR4 Trace Width (mils)
4
DC Gain (-2, -1, 0, +1, +2)
0 dB (CFG[2:1] pins floating)
Linear Range (900 mV, 1000 mV, or 1200 mV)
1200 mV (CFG[2:1] pins floating)
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8.2.2 Detailed Design Procedure
The TUSB1002A differential receivers and transmitters have internal BIAS and termination. For this reason, the
TUSB1002A must be connected to the USB3.2 host and receptacle through external A/C coupling capacitors. In
this example, as depicted in Table 4, 100 nF capacitors are placed on TX2P and TX2N, RX1P and RX1N, and
TX1P and TX1N. 330 nF A/C coupling capacitors along with 220 kΩ resistors are placed on the RX2P and
RX2N. Inclusion of the 330 nF capacitors and 220k resistors is optional. The ordered list below details the three
implementation options for the RX2p/n path.
Three implementation options for USB connector to TUSB1002A's RX pins:
1. DC couple TUSB1002A's RX pins to USB connector. No 330 nF capacitors and no 220 kΩ pull-down
resistors.
2. 330 nF capacitors with 220 kΩ resistors as depicted in Figure 18. The purpose of 220 kΩ resistors is to
discharge the capacitor within 250ms after a USB device is removed from the USB connector.
3. The stub from the 220 kΩ resistor pad may create impedance discontinuities causing negative impact to
performance. Assuming leakage current from external components is enough to discharge capacitor, 330 nF
capacitor without the 220 kΩ resistor is a valid option.
CH2_EQ2
CH2_EQ1
USB_VBUS
DCBOOST#
CFG2
R15
220k
100nF
TX1P
100nF
TX1N
RSVD1
R16
220k
GND
23
Optional
VCC
13
CFG2
15
CH2_EQ1
16
14
8
7
25
C2
2
3
4
5
100nF
100nF
C4
RX1P
C6
RX1N
MODE
100nF
100nF
VCC_3P3V
1
VCC_3P3V
R1
1M
C1
GND
9
24
USB3_TYPEA_CONNECTER
C8
0.001uF
TUSB1002A
24-PIN RGE
22
EN
C5
HOST_DP
10
CFG1
C3
SSTXP 9
SHIELD0 10
SHIELD1 11
HOST_DM
12 TX2P
11 TX2N
CH1_EQ2
330nF
VCC_3P3V
RX2P 19
RX2N 20
GND 21
CH1_EQ1
C13
330nF
VCC
C12
GND 7
SSTXN 8
C7
100nF
CH2_EQ2
18
U1
17
DP 3
GND 4
5
SSRXN
SSRXP 6
GND
Optional
VBUS 1
DM 2
6
GND
J1
HOST_RXP
HOST_RXN
CONNECT TO
USB3.1 HOST
HOST_TXP
HOST_TXN
VCC_3P3V
R2
DNI
C9
10uF
C10
100nF
C11
100nF
CFG1
CH1_EQ2
CH1_EQ1
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Figure 18. Host Implementation Schematic
The USB3.2 Dual channel operation is used in this example. Mode pin should be left floating (unconnected)
when using this mode.
The TUSB1002A compensates for channel loss in both the upstream (D to C) and downstream direction (A to B).
This is done by configuring the CH1_EQ[2:1] and CH2_EQ[2:1] pins to the equalization setting that matches as
close possible to the channel insertion loss. In this particular example, CH1_EQ[2:1] is for path A to B which is
the channel between USB3.2 host and the TUSB1002A, and CH2_EQ[2:1] is for path C to D which is the
channel between TUSB1002A and the USB3.2 receptacle.
The TUSB1002A supports 5 levels of DC gain that are selected by the CFG[2:1] pins. Typically, the DC gain
should be set to 0 dB but may need to be adjusted to correct any one of the following conditions:
1. Input VID too high resulting in VOD being greater than USB 3.2 defined swing. For this case, a negative DC
gain should be used.
2. Input VID too low resulting in VOD being less than USB 3.2 defined swing. For this case, a positive DC gain
should be used.
3. Low frequency discontinuities in the channel resulting in DC component of the signal clipping the vertical eye
mask. For this case, a positive DC gain should be used.
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It is assumed in this example the incoming VID is at the nominal defined USB3.2 range and the channel is linear
across frequency. The CFG1 and CFG2 pins can both be left floating if these assumptions are true.
In this particular example, the channel A-B has a trace length of 8 inches with a 4 mil trace width. This particular
channel has about 0.83 dB per inch of insertion loss at 5 GHz. This equates to approximately 6.7 dB of loss for
the entire 8 inches of trace. An additional 1.5 dB of loss is added due to package of the USB3.2 Host,
TUSB1002A, and the A/C coupling capacitor. This brings the entire channel loss at 5 GHz to 6.7 dB + 1.5 dB =
8.2 dB. A typical USB 3.1 host/device will have around 3 dB of transmitter de-emphasis. Transmitter deemphasis pre-compensates for the loss of the output channel. With 3 dB of de-emphasis, the total equalization
required by the TUSB1002A is in the 5.2 dB (8.2 dB - 3 dB) range. The channel A-B for this example is
connected to TUSB1002A's RX1P/N input and therefore CH1_EQ[2:1] pins are used for adjusting TUSB1002A
RX1P/N equalization settings. The CH1_EQ[2:1] pins should be set such that TUSB1002A equalization is
between 5dB and 8dB.
The channel C-D has a trace length of 2 inches with a 4mil trace width. Assuming 0.83 dB per inch of insertion
loss, the 2 inch trace will equate to about 1.66 dB of loss at 5 GHz. An additional 2dB of loss needs to be added
due to package, A/C coupling capacitor, and the USB 3.1 receptacle. The total loss is around 3.66 dB. Because
channel C-D includes a USB 3.1 receptacle, the actual total loss could be much greater than 3.66dB due to the
fact that devices plugged into the receptacle will also have loss. The device plugged into receptacle will have
either a short or long channel. USB3.2 standard defines total loss limit of 23dB that is distributed as 8.5 dB for
Host, 8.5dB for device, and 6.0dB for cable. With variable channel of devices plugged into the USB3.2
receptacle, configuring TUSB1002A's RX2P/N equalization settings is not as straight forward as Channel A-B.
Engineer can not set TUSB1002A CH2_EQ[2:1] pins to the largest equalization setting to accommodate the
largest allowed USB3.2 device/cable loss of 14.5 dB. Doing so will result in TUSB1002A operating outside its
linear range when a device with short channel is plugged into the receptacle. For this reason, it is recommended
to configure TUSB1002A CH2_EQ[2:1] pins to equalize a shorter device channel. This will result in requiring
USB3.2 host to compensate for remaining channel loss for the worse case USB3.2 channel of 14.5 dB. The
definition of a short device channel is not specified in USB 3.2 specification. Therefore, an engineer must make
their own loss estimate of what constitutes a short device channel. For particular example, we will assume the
short channel is around 2 to 3 dB. The device's channel loss will need to be added to estimated Channel C-D
loss minus the typical 3db of de-emphasis. This means CH2_EQ[2:1] pins should be configured to handle a loss
of 3 to 5 db.
8.2.3 Application Curves
Freq = 5 GHz
dB(SDD21) = –6.666
Figure 19. Insertion Loss for 8inch 4 mil FR4 Trace
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8.3 Typical SATA, PCIe and SATA Express Application
Downstream
A
B
C
TXP2
RXP2
SATA/PCIe/
SATA Express
Host
+
-
D
FR4 trace
of length Y
RXN2
miniCard / mSATA
socket
FR4 trace
of length X
+
-
+
-
TXN2
TUSB1002A
RXP1
TXP1
+
-
+
-
TXN1
+
-
RXN1
+
-
+
-
SATA/PCIe/
SATA Express
Device
Upstream
Figure 20. SATA/PCIe/SATA Express Typical Application
8.3.1 Design Requirements
Table 5. Design Parameters
PARAMETER
VALUE
VCC supply (3 V to 3.6 V)
3.3 V
PCIe Support Required (Yes/No)
Yes
SATA Express Support Required (Yes/No)
Yes
SATA Support Required (Yes/No)
Yes, then ferrite beads (FB1 and FB2) and 49.9-ohm required.
No, then ferrite bead (FB1 and FB2) and 49.9-ohm not required.
TX1, TX2, RX2 A/C coupling Capacitor (176 nF to 265 nF)
220 nF ±10%
RX1 A/C coupling Capacitor (297 nF to 363 nF)
Optional. But if implemented suggest 330 nF ±10%
A to B FR4 Length (inches)
8
A to B FR4 Trace Width (mils)
4
C to D FR4 length (inches)
2
C to D FR4 Trace Width (mils)
4
DC Gain (-2, -1, 0, +1, +2)
Not configurable when MODE = "R", CFG1 = "0", and CFG2 = "0".
Will always default to 0 dB
Linear Range (900 mV, 1000 mV, or 1200 mV)
Not configurable when MODE = "R", CFG1 = "0", and CFG2 = "0".
Will always default to 1200mV
8.3.2 Detailed Design Procedure
The MODE pin = "R", CFG1 = "0", and CFG2 = "0" will place the TUSB1002A into PCIe mode. In this mode, the
TUSB1002A will have its DC gain fixed at 0dB and its linearity range fixed at 1200mV. The TUSB1002A will
perform far-end receiver termination detection and enable both upstream and downstream paths when far-end
termination is detected on both TX1 and TX2.
The AC coupling capacitor range defined for a SATA device is a lot smaller than the AC-coupling capacitor range
defined for SATA Express and PCI Express (PCIe) as indicated by Figure 21. The AC-coupling capacitor range
defined for SATA Express and PCI Express is within the same range as the AC-coupling capacitor range defined
by USB 3.1. The TUSB1002A will be able to detect PCIe and SATA Express device's receiver termination. But
the SATA 12nF (max) AC-coupling capacitor prevents TUSB1002A from detecting the SATA device receiver
termination. To correct this problem, a ferrite bead along with 49.9 ohm resistor must be placed between CTX2
and miniCard/mSATA socket. These components can be isolated from the high-speed channel when PCIe or
SATA Express is active by using an NFET as shown in Figure 22. The NFET should be enabled whenever a
22
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SATA device is present. The ferrite bead chosen must present at least 600 ohms impedance at 100MHz so as to
not impact high-speed signalling. It is recommended to use Murata BLM03AG601SN1 or BLM03HD601SN1D or
a ferrite bead with similar characteristics from a different vendor. For applications which only require support for
PCIe and SATA Express and do not need to support SATA, the ferrite beads and 49.9 ohm resistors are not
needed.
176nF t 265nF
12nF (max)
+
-
+
-
+
-
SATA
Device
+
-
SATA
Express
Device
+
-
+
-
PCIe
Device
75nF t 265nF
Figure 21. AC-Coupling capacitor Implementation for SATA, SATA Express, and PCIe Devices
The TUSB1002A power is at P(U0_SSP_1200mV) when both its upstream and downstream paths are enabled. In
order to save system power in system S3/S4/S5 states, it is suggested to control the TUSB1002A EN pin.
Anytime the system enters a low power state (S3, S4, or S5), it is suggested to de-assert the EN pin. While EN
pin is de-asserted, the TUSB1002A will consume P(SHUTDOWN). Assertion of this pin is necessary anytime the
system exits a lower power state.
The TUSB1002A compensates for channel loss in both the upstream (C to D) and downstream direction (A to B).
This is done by configuring the CH1_EQ[2:1] and CH2_EQ[2:1] pins to the equalization setting that matches as
close possible to the channel insertion loss. In this particular example, CH2_EQ[2:1] is for path A to B which is
the channel between PCIe/SATA/SATA Express host and the TUSB1002A, and CH1_EQ[2:1] is for path C to D
which is the channel between TUSB1002A and the miniCard/mSATA socket.
In this particular example, the channel A-B has a trace length of 8 inches with a 4 mil trace width. This particular
channel has about 0.83 dB per inch of insertion loss at 5 GHz. This equates to approximately 6.7 dB of loss for
the entire 8 inches of trace as depicted in Figure 19. An additional 1.5 dB of loss is added due to package of the
PCIe/SATA/SATA Express Host, TUSB1002A, and the A/C coupling capacitor. This brings the entire channel
loss at 5 GHz to 6.7 dB + 1.5 dB = 8.2 dB. The channel A-B for this example is connected to TUSB1002A
RX2P/N input and therefore CH2_EQ[2:1] pins are used for adjusting TUSB1002A RX2P/N equalization settings.
The CH2_EQ[2:1] pins should be set such that TUSB1002A equalization is between 5dB and 8dB. A value closer
to 5 dB maybe best if Host has transmitter de-emphasis.
A similar method should be used for the upstream path (C to D). In this particular example, C to D has a trace
length of 2 inches with a 4-mil trace width. This equates to approximately 1.5 dB at 5 GHz. The SATA/SATA
Express/PCIe device will have its own channel loss. This loss can be added to the C to D channel loss. For this
example, we will assume a value of 5dB is acceptable to compensate for C to D channel loss as well as loss
associated with the SATA/SATA Express/PCIe device. The CH1_EQ[2:1] pins should be set such that
TUSB1002A equalization is 5dB.
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VCC (3.3V)
VCC (3.3V)
REQ2A
10 µF
REQ2B
100nF
100nF
VCC (3.3V)
REQ2C
SATA_EN
REQ2D
CRX2
+
-
+
-
CTX1
RX2P
RX2N
GND
TX1P
TX1N
RSVD1
TUSB1002A
49.9Q
FB1
FB2
CTX2
TX2P
TX2N
GND
RX1P
RX1N
MODE
VCC
CH1_EQ1
CH1_EQ2
CFG1
EN
GND
TPAD
SATA/PCIe/
SATA Express
Host
49.9Q
miniCard / mSATA
socket
GND
CH2_EQ2
CH2_EQ1
CFG2
DCBOOST#
VCC
10
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