TUSB1106IPWRQ1

TUSB1106-Q1 SCAS916 – AUGUST 2011 www.ti.com ADVANCED UNIVERSAL SERIAL BUS TRANSCEIVERS Check for Samples: TUSB1106-Q1 FEATURES • 1 • • • • • • • • • • Qualified for Automotive Applications Compatible With Universal Serial Bus Specification Rev. 2.0 Transmit and Receive Serial Data at Both Full-Speed (12-Mbit/s) and Low-Speed (1.5-Mbit/s) Data Rates Integrated Bypassable 5-V to 3.3-V Voltage Regulator for Powering Via USB VBUS VBUS Disconnection Indication Through VP and VM Used as USB Device Transceiver or USB Host Transceiver Stable RCV Output During SE0 Condition Two Single-Ended Receivers With Hysteresis Low-Power Operation, Ideal for Portable Equipment Support I/O Voltage Range From 1.65 V to 3.6 V Available in a Thin Shrink Small-Outline Package [TSSOP (PW)] PW PACKAGE (TOP VIEW) V p u(3 .3) 1 16 V C C (5 .0 ) SO FTCO N 2 15 V reg (3 .3 ) OE 3 14 V M O R CV 4 13 V PO VP 5 12 D + VM 6 11 D − S U S PN D 7 10 S PE E D GN D 8 9 V C C (I /O ) DESCRIPTION The TUSB1106-Q1 universal serial bus (USB) transceiver is compliant with the Universal Serial Bus Specification Rev. 2.0. This device can transmit and receive serial data at both full-speed (12-Mbit/s) and low-speed (1.5-Mbit/s) data rates. The TUSB1106-Q1 can be used as USB device transceiver or USB host transceiver. The device allows USB application-specific ICs (ASICs) and programmable logic devices (PLDs), with power-supply voltages from 1.65 V to 3.6 V, to interface with the physical layer (PHY) of the universal serial bus. It has an integrated 5-V to 3.3-V voltage regulator for direct powering via the USB supply VBUS. The TUSB1106-Q1 allows only differential input mode and is available in a PW package. The TUSB1106-Q1 is ideal for portable electronic devices such as mobile phones, personal digital assistants, information appliances, and digital still cameras. ORDERING INFORMATION TA –40°C to 85°C (1) (2) PACKAGE (1) TSSOP – PW (2) Reel of 2000 ORDERABLE PART NUMBER TUSB1106IPWRQ1 TOP-SIDE MARKING TU1106I Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2011, Texas Instruments Incorporated TUSB1106-Q1 SCAS916 – AUGUST 2011 www.ti.com FUNCTIONAL BLOCK DIAGRAM TUSB1106-Q1 2 A. Connect to D– for low-speed operation and to D+ for high-speed operation. B. Pin function depends on device type. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TUSB1106-Q1 TUSB1106-Q1 SCAS916 – AUGUST 2011 www.ti.com TERMINAL FUNCTIONS TERMINAL NAME NO. I/O DESCRIPTION OE 3 I Output enable (CMOS level with respect to VCC(I/O), active LOW). Enables the transceiver to transmit data on the USB bus input pad. Push pull, CMOS. RCV 4 O Differential data receiver (CMOS level with respect to VCC(I/O)). Driven LOW when input SUSPND is HIGH. The output state of RCV is preserved and stable during an SE0 condition output pad. Push pull, 4-mA output drive, CMOS. VP 5 O Single-ended D+ receiver (CMOS level with respect to V). For external detection of single-ended zero (SE0), error conditions, speed of connected device. Driven HIGH when no supply voltage is connected to VCC(5.0) and Vreg(3.3) output pad. Push pull, 4-mA output drive, CMOS. VM 6 O Single-ended D– receiver (CMOS level with respect to VCC(I/O)). For external detection of single-ended zero (SE0), error conditions, speed of connected device. Driven HIGH when no supply voltage is connected to VCC(5.0) and Vreg(3.3) output pad. Push pull, 4-mA output drive, CMOS. SUSPND 7 I Suspend (CMOS level with respect to VCC(I/O)). A HIGH level enables low-power state while the USB bus is inactive and drives output RCV to a LOW-level input pad. Push pull, CMOS. I Mode (CMOS level with respect to VCC(I/O)). A HIGH level enables the differential input mode (VPO, VMO), whereas a LOW level enables a single-ended input mode (VO, FSE0). See Table 5 and Table 6 input pad. Push pull, CMOS. MODE GND 8 Ground supply VCC(I/O) 9 Supply voltage for digital I/O pins (1.65 to 3.6 V). When VCC(I/O) is not connected, the D+ and D– pins are in 3-state. This supply pin is independent of VCC(5.0) and Vreg(3.3) and must never exceed the Vreg(3.3) voltage. SPEED 10 I D– 11 AI/O Negative USB data bus connection (analog, differential). For low-speed mode, connect to pin Vpu(3.3) via a 1.5-kΩ resistor. D+ 12 AI/O Positive USB data bus connection (analog, differential). For full-speed mode, connect to pin Vpu(3.3) via a 1.5-kΩ resistor. VPO/VO VPO I Driver data (CMOS level with respect to VCC(I/O), Schmitt trigger). See Driving Function table. Push pull, CMOS. I Driver data (CMOS level with respect to VCC(I/O), Schmitt trigger). See Driving Function table. Push pull, CMOS. 13 VMO/FSE0 Speed selection (CMOS level with respect to VCC(I/O)). Adjusts the slew rate of differential data outputs D+ and D– according to the transmission speed. Input pad, push pull, CMOS. LOW – low speed (1.5 Mbit/s) HIGH – full speed (12 Mbit/s) VMO 14 Vreg(3.3) 15 Internal regulator option. Regulated supply-voltage output (3 V to 3.6 V) during 5-V operation. A decoupling capacitor of at least 0.1 mF is required for the regulator bypass option. Used as a supply-voltage input for 3.3 V ± 10% operation. VCC(5.0) 16 Internal regulator option. Supply-voltage input (4 V to 5.5 V). Can be connected directly to USB supply VBUS regulator bypass option. Connect to Vreg(3.3). Vpu(3.3) 1 Pullup supply voltage (3.3 V ± 10%). Connect an external 1.5-kΩ resistor on D+ (full speed) or D– (low speed). Pin function is controlled by input SOFTCON. SOFTCON = LOW – Vpu(3.3) floating (high impedance), ensures zero pullup current SOFTCON = HIGH – Vpu(3.3) = 3.3 V, internally connected to Vreg(3.3) SOFTCON 2 I Software-controlled USB connection. A HIGH level applies 3.3 V to pin Vpu(3.3), which is connected to an external 1.5-kΩ pullup resistor. This allows USB connect/disconnect signaling to be controlled by software input pad. Push pull, CMOS. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TUSB1106-Q1 3 TUSB1106-Q1 SCAS916 – AUGUST 2011 www.ti.com FUNCTIONAL DESCRIPTION Function Selection FUNCTION TABLE SUSPND OE D+, D– RCV VP, VM L L Driving and receiving Active Active Normal driving (differential receiver active) L H Receiving (1) Active H H (1) (2) (3) L H Driving High-Z (1) FUNCTION Active Receiving Inactive (2) Active Driving during suspend (3) (differential receiver inactive) Inactive (2) Active Low-power state Signal levels on D+ and D– are determined by other USB devices and external pullup/pulldown resistors. In suspend mode (SUSPND = HIGH) the differential receiver is inactive and output RCV is always LOW. Out of suspend (K), signaling is detected via the single-ended receivers VP and VM. During suspend, the slew-rate control circuit of low-speed operation is disabled. The D+ and D– lines are still driven to their intended states, without slew-rate control. This is permitted because driving during suspend is used to signal remote wakeup by driving a K signal (one transition from idle to K state) for a period of 1 ms to 15 ms. Operating Functions Driving Function (Pin OE = L) Using Differential Input Data Interface DATA STATE VMO VPO DATA LOW SPEED FULL SPEED L L SE0 X X H L Differential logic 0 J K L H Differential logic 1 K J H H Illegal state X X Table 1. Receiving Function (Pin OE = H) DATA STATE RCV VP (1) VM (1) LOW SPEED FULL SPEED Differential logic 0 L L H J K Differential logic 1 H H L K J L L X X D+, D– SE0 (1) (2) RCV* (2) VP = VM = H indicates the sharing mode (VCC(5.0) and Vreg(3.3) are disconnected). RCV* denotes the signal level on output RCV just before SE0 state occurs. This level is stable during the SE0 period. Power-Supply Configurations The TUSB1106-Q1 can be used with different power-supply configurations, which can be dynamically changed. An overview is given in Table 3. • Normal mode – Both VCC(I/O) and VCC(5.0) or (VCC(5.0) and Vreg(3.3)) are connected. For 5-V operation, VCC(5.0) is connected to a 5-V source (4 V to 5.5 V). The internal voltage regulator then produces 3.3 V for the USB connections. For 3.3-V operation, both VCC(5.0) and Vreg(3.3) are connected to a 3.3-V source (3 V to 3.6 V). VCC(I/O) is independently connected to a voltage source (1.65 V to 3.6 V), depending on the supply voltage of the external circuit. • Disable mode – VCC(I/O) is not connected, VCC(5.0) or (VCC(5.0) and Vreg(3.3)) are connected. In this mode, the internal circuits of the TUSB1106-Q1 ensure that the D+ and D– pins are in 3-state and the power consumption drops to the low-power (suspended) state level. Some hysteresis is built into the detection of VCC(I/O) lost. • Sharing mode – VCC(I/O) is connected, (VCC(5.0) and Vreg(3.3)) are not connected. In this mode, the D+ and D– pins are made 3-state and the TUSB1106-Q1 allows external signals of up to 3.6 V to share the D+ and D– 4 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TUSB1106-Q1 TUSB1106-Q1 SCAS916 – AUGUST 2011 www.ti.com lines. The internal circuits of the TUSB1106-Q1 ensure that virtually no current (maximum 10 μA) is drawn via the D+ and D– lines. The power consumption through VCC(I/O) drops to the low-power (suspended) state level. Both the VP and VM pins are driven HIGH to indicate this mode. Pin RCV is made LOW. Some hysteresis is built into the detection of Vreg(3.3) lost. Table 2. Pin States in Disable or Sharing Mode PINS DISABLE-MODE STATE VCC(5.0)/Vreg(3.3) Not present VCC(I/O) Not present 1.65-V to 3.6-V input Vpu(3.3) High impedance (off) High impedance (off) D+, D– High impedance High impedance VP, VM Invalid (1) H (2) L RCV Invalid Inputs (VO/VPO, FSE0/VMO, SPEED, SUSPND, OE, SOFTCON) (1) (2) SHARING-MODE STATE 5-V input/3.3-V output, 3.3-V input/3.3-V input High impedance High impedance High impedance or driven LOW High impedance or driven LOW Table 3. Power-Supply Configuration Overview (1) VCC(5.0) or Vreg(3.3) VCC(I/O) CONFIGURATION Connected Connected Normal mode SPECIAL CHARACTERISTICS Connected Not connected Disable mode D+, D–, and Vpu(3.3) are in high impedance. VP, VM, and RCV are invalid. (1) Not connected Connected Sharing mode D+, D–, and Vpu(3.3) are in high impedance. VP and VM are driven HIGH. RCV is driven LOW. High impedance or driven LOW Power-Supply Input Options The TUSB1106-Q1 has two power-supply input options. • Internal regulator – VCC(5.0) is connected to 4 V to 5.5 V. The internal regulator is used to supply the internal circuitry with 3.3 V (nominal). Vreg(3.3) becomes a 3.3-V output reference. • Regulator bypass – VCC(5.0) and Vreg(3.3) are connected to the same supply. The internal regulator is bypassed and the internal circuitry is supplied directly from the Vreg(3.3) power supply. The voltage range is 3 V to 3.6 V to comply with the USB specification. The supply-voltage range for each input option is specified in Table 4. Table 4. Power-Supply Input Options INPUT OPTION VCC(5.0) VREG(3.3) VCC(I/O) Internal regulator Supply input for internal regulator (4 V to 5.5 V) Voltage-reference output (3.3 V, 300 μA) Supply input for digital I/O pins (1.65 V to 3.6 V) Regulator bypass Connected to Vreg(3.3) with maximum voltage drop of 0.3 V (2.7 V to 3.6 V) Supply input (3 V to 3.6 V) Supply input for digital I/O pins (1.65 V to 3.6 V) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TUSB1106-Q1 5 TUSB1106-Q1 SCAS916 – AUGUST 2011 www.ti.com ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCC(5.0) Supply voltage range –0.5 6 V VI(I/O) Supply voltage range –0.5 4.6 V VCCreg(3.3) Regulated voltage range –0.5 4.6 V VI DC input voltage –0.5 VCC(I/O) + 0.5 V IIK Input clamp current Tstg Storage temperature range (1) VI = –1.8 V to 5.4 V –40 100 mA 125 °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS MIN NOM MAX VCC(5.0) Supply voltage, internal regulator option 5-V operation 4 5 5.5 V VCCreg(3.3) Supply voltage, regulator bypass option 3.3-V operation 3 3.3 3.6 V VCC(I/O) I/O supply voltage 1.65 3.6 V VI I/O supply voltage 0 VCC(I/O) V VI/O Input voltage on analog I/O pins (D+, D–) 0 3.6 V Tc Junction temperature –40 85 °C 6 Submit Documentation Feedback UNIT Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TUSB1106-Q1 TUSB1106-Q1 SCAS916 – AUGUST 2011 www.ti.com STATIC ELECTRICAL CHARACTERISTICS – SUPPLY PINS over recommended ranges of operating free-air temperature and supply voltage (unless otherwise noted) PARAMETER TEST CONDITIONS MIN Vreg(3.3) Regulated supply-voltage output Internal regulator option, Iload ≤ 300 μA (1) ICC Operating supply current Full-speed transmitting and receiving at 12 Mbit/s, CL = 50 pF on D+ and D– (3) ICC(I/O) Operating I/O supply current Full-speed transmitting and receiving at 12 Mbit/s (3) ICC(idle) Supply current during full-speed idle and SE0 Full-speed idle: VD+ > 2.7 V, VD– < 0.3 V SE0: VD+ < 0.3 V, VD– < 0.3 V (4) ICC(I/O)(static) Static I/O supply current Full-speed idle, SE0 or suspend ICC(susp) Suspend supply current SUSPND = HIGH (4) Disable-mode supply current VCC(I/O) not connected ICC(I/O)(sharing) Sharing-mode I/O supply current VCC(5.0) or Vreg(3.3) not connected IDx(sharing) Sharing-mode load current on D+ and D– VCC(5.0) or Vreg(3.3) not connected, SOFTCON = LOW, VDx = 3.6 V Vreg(3.3)th Regulated supply-voltage detection threshold 1.65 V ≤ VCC(I/O) ≤ Vreg(3.3), 2.7 V ≤ Vreg(3.3) ≤ 3.6 V Vreg(3.3)hys Regulated supply-voltage detection hysteresis VCC(I/O) = 1.8 V VCC(I/O)th I/O supply-voltage detection threshold Vreg(3.3) = 2.7 V to 3.6 V I/O supply-voltage detection hysteresis Vreg(3.3) = 3.3 V (1) (2) (3) (4) (5) 3 (4) ICC(dis) VCC(I/O)hys (2) TYP MAX 3.3 3.6 6 8 mA 2.3 2.5 mA 500 μA 10 22 μA 10 22 μA 10 22 μA 10 22 μA 10 μA Supply lost during power down Supply detect during power up (5) V 0.8 V 2.4 0.45 Supply lost during power down Supply detect during power up UNIT V 0.5 V 1.4 0.45 V Iload includes the pullup resistor current via Vpu(3.3). In suspend mode, the typical voltage is 2.8 V. Maximum value is characterized only, not tested in production. Excluding any load current and Vpu(3.3)/Vsw source current to the 1.5-kΩ and 15-kΩ pullup and pulldown resistors (200 μA typ) When VCC(I/O) < 2.7 V, the minimum value for Vreg(3.3)th (present) is 2 V. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TUSB1106-Q1 7 TUSB1106-Q1 SCAS916 – AUGUST 2011 www.ti.com STATIC ELECTRICAL CHARACTERISTICS – DIGITAL PINS over recommended ranges of operating free-air temperature and supply voltage (unless otherwise noted) PARAMETER TEST CONDITIONS VCC(I/O) VIL LOW-level input voltage 1.65 V to 3.6 V VIH HIGH-level input voltage 1.65 V to 3.6 V IOL = 100 μA IOL = 2 mA IOL = 100 μA VOL LOW-level output voltage IOL = 2 mA IOL = 100 μA IOL = 2 mA IOL = 100 μA IOL = 2 mA IOH = 100 μA IOH = 2 mA IOH = 100 μA VOH HIGH-level output voltage IOH = 2 mA IOH = 100 μA IOH = 2 mA IOH = 100 μA IOH = 2 mA ILI Input leakage current CIN Input capacitance 8 MIN 0.3 VCC(I/O) 0.6 VCC(I/O) 0.4 0.15 0.4 0.4 VCC(I/O) – 0.15 VCC(I/O) – 0.4 1.5 1.25 Submit Documentation Feedback V 2.15 1.9 2.85 2.6 –1 Pin to GND V 0.15 3.3 V ± 0.3 V 3.3 V ± 0.3 V V 0.15 2.5 V ± 0.2 V 2.5 V ± 0.2 V V 0.4 1.8 V ± 0.15 V 1.8 V ± 0.15 V UNIT 0.15 1.65 V to 3.6 V 1.65 V to 3.6 V MAX 1 μA 3.5 pF Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TUSB1106-Q1 TUSB1106-Q1 SCAS916 – AUGUST 2011 www.ti.com STATIC ELECTRICAL CHARACTERISTICS – ANALOG I/O PINS over recommended ranges of operating free-air temperature and supply voltage, VCC = 4 V to 5.5 V or Vreg(3.3) = 3 V to 3.6 V, VGND = 0 V, TA = –40°C to 85°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VDI Differential input sensitivity |VI(D+) – VI(D–)| 0.2 VCM Differential common-mode voltage Includes VDI range 0.8 2.5 V VIL LOW-level input voltage, single-ended receiver 2 0.8 V VIH HIGH-level input voltage, single-ended receiver 0.4 Vhys Hysteresis voltage, single-ended receiver VOL LOW-level output voltage RL = 1.5 kΩ to 3.6 V VOH HIGH-level output voltage RL = 1.5 kΩ to GND ILZ OFF-state leakage current CIN Transceiver capacitance Pin to GND ZDRV Driver output impedance Steady-state drive ZINP Input impedance RSW Internal switch resistance at Vpu(3.3) VTERM Termination voltage for upstream port pullup (RPU) (1) (2) (3) (4) V V 2.8 (1) 34 (2) 39 0.7 V 0.3 V 3.6 V 1 μA 25 pF 44 10 3 (3) (4) Ω MΩ 13 Ω 3.6 V VOH(min) = Vreg(3.3) – 0.2 V Includes external resistors of 33 Ω ±1% on both D+ and D– This voltage is available at Vreg(3.3) and Vpu(3.3). In suspend mode, the minimum voltage is 2.7 V. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TUSB1106-Q1 9 TUSB1106-Q1 SCAS916 – AUGUST 2011 www.ti.com DYNAMIC ELECTRICAL CHARACTERISTICS – ANALOG I/O PINS (D+, D–) (1) Driver Characteristics, Full-Speed Mode (2) over recommended ranges of operating free-air temperature and supply voltage, VCC = 4 V to 5.5 V or Vreg(3.3) = 3 V to 3.6 V, VCC(I/O) = 1.65 V to 3.6 V, VGND = 0 V, see Table 10 for valid voltage level combinations, TA = –40°C to 85°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN MAX UNIT tFR Rise time CL = 50 pF to 125 pF, 10% to 90% of |VOH – VOL| (see Figure 1) 4 20 ns tFF Fall time CL = 50 pF to 125 pF, 90% to 10% of |VOH – VOL| (see Figure 1) 4 20 ns FRFM Differential rise/fall time matching (tFR/tFF) Excluding the first transition from idle state 90 111.1 % VCRS Output signal crossover voltage Excluding the first transition from idle state (see Figure 10) 1.3 2 V (1) (2) Test circuit, see Figure 13 Driver timing in low-speed mode is not specified. Low-speed delay timings are dominated by the slow rise/fall times tLR and tLF. DYNAMIC ELECTRICAL CHARACTERISTICS – ANALOG I/O PINS (D+, D–) (1) Driver Characteristics, Low-Speed Mode (2) over recommended ranges of operating free-air temperature and supply voltage, VCC = 4 V to 5.5 V or Vreg(3.3) = 3 V to 3.6 V, VCC(I/O) = 1.65 V to 3.6 V, VGND = 0 V, see Table 10 for valid voltage level combinations, TA = –40°C to 85°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN MAX UNIT 75 300 ns tLR Rise time CL = 200 pF to 600 pF, 10% to 90% of |VOH – VOL| (see Figure 1) tLF Fall time CL = 200 pF to 600 pF, 90% to 10% of |VOH – VOL| (see Figure 1) 75 300 ns LRFM Differential rise/fall time matching (tLR/tLF) Excluding the first transition from idle state 80 125 % VCRS Output signal crossover voltage Excluding the first transition from idle state (see Figure 10) 1.3 2 V (1) (2) Test circuit, see Figure 13 Driver timing in low-speed mode is not specified. Low-speed delay timings are dominated by the slow rise/fall times tLR and tLF. DYNAMIC ELECTRICAL CHARACTERISTICS – ANALOG I/O PINS (D+, D–) (1) Driver Timing, Full-Speed Mode (2) over recommended ranges of operating free-air temperature and supply voltage, VCC = 4 V to 5.5 V or Vreg(3.3) = 3 V to 3.6 V, VCC(I/O) = 1.65 V to 3.6 V, VGND = 0 V, see Table 10 for valid voltage level combinations, TA = –40°C to 85°C (unless otherwise noted) PARAMETER tPLH(drv) tPHL(drv) tPHZ tPLZ tPZH tPZL (1) (2) 10 Driver propagation delay (VO/VPO, FSE0/VMO to D+, D–) Driver disable delay (OE to D+, D–) Driver enable delay (OE to D+, D–) TEST CONDITIONS MIN MAX LOW to HIGH (see Figure 4) 18 HIGH to LOW (see Figure 4) 18 HIGH to OFF (see Figure 2) 15 LOW to OFF (see Figure 2) 15 OFF to HIGH (see Figure 2) 15 OFF to LOW (see Figure 2) 15 UNIT ns ns ns Test circuit, see Figure ? Driver timing in low-speed mode is not specified. Low-speed delay timings are dominated by the slow rise/fall times tLR and tLF. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TUSB1106-Q1 TUSB1106-Q1 SCAS916 – AUGUST 2011 www.ti.com DYNAMIC ELECTRICAL CHARACTERISTICS FOR ANALOG I/O PINS (D+, D–) (1) Receiver Timing, Full-Speed and Low-Speed Mode, Differential Receiver over recommended ranges of operating free-air temperature and supply voltage, VCC = 4 V to 5.5 V or Vreg(3.3) = 3 V to 3.6 V, VCC(I/O) = 1.65 V to 3.6 V, VGND = 0 V, see Table 10 for valid voltage level combinations, TA = –40°C to 85°C (unless otherwise noted) PARAMETER tPLH(rcv) tPHL(rcv) (1) TEST CONDITIONS Propagation delay (D+, D– to RCV) MIN MAX LOW to HIGH (see Figure 3) 15 HIGH to LOW (see Figure 3) 15 UNIT ns Test circuit, see Figure ? DYNAMIC ELECTRICAL CHARACTERISTICS FOR ANALOG I/O PINS (D+, D–) (1) Receiver Timing, Full-Speed and Low-Speed Mode, Single-Ended Receiver over recommended ranges of operating free-air temperature and supply voltage, VCC = 4 V to 5.5 V or Vreg(3.3) = 3 V to 3.6 V, VCC(I/O) = 1.65 V to 3.6 V, VGND = 0 V, see Table 10 for valid voltage level combinations, TA = –40°C to 85°C (unless otherwise noted) PARAMETER tPLH(se) tPHL(se) (1) TEST CONDITIONS Propagation delay (D+, D– to VP, VM) MIN MAX LOW to HIGH (see Figure 3) 18 HIGH to LOW (see Figure 3) 18 UNIT ns Test circuit, see Figure 13 tFR,tLR VOH 1.8 V tFF,tLF 90% 0.9 V Logic Input 0.9 V 90% 0V 10% 10% VOL MGS96 3 tPZH tPZL VOH VOH − 0.3 V Differential Data Lines VOL Figure 1. Rise and Fall Times 2.0 V Differential Data Lines tPHZ tPLZ VCRS VOL + 0.3 V MG S96 6 Figure 2. OE to D+, D– 1.8 V VCRS 0.8 V VCRS tPLH(rcv) tPLH(se) VOH Logic Output Logic Output 0.9 V 0V tPHL(rcv) tPHL(se) VOH Differential Data Lines 0.9 V 0.9 V VOL MGS965 Figure 3. D+, D– to RCV, VP, VM 0.9 V tPLH(drv) VCRS tPHL(drv) VCRS VOL MGS9 64 Figure 4. VO/VPO, FSE0/VMO to D+, D– Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TUSB1106-Q1 11 TUSB1106-Q1 SCAS916 – AUGUST 2011 www.ti.com APPLICATION INFORMATION Test Point 33 Ω 500 Ω D.U.T. + 50 pF V – MBL142 Figure 5. Load for Enable and Disable Times A. V = 0 V for tPZH, tPHZ B. V = Vreg(3.3) for tPZL, tPLZ Test Point 25 pF D.U.T. MGS968 Figure 6. Load for VM, VP, and RCV VPU(3.3) 1.5 kΩ D.U.T. D+/D– 33 Ω CL 15 kΩ Test Point Figure 7. Load for D+, D– 12 A. Full-speed mode: connected to D+ B. Low-speed mode: Connected to D– C. Load capacitance: • CL = 50 pF or 125 pF (full-speed mode, minimum or maximum timing) • CL = 200 pF or 600 pF (low-speed mode, minimum or maximum timing) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TUSB1106-Q1 TUSB1106-Q1 SCAS916 – AUGUST 2011 www.ti.com 1.65 V to 3.6 V 3.3 V 0.1 µF GND V V OE CC CC(I/O) V reg(3.3) SPEED 0.1 µF SOFTCON V CC(5.0) SUSPND 1.5 kW V System ASIC V GND pu(3.3) 33 W RCV BUS 0.1 µF GND D+ VMO/FSE0 33 W VPO/VO D– VP TUSB1106-Q1 VM GND GND Figure 8. Peripheral-Side (Full-Speed) Regulator Bypass Mode Peripheral-Side (Full-Speed) Regulator Bypass Mode This mode is applicable when there is a 3.3-V supply already available on the board. The VBUS pin of the USB connector, if left unused at the peripheral side, should be terminated with a 0.1-μF capacitor. While operating at full speed, the 1.5-kΩ resistor must be connected between the D+ line and VPU(3.3) or an external 3.3-V supply. When the VCC(5.0) and the Vreg(3.3) are connected together, the device operates at regulator bypass mode. This enables power savings since the regulator is turned off. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TUSB1106-Q1 13 TUSB1106-Q1 SCAS916 – AUGUST 2011 www.ti.com 1.65 V to 3.6 V 3.3 V 0.1 µF GND V V OE CC CC(I/O) V reg(3.3) SPEED 0.1 µF SOFTCON V CC(5.0) SUSPND GND 1.5 kW V V pu(3.3) BUS 0.1 µF System ASIC RCV 33 W GND D+ VMO/FSE0 33 W VPO/VO D– VP TUSB1106-Q1 VM GND GND Figure 9. Peripheral-Side (Low-Speed) Regulator Bypass Mode Peripheral-Side (Low-Speed) Regulator Bypass Mode This mode is applicable when there is a 3.3-V supply already available on the board. The VBUS pin of the USB connector, if left unused at the peripheral side, should be terminated with a 0.1-μF capacitor. While operating at low speed, the 1.5-kΩ resistor must to be connected between the D– line and VPU(3.3) or an external 3.3-V supply. When the VCC(5.0) and the Vreg(3.3) are connected together, the device operates at regulator bypass mode. This enables power savings since the regulator is turned off. 14 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TUSB1106-Q1 TUSB1106-Q1 SCAS916 – AUGUST 2011 www.ti.com 1.65 V to 3.6 V 0.1 µF GND V V OE CC CC(I/O) V reg(3.3) SPEED 0.1 µF SOFTCON V CC(5.0) SUSPND GND 1.5 kW V System ASIC V 0.1 µF BUS PU(3.3) RCV 33 W VMO/FSE0 D+ VPO/VO D– GND 33 W VP TUSB1106-Q1 VM GND GND Figure 10. Peripheral-Side (Full-Speed) Internal Regulator Mode Peripheral-Side (Full-Speed) Internal Regulator Mode The USB side of the TUSB1106-Q1 can be powered from the VBUS line directly if a 3.3-V supply is not present on board. In this case, the internal regulator can be used to provide the 3.3-V supply for USB signaling. The VCC(5.0) is connected to the VBUS, which receives 5-V supply from the host, and generates the 3.3-V output at the Vreg(3.3) pin. In this mode, it is important that both VCC(5.0) and Vreg(3.3) pins have individual bypass capacitors in the range of 0.1 μF. Powering VCC(5.0) through the VBUS port of the USB connector realizes significant power saving for portable applications, such as cell phones, PDAs, etc. In this operating mode, the ICC(5.0) current is fed from the host. The USB-side power consumption, ICC(5.0) is 4 mA (with the regulator active), as opposed to logic-side ICC(IO) of 1 mA under full-speed operation. While operating at full speed, the 1.5-kΩ resistor must be connected between the D+ line and the VPU(3.3) or an external 3.3-V supply. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TUSB1106-Q1 15 TUSB1106-Q1 SCAS916 – AUGUST 2011 www.ti.com 1.65 V to 3.6 V 0.1 µF GND V V OE CC CC(I/O) V reg(3.3) 0.1 µF SPEED SOFTCON GND V CC(5.0) SUSPND 1.5 kW V System ASIC 0.1 µF V BUS PU(3.3) RCV 33 W GND D+ VMO/FSE0 33 W D– VPO/VO VP TUSB1106-Q1 VM GND GND Figure 11. Peripheral-Side (Low-Speed) Internal Regulator Mode Peripheral-Side (Low-Speed) Internal Regulator Mode The USB side of the TUSB1106-Q1 can be powered from the VBUS line directly if a 3.3-V supply is not present on board. In this case, the internal regulator can be used to provide the 3.3-V supply for the USB signaling. The VCC(5.0) is connected to the VBUS, which receives 5-V supply from the host, and generates the 3.3-V output at the Vreg(3.3) pin. In this mode, it is important that both VCC(5.0) and Vreg(3.3) pins have individual bypass capacitors in the range of 0.1 μF. Powering VCC(5.0) through the VBUS port of the USB connector realizes significant power saving for portable applications, such as cell phones, PDAs, etc. In this operating mode, the ICC(5.0) current is fed from the host side. The USB-side power consumption, ICC(5.0) is 4 mA (with the regulator active), as opposed to logic-side ICC(IO) of 1 mA under full-speed operation. While operating at low speed, the 1.5-kΩ resistor must be connected between the D– line and the VPU(3.3) or an external 3.3-V supply. 16 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TUSB1106-Q1 TUSB1106-Q1 SCAS916 – AUGUST 2011 www.ti.com 1.65 V to 3.6 V 0.1 µF GND V CC(I/O) 5V 5V 0.1 µF V reg(3.3) SOFTCON CC(5.0) SUSPND 0.1 µF V CC SPEED GND V V OE V BUS pu(3.3) GND 33 W RCV D+ System ASIC VMO/FSE0 33 W D– VPO/VO 15 kW VP 15 kW TUSB1106-Q1 VM GND GND GND GND Figure 12. Host Side (VCC(5.0) Supplied From VBUS Pin) Host Side (VCC(5.0) Supplied From VBUS Pin) If there is no 3.3-V supply on board, an external 5-V supply can support the USB-side power needs. When the VCC(5.0) is connected to an external 5-V supply, the on-chip regulator generates the 3.3-V internal supply rail, which is used to drive the USB signaling levels at the USB side of the TUSB1106-Q1. The logic-side I/Os can operate at any voltage range from 1.65 V to 3.6 V. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TUSB1106-Q1 17 TUSB1106-Q1 SCAS916 – AUGUST 2011 www.ti.com 1.65 V to 3.6 V 0.1 µF 3.3 V GND V CC(I/O) OE V CC 5V V reg(3.3) SPEED 0.1 µF SOFTCON V CC(5.0) SUSPND GND V BUS V pu(3.3) 33 W RCV D+ System ASIC VMO/FSE0 33 W D– VPO/VO 15 kW 15 kW VP TUSB1106-Q1 VM GND GND GND GND Figure 13. Host-Side (3.3-V Supply Present) Internal Regulator Bypass Mode Host-Side (3.3-V Supply Present) Internal Regulator Bypass Mode If a 3.3-V supply supports the USB-side power, VCC(5.0) and Vreg(3.3) must to be tied together and connected to a 3.3-V supply. It also makes the regulator inactive. 18 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TUSB1106-Q1 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TUSB1106IPWRQ1 ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TU1106I (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of